From dc9ef7d2d6a2be8f0beb4cc9d6ccf631b93eb900 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 4 Oct 2023 16:28:12 +0200 Subject: [PATCH] Big refactoring + Improvements for future auto-generation script (#8) --- Bender.yml | 8 +- CHANGELOG.md | 19 + Makefile | 8 +- README.md | 27 +- src/floo_axi_chimney.sv | 513 +++---- src/floo_axi_flit_pkg.sv | 224 --- src/floo_axi_pkg.sv | 145 ++ src/floo_narrow_wide_chimney.sv | 1485 ++++++++++--------- src/floo_narrow_wide_flit_pkg.sv | 355 ----- src/floo_narrow_wide_pkg.sv | 223 +++ src/floo_narrow_wide_router.sv | 171 ++- src/floo_param_pkg.sv | 41 - src/floo_pkg.sv | 23 + src/floo_rob.sv | 7 +- src/floo_route_select.sv | 8 +- src/floo_wormhole_arbiter.sv | 2 +- src/synth/floo_synth_axi_chimney.sv | 26 +- src/synth/floo_synth_endpoint.sv | 105 +- src/synth/floo_synth_narrow_wide_chimney.sv | 73 +- src/synth/floo_synth_narrow_wide_router.sv | 30 +- src/synth/floo_synth_router.sv | 60 +- test/floo_axi_rand_slave.sv | 23 +- test/floo_dma_test_node.sv | 7 +- test/floo_test_pkg.sv | 28 + test/tb_floo_axi_chimney.sv | 42 +- test/tb_floo_axi_chimney.wave.tcl | 20 +- test/tb_floo_dma_chimney.sv | 40 +- test/tb_floo_dma_mesh.sv | 340 ++--- test/tb_floo_dma_nw_chimney.sv | 394 ++--- test/tb_floo_narrow_wide_chimney.sv | 335 +++-- test/tb_floo_narrow_wide_chimney.wave.tcl | 44 +- test/tb_floo_rob.sv | 121 +- test/tb_floo_router.sv | 57 +- util/axi_cfg.hjson | 18 +- util/flit_gen.py | 102 +- util/floo_flit_pkg.sv.mako | 137 ++ util/floo_flit_pkg.sv.tpl | 166 --- util/narrow_wide_cfg.hjson | 33 +- 38 files changed, 2673 insertions(+), 2787 deletions(-) delete mode 100644 src/floo_axi_flit_pkg.sv create mode 100644 src/floo_axi_pkg.sv delete mode 100644 src/floo_narrow_wide_flit_pkg.sv create mode 100644 src/floo_narrow_wide_pkg.sv delete mode 100644 src/floo_param_pkg.sv create mode 100644 util/floo_flit_pkg.sv.mako delete mode 100644 util/floo_flit_pkg.sv.tpl diff --git a/Bender.yml b/Bender.yml index b0e7f00e..c1546b35 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,10 +19,9 @@ export_include_dirs: sources: # Level 0 - - src/floo_axi_flit_pkg.sv - - src/floo_narrow_wide_flit_pkg.sv + - src/floo_axi_pkg.sv + - src/floo_narrow_wide_pkg.sv - src/floo_pkg.sv - - src/floo_param_pkg.sv # Level 1 - src/floo_cut.sv - src/floo_fifo.sv @@ -64,9 +63,10 @@ sources: - target: any(synthesis,spyglass) files: # Level 0 + - test/floo_test_pkg.sv + # Level 1 - src/synth/floo_synth_axi_chimney.sv - src/synth/floo_synth_narrow_wide_chimney.sv - src/synth/floo_synth_router.sv - - src/synth/floo_synth_router_simple.sv - src/synth/floo_synth_narrow_wide_router.sv - src/synth/floo_synth_endpoint.sv diff --git a/CHANGELOG.md b/CHANGELOG.md index 711df577..29c9e03c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,6 +4,25 @@ All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## Unreleased + +### Changed + +- Renamed `*_flit_pkg` to `*_pkg` +- New naming scheme of ports: All AXI ports are now prefixed with `axi_`, all FlooNoC links are now prefixed with `floo_` +- Renamed `floo_param_pkg` to `floo_test_pkg` +- Renamed AXI `resp_t` structs to `rsp_t` +- Changed configuration format to align with upcoming FlooNoC generation script + +### Added + +- Table based routing support in `narrow_wide_chimney` +- Support for different number of inputs and outputs in `narrow_wide_router` + +### Fixed + +- Test modules `floo_axi_rand_slave` & `floo_dma_test_node` now support `addr_width > 32` + ## [0.1.0] - 2023-06-19 ### Added diff --git a/Makefile b/Makefile index c146bdd9..0041cf45 100644 --- a/Makefile +++ b/Makefile @@ -67,17 +67,19 @@ endif ################### FLIT_CFG ?= $(shell find util -name "*.hjson") -FLIT_SRC ?= $(patsubst util/%_cfg.hjson,src/floo_%_flit_pkg.sv,$(FLIT_CFG)) +FLIT_SRC ?= $(patsubst util/%_cfg.hjson,src/floo_%_pkg.sv,$(FLIT_CFG)) +FLIT_GEN ?= util/flit_gen.py +FLIT_TPL ?= util/floo_flit_pkg.sv.mako .PHONY: sources clean-sources sources: $(FLIT_SRC) -src/floo_%_flit_pkg.sv: util/%_cfg.hjson +src/floo_%_pkg.sv: util/%_cfg.hjson $(FLIT_GEN) $(FLIT_TPL) ./util/flit_gen.py -c $< > $@ $(VERIBLE_FMT) --inplace --try_wrap_long_lines $@ clean-sources: - rm -f src/floo_*_flit_pkg.sv + rm -f src/floo_*_pkg.sv ###################### # Traffic Generation # diff --git a/README.md b/README.md index 4cde390c..4cc31239 100644 --- a/README.md +++ b/README.md @@ -146,37 +146,34 @@ The data structs for the flits and the links are auto-generated and can be confi The AXI channels(s) needs to be configured in `util/*cfg.hjson`. The following example shows the configuration for a single AXI channel with 64-bit data width, 32-bit address width, 3-bit ID width, and 1-bit user width (beware that ID width can be different for input and output channels). - ``` +``` axi_channels: [ - {name: 'axi', params: {dw: 64, aw: 32, iw: 3, uw: 1 }}, + {name: 'axi', direction: 'input', params: {dw: 64, aw: 32, iw: 3, uw: 1 }}, ] ``` Multiple physical links can be declared and the mapping of the AXI channels to the physical link can be configured in `util/*cfg.json`. The following example shows the configuration for two physical channels, one for requests and one for responses. The mapping of the AXI channels to the physical link is done by specifying the AXI channels in the `map` field. ``` - phys_channels: [ - 'req', - 'rsp' - ], - map: { - req: ["axi_aw", "axi_w", "axi_ar"], - rsp: ["axi_b", "axi_r"] + channel_mapping: { + req: {axi: ['aw', 'w', 'ar']}, + rsp: {axi: ['b', 'r']} }, ``` -FlooNoC does not send any header and tail flits to avoid serilization overhead. Instead additional needed information is sent in parallel and can be specified with the `meta` argument and the number of bits required. For instance, the `rob_req` field specifies if a responses needs to be reorderd. The `rob_idx` field specifies the index of the ROB that is used to track the outstanding requests. The `dst_id` & `src_id` fields specifies source and destination to route the packet. The `last` field specifies the last signal of the of a burst transfer used in wormhole routing. +FlooNoC does not send any header and tail flits to avoid serilization overhead. Instead additional needed information is sent in parallel and can be specified with the `header` argument and the number of bits required. For instance, the `rob_req` field specifies if a responses needs to be reorderd. The `rob_idx` field specifies the index of the ROB that is used to track the outstanding requests. The `dst_id` & `src_id` fields specifies source and destination to route the packet. The `last` field specifies the last signal of the of a burst transfer used in wormhole routing. ``` - meta: { + header: { rob_req: 1, - rob_idx: 7, + rob_idx: 6, dst_id: 6, src_id: 6, - last: 1 + last: 1, + atop: 1, } ``` -Finally, the package source files can be generated with the following command: +Finally, the package source files can be generated with: ```sh -python util/flit_gen.py -c /path/to/cfg.hjson -o /path/to/outdir +make sources ``` diff --git a/src/floo_axi_chimney.sv b/src/floo_axi_chimney.sv index 6ec58dbe..a694ad8a 100644 --- a/src/floo_axi_chimney.sv +++ b/src/floo_axi_chimney.sv @@ -11,7 +11,7 @@ /// A bidirectional network interface for connecting AXI4 Buses to the NoC module floo_axi_chimney import floo_pkg::*; - import floo_axi_flit_pkg::*; + import floo_axi_pkg::*; #( /// Atomic operation support parameter bit AtopSupport = 1'b1, @@ -54,59 +54,60 @@ module floo_axi_chimney input sram_cfg_t sram_cfg_i, /// AXI4 side interfaces input axi_in_req_t axi_in_req_i, - output axi_in_resp_t axi_in_rsp_o, + output axi_in_rsp_t axi_in_rsp_o, output axi_out_req_t axi_out_req_o, - input axi_out_resp_t axi_out_rsp_i, + input axi_out_rsp_t axi_out_rsp_i, /// Coordinates/ID of the current tile input xy_id_t xy_id_i, input src_id_t id_i, /// Output to NoC - output req_flit_t req_o, - output rsp_flit_t rsp_o, + output floo_req_t floo_req_o, + output floo_rsp_t floo_rsp_o, /// Input from NoC - input req_flit_t req_i, - input rsp_flit_t rsp_i + input floo_req_t floo_req_i, + input floo_rsp_t floo_rsp_i ); // AX queue - axi_in_aw_chan_t aw_queue; - axi_in_ar_chan_t ar_queue; - logic aw_queue_valid_out, aw_queue_ready_in; - logic ar_queue_valid_out, ar_queue_ready_in; + axi_in_aw_chan_t axi_aw_queue; + axi_in_ar_chan_t axi_ar_queue; + logic axi_aw_queue_valid_out, axi_aw_queue_ready_in; + logic axi_ar_queue_valid_out, axi_ar_queue_ready_in; axi_in_req_t axi_out_req_id_mapped; - axi_in_resp_t axi_out_rsp_id_mapped; + axi_in_rsp_t axi_out_rsp_id_mapped; `AXI_ASSIGN_REQ_STRUCT(axi_out_req_o, axi_out_req_id_mapped) `AXI_ASSIGN_RESP_STRUCT(axi_out_rsp_id_mapped, axi_out_rsp_i) - req_data_t [AxiInAw:AxiInAr] req_data_arb_data_in; - rsp_data_t [AxiInB:AxiInR] rsp_data_arb_data_in; - logic [AxiInAw:AxiInAr] req_data_arb_req_in, req_data_arb_gnt_out; - logic [AxiInB:AxiInR] rsp_data_arb_req_in, rsp_data_arb_gnt_out; + floo_req_chan_t [AxiAw:AxiAr] floo_req_arb_in; + floo_rsp_chan_t [AxiB:AxiR] floo_rsp_arb_in; + logic [AxiAw:AxiAr] floo_req_arb_req_in, floo_req_arb_gnt_out; + logic [AxiB:AxiR] floo_rsp_arb_req_in, floo_rsp_arb_gnt_out; // flit queue - req_flit_t req_in; - rsp_flit_t rsp_in; - logic req_ready_out, rsp_ready_out; + floo_req_chan_t floo_req_in; + floo_rsp_chan_t floo_rsp_in; + logic floo_req_in_valid, floo_rsp_in_valid; + logic floo_req_out_ready, floo_rsp_out_ready; logic [NumAxiChannels-1:0] axi_valid_in, axi_ready_out; // Flit packing - axi_in_aw_data_t aw_data; - axi_in_w_data_t w_data; - axi_in_ar_data_t ar_data; - axi_in_b_data_t b_data; - axi_in_r_data_t r_data; - axi_in_aw_chan_t aw_id_mod; - axi_in_ar_chan_t ar_id_mod; + floo_axi_aw_flit_t floo_axi_aw; + floo_axi_w_flit_t floo_axi_w; + floo_axi_ar_flit_t floo_axi_ar; + floo_axi_b_flit_t floo_axi_b; + floo_axi_r_flit_t floo_axi_r; + axi_in_aw_chan_t axi_aw_id_mod; + axi_in_ar_chan_t axi_ar_id_mod; // Flit unpacking - axi_in_aw_chan_t unpack_aw_data; - axi_in_ar_chan_t unpack_ar_data; - axi_in_w_chan_t unpack_w_data; - axi_in_b_chan_t unpack_b_data; - axi_in_r_chan_t unpack_r_data; - req_generic_t unpack_req_generic; - rsp_generic_t unpack_rsp_generic; + axi_in_aw_chan_t axi_unpack_aw; + axi_in_ar_chan_t axi_unpack_ar; + axi_in_w_chan_t axi_unpack_w; + axi_in_b_chan_t axi_unpack_b; + axi_in_r_chan_t axi_unpack_r; + floo_req_generic_flit_t unpack_req_generic; + floo_rsp_generic_flit_t unpack_rsp_generic; // Flit arbitration typedef enum logic {SelAw, SelW} aw_w_sel_e; @@ -146,12 +147,12 @@ module floo_axi_chimney ) i_aw_queue ( .clk_i, .rst_ni, - .data_i ( axi_in_req_i.aw ), - .valid_i ( axi_in_req_i.aw_valid ), - .ready_o ( axi_in_rsp_o.aw_ready ), - .data_o ( aw_queue ), - .valid_o ( aw_queue_valid_out ), - .ready_i ( aw_queue_ready_in ) + .data_i ( axi_in_req_i.aw ), + .valid_i ( axi_in_req_i.aw_valid ), + .ready_o ( axi_in_rsp_o.aw_ready ), + .data_o ( axi_aw_queue ), + .valid_o ( axi_aw_queue_valid_out ), + .ready_i ( axi_aw_queue_ready_in ) ); spill_register #( @@ -159,54 +160,56 @@ module floo_axi_chimney ) i_ar_queue ( .clk_i, .rst_ni, - .data_i ( axi_in_req_i.ar ), - .valid_i ( axi_in_req_i.ar_valid ), - .ready_o ( axi_in_rsp_o.ar_ready ), - .data_o ( ar_queue ), - .valid_o ( ar_queue_valid_out ), - .ready_i ( ar_queue_ready_in ) + .data_i ( axi_in_req_i.ar ), + .valid_i ( axi_in_req_i.ar_valid ), + .ready_o ( axi_in_rsp_o.ar_ready ), + .data_o ( axi_ar_queue ), + .valid_o ( axi_ar_queue_valid_out ), + .ready_i ( axi_ar_queue_ready_in ) ); end else begin : gen_no_ax_cuts - assign aw_queue = axi_in_req_i.aw; - assign aw_queue_valid_out = axi_in_req_i.aw_valid; - assign axi_in_rsp_o.aw_ready = aw_queue_ready_in; + assign axi_aw_queue = axi_in_req_i.aw; + assign axi_aw_queue_valid_out = axi_in_req_i.aw_valid; + assign axi_in_rsp_o.aw_ready = axi_aw_queue_ready_in; - assign ar_queue = axi_in_req_i.ar; - assign ar_queue_valid_out = axi_in_req_i.ar_valid; - assign axi_in_rsp_o.ar_ready = ar_queue_ready_in; + assign axi_ar_queue = axi_in_req_i.ar; + assign axi_ar_queue_valid_out = axi_in_req_i.ar_valid; + assign axi_in_rsp_o.ar_ready = axi_ar_queue_ready_in; end if (CutRsp) begin : gen_rsp_cuts spill_register #( - .T ( req_data_t ) + .T ( floo_req_chan_t ) ) i_data_req_arb ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .data_i ( req_i.data ), - .valid_i ( req_i.valid ), - .ready_o ( req_o.ready ), - .data_o ( req_in.data ), - .valid_o ( req_in.valid ), - .ready_i ( req_ready_out ) + .data_i ( floo_req_i.req ), + .valid_i ( floo_req_i.valid ), + .ready_o ( floo_req_o.ready ), + .data_o ( floo_req_in ), + .valid_o ( floo_req_in_valid ), + .ready_i ( floo_req_out_ready ) ); spill_register #( - .T ( rsp_data_t ) + .T ( floo_rsp_chan_t ) ) i_data_rsp_arb ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .data_i ( rsp_i.data ), - .valid_i ( rsp_i.valid ), - .ready_o ( rsp_o.ready ), - .data_o ( rsp_in.data ), - .valid_o ( rsp_in.valid ), - .ready_i ( rsp_ready_out ) + .data_i ( floo_rsp_i.rsp ), + .valid_i ( floo_rsp_i.valid ), + .ready_o ( floo_rsp_o.ready ), + .data_o ( floo_rsp_in ), + .valid_o ( floo_rsp_in_valid ), + .ready_i ( floo_rsp_out_ready ) ); end else begin : gen_no_rsp_cuts - assign req_in = req_i; - assign req_o.ready = req_ready_out; - assign rsp_in = rsp_i; - assign rsp_o.ready = rsp_ready_out; + assign floo_req_in = floo_req_i.req; + assign floo_req_in_valid = floo_req_i.valid; + assign floo_req_o.ready = floo_req_out_ready; + assign floo_rsp_in = floo_rsp_i.rsp; + assign floo_rsp_in_valid = floo_rsp_i.valid; + assign floo_rsp_o.ready = floo_rsp_out_ready; end /////////////////////// @@ -214,7 +217,7 @@ module floo_axi_chimney /////////////////////// // AW/B RoB - axi_in_b_chan_t b_rob_out, b_rob_in; + axi_in_b_chan_t axi_b_rob_out, axi_b_rob_in; logic aw_rob_req_out; rob_idx_t aw_rob_idx_out; logic aw_rob_valid_in, aw_rob_ready_out; @@ -223,7 +226,7 @@ module floo_axi_chimney logic b_rob_valid_out, b_rob_ready_in; // AR/R RoB - axi_in_r_chan_t r_rob_out, r_rob_in; + axi_in_r_chan_t axi_r_rob_out, axi_r_rob_in; logic ar_rob_req_out; rob_idx_t ar_rob_idx_out; logic ar_rob_valid_out, ar_rob_ready_in; @@ -232,13 +235,13 @@ module floo_axi_chimney if (AtopSupport) begin : gen_atop_support // Bypass AW/B RoB - assign aw_rob_valid_in = aw_queue_valid_out && (aw_queue.atop == axi_pkg::ATOP_NONE); - assign aw_queue_ready_in = (aw_queue.atop == axi_pkg::ATOP_NONE)? + assign aw_rob_valid_in = axi_aw_queue_valid_out && (axi_aw_queue.atop == axi_pkg::ATOP_NONE); + assign axi_aw_queue_ready_in = (axi_aw_queue.atop == axi_pkg::ATOP_NONE)? aw_rob_ready_out : aw_rob_ready_in; end else begin : gen_no_atop_support - assign aw_rob_valid_in = aw_queue_valid_out; - assign aw_queue_ready_in = aw_rob_ready_out; - `ASSERT(NoAtopSupport, !(aw_queue_valid_out && (aw_queue.atop != axi_pkg::ATOP_NONE))) + assign aw_rob_valid_in = axi_aw_queue_valid_out; + assign axi_aw_queue_ready_in = aw_rob_ready_out; + `ASSERT(NoAtopSupport, !(axi_aw_queue_valid_out && (axi_aw_queue.atop != axi_pkg::ATOP_NONE))) end floo_simple_rob #( @@ -257,21 +260,21 @@ module floo_axi_chimney .sram_cfg_i, .ax_valid_i ( aw_rob_valid_in ), .ax_ready_o ( aw_rob_ready_out ), - .ax_len_i ( aw_queue.len ), - .ax_dest_i ( dst_id[AxiInAw] ), + .ax_len_i ( axi_aw_queue.len ), + .ax_dest_i ( dst_id[AxiAw] ), .ax_valid_o ( aw_rob_valid_out ), .ax_ready_i ( aw_rob_ready_in ), .ax_rob_req_o ( aw_rob_req_out ), .ax_rob_idx_o ( aw_rob_idx_out ), .rsp_valid_i ( b_rob_valid_in ), .rsp_ready_o ( b_rob_ready_out ), - .rsp_i ( b_rob_in ), - .rsp_rob_req_i ( rsp_in.data.axi_in_b.rob_req ), - .rsp_rob_idx_i ( rsp_in.data.axi_in_b.rob_idx ), - .rsp_last_i ( rsp_in.data.axi_in_b.last ), + .rsp_i ( axi_b_rob_in ), + .rsp_rob_req_i ( floo_rsp_in.axi_b.hdr.rob_req ), + .rsp_rob_idx_i ( floo_rsp_in.axi_b.hdr.rob_idx ), + .rsp_last_i ( floo_rsp_in.axi_b.hdr.last ), .rsp_valid_o ( b_rob_valid_out ), .rsp_ready_i ( b_rob_ready_in ), - .rsp_o ( b_rob_out ) + .rsp_o ( axi_b_rob_out ) ); typedef logic [AxiInDataWidth-1:0] r_rob_data_t; @@ -298,23 +301,23 @@ module floo_axi_chimney .clk_i, .rst_ni, .sram_cfg_i, - .ax_valid_i ( ar_queue_valid_out ), - .ax_ready_o ( ar_queue_ready_in ), - .ax_len_i ( ar_queue.len ), - .ax_dest_i ( dst_id[AxiInAr] ), + .ax_valid_i ( axi_ar_queue_valid_out ), + .ax_ready_o ( axi_ar_queue_ready_in ), + .ax_len_i ( axi_ar_queue.len ), + .ax_dest_i ( dst_id[AxiAr] ), .ax_valid_o ( ar_rob_valid_out ), .ax_ready_i ( ar_rob_ready_in ), .ax_rob_req_o ( ar_rob_req_out ), .ax_rob_idx_o ( ar_rob_idx_out ), .rsp_valid_i ( r_rob_valid_in ), .rsp_ready_o ( r_rob_ready_out ), - .rsp_i ( r_rob_in ), - .rsp_rob_req_i ( rsp_in.data.axi_in_r.rob_req ), - .rsp_rob_idx_i ( rsp_in.data.axi_in_r.rob_idx ), - .rsp_last_i ( rsp_in.data.axi_in_r.last ), + .rsp_i ( axi_r_rob_in ), + .rsp_rob_req_i ( floo_rsp_in.axi_r.hdr.rob_req ), + .rsp_rob_idx_i ( floo_rsp_in.axi_r.hdr.rob_idx ), + .rsp_last_i ( floo_rsp_in.axi_r.hdr.last ), .rsp_valid_o ( r_rob_valid_out ), .rsp_ready_i ( r_rob_ready_in ), - .rsp_o ( r_rob_out ) + .rsp_o ( axi_r_rob_out ) ); end else begin : gen_rob floo_rob #( @@ -332,24 +335,24 @@ module floo_axi_chimney .clk_i, .rst_ni, .sram_cfg_i, - .ax_valid_i ( ar_queue_valid_out ), - .ax_ready_o ( ar_queue_ready_in ), - .ax_len_i ( ar_queue.len ), - .ax_id_i ( ar_queue.id ), - .ax_dest_i ( dst_id[AxiInAr] ), + .ax_valid_i ( axi_ar_queue_valid_out ), + .ax_ready_o ( axi_ar_queue_ready_in ), + .ax_len_i ( axi_ar_queue.len ), + .ax_id_i ( axi_ar_queue.id ), + .ax_dest_i ( dst_id[AxiAr] ), .ax_valid_o ( ar_rob_valid_out ), .ax_ready_i ( ar_rob_ready_in ), .ax_rob_req_o ( ar_rob_req_out ), .ax_rob_idx_o ( ar_rob_idx_out ), .rsp_valid_i ( r_rob_valid_in ), .rsp_ready_o ( r_rob_ready_out ), - .rsp_i ( r_rob_in ), - .rsp_rob_req_i ( rsp_in.data.axi_in_r.rob_req ), - .rsp_rob_idx_i ( rsp_in.data.axi_in_r.rob_idx ), - .rsp_last_i ( rsp_in.data.axi_in_r.last ), + .rsp_i ( axi_r_rob_in ), + .rsp_rob_req_i ( floo_rsp_in.axi_r.hdr.rob_req ), + .rsp_rob_idx_i ( floo_rsp_in.axi_r.hdr.rob_idx ), + .rsp_last_i ( floo_rsp_in.axi_r.hdr.last ), .rsp_valid_o ( r_rob_valid_out ), .rsp_ready_i ( r_rob_ready_in ), - .rsp_o ( r_rob_out ) + .rsp_o ( axi_r_rob_out ) ); end @@ -361,27 +364,27 @@ module floo_axi_chimney if (RouteAlgo == XYRouting) begin : gen_xy_routing xy_id_t aw_xy_id_q, aw_xy_id, ar_xy_id; assign src_id = xy_id_i; - assign aw_xy_id.x = aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; - assign aw_xy_id.y = aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; - assign ar_xy_id.x = ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; - assign ar_xy_id.y = ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; - assign dst_id[AxiInAw] = aw_xy_id; - assign dst_id[AxiInAr] = ar_xy_id; - assign dst_id[AxiInW] = aw_xy_id_q; - assign dst_id[AxiInB] = aw_out_data_out.src_id; - assign dst_id[AxiInR] = ar_out_data_out.src_id; - `FFL(aw_xy_id_q, aw_xy_id, aw_queue_valid_out && aw_queue_ready_in, '0) + assign aw_xy_id.x = axi_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; + assign aw_xy_id.y = axi_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; + assign ar_xy_id.x = axi_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; + assign ar_xy_id.y = axi_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; + assign dst_id[AxiAw] = aw_xy_id; + assign dst_id[AxiAr] = ar_xy_id; + assign dst_id[AxiW] = aw_xy_id_q; + assign dst_id[AxiB] = aw_out_data_out.src_id; + assign dst_id[AxiR] = ar_out_data_out.src_id; + `FFL(aw_xy_id_q, aw_xy_id, axi_aw_queue_valid_out && axi_aw_queue_ready_in, '0) end else if (RouteAlgo == IdTable) begin : gen_id_table_routing id_t aw_id_q, aw_id, ar_id; assign src_id = id_i; - assign aw_id = aw_queue.addr[IdTableAddrOffset+:$bits(id_i)]; - assign ar_id = ar_queue.addr[IdTableAddrOffset+:$bits(id_i)]; - assign dst_id[AxiInAw] = aw_id; - assign dst_id[AxiInAr] = ar_id; - assign dst_id[AxiInW] = aw_id_q; - assign dst_id[AxiInB] = aw_out_data_out.src_id; - assign dst_id[AxiInR] = ar_out_data_out.src_id; - `FFL(aw_id_q, aw_id, aw_queue_valid_out && aw_queue_ready_in, '0) + assign aw_id = axi_aw_queue.addr[IdTableAddrOffset+:$bits(id_i)]; + assign ar_id = axi_ar_queue.addr[IdTableAddrOffset+:$bits(id_i)]; + assign dst_id[AxiAw] = aw_id; + assign dst_id[AxiAr] = ar_id; + assign dst_id[AxiW] = aw_id_q; + assign dst_id[AxiB] = aw_out_data_out.src_id; + assign dst_id[AxiR] = ar_out_data_out.src_id; + `FFL(aw_id_q, aw_id, axi_aw_queue_valid_out && axi_aw_queue_ready_in, '0) end else begin : gen_no_routing // TODO: Implement other routing algorithms $fatal(1, "Routing algorithm not implemented"); @@ -392,123 +395,123 @@ module floo_axi_chimney /////////////////// always_comb begin - aw_data = '0; - aw_data.rob_req = aw_rob_req_out; - aw_data.rob_idx = aw_rob_idx_out; - aw_data.dst_id = dst_id[AxiInAw]; - aw_data.src_id = src_id; - aw_data.last = 1'b1; - aw_data.axi_ch = AxiInAw; - aw_data.aw = aw_queue; - aw_data.atop = aw_queue.atop != axi_pkg::ATOP_NONE; + floo_axi_aw = '0; + floo_axi_aw.hdr.rob_req = aw_rob_req_out; + floo_axi_aw.hdr.rob_idx = aw_rob_idx_out; + floo_axi_aw.hdr.dst_id = dst_id[AxiAw]; + floo_axi_aw.hdr.src_id = src_id; + floo_axi_aw.hdr.last = 1'b1; + floo_axi_aw.hdr.axi_ch = AxiAw; + floo_axi_aw.hdr.atop = axi_aw_queue.atop != axi_pkg::ATOP_NONE; + floo_axi_aw.aw = axi_aw_queue; end always_comb begin - w_data = '0; - w_data.rob_req = aw_rob_req_out; - w_data.rob_idx = aw_rob_idx_out; - w_data.dst_id = dst_id[AxiInW]; - w_data.src_id = src_id; - w_data.last = axi_in_req_i.w.last; - w_data.axi_ch = AxiInW; - w_data.w = axi_in_req_i.w; + floo_axi_w = '0; + floo_axi_w.hdr.rob_req = aw_rob_req_out; + floo_axi_w.hdr.rob_idx = aw_rob_idx_out; + floo_axi_w.hdr.dst_id = dst_id[AxiW]; + floo_axi_w.hdr.src_id = src_id; + floo_axi_w.hdr.last = axi_in_req_i.w.last; + floo_axi_w.hdr.axi_ch = AxiW; + floo_axi_w.w = axi_in_req_i.w; end always_comb begin - ar_data = '0; - ar_data.rob_req = ar_rob_req_out; - ar_data.rob_idx = ar_rob_idx_out; - ar_data.dst_id = dst_id[AxiInAr]; - ar_data.src_id = src_id; - ar_data.last = 1'b1; - ar_data.axi_ch = AxiInAr; - ar_data.ar = ar_queue; + floo_axi_ar = '0; + floo_axi_ar.hdr.rob_req = ar_rob_req_out; + floo_axi_ar.hdr.rob_idx = ar_rob_idx_out; + floo_axi_ar.hdr.dst_id = dst_id[AxiAr]; + floo_axi_ar.hdr.src_id = src_id; + floo_axi_ar.hdr.last = 1'b1; + floo_axi_ar.hdr.axi_ch = AxiAr; + floo_axi_ar.ar = axi_ar_queue; end always_comb begin - b_data = '0; - b_data.rob_req = aw_out_data_out.rob_req; - b_data.rob_idx = aw_out_data_out.rob_idx; - b_data.dst_id = aw_out_data_out.src_id; - b_data.src_id = src_id; - b_data.last = 1'b1; - b_data.axi_ch = AxiInB; - b_data.b = axi_out_rsp_id_mapped.b; - b_data.b.id = aw_out_data_out.id; - b_data.atop = aw_out_data_out.atop; + floo_axi_b = '0; + floo_axi_b.hdr.rob_req = aw_out_data_out.rob_req; + floo_axi_b.hdr.rob_idx = aw_out_data_out.rob_idx; + floo_axi_b.hdr.dst_id = aw_out_data_out.src_id; + floo_axi_b.hdr.src_id = src_id; + floo_axi_b.hdr.last = 1'b1; + floo_axi_b.hdr.axi_ch = AxiB; + floo_axi_b.hdr.atop = aw_out_data_out.atop; + floo_axi_b.b = axi_out_rsp_id_mapped.b; + floo_axi_b.b.id = aw_out_data_out.id; end always_comb begin - r_data = '0; - r_data.rob_req = ar_out_data_out.rob_req; - r_data.rob_idx = ar_out_data_out.rob_idx; - r_data.dst_id = ar_out_data_out.src_id; - r_data.src_id = src_id; - r_data.last = axi_out_rsp_i.r.last; - r_data.axi_ch = AxiInR; - r_data.r = axi_out_rsp_id_mapped.r; - r_data.r.id = ar_out_data_out.id; - r_data.atop = ar_out_data_out.atop; + floo_axi_r = '0; + floo_axi_r.hdr.rob_req = ar_out_data_out.rob_req; + floo_axi_r.hdr.rob_idx = ar_out_data_out.rob_idx; + floo_axi_r.hdr.dst_id = ar_out_data_out.src_id; + floo_axi_r.hdr.src_id = src_id; + floo_axi_r.hdr.last = axi_out_rsp_i.r.last; + floo_axi_r.hdr.axi_ch = AxiR; + floo_axi_r.hdr.atop = ar_out_data_out.atop; + floo_axi_r.r = axi_out_rsp_id_mapped.r; + floo_axi_r.r.id = ar_out_data_out.id; end always_comb begin aw_w_sel_d = aw_w_sel_q; - if (aw_queue_valid_out && aw_queue_ready_in) aw_w_sel_d = SelW; + if (axi_aw_queue_valid_out && axi_aw_queue_ready_in) aw_w_sel_d = SelW; if (axi_in_req_i.w_valid && axi_in_rsp_o.w_ready && axi_in_req_i.w.last) aw_w_sel_d = SelAw; end `FF(aw_w_sel_q, aw_w_sel_d, SelAw) - assign req_data_arb_req_in[AxiInAw] = (aw_w_sel_q == SelAw) && (aw_rob_valid_out || - ((aw_queue.atop != axi_pkg::ATOP_NONE) && - aw_queue_valid_out)); - assign req_data_arb_req_in[AxiInW] = (aw_w_sel_q == SelW) && axi_in_req_i.w_valid; - assign req_data_arb_req_in[AxiInAr] = ar_rob_valid_out; - assign rsp_data_arb_req_in[AxiInB] = axi_out_rsp_i.b_valid; - assign rsp_data_arb_req_in[AxiInR] = axi_out_rsp_i.r_valid; - - assign aw_rob_ready_in = req_data_arb_gnt_out[AxiInAw] && (aw_w_sel_q == SelAw); - assign axi_in_rsp_o.w_ready = req_data_arb_gnt_out[AxiInW] && (aw_w_sel_q == SelW); - assign ar_rob_ready_in = req_data_arb_gnt_out[AxiInAr]; - assign axi_out_req_id_mapped.b_ready = rsp_data_arb_gnt_out[AxiInB]; - assign axi_out_req_id_mapped.r_ready = rsp_data_arb_gnt_out[AxiInR]; - - assign req_data_arb_data_in[AxiInAw] = aw_data; - assign req_data_arb_data_in[AxiInW] = w_data; - assign req_data_arb_data_in[AxiInAr] = ar_data; - assign rsp_data_arb_data_in[AxiInB] = b_data; - assign rsp_data_arb_data_in[AxiInR] = r_data; + assign floo_req_arb_req_in[AxiAw] = (aw_w_sel_q == SelAw) && (aw_rob_valid_out || + ((axi_aw_queue.atop != axi_pkg::ATOP_NONE) && + axi_aw_queue_valid_out)); + assign floo_req_arb_req_in[AxiW] = (aw_w_sel_q == SelW) && axi_in_req_i.w_valid; + assign floo_req_arb_req_in[AxiAr] = ar_rob_valid_out; + assign floo_rsp_arb_req_in[AxiB] = axi_out_rsp_i.b_valid; + assign floo_rsp_arb_req_in[AxiR] = axi_out_rsp_i.r_valid; + + assign aw_rob_ready_in = floo_req_arb_gnt_out[AxiAw] && (aw_w_sel_q == SelAw); + assign axi_in_rsp_o.w_ready = floo_req_arb_gnt_out[AxiW] && (aw_w_sel_q == SelW); + assign ar_rob_ready_in = floo_req_arb_gnt_out[AxiAr]; + assign axi_out_req_id_mapped.b_ready = floo_rsp_arb_gnt_out[AxiB]; + assign axi_out_req_id_mapped.r_ready = floo_rsp_arb_gnt_out[AxiR]; + + assign floo_req_arb_in[AxiAw] = floo_axi_aw; + assign floo_req_arb_in[AxiW] = floo_axi_w; + assign floo_req_arb_in[AxiAr] = floo_axi_ar; + assign floo_rsp_arb_in[AxiB] = floo_axi_b; + assign floo_rsp_arb_in[AxiR] = floo_axi_r; /////////////////////// // FLIT ARBITRATION // /////////////////////// floo_wormhole_arbiter #( - .NumRoutes ( NumVirtPerPhys[PhysReq] ), - .flit_t ( req_generic_t ) + .NumRoutes ( 3 ), + .flit_t ( floo_req_generic_flit_t ) ) i_req_wormhole_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( req_data_arb_req_in ), - .data_i ( req_data_arb_data_in ), - .ready_o ( req_data_arb_gnt_out ), - .data_o ( req_o.data ), - .ready_i ( req_i.ready ), - .valid_o ( req_o.valid ) + .valid_i ( floo_req_arb_req_in ), + .data_i ( floo_req_arb_in ), + .ready_o ( floo_req_arb_gnt_out ), + .data_o ( floo_req_o.req ), + .ready_i ( floo_req_i.ready ), + .valid_o ( floo_req_o.valid ) ); floo_wormhole_arbiter #( - .NumRoutes ( NumVirtPerPhys[PhysRsp] ), - .flit_t ( rsp_generic_t ) + .NumRoutes ( 2 ), + .flit_t ( floo_rsp_generic_flit_t ) ) i_rsp_wormhole_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .valid_i ( rsp_data_arb_req_in ), - .data_i ( rsp_data_arb_data_in ), - .ready_o ( rsp_data_arb_gnt_out ), - .data_o ( rsp_o.data ), - .ready_i ( rsp_i.ready ), - .valid_o ( rsp_o.valid ) + .valid_i ( floo_rsp_arb_req_in ), + .data_i ( floo_rsp_arb_in ), + .ready_o ( floo_rsp_arb_gnt_out ), + .data_o ( floo_rsp_o.rsp ), + .ready_i ( floo_rsp_i.ready ), + .valid_o ( floo_rsp_o.valid ) ); //////////////////// @@ -519,61 +522,61 @@ module floo_axi_chimney logic b_sel_atop, r_sel_atop; logic b_rob_pending_q, r_rob_pending_q; - assign is_atop_b_rsp = AtopSupport && axi_valid_in[AxiInB] && unpack_rsp_generic.atop; - assign is_atop_r_rsp = AtopSupport && axi_valid_in[AxiInR] && unpack_rsp_generic.atop; + assign is_atop_b_rsp = AtopSupport && axi_valid_in[AxiB] && unpack_rsp_generic.hdr.atop; + assign is_atop_r_rsp = AtopSupport && axi_valid_in[AxiR] && unpack_rsp_generic.hdr.atop; assign b_sel_atop = is_atop_b_rsp && !b_rob_pending_q; assign r_sel_atop = is_atop_r_rsp && !r_rob_pending_q; - assign unpack_aw_data = req_in.data.axi_in_aw.aw; - assign unpack_w_data = req_in.data.axi_in_w.w; - assign unpack_ar_data = req_in.data.axi_in_ar.ar; - assign unpack_r_data = rsp_in.data.axi_in_r.r; - assign unpack_b_data = rsp_in.data.axi_in_b.b; - assign unpack_req_generic = req_in.data.gen; - assign unpack_rsp_generic = rsp_in.data.gen; - - assign axi_valid_in[AxiInAw] = req_in.valid && (unpack_req_generic.axi_ch == AxiInAw); - assign axi_valid_in[AxiInW] = req_in.valid && (unpack_req_generic.axi_ch == AxiInW); - assign axi_valid_in[AxiInAr] = req_in.valid && (unpack_req_generic.axi_ch == AxiInAr); - assign axi_valid_in[AxiInB] = rsp_in.valid && (unpack_rsp_generic.axi_ch == AxiInB); - assign axi_valid_in[AxiInR] = rsp_in.valid && (unpack_rsp_generic.axi_ch == AxiInR); - - assign axi_ready_out[AxiInAw] = axi_out_rsp_i.aw_ready && !aw_out_full; - assign axi_ready_out[AxiInW] = axi_out_rsp_i.w_ready; - assign axi_ready_out[AxiInAr] = axi_out_rsp_i.ar_ready && !ar_out_full; - assign axi_ready_out[AxiInB] = b_rob_ready_out || b_sel_atop && axi_in_req_i.b_ready; - assign axi_ready_out[AxiInR] = r_rob_ready_out || r_sel_atop && axi_in_req_i.r_ready; - - assign req_ready_out = axi_ready_out[unpack_req_generic.axi_ch]; - assign rsp_ready_out = axi_ready_out[unpack_rsp_generic.axi_ch]; + assign axi_unpack_aw = floo_req_in.axi_aw.aw; + assign axi_unpack_w = floo_req_in.axi_w.w; + assign axi_unpack_ar = floo_req_in.axi_ar.ar; + assign axi_unpack_r = floo_rsp_in.axi_r.r; + assign axi_unpack_b = floo_rsp_in.axi_b.b; + assign unpack_req_generic = floo_req_in.generic; + assign unpack_rsp_generic = floo_rsp_in.generic; + + assign axi_valid_in[AxiAw] = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAw); + assign axi_valid_in[AxiW] = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiW); + assign axi_valid_in[AxiAr] = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAr); + assign axi_valid_in[AxiB] = floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiB); + assign axi_valid_in[AxiR] = floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiR); + + assign axi_ready_out[AxiAw] = axi_out_rsp_i.aw_ready && !aw_out_full; + assign axi_ready_out[AxiW] = axi_out_rsp_i.w_ready; + assign axi_ready_out[AxiAr] = axi_out_rsp_i.ar_ready && !ar_out_full; + assign axi_ready_out[AxiB] = b_rob_ready_out || b_sel_atop && axi_in_req_i.b_ready; + assign axi_ready_out[AxiR] = r_rob_ready_out || r_sel_atop && axi_in_req_i.r_ready; + + assign floo_req_out_ready = axi_ready_out[unpack_req_generic.hdr.axi_ch]; + assign floo_rsp_out_ready = axi_ready_out[unpack_rsp_generic.hdr.axi_ch]; ///////////////////////////// // AXI req/rsp generation // //////////////////////////// - assign axi_out_req_id_mapped.aw_valid = axi_valid_in[AxiInAw] && !aw_out_full; - assign axi_out_req_id_mapped.w_valid = axi_valid_in[AxiInW]; - assign axi_out_req_id_mapped.ar_valid = axi_valid_in[AxiInAr] && !ar_out_full; - assign b_rob_valid_in = axi_valid_in[AxiInB] && !is_atop_b_rsp; - assign r_rob_valid_in = axi_valid_in[AxiInR] && !is_atop_r_rsp; + assign axi_out_req_id_mapped.aw_valid = axi_valid_in[AxiAw] && !aw_out_full; + assign axi_out_req_id_mapped.w_valid = axi_valid_in[AxiW]; + assign axi_out_req_id_mapped.ar_valid = axi_valid_in[AxiAr] && !ar_out_full; + assign b_rob_valid_in = axi_valid_in[AxiB] && !is_atop_b_rsp; + assign r_rob_valid_in = axi_valid_in[AxiR] && !is_atop_r_rsp; assign axi_in_rsp_o.b_valid = b_rob_valid_out || is_atop_b_rsp; assign axi_in_rsp_o.r_valid = r_rob_valid_out || is_atop_r_rsp; assign b_rob_ready_in = axi_in_req_i.b_ready && !b_sel_atop; assign r_rob_ready_in = axi_in_req_i.r_ready && !r_sel_atop; - assign axi_out_req_id_mapped.aw = aw_id_mod; - assign axi_out_req_id_mapped.w = unpack_w_data; - assign axi_out_req_id_mapped.ar = ar_id_mod; - assign b_rob_in = unpack_b_data; - assign r_rob_in = unpack_r_data; - assign axi_in_rsp_o.b = (b_sel_atop)? unpack_b_data : b_rob_out; - assign axi_in_rsp_o.r = (r_sel_atop)? unpack_r_data : r_rob_out; + assign axi_out_req_id_mapped.aw = axi_aw_id_mod; + assign axi_out_req_id_mapped.w = axi_unpack_w; + assign axi_out_req_id_mapped.ar = axi_ar_id_mod; + assign axi_b_rob_in = axi_unpack_b; + assign axi_r_rob_in = axi_unpack_r; + assign axi_in_rsp_o.b = (b_sel_atop)? axi_unpack_b : axi_b_rob_out; + assign axi_in_rsp_o.r = (r_sel_atop)? axi_unpack_r : axi_r_rob_out; logic is_atop, atop_has_r_rsp; - assign is_atop = AtopSupport && axi_valid_in[AxiInAw] && - (unpack_aw_data.atop != axi_pkg::ATOP_NONE); - assign atop_has_r_rsp = AtopSupport && axi_valid_in[AxiInAw] && - unpack_aw_data.atop[axi_pkg::ATOP_R_RESP]; + assign is_atop = AtopSupport && axi_valid_in[AxiAw] && + (axi_unpack_aw.atop != axi_pkg::ATOP_NONE); + assign atop_has_r_rsp = AtopSupport && axi_valid_in[AxiAw] && + axi_unpack_aw.atop[axi_pkg::ATOP_R_RESP]; assign aw_out_push = axi_out_req_o.aw_valid && axi_out_rsp_i.aw_ready; assign ar_out_push = axi_out_req_o.ar_valid && axi_out_rsp_i.ar_ready || @@ -583,18 +586,18 @@ module floo_axi_chimney assign ar_out_pop = axi_out_rsp_i.r_valid && axi_out_req_o.r_ready && axi_out_rsp_i.r.last; assign aw_out_data_in = '{ - id: unpack_aw_data.id, - rob_req: unpack_req_generic.rob_req, - rob_idx: unpack_req_generic.rob_idx, - src_id: unpack_req_generic.src_id, - atop: unpack_req_generic.atop + id: axi_unpack_aw.id, + rob_req: unpack_req_generic.hdr.rob_req, + rob_idx: unpack_req_generic.hdr.rob_idx, + src_id: unpack_req_generic.hdr.src_id, + atop: unpack_req_generic.hdr.atop }; assign ar_out_data_in = '{ - id: (is_atop && atop_has_r_rsp)? unpack_aw_data.id : unpack_ar_data.id, - rob_req: unpack_req_generic.rob_req, - rob_idx: unpack_req_generic.rob_idx, - src_id: unpack_req_generic.src_id, - atop: unpack_req_generic.atop + id: (is_atop && atop_has_r_rsp)? axi_unpack_aw.id : axi_unpack_ar.id, + rob_req: unpack_req_generic.hdr.rob_req, + rob_idx: unpack_req_generic.hdr.rob_idx, + src_id: unpack_req_generic.hdr.src_id, + atop: unpack_req_generic.hdr.atop }; floo_meta_buffer #( @@ -644,10 +647,10 @@ module floo_axi_chimney always_comb begin // Assign the outgoing AX an unique ID - aw_id_mod = unpack_aw_data; - ar_id_mod = unpack_ar_data; - aw_id_mod.id = aw_out_id; - ar_id_mod.id = ar_out_id; + axi_aw_id_mod = axi_unpack_aw; + axi_ar_id_mod = axi_unpack_ar; + axi_aw_id_mod.id = aw_out_id; + axi_ar_id_mod.id = ar_out_id; end // Registers diff --git a/src/floo_axi_flit_pkg.sv b/src/floo_axi_flit_pkg.sv deleted file mode 100644 index b76f3f01..00000000 --- a/src/floo_axi_flit_pkg.sv +++ /dev/null @@ -1,224 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// This file is auto-generated. Do not edit! Edit the template file instead - - -`include "axi/typedef.svh" - -package floo_axi_flit_pkg; - - localparam int unsigned NumPhysChannels = 2; - localparam int unsigned NumAxiChannels = 5; - - //////////////////////// - // AXI Parameters // - //////////////////////// - - localparam int unsigned AxiInAddrWidth = 32; - localparam int unsigned AxiInDataWidth = 64; - localparam int unsigned AxiInIdWidth = 3; - localparam int unsigned AxiInUserWidth = 1; - - localparam int unsigned AxiOutAddrWidth = 32; - localparam int unsigned AxiOutDataWidth = 64; - localparam int unsigned AxiOutIdWidth = 3; - localparam int unsigned AxiOutUserWidth = 1; - - - typedef logic [31:0] axi_in_addr_t; - typedef logic [63:0] axi_in_data_t; - typedef logic [7:0] axi_in_strb_t; - typedef logic [2:0] axi_in_id_t; - typedef logic [0:0] axi_in_user_t; - - typedef logic [31:0] axi_out_addr_t; - typedef logic [63:0] axi_out_data_t; - typedef logic [7:0] axi_out_strb_t; - typedef logic [2:0] axi_out_id_t; - typedef logic [0:0] axi_out_user_t; - - - `AXI_TYPEDEF_ALL(axi_in, axi_in_addr_t, axi_in_id_t, axi_in_data_t, axi_in_strb_t, axi_in_user_t) - `AXI_TYPEDEF_ALL(axi_out, axi_out_addr_t, axi_out_id_t, axi_out_data_t, axi_out_strb_t, - axi_out_user_t) - - ////////////////////// - // AXI Channels // - ////////////////////// - - typedef enum logic [2:0] { - AxiInAw, - AxiInW, - AxiInAr, - AxiInB, - AxiInR - } axi_ch_e; - - /////////////////////////// - // Physical Channels // - /////////////////////////// - - typedef enum int { - PhysReq, - PhysRsp - } phys_chan_e; - - ///////////////////////// - // Channel Mapping // - ///////////////////////// - - localparam int NumVirtPerPhys[NumPhysChannels] = '{3, 2}; - - localparam int PhysChanMapping[NumAxiChannels] = '{PhysReq, PhysReq, PhysReq, PhysRsp, PhysRsp}; - - localparam int VirtChanMapping[NumPhysChannels][3] = '{ - '{AxiInAw, AxiInW, AxiInAr}, - '{AxiInB, AxiInR, 0} - }; - - /////////////////////// - // Meta Typedefs // - /////////////////////// - - typedef logic [0:0] rob_req_t; - typedef logic [5:0] rob_idx_t; - typedef logic [5:0] dst_id_t; - typedef logic [5:0] src_id_t; - typedef logic [0:0] last_t; - typedef logic [0:0] atop_t; - typedef logic [2:0] axi_ch_t; - - //////////////////////////// - // AXI Packet Structs // - //////////////////////////// - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - axi_in_aw_chan_t aw; - logic [2:0] rsvd; - } axi_in_aw_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - axi_in_w_chan_t w; - } axi_in_w_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - axi_in_ar_chan_t ar; - logic [8:0] rsvd; - } axi_in_ar_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - logic [73:0] rsvd; - } req_generic_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - axi_in_b_chan_t b; - logic [64:0] rsvd; - } axi_in_b_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - axi_in_r_chan_t r; - } axi_in_r_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - logic [70:0] rsvd; - } rsp_generic_t; - - - - /////////////////////////// - // AXI Packet Unions // - /////////////////////////// - - typedef union packed { - axi_in_aw_data_t axi_in_aw; - axi_in_w_data_t axi_in_w; - axi_in_ar_data_t axi_in_ar; - req_generic_t gen; - } req_data_t; - - typedef union packed { - axi_in_b_data_t axi_in_b; - axi_in_r_data_t axi_in_r; - rsp_generic_t gen; - } rsp_data_t; - - - /////////////////////////////// - // Physical Flit Structs // - /////////////////////////////// - - typedef struct packed { - logic valid; - logic ready; - req_data_t data; - } req_flit_t; - - typedef struct packed { - logic valid; - logic ready; - rsp_data_t data; - } rsp_flit_t; - - - ////////////////////////////// - // Phys Packeed Structs // - ////////////////////////////// - - typedef struct packed { - req_flit_t req; - rsp_flit_t rsp; - } flit_t; - -endpackage - diff --git a/src/floo_axi_pkg.sv b/src/floo_axi_pkg.sv new file mode 100644 index 00000000..27ceb1cd --- /dev/null +++ b/src/floo_axi_pkg.sv @@ -0,0 +1,145 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// This file is auto-generated. Do not edit! Edit the template file instead + + +`include "axi/typedef.svh" + +package floo_axi_pkg; + + //////////////////////// + // AXI Parameters // + //////////////////////// + + localparam int unsigned AxiInAddrWidth = 32; + localparam int unsigned AxiInDataWidth = 64; + localparam int unsigned AxiInIdWidth = 3; + localparam int unsigned AxiInUserWidth = 1; + + localparam int unsigned AxiOutAddrWidth = 32; + localparam int unsigned AxiOutDataWidth = 64; + localparam int unsigned AxiOutIdWidth = 3; + localparam int unsigned AxiOutUserWidth = 1; + + typedef logic [AxiInAddrWidth-1:0] axi_in_addr_t; + typedef logic [AxiInDataWidth-1:0] axi_in_data_t; + typedef logic [AxiInDataWidth/8-1:0] axi_in_strb_t; + typedef logic [AxiInIdWidth-1:0] axi_in_id_t; + typedef logic [AxiInUserWidth-1:0] axi_in_user_t; + + typedef logic [AxiOutAddrWidth-1:0] axi_out_addr_t; + typedef logic [AxiOutDataWidth-1:0] axi_out_data_t; + typedef logic [AxiOutDataWidth/8-1:0] axi_out_strb_t; + typedef logic [AxiOutIdWidth-1:0] axi_out_id_t; + typedef logic [AxiOutUserWidth-1:0] axi_out_user_t; + + `AXI_TYPEDEF_ALL_CT(axi_in, axi_in_req_t, axi_in_rsp_t, axi_in_addr_t, axi_in_id_t, axi_in_data_t, + axi_in_strb_t, axi_in_user_t) + `AXI_TYPEDEF_ALL_CT(axi_out, axi_out_req_t, axi_out_rsp_t, axi_out_addr_t, axi_out_id_t, + axi_out_data_t, axi_out_strb_t, axi_out_user_t) + + ///////////////////////// + // Header Typedefs // + ///////////////////////// + + typedef logic [5:0] rob_idx_t; + typedef logic [5:0] dst_id_t; + typedef logic [5:0] src_id_t; + typedef logic [2:0] axi_ch_t; + + typedef struct packed { + logic rob_req; + rob_idx_t rob_idx; + dst_id_t dst_id; + src_id_t src_id; + logic last; + logic atop; + axi_ch_t axi_ch; + } hdr_t; + + + //////////////////////////// + // AXI Flits Typedefs // + //////////////////////////// + + typedef struct packed { + hdr_t hdr; + axi_in_aw_chan_t aw; + logic [2:0] rsvd; + } floo_axi_aw_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_in_w_chan_t w; + } floo_axi_w_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_in_b_chan_t b; + logic [64:0] rsvd; + } floo_axi_b_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_in_ar_chan_t ar; + logic [8:0] rsvd; + } floo_axi_ar_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_in_r_chan_t r; + } floo_axi_r_flit_t; + + + //////////////////////////////// + // Generic Flits Typedefs // + //////////////////////////////// + + typedef struct packed { + hdr_t hdr; + logic [73:0] rsvd; + } floo_req_generic_flit_t; + + typedef struct packed { + hdr_t hdr; + logic [70:0] rsvd; + } floo_rsp_generic_flit_t; + + + ////////////////////////// + // Channel Typedefs // + ////////////////////////// + + typedef union packed { + floo_axi_aw_flit_t axi_aw; + floo_axi_w_flit_t axi_w; + floo_axi_ar_flit_t axi_ar; + floo_req_generic_flit_t generic; + } floo_req_chan_t; + + typedef union packed { + floo_axi_b_flit_t axi_b; + floo_axi_r_flit_t axi_r; + floo_rsp_generic_flit_t generic; + } floo_rsp_chan_t; + + /////////////////////// + // Link Typedefs // + /////////////////////// + + typedef struct packed { + logic valid; + logic ready; + floo_req_chan_t req; + } floo_req_t; + + typedef struct packed { + logic valid; + logic ready; + floo_rsp_chan_t rsp; + } floo_rsp_t; + +endpackage + diff --git a/src/floo_narrow_wide_chimney.sv b/src/floo_narrow_wide_chimney.sv index 80b48363..600c75f2 100644 --- a/src/floo_narrow_wide_chimney.sv +++ b/src/floo_narrow_wide_chimney.sv @@ -11,7 +11,7 @@ /// A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC module floo_narrow_wide_chimney import floo_pkg::*; - import floo_narrow_wide_flit_pkg::*; + import floo_narrow_wide_pkg::*; #( /// Atomic operation support, currently only implemented for /// the narrow network! @@ -27,8 +27,6 @@ module floo_narrow_wide_chimney parameter int unsigned XYAddrOffsetX = 0, /// Y Coordinate address offset for XY routing parameter int unsigned XYAddrOffsetY = 0, - /// ID address offset for ID routing - parameter int unsigned IdTableAddrOffset = 8, /// Number of maximum oustanding requests on the narrow network parameter int unsigned NarrowMaxTxns = 32, /// Number of maximum oustanding requests on the wide network @@ -53,87 +51,98 @@ module floo_narrow_wide_chimney parameter bit CutRsp = 1'b1, /// Only used for XYRouting parameter type xy_id_t = logic, + parameter type id_t = logic, + /// Only used for IDRouting + parameter type id_rule_t = logic, + parameter int unsigned NumIDs = 1, + parameter int unsigned NumRules = NumIDs, /// Type for implementation inputs and outputs - parameter type sram_cfg_t = logic, - /// Derived parameters, do not change - localparam type narrow_rob_idx_t = logic [$clog2(NarrowReorderBufferSize)-1:0], - localparam type wide_rob_idx_t = logic [$clog2(WideReorderBufferSize)-1:0] -) ( - input logic clk_i, - input logic rst_ni, - input logic test_enable_i, - input sram_cfg_t sram_cfg_i, - /// AXI4 side interfaces - input narrow_in_req_t narrow_in_req_i, - output narrow_in_resp_t narrow_in_rsp_o, - output narrow_out_req_t narrow_out_req_o, - input narrow_out_resp_t narrow_out_rsp_i, - input wide_in_req_t wide_in_req_i, - output wide_in_resp_t wide_in_rsp_o, - output wide_out_req_t wide_out_req_o, - input wide_out_resp_t wide_out_rsp_i, - /// Coordinates/ID of the current tile - input xy_id_t xy_id_i, - input src_id_t id_i, - /// Output to NoC - output narrow_req_flit_t narrow_req_o, - output narrow_rsp_flit_t narrow_rsp_o, - output wide_flit_t wide_o, - /// Input from NoC - input narrow_req_flit_t narrow_req_i, - input narrow_rsp_flit_t narrow_rsp_i, - input wide_flit_t wide_i -); - - // AX queue - narrow_in_aw_chan_t narrow_aw_queue; - narrow_in_ar_chan_t narrow_ar_queue; - wide_in_aw_chan_t wide_aw_queue; - wide_in_ar_chan_t wide_ar_queue; - logic narrow_aw_queue_valid_out, narrow_aw_queue_ready_in; - logic narrow_ar_queue_valid_out, narrow_ar_queue_ready_in; - logic wide_aw_queue_valid_out, wide_aw_queue_ready_in; - logic wide_ar_queue_valid_out, wide_ar_queue_ready_in; - - narrow_in_req_t narrow_out_req_id_mapped; - narrow_in_resp_t narrow_out_rsp_id_mapped; - wide_in_req_t wide_out_req_id_mapped; - wide_in_resp_t wide_out_rsp_id_mapped; - `AXI_ASSIGN_REQ_STRUCT(narrow_out_req_o, narrow_out_req_id_mapped) - `AXI_ASSIGN_RESP_STRUCT(narrow_out_rsp_id_mapped, narrow_out_rsp_i) - `AXI_ASSIGN_REQ_STRUCT(wide_out_req_o, wide_out_req_id_mapped) - `AXI_ASSIGN_RESP_STRUCT(wide_out_rsp_id_mapped, wide_out_rsp_i) - - narrow_req_data_t [WideInAw:NarrowInAw] narrow_req_data_arb_data_in; - narrow_rsp_data_t [WideInB:NarrowInB] narrow_rsp_data_arb_data_in; - wide_data_t [WideInR:WideInW] wide_data_arb_data_in; - logic [WideInAw:NarrowInAw] narrow_req_data_arb_req_in, narrow_req_data_arb_gnt_out; - logic [WideInB:NarrowInB] narrow_rsp_data_arb_req_in, narrow_rsp_data_arb_gnt_out; - logic [WideInR:WideInW] wide_data_arb_req_in, wide_data_arb_gnt_out; + parameter type sram_cfg_t = logic + ) ( + input logic clk_i, + input logic rst_ni, + input logic test_enable_i, + input sram_cfg_t sram_cfg_i, + /// AXI4 side interfaces + input axi_narrow_in_req_t axi_narrow_in_req_i, + output axi_narrow_in_rsp_t axi_narrow_in_rsp_o, + output axi_narrow_out_req_t axi_narrow_out_req_o, + input axi_narrow_out_rsp_t axi_narrow_out_rsp_i, + input axi_wide_in_req_t axi_wide_in_req_i, + output axi_wide_in_rsp_t axi_wide_in_rsp_o, + output axi_wide_out_req_t axi_wide_out_req_o, + input axi_wide_out_rsp_t axi_wide_out_rsp_i, + /// Coordinates/ID of the current tile + input xy_id_t xy_id_i, + input id_t id_i, + /// Routing table + input id_rule_t[NumRules-1:0] id_map_i, + /// Output to NoC + output floo_req_t floo_req_o, + output floo_rsp_t floo_rsp_o, + output floo_wide_t floo_wide_o, + /// Input from NoC + input floo_req_t floo_req_i, + input floo_rsp_t floo_rsp_i, + input floo_wide_t floo_wide_i + ); + + typedef logic [$clog2(NarrowReorderBufferSize)-1:0] narrow_rob_idx_t; + typedef logic [$clog2(WideReorderBufferSize)-1:0] wide_rob_idx_t; + + // AX queue + axi_narrow_in_aw_chan_t axi_narrow_aw_queue; + axi_narrow_in_ar_chan_t axi_narrow_ar_queue; + axi_wide_in_aw_chan_t axi_wide_aw_queue; + axi_wide_in_ar_chan_t axi_wide_ar_queue; + logic axi_narrow_aw_queue_valid_out, axi_narrow_aw_queue_ready_in; + logic axi_narrow_ar_queue_valid_out, axi_narrow_ar_queue_ready_in; + logic axi_wide_aw_queue_valid_out, axi_wide_aw_queue_ready_in; + logic axi_wide_ar_queue_valid_out, axi_wide_ar_queue_ready_in; + + axi_narrow_in_req_t axi_narrow_out_req_id_mapped; + axi_narrow_in_rsp_t axi_narrow_out_rsp_id_mapped; + axi_wide_in_req_t axi_wide_out_req_id_mapped; + axi_wide_in_rsp_t axi_wide_out_rsp_id_mapped; + `AXI_ASSIGN_REQ_STRUCT(axi_narrow_out_req_o, + axi_narrow_out_req_id_mapped) + `AXI_ASSIGN_RESP_STRUCT(axi_narrow_out_rsp_id_mapped, + axi_narrow_out_rsp_i) + `AXI_ASSIGN_REQ_STRUCT(axi_wide_out_req_o, + axi_wide_out_req_id_mapped) + `AXI_ASSIGN_RESP_STRUCT(axi_wide_out_rsp_id_mapped, + axi_wide_out_rsp_i) + + floo_req_chan_t [WideAr:NarrowAw] floo_req_arb_in; + floo_rsp_chan_t [WideB:NarrowB] floo_rsp_arb_in; + floo_wide_chan_t [WideR:WideW] floo_wide_arb_in; + logic [WideAr:NarrowAw] floo_req_arb_req_in, floo_req_arb_gnt_out; + logic [WideB:NarrowB] floo_rsp_arb_req_in, floo_rsp_arb_gnt_out; + logic [WideR:WideW] floo_wide_arb_req_in, floo_wide_arb_gnt_out; // flit queue - narrow_req_flit_t narrow_req_in; - narrow_rsp_flit_t narrow_rsp_in; - wide_flit_t wide_in; - logic narrow_req_ready_out, narrow_rsp_ready_out; - logic wide_ready_out; - logic [NumAxiChannels-1:0] axi_valid_in, axi_ready_out; + floo_req_chan_t floo_req_in; + floo_rsp_chan_t floo_rsp_in; + floo_wide_chan_t floo_wide_in; + logic floo_req_in_valid, floo_rsp_in_valid, floo_wide_in_valid; + logic floo_req_out_ready, floo_rsp_out_ready, floo_wide_out_ready; + logic [NumNarrowWideAxiChannels-1:0] axi_valid_in, axi_ready_out; // Flit packing - narrow_in_aw_data_t narrow_aw_data; - narrow_in_ar_data_t narrow_ar_data; - narrow_in_w_data_t narrow_w_data; - narrow_in_b_data_t narrow_b_data; - narrow_in_r_data_t narrow_r_data; - narrow_in_aw_chan_t narrow_aw_id_mod; - narrow_in_ar_chan_t narrow_ar_id_mod; - wide_in_aw_data_t wide_aw_data; - wide_in_ar_data_t wide_ar_data; - wide_in_w_data_t wide_w_data; - wide_in_b_data_t wide_b_data; - wide_in_r_data_t wide_r_data; - wide_in_aw_chan_t wide_aw_id_mod; - wide_in_ar_chan_t wide_ar_id_mod; + floo_narrow_aw_flit_t floo_narrow_aw; + floo_narrow_ar_flit_t floo_narrow_ar; + floo_narrow_w_flit_t floo_narrow_w; + floo_narrow_b_flit_t floo_narrow_b; + floo_narrow_r_flit_t floo_narrow_r; + axi_narrow_in_aw_chan_t axi_narrow_aw_id_mod; + axi_narrow_in_ar_chan_t axi_narrow_ar_id_mod; + floo_wide_aw_flit_t floo_wide_aw; + floo_wide_ar_flit_t floo_wide_ar; + floo_wide_w_flit_t floo_wide_w; + floo_wide_b_flit_t floo_wide_b; + floo_wide_r_flit_t floo_wide_r; + axi_wide_in_aw_chan_t axi_wide_aw_id_mod; + axi_wide_in_ar_chan_t axi_wide_ar_id_mod; // Flit arbitration typedef enum logic {SelAw, SelW} aw_w_sel_e; @@ -141,56 +150,54 @@ module floo_narrow_wide_chimney aw_w_sel_e wide_aw_w_sel_q, wide_aw_w_sel_d; // Flit unpacking - narrow_in_aw_chan_t narrow_unpack_aw_data; - narrow_in_w_chan_t narrow_unpack_w_data; - narrow_in_b_chan_t narrow_unpack_b_data; - narrow_in_ar_chan_t narrow_unpack_ar_data; - narrow_in_r_chan_t narrow_unpack_r_data; - wide_in_aw_chan_t wide_unpack_aw_data; - wide_in_w_chan_t wide_unpack_w_data; - wide_in_b_chan_t wide_unpack_b_data; - wide_in_ar_chan_t wide_unpack_ar_data; - wide_in_r_chan_t wide_unpack_r_data; - narrow_req_generic_t narrow_unpack_req_generic; - narrow_rsp_generic_t narrow_unpack_rsp_generic; - wide_generic_t wide_unpack_generic; - - typedef dst_id_t id_t; + axi_narrow_in_aw_chan_t axi_narrow_unpack_aw; + axi_narrow_in_w_chan_t axi_narrow_unpack_w; + axi_narrow_in_b_chan_t axi_narrow_unpack_b; + axi_narrow_in_ar_chan_t axi_narrow_unpack_ar; + axi_narrow_in_r_chan_t axi_narrow_unpack_r; + axi_wide_in_aw_chan_t axi_wide_unpack_aw; + axi_wide_in_w_chan_t axi_wide_unpack_w; + axi_wide_in_b_chan_t axi_wide_unpack_b; + axi_wide_in_ar_chan_t axi_wide_unpack_ar; + axi_wide_in_r_chan_t axi_wide_unpack_r; + floo_req_generic_flit_t floo_narrow_unpack_req_generic; + floo_rsp_generic_flit_t floo_narrow_unpack_rsp_generic; + floo_wide_generic_flit_t floo_wide_unpack_generic; // ID tracking typedef struct packed { - narrow_in_id_t id; - logic rob_req; - narrow_rob_idx_t rob_idx; - id_t src_id; - logic atop; + axi_narrow_in_id_t id; + logic rob_req; + narrow_rob_idx_t rob_idx; + id_t src_id; + logic atop; } narrow_id_out_buf_t; typedef struct packed { - wide_in_id_t id; - logic rob_req; - wide_rob_idx_t rob_idx; - id_t src_id; + axi_wide_in_id_t id; + logic rob_req; + wide_rob_idx_t rob_idx; + id_t src_id; } wide_id_out_buf_t; // Routing - id_t [NumAxiChannels-1:0] dst_id; + id_t [NumNarrowWideAxiChannels-1:0] dst_id; id_t src_id; logic narrow_aw_out_push, narrow_aw_out_pop; logic narrow_ar_out_push, narrow_ar_out_pop; logic narrow_aw_out_full; logic narrow_ar_out_full; - narrow_out_id_t narrow_aw_out_id; - narrow_out_id_t narrow_ar_out_id; + axi_narrow_out_id_t narrow_aw_out_id; + axi_narrow_out_id_t narrow_ar_out_id; narrow_id_out_buf_t narrow_aw_out_data_in, narrow_aw_out_data_out; narrow_id_out_buf_t narrow_ar_out_data_in, narrow_ar_out_data_out; logic wide_aw_out_push, wide_aw_out_pop; logic wide_ar_out_push, wide_ar_out_pop; logic wide_aw_out_full; logic wide_ar_out_full; - wide_out_id_t wide_aw_out_id; - wide_out_id_t wide_ar_out_id; + axi_wide_out_id_t wide_aw_out_id; + axi_wide_out_id_t wide_ar_out_id; wide_id_out_buf_t wide_aw_out_data_in, wide_aw_out_data_out; wide_id_out_buf_t wide_ar_out_data_in, wide_ar_out_data_out; @@ -200,118 +207,121 @@ module floo_narrow_wide_chimney if (CutAx) begin : gen_ax_cuts spill_register #( - .T ( narrow_in_aw_chan_t ) + .T ( axi_narrow_in_aw_chan_t ) ) i_narrow_aw_queue ( .clk_i, .rst_ni, - .data_i ( narrow_in_req_i.aw ), - .valid_i ( narrow_in_req_i.aw_valid ), - .ready_o ( narrow_in_rsp_o.aw_ready ), - .data_o ( narrow_aw_queue ), - .valid_o ( narrow_aw_queue_valid_out ), - .ready_i ( narrow_aw_queue_ready_in ) + .data_i ( axi_narrow_in_req_i.aw ), + .valid_i ( axi_narrow_in_req_i.aw_valid ), + .ready_o ( axi_narrow_in_rsp_o.aw_ready ), + .data_o ( axi_narrow_aw_queue ), + .valid_o ( axi_narrow_aw_queue_valid_out ), + .ready_i ( axi_narrow_aw_queue_ready_in ) ); spill_register #( - .T ( narrow_in_ar_chan_t ) + .T ( axi_narrow_in_ar_chan_t ) ) i_narrow_ar_queue ( .clk_i, .rst_ni, - .data_i ( narrow_in_req_i.ar ), - .valid_i ( narrow_in_req_i.ar_valid ), - .ready_o ( narrow_in_rsp_o.ar_ready ), - .data_o ( narrow_ar_queue ), - .valid_o ( narrow_ar_queue_valid_out ), - .ready_i ( narrow_ar_queue_ready_in ) + .data_i ( axi_narrow_in_req_i.ar ), + .valid_i ( axi_narrow_in_req_i.ar_valid ), + .ready_o ( axi_narrow_in_rsp_o.ar_ready ), + .data_o ( axi_narrow_ar_queue ), + .valid_o ( axi_narrow_ar_queue_valid_out ), + .ready_i ( axi_narrow_ar_queue_ready_in ) ); spill_register #( - .T ( wide_in_aw_chan_t ) + .T ( axi_wide_in_aw_chan_t ) ) i_wide_aw_queue ( .clk_i, .rst_ni, - .data_i ( wide_in_req_i.aw ), - .valid_i ( wide_in_req_i.aw_valid ), - .ready_o ( wide_in_rsp_o.aw_ready ), - .data_o ( wide_aw_queue ), - .valid_o ( wide_aw_queue_valid_out ), - .ready_i ( wide_aw_queue_ready_in ) + .data_i ( axi_wide_in_req_i.aw ), + .valid_i ( axi_wide_in_req_i.aw_valid ), + .ready_o ( axi_wide_in_rsp_o.aw_ready ), + .data_o ( axi_wide_aw_queue ), + .valid_o ( axi_wide_aw_queue_valid_out ), + .ready_i ( axi_wide_aw_queue_ready_in ) ); spill_register #( - .T ( wide_in_ar_chan_t ) + .T ( axi_wide_in_ar_chan_t ) ) i_wide_ar_queue ( .clk_i, .rst_ni, - .data_i ( wide_in_req_i.ar ), - .valid_i ( wide_in_req_i.ar_valid ), - .ready_o ( wide_in_rsp_o.ar_ready ), - .data_o ( wide_ar_queue ), - .valid_o ( wide_ar_queue_valid_out ), - .ready_i ( wide_ar_queue_ready_in ) + .data_i ( axi_wide_in_req_i.ar ), + .valid_i ( axi_wide_in_req_i.ar_valid ), + .ready_o ( axi_wide_in_rsp_o.ar_ready ), + .data_o ( axi_wide_ar_queue ), + .valid_o ( axi_wide_ar_queue_valid_out ), + .ready_i ( axi_wide_ar_queue_ready_in ) ); end else begin : gen_ax_no_cuts - assign narrow_aw_queue = narrow_in_req_i.aw; - assign narrow_aw_queue_valid_out = narrow_in_req_i.aw_valid; - assign narrow_in_rsp_o.aw_ready = narrow_aw_queue_ready_in; - assign narrow_ar_queue = narrow_in_req_i.ar; - assign narrow_ar_queue_valid_out = narrow_in_req_i.ar_valid; - assign narrow_in_rsp_o.ar_ready = narrow_ar_queue_ready_in; - assign wide_aw_queue = wide_in_req_i.aw; - assign wide_aw_queue_valid_out = wide_in_req_i.aw_valid; - assign wide_in_rsp_o.aw_ready = wide_aw_queue_ready_in; - assign wide_ar_queue = wide_in_req_i.ar; - assign wide_ar_queue_valid_out = wide_in_req_i.ar_valid; - assign wide_in_rsp_o.ar_ready = wide_ar_queue_ready_in; + assign axi_narrow_aw_queue = axi_narrow_in_req_i.aw; + assign axi_narrow_aw_queue_valid_out = axi_narrow_in_req_i.aw_valid; + assign axi_narrow_in_rsp_o.aw_ready = axi_narrow_aw_queue_ready_in; + assign axi_narrow_ar_queue = axi_narrow_in_req_i.ar; + assign axi_narrow_ar_queue_valid_out = axi_narrow_in_req_i.ar_valid; + assign axi_narrow_in_rsp_o.ar_ready = axi_narrow_ar_queue_ready_in; + assign axi_wide_aw_queue = axi_wide_in_req_i.aw; + assign axi_wide_aw_queue_valid_out = axi_wide_in_req_i.aw_valid; + assign axi_wide_in_rsp_o.aw_ready = axi_wide_aw_queue_ready_in; + assign axi_wide_ar_queue = axi_wide_in_req_i.ar; + assign axi_wide_ar_queue_valid_out = axi_wide_in_req_i.ar_valid; + assign axi_wide_in_rsp_o.ar_ready = axi_wide_ar_queue_ready_in; end if (CutRsp) begin : gen_rsp_cuts spill_register #( - .T ( narrow_req_data_t ) + .T ( floo_req_chan_t ) ) i_narrow_data_req_arb ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .data_i ( narrow_req_i.data ), - .valid_i ( narrow_req_i.valid ), - .ready_o ( narrow_req_o.ready ), - .data_o ( narrow_req_in.data ), - .valid_o ( narrow_req_in.valid ), - .ready_i ( narrow_req_ready_out ) + .clk_i, + .rst_ni, + .data_i ( floo_req_i.req ), + .valid_i ( floo_req_i.valid ), + .ready_o ( floo_req_o.ready ), + .data_o ( floo_req_in ), + .valid_o ( floo_req_in_valid ), + .ready_i ( floo_req_out_ready ) ); spill_register #( - .T ( narrow_rsp_data_t ) + .T ( floo_rsp_chan_t ) ) i_narrow_data_rsp_arb ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .data_i ( narrow_rsp_i.data ), - .valid_i ( narrow_rsp_i.valid ), - .ready_o ( narrow_rsp_o.ready ), - .data_o ( narrow_rsp_in.data ), - .valid_o ( narrow_rsp_in.valid ), - .ready_i ( narrow_rsp_ready_out ) + .clk_i, + .rst_ni, + .data_i ( floo_rsp_i.rsp ), + .valid_i ( floo_rsp_i.valid ), + .ready_o ( floo_rsp_o.ready ), + .data_o ( floo_rsp_in ), + .valid_o ( floo_rsp_in_valid ), + .ready_i ( floo_rsp_out_ready ) ); spill_register #( - .T ( wide_data_t ) + .T ( floo_wide_chan_t ) ) i_wide_data_req_arb ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .data_i ( wide_i.data ), - .valid_i ( wide_i.valid ), - .ready_o ( wide_o.ready ), - .data_o ( wide_in.data ), - .valid_o ( wide_in.valid ), - .ready_i ( wide_ready_out ) + .clk_i, + .rst_ni, + .data_i ( floo_wide_i.wide ), + .valid_i ( floo_wide_i.valid ), + .ready_o ( floo_wide_o.ready ), + .data_o ( floo_wide_in ), + .valid_o ( floo_wide_in_valid ), + .ready_i ( floo_wide_out_ready ) ); end else begin : gen_no_rsp_cuts - assign narrow_req_in = narrow_req_i; - assign narrow_rsp_in = narrow_rsp_i; - assign wide_in = wide_i; - assign narrow_req_o.ready = narrow_req_ready_out; - assign narrow_rsp_o.ready = narrow_rsp_ready_out; - assign wide_o.ready = wide_ready_out; + assign floo_req_in = floo_req_i.req; + assign floo_rsp_in = floo_rsp_i.rsp; + assign floo_wide_in = floo_wide_i.wide; + assign floo_req_in_valid = floo_req_i.valid; + assign floo_rsp_in_valid = floo_rsp_i.valid; + assign floo_wide_in_valid = floo_wide_i.valid; + assign floo_req_o.ready = floo_req_out_ready; + assign floo_rsp_o.ready = floo_rsp_out_ready; + assign floo_wide_o.ready = floo_wide_out_ready; end /////////////////////// @@ -319,14 +329,14 @@ module floo_narrow_wide_chimney /////////////////////// // AW/B RoB - narrow_in_b_chan_t narrow_b_rob_out, narrow_b_rob_in; + axi_narrow_in_b_chan_t axi_narrow_b_rob_out, axi_narrow_b_rob_in; logic narrow_aw_rob_req_out; narrow_rob_idx_t narrow_aw_rob_idx_out; logic narrow_aw_rob_valid_out, narrow_aw_rob_ready_in; logic narrow_aw_rob_valid_in, narrow_aw_rob_ready_out; logic narrow_b_rob_valid_in, narrow_b_rob_ready_out; logic narrow_b_rob_valid_out, narrow_b_rob_ready_in; - wide_in_b_chan_t wide_b_rob_out, wide_b_rob_in; + axi_wide_in_b_chan_t axi_wide_b_rob_out, axi_wide_b_rob_in; logic wide_aw_rob_req_out; narrow_rob_idx_t wide_aw_rob_idx_out; logic wide_aw_rob_valid_out, wide_aw_rob_ready_in; @@ -334,13 +344,13 @@ module floo_narrow_wide_chimney logic wide_b_rob_valid_out, wide_b_rob_ready_in; // AR/R RoB - narrow_in_r_chan_t narrow_r_rob_out, narrow_r_rob_in; + axi_narrow_in_r_chan_t axi_narrow_r_rob_out, axi_narrow_r_rob_in; logic narrow_ar_rob_req_out; narrow_rob_idx_t narrow_ar_rob_idx_out; logic narrow_ar_rob_valid_out, narrow_ar_rob_ready_in; logic narrow_r_rob_valid_in, narrow_r_rob_ready_out; logic narrow_r_rob_valid_out, narrow_r_rob_ready_in; - wide_in_r_chan_t wide_r_rob_out, wide_r_rob_in; + axi_wide_in_r_chan_t axi_wide_r_rob_out, axi_wide_r_rob_in; logic wide_ar_rob_req_out; wide_rob_idx_t wide_ar_rob_idx_out; logic wide_ar_rob_valid_out, wide_ar_rob_ready_in; @@ -350,21 +360,21 @@ module floo_narrow_wide_chimney logic narrow_b_rob_rob_req; logic narrow_b_rob_last; narrow_rob_idx_t narrow_b_rob_rob_idx; - assign narrow_b_rob_rob_req = narrow_rsp_in.data.narrow_in_b.rob_req; - assign narrow_b_rob_rob_idx = narrow_rob_idx_t'(narrow_rsp_in.data.narrow_in_b.rob_idx); - assign narrow_b_rob_last = narrow_rsp_in.data.narrow_in_b.last; + assign narrow_b_rob_rob_req = floo_rsp_in.narrow_b.hdr.rob_req; + assign narrow_b_rob_rob_idx = floo_rsp_in.narrow_b.hdr.rob_idx; + assign narrow_b_rob_last = floo_rsp_in.narrow_b.hdr.last; if (AtopSupport) begin : gen_atop_support // Bypass AW/B RoB - assign narrow_aw_rob_valid_in = narrow_aw_queue_valid_out && - (narrow_aw_queue.atop == axi_pkg::ATOP_NONE); - assign narrow_aw_queue_ready_in = (narrow_aw_queue.atop == axi_pkg::ATOP_NONE)? + assign narrow_aw_rob_valid_in = axi_narrow_aw_queue_valid_out && + (axi_narrow_aw_queue.atop == axi_pkg::ATOP_NONE); + assign axi_narrow_aw_queue_ready_in = (axi_narrow_aw_queue.atop == axi_pkg::ATOP_NONE)? narrow_aw_rob_ready_out : narrow_aw_rob_ready_in; end else begin : gen_no_atop_support - assign narrow_aw_rob_valid_in = narrow_aw_queue_valid_out; - assign narrow_aw_queue_ready_in = narrow_aw_rob_ready_in; - `ASSERT(NoAtopSupport, !(narrow_aw_queue_valid_out && - (narrow_aw_queue.atop != axi_pkg::ATOP_NONE))) + assign narrow_aw_rob_valid_in = axi_narrow_aw_queue_valid_out; + assign axi_narrow_aw_queue_ready_in = narrow_aw_rob_ready_in; + `ASSERT(NoAtopSupport, !(axi_narrow_aw_queue_valid_out && + (axi_narrow_aw_queue.atop != axi_pkg::ATOP_NONE))) end floo_simple_rob #( @@ -372,8 +382,8 @@ module floo_narrow_wide_chimney .MaxRoTxnsPerId ( NarrowMaxTxnsPerId ), .OnlyMetaData ( 1'b1 ), .ax_len_t ( axi_pkg::len_t ), - .rsp_chan_t ( narrow_in_b_chan_t ), - .rsp_meta_t ( narrow_in_b_chan_t ), + .rsp_chan_t ( axi_narrow_in_b_chan_t ), + .rsp_meta_t ( axi_narrow_in_b_chan_t ), .rob_idx_t ( narrow_rob_idx_t ), .dest_t ( id_t ), .sram_cfg_t ( sram_cfg_t ) @@ -383,37 +393,37 @@ module floo_narrow_wide_chimney .sram_cfg_i, .ax_valid_i ( narrow_aw_rob_valid_in ), .ax_ready_o ( narrow_aw_rob_ready_out ), - .ax_len_i ( narrow_aw_queue.len ), - .ax_dest_i ( dst_id[NarrowInAw] ), + .ax_len_i ( axi_narrow_aw_queue.len ), + .ax_dest_i ( dst_id[NarrowAw] ), .ax_valid_o ( narrow_aw_rob_valid_out ), .ax_ready_i ( narrow_aw_rob_ready_in ), .ax_rob_req_o ( narrow_aw_rob_req_out ), .ax_rob_idx_o ( narrow_aw_rob_idx_out ), .rsp_valid_i ( narrow_b_rob_valid_in ), .rsp_ready_o ( narrow_b_rob_ready_out ), - .rsp_i ( narrow_b_rob_in ), + .rsp_i ( axi_narrow_b_rob_in ), .rsp_rob_req_i ( narrow_b_rob_rob_req ), .rsp_rob_idx_i ( narrow_b_rob_rob_idx ), .rsp_last_i ( narrow_b_rob_last ), .rsp_valid_o ( narrow_b_rob_valid_out ), .rsp_ready_i ( narrow_b_rob_ready_in ), - .rsp_o ( narrow_b_rob_out ) + .rsp_o ( axi_narrow_b_rob_out ) ); logic wide_b_rob_rob_req; logic wide_b_rob_last; narrow_rob_idx_t wide_b_rob_rob_idx; - assign wide_b_rob_rob_req = narrow_rsp_in.data.wide_in_b.rob_req; - assign wide_b_rob_rob_idx = narrow_rob_idx_t'(narrow_rsp_in.data.wide_in_b.rob_idx); - assign wide_b_rob_last = narrow_rsp_in.data.wide_in_b.last; + assign wide_b_rob_rob_req = floo_rsp_in.wide_b.hdr.rob_req; + assign wide_b_rob_rob_idx = floo_rsp_in.wide_b.hdr.rob_idx; + assign wide_b_rob_last = floo_rsp_in.wide_b.hdr.last; floo_simple_rob #( .ReorderBufferSize ( WideReorderBufferSize ), .MaxRoTxnsPerId ( WideMaxTxnsPerId ), .OnlyMetaData ( 1'b1 ), .ax_len_t ( axi_pkg::len_t ), - .rsp_chan_t ( wide_in_b_chan_t ), - .rsp_meta_t ( wide_in_b_chan_t ), + .rsp_chan_t ( axi_wide_in_b_chan_t ), + .rsp_meta_t ( axi_wide_in_b_chan_t ), .rob_idx_t ( narrow_rob_idx_t ), .dest_t ( id_t ), .sram_cfg_t ( sram_cfg_t ) @@ -421,45 +431,45 @@ module floo_narrow_wide_chimney .clk_i, .rst_ni, .sram_cfg_i, - .ax_valid_i ( wide_aw_queue_valid_out ), - .ax_ready_o ( wide_aw_queue_ready_in ), - .ax_len_i ( wide_aw_queue.len ), - .ax_dest_i ( dst_id[WideInAw] ), - .ax_valid_o ( wide_aw_rob_valid_out ), - .ax_ready_i ( wide_aw_rob_ready_in ), - .ax_rob_req_o ( wide_aw_rob_req_out ), - .ax_rob_idx_o ( wide_aw_rob_idx_out ), - .rsp_valid_i ( wide_b_rob_valid_in ), - .rsp_ready_o ( wide_b_rob_ready_out ), - .rsp_i ( wide_b_rob_in ), - .rsp_rob_req_i ( wide_b_rob_rob_req ), - .rsp_rob_idx_i ( wide_b_rob_rob_idx ), - .rsp_last_i ( wide_b_rob_last ), - .rsp_valid_o ( wide_b_rob_valid_out ), - .rsp_ready_i ( wide_b_rob_ready_in ), - .rsp_o ( wide_b_rob_out ) + .ax_valid_i ( axi_wide_aw_queue_valid_out ), + .ax_ready_o ( axi_wide_aw_queue_ready_in ), + .ax_len_i ( axi_wide_aw_queue.len ), + .ax_dest_i ( dst_id[WideAw] ), + .ax_valid_o ( wide_aw_rob_valid_out ), + .ax_ready_i ( wide_aw_rob_ready_in ), + .ax_rob_req_o ( wide_aw_rob_req_out ), + .ax_rob_idx_o ( wide_aw_rob_idx_out ), + .rsp_valid_i ( wide_b_rob_valid_in ), + .rsp_ready_o ( wide_b_rob_ready_out ), + .rsp_i ( axi_wide_b_rob_in ), + .rsp_rob_req_i ( wide_b_rob_rob_req ), + .rsp_rob_idx_i ( wide_b_rob_rob_idx ), + .rsp_last_i ( wide_b_rob_last ), + .rsp_valid_o ( wide_b_rob_valid_out ), + .rsp_ready_i ( wide_b_rob_ready_in ), + .rsp_o ( axi_wide_b_rob_out ) ); typedef struct packed { - narrow_in_id_t id; - narrow_in_user_t user; - axi_pkg::resp_t resp; - logic last; + axi_narrow_in_id_t id; + axi_narrow_in_user_t user; + axi_pkg::resp_t resp; + logic last; } narrow_meta_t; typedef struct packed { - wide_in_id_t id; - wide_in_user_t user; - axi_pkg::resp_t resp; - logic last; + axi_wide_in_id_t id; + axi_wide_in_user_t user; + axi_pkg::resp_t resp; + logic last; } wide_meta_t; logic narrow_r_rob_rob_req; logic narrow_r_rob_last; narrow_rob_idx_t narrow_r_rob_rob_idx; - assign narrow_r_rob_rob_req = narrow_rsp_in.data.narrow_in_r.rob_req; - assign narrow_r_rob_rob_idx = narrow_rob_idx_t'(narrow_rsp_in.data.narrow_in_r.rob_idx); - assign narrow_r_rob_last = narrow_rsp_in.data.narrow_in_r.last; + assign narrow_r_rob_rob_req = floo_rsp_in.narrow_r.hdr.rob_req; + assign narrow_r_rob_rob_idx = floo_rsp_in.narrow_r.hdr.rob_idx; + assign narrow_r_rob_last = floo_rsp_in.narrow_r.hdr.last; if (NarrowRoBSimple) begin : gen_narrow_simple_rob floo_simple_rob #( @@ -467,8 +477,8 @@ module floo_narrow_wide_chimney .MaxRoTxnsPerId ( NarrowMaxTxnsPerId ), .OnlyMetaData ( 1'b0 ), .ax_len_t ( axi_pkg::len_t ), - .rsp_chan_t ( narrow_in_r_chan_t ), - .rsp_data_t ( narrow_in_data_t ), + .rsp_chan_t ( axi_narrow_in_r_chan_t ), + .rsp_data_t ( axi_narrow_in_data_t ), .rsp_meta_t ( narrow_meta_t ), .rob_idx_t ( narrow_rob_idx_t ), .dest_t ( id_t ), @@ -477,23 +487,23 @@ module floo_narrow_wide_chimney .clk_i, .rst_ni, .sram_cfg_i, - .ax_valid_i ( narrow_ar_queue_valid_out ), - .ax_ready_o ( narrow_ar_queue_ready_in ), - .ax_len_i ( narrow_ar_queue.len ), - .ax_dest_i ( dst_id[NarrowInAr] ), - .ax_valid_o ( narrow_ar_rob_valid_out ), - .ax_ready_i ( narrow_ar_rob_ready_in ), - .ax_rob_req_o ( narrow_ar_rob_req_out ), - .ax_rob_idx_o ( narrow_ar_rob_idx_out ), - .rsp_valid_i ( narrow_r_rob_valid_in ), - .rsp_ready_o ( narrow_r_rob_ready_out ), - .rsp_i ( narrow_r_rob_in ), - .rsp_rob_req_i ( narrow_r_rob_rob_req ), - .rsp_rob_idx_i ( narrow_r_rob_rob_idx ), - .rsp_last_i ( narrow_r_rob_last ), - .rsp_valid_o ( narrow_r_rob_valid_out ), - .rsp_ready_i ( narrow_r_rob_ready_in ), - .rsp_o ( narrow_r_rob_out ) + .ax_valid_i ( axi_narrow_ar_queue_valid_out ), + .ax_ready_o ( axi_narrow_ar_queue_ready_in ), + .ax_len_i ( axi_narrow_ar_queue.len ), + .ax_dest_i ( dst_id[NarrowAr] ), + .ax_valid_o ( narrow_ar_rob_valid_out ), + .ax_ready_i ( narrow_ar_rob_ready_in ), + .ax_rob_req_o ( narrow_ar_rob_req_out ), + .ax_rob_idx_o ( narrow_ar_rob_idx_out ), + .rsp_valid_i ( narrow_r_rob_valid_in ), + .rsp_ready_o ( narrow_r_rob_ready_out ), + .rsp_i ( axi_narrow_r_rob_in ), + .rsp_rob_req_i ( narrow_r_rob_rob_req ), + .rsp_rob_idx_i ( narrow_r_rob_rob_idx ), + .rsp_last_i ( narrow_r_rob_last ), + .rsp_valid_o ( narrow_r_rob_valid_out ), + .rsp_ready_i ( narrow_r_rob_ready_in ), + .rsp_o ( axi_narrow_r_rob_out ) ); end else begin : gen_narrow_rob floo_rob #( @@ -501,9 +511,9 @@ module floo_narrow_wide_chimney .MaxRoTxnsPerId ( NarrowMaxTxnsPerId ), .OnlyMetaData ( 1'b0 ), .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( narrow_in_id_t ), - .rsp_chan_t ( narrow_in_r_chan_t ), - .rsp_data_t ( narrow_in_data_t ), + .ax_id_t ( axi_narrow_in_id_t ), + .rsp_chan_t ( axi_narrow_in_r_chan_t ), + .rsp_data_t ( axi_narrow_in_data_t ), .rsp_meta_t ( narrow_meta_t ), .rob_idx_t ( narrow_rob_idx_t ), .dest_t ( id_t ), @@ -512,33 +522,33 @@ module floo_narrow_wide_chimney .clk_i, .rst_ni, .sram_cfg_i, - .ax_valid_i ( narrow_ar_queue_valid_out ), - .ax_ready_o ( narrow_ar_queue_ready_in ), - .ax_len_i ( narrow_ar_queue.len ), - .ax_id_i ( narrow_ar_queue.id ), - .ax_dest_i ( dst_id[NarrowInAr] ), - .ax_valid_o ( narrow_ar_rob_valid_out ), - .ax_ready_i ( narrow_ar_rob_ready_in ), - .ax_rob_req_o ( narrow_ar_rob_req_out ), - .ax_rob_idx_o ( narrow_ar_rob_idx_out ), - .rsp_valid_i ( narrow_r_rob_valid_in ), - .rsp_ready_o ( narrow_r_rob_ready_out ), - .rsp_i ( narrow_r_rob_in ), - .rsp_rob_req_i ( narrow_r_rob_rob_req ), - .rsp_rob_idx_i ( narrow_r_rob_rob_idx ), - .rsp_last_i ( narrow_r_rob_last ), - .rsp_valid_o ( narrow_r_rob_valid_out ), - .rsp_ready_i ( narrow_r_rob_ready_in ), - .rsp_o ( narrow_r_rob_out ) + .ax_valid_i ( axi_narrow_ar_queue_valid_out ), + .ax_ready_o ( axi_narrow_ar_queue_ready_in ), + .ax_len_i ( axi_narrow_ar_queue.len ), + .ax_id_i ( axi_narrow_ar_queue.id ), + .ax_dest_i ( dst_id[NarrowAr] ), + .ax_valid_o ( narrow_ar_rob_valid_out ), + .ax_ready_i ( narrow_ar_rob_ready_in ), + .ax_rob_req_o ( narrow_ar_rob_req_out ), + .ax_rob_idx_o ( narrow_ar_rob_idx_out ), + .rsp_valid_i ( narrow_r_rob_valid_in ), + .rsp_ready_o ( narrow_r_rob_ready_out ), + .rsp_i ( axi_narrow_r_rob_in ), + .rsp_rob_req_i ( narrow_r_rob_rob_req ), + .rsp_rob_idx_i ( narrow_r_rob_rob_idx ), + .rsp_last_i ( narrow_r_rob_last ), + .rsp_valid_o ( narrow_r_rob_valid_out ), + .rsp_ready_i ( narrow_r_rob_ready_in ), + .rsp_o ( axi_narrow_r_rob_out ) ); end logic wide_r_rob_rob_req; logic wide_r_rob_last; wide_rob_idx_t wide_r_rob_rob_idx; - assign wide_r_rob_rob_req = wide_in.data.wide_in_r.rob_req; - assign wide_r_rob_rob_idx = wide_rob_idx_t'(wide_in.data.wide_in_r.rob_idx); - assign wide_r_rob_last = wide_in.data.wide_in_r.last; + assign wide_r_rob_rob_req = floo_wide_in.wide_r.hdr.rob_req; + assign wide_r_rob_rob_idx = floo_wide_in.wide_r.hdr.rob_idx; + assign wide_r_rob_last = floo_wide_in.wide_r.hdr.last; if (WideRoBSimple) begin : gen_wide_simple_rob floo_simple_rob #( @@ -546,8 +556,8 @@ module floo_narrow_wide_chimney .MaxRoTxnsPerId ( WideMaxTxnsPerId ), .OnlyMetaData ( 1'b0 ), .ax_len_t ( axi_pkg::len_t ), - .rsp_chan_t ( wide_in_r_chan_t ), - .rsp_data_t ( wide_in_data_t ), + .rsp_chan_t ( axi_wide_in_r_chan_t ), + .rsp_data_t ( axi_wide_in_data_t ), .rsp_meta_t ( wide_meta_t ), .rob_idx_t ( wide_rob_idx_t ), .dest_t ( id_t ), @@ -556,23 +566,23 @@ module floo_narrow_wide_chimney .clk_i, .rst_ni, .sram_cfg_i, - .ax_valid_i ( wide_ar_queue_valid_out ), - .ax_ready_o ( wide_ar_queue_ready_in ), - .ax_len_i ( wide_ar_queue.len ), - .ax_dest_i ( dst_id[WideInAr] ), - .ax_valid_o ( wide_ar_rob_valid_out ), - .ax_ready_i ( wide_ar_rob_ready_in ), - .ax_rob_req_o ( wide_ar_rob_req_out ), - .ax_rob_idx_o ( wide_ar_rob_idx_out ), - .rsp_valid_i ( wide_r_rob_valid_in ), - .rsp_ready_o ( wide_r_rob_ready_out ), - .rsp_i ( wide_r_rob_in ), - .rsp_rob_req_i ( wide_r_rob_rob_req ), - .rsp_rob_idx_i ( wide_r_rob_rob_idx ), - .rsp_last_i ( wide_r_rob_last ), - .rsp_valid_o ( wide_r_rob_valid_out ), - .rsp_ready_i ( wide_r_rob_ready_in ), - .rsp_o ( wide_r_rob_out ) + .ax_valid_i ( axi_wide_ar_queue_valid_out ), + .ax_ready_o ( axi_wide_ar_queue_ready_in ), + .ax_len_i ( axi_wide_ar_queue.len ), + .ax_dest_i ( dst_id[WideAr] ), + .ax_valid_o ( wide_ar_rob_valid_out ), + .ax_ready_i ( wide_ar_rob_ready_in ), + .ax_rob_req_o ( wide_ar_rob_req_out ), + .ax_rob_idx_o ( wide_ar_rob_idx_out ), + .rsp_valid_i ( wide_r_rob_valid_in ), + .rsp_ready_o ( wide_r_rob_ready_out ), + .rsp_i ( wide_r_rob_in ), + .rsp_rob_req_i ( wide_r_rob_rob_req ), + .rsp_rob_idx_i ( wide_r_rob_rob_idx ), + .rsp_last_i ( wide_r_rob_last ), + .rsp_valid_o ( wide_r_rob_valid_out ), + .rsp_ready_i ( wide_r_rob_ready_in ), + .rsp_o ( wide_r_rob_out ) ); end else begin : gen_wide_rob floo_rob #( @@ -580,9 +590,9 @@ module floo_narrow_wide_chimney .MaxRoTxnsPerId ( WideMaxTxnsPerId ), .OnlyMetaData ( 1'b0 ), .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( wide_in_id_t ), - .rsp_chan_t ( wide_in_r_chan_t ), - .rsp_data_t ( wide_in_data_t ), + .ax_id_t ( axi_wide_in_id_t ), + .rsp_chan_t ( axi_wide_in_r_chan_t ), + .rsp_data_t ( axi_wide_in_data_t ), .rsp_meta_t ( wide_meta_t ), .rob_idx_t ( wide_rob_idx_t ), .dest_t ( id_t ), @@ -591,24 +601,24 @@ module floo_narrow_wide_chimney .clk_i, .rst_ni, .sram_cfg_i, - .ax_valid_i ( wide_ar_queue_valid_out ), - .ax_ready_o ( wide_ar_queue_ready_in ), - .ax_len_i ( wide_ar_queue.len ), - .ax_id_i ( wide_ar_queue.id ), - .ax_dest_i ( dst_id[WideInAr] ), - .ax_valid_o ( wide_ar_rob_valid_out ), - .ax_ready_i ( wide_ar_rob_ready_in ), - .ax_rob_req_o ( wide_ar_rob_req_out ), - .ax_rob_idx_o ( wide_ar_rob_idx_out ), - .rsp_valid_i ( wide_r_rob_valid_in ), - .rsp_ready_o ( wide_r_rob_ready_out ), - .rsp_i ( wide_r_rob_in ), - .rsp_rob_req_i ( wide_r_rob_rob_req ), - .rsp_rob_idx_i ( wide_r_rob_rob_idx ), - .rsp_last_i ( wide_r_rob_last ), - .rsp_valid_o ( wide_r_rob_valid_out ), - .rsp_ready_i ( wide_r_rob_ready_in ), - .rsp_o ( wide_r_rob_out ) + .ax_valid_i ( axi_wide_ar_queue_valid_out ), + .ax_ready_o ( axi_wide_ar_queue_ready_in ), + .ax_len_i ( axi_wide_ar_queue.len ), + .ax_id_i ( axi_wide_ar_queue.id ), + .ax_dest_i ( dst_id[WideAr] ), + .ax_valid_o ( wide_ar_rob_valid_out ), + .ax_ready_i ( wide_ar_rob_ready_in ), + .ax_rob_req_o ( wide_ar_rob_req_out ), + .ax_rob_idx_o ( wide_ar_rob_idx_out ), + .rsp_valid_i ( wide_r_rob_valid_in ), + .rsp_ready_o ( wide_r_rob_ready_out ), + .rsp_i ( axi_wide_r_rob_in ), + .rsp_rob_req_i ( wide_r_rob_rob_req ), + .rsp_rob_idx_i ( wide_r_rob_rob_idx ), + .rsp_last_i ( wide_r_rob_last ), + .rsp_valid_o ( wide_r_rob_valid_out ), + .rsp_ready_i ( wide_r_rob_ready_in ), + .rsp_o ( axi_wide_r_rob_out ) ); end @@ -621,46 +631,70 @@ module floo_narrow_wide_chimney xy_id_t narrow_aw_xy_id_q, narrow_aw_xy_id, narrow_ar_xy_id; xy_id_t wide_aw_xy_id_q, wide_aw_xy_id, wide_ar_xy_id; assign src_id = xy_id_i; - assign narrow_aw_xy_id.x = narrow_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; - assign narrow_aw_xy_id.y = narrow_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; - assign narrow_ar_xy_id.x = narrow_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; - assign narrow_ar_xy_id.y = narrow_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; - assign wide_aw_xy_id.x = wide_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; - assign wide_aw_xy_id.y = wide_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; - assign wide_ar_xy_id.x = wide_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; - assign wide_ar_xy_id.y = wide_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; - assign dst_id[NarrowInAw] = narrow_aw_xy_id; - assign dst_id[NarrowInAr] = narrow_ar_xy_id; - assign dst_id[NarrowInW] = narrow_aw_xy_id_q; - assign dst_id[NarrowInB] = narrow_aw_out_data_out.src_id; - assign dst_id[NarrowInR] = narrow_ar_out_data_out.src_id; - assign dst_id[WideInAw] = wide_aw_xy_id; - assign dst_id[WideInAr] = wide_ar_xy_id; - assign dst_id[WideInW] = wide_aw_xy_id_q; - assign dst_id[WideInB] = wide_aw_out_data_out.src_id; - assign dst_id[WideInR] = wide_ar_out_data_out.src_id; - `FFL(narrow_aw_xy_id_q,narrow_aw_xy_id,narrow_aw_queue_valid_out && narrow_aw_queue_ready_in,'0) - `FFL(wide_aw_xy_id_q, wide_aw_xy_id, wide_aw_queue_valid_out && wide_aw_queue_ready_in, '0) + assign narrow_aw_xy_id.x = axi_narrow_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; + assign narrow_aw_xy_id.y = axi_narrow_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; + assign narrow_ar_xy_id.x = axi_narrow_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; + assign narrow_ar_xy_id.y = axi_narrow_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; + assign wide_aw_xy_id.x = axi_wide_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; + assign wide_aw_xy_id.y = axi_wide_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; + assign wide_ar_xy_id.x = axi_wide_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)]; + assign wide_ar_xy_id.y = axi_wide_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)]; + assign dst_id[NarrowAw] = narrow_aw_xy_id; + assign dst_id[NarrowAr] = narrow_ar_xy_id; + assign dst_id[NarrowW] = narrow_aw_xy_id_q; + assign dst_id[NarrowB] = narrow_aw_out_data_out.src_id; + assign dst_id[NarrowR] = narrow_ar_out_data_out.src_id; + assign dst_id[WideAw] = wide_aw_xy_id; + assign dst_id[WideAr] = wide_ar_xy_id; + assign dst_id[WideW] = wide_aw_xy_id_q; + assign dst_id[WideB] = wide_aw_out_data_out.src_id; + assign dst_id[WideR] = wide_ar_out_data_out.src_id; + `FFL(narrow_aw_xy_id_q,narrow_aw_xy_id, axi_narrow_aw_queue_valid_out && + axi_narrow_aw_queue_ready_in,'0) + `FFL(wide_aw_xy_id_q, wide_aw_xy_id, axi_wide_aw_queue_valid_out && + axi_wide_aw_queue_ready_in, '0) end else if (RouteAlgo == IdTable) begin : gen_id_table_routing - id_t narrow_aw_id_q, narrow_aw_id, narrow_ar_id; - id_t wide_aw_id_q, wide_aw_id, wide_ar_id; + typedef enum logic [1:0] {NarrowAwReq, NarrowArReq, WideAwReq, WideArReq} axi_req_ch_e; + id_t narrow_aw_id_q, wide_aw_id_q; + axi_narrow_in_addr_t [WideArReq:NarrowAwReq] decode_addr_in; + id_t [WideArReq:NarrowAwReq] dst_addr_out; + + assign decode_addr_in[NarrowAwReq] = axi_narrow_aw_queue.addr; + assign decode_addr_in[NarrowArReq] = axi_narrow_ar_queue.addr; + assign decode_addr_in[WideAwReq] = axi_wide_aw_queue.addr; + assign decode_addr_in[WideArReq] = axi_wide_ar_queue.addr; + + addr_decode #( + .NoIndices ( NumIDs ), + .NoRules ( NumRules ), + .addr_t ( axi_narrow_in_addr_t ), + .rule_t ( id_rule_t ), + .idx_t ( id_t ) + ) i_addr_dst_decode [3:0] ( + .addr_i ( decode_addr_in ), + .addr_map_i ( id_map_i ), + .idx_o ( dst_addr_out ), + .dec_valid_o ( ), + .dec_error_o ( ), + .en_default_idx_i ( 1'b0 ), + .default_idx_i ( '0 ) + ); + assign src_id = id_i; - assign narrow_aw_id = narrow_aw_queue.addr[IdTableAddrOffset+:$bits(id_i)]; - assign narrow_ar_id = narrow_ar_queue.addr[IdTableAddrOffset+:$bits(id_i)]; - assign wide_aw_id = wide_aw_queue.addr[IdTableAddrOffset+:$bits(id_i)]; - assign wide_ar_id = wide_ar_queue.addr[IdTableAddrOffset+:$bits(id_i)]; - assign dst_id[NarrowInAw] = narrow_aw_id; - assign dst_id[NarrowInAr] = narrow_ar_id; - assign dst_id[NarrowInW] = narrow_aw_id_q; - assign dst_id[NarrowInB] = narrow_aw_out_data_out.src_id; - assign dst_id[NarrowInR] = narrow_ar_out_data_out.src_id; - assign dst_id[WideInAw] = wide_aw_id; - assign dst_id[WideInAr] = wide_ar_id; - assign dst_id[WideInW] = wide_aw_id_q; - assign dst_id[WideInB] = wide_aw_out_data_out.src_id; - assign dst_id[WideInR] = wide_ar_out_data_out.src_id; - `FFL(narrow_aw_id_q, narrow_aw_id, narrow_aw_queue_valid_out && narrow_aw_queue_ready_in, '0) - `FFL(wide_aw_id_q, wide_aw_id, wide_aw_queue_valid_out && wide_aw_queue_ready_in, '0) + assign dst_id[NarrowAw] = dst_addr_out[NarrowAwReq]; + assign dst_id[NarrowW] = narrow_aw_id_q; + assign dst_id[NarrowAr] = dst_addr_out[NarrowArReq]; + assign dst_id[NarrowB] = narrow_aw_out_data_out.src_id; + assign dst_id[NarrowR] = narrow_ar_out_data_out.src_id; + assign dst_id[WideAw] = dst_addr_out[WideAwReq]; + assign dst_id[WideW] = wide_aw_id_q; + assign dst_id[WideAr] = dst_addr_out[WideArReq]; + assign dst_id[WideB] = wide_aw_out_data_out.src_id; + assign dst_id[WideR] = wide_ar_out_data_out.src_id; + `FFL(narrow_aw_id_q, dst_id[NarrowAw], axi_narrow_aw_queue_valid_out && + axi_narrow_aw_queue_ready_in, '0) + `FFL(wide_aw_id_q, dst_id[WideAw], axi_wide_aw_queue_valid_out && + axi_wide_aw_queue_ready_in, '0) end else begin : gen_no_routing // TODO: Implement other routing algorithms $fatal(1, "Routing algorithm not implemented"); @@ -671,135 +705,136 @@ module floo_narrow_wide_chimney /////////////////// always_comb begin - narrow_aw_data = '0; - narrow_aw_data.rob_req = narrow_aw_rob_req_out; - narrow_aw_data.rob_idx = rob_idx_t'(narrow_aw_rob_idx_out); - narrow_aw_data.dst_id = dst_id[NarrowInAw]; - narrow_aw_data.src_id = src_id; - narrow_aw_data.last = 1'b1; - narrow_aw_data.axi_ch = NarrowInAw; - narrow_aw_data.aw = narrow_aw_queue; - narrow_aw_data.atop = narrow_aw_queue.atop != axi_pkg::ATOP_NONE; + floo_narrow_aw = '0; + floo_narrow_aw.hdr.rob_req = narrow_aw_rob_req_out; + floo_narrow_aw.hdr.rob_idx = rob_idx_t'(narrow_aw_rob_idx_out); + floo_narrow_aw.hdr.dst_id = dst_id[NarrowAw]; + floo_narrow_aw.hdr.src_id = src_id; + floo_narrow_aw.hdr.last = 1'b1; + floo_narrow_aw.hdr.axi_ch = NarrowAw; + floo_narrow_aw.hdr.atop = axi_narrow_aw_queue.atop != axi_pkg::ATOP_NONE; + floo_narrow_aw.aw = axi_narrow_aw_queue; end always_comb begin - narrow_w_data = '0; - narrow_w_data.rob_req = narrow_aw_rob_req_out; - narrow_w_data.rob_idx = rob_idx_t'(narrow_aw_rob_idx_out); - narrow_w_data.dst_id = dst_id[NarrowInW]; - narrow_w_data.src_id = src_id; - narrow_w_data.last = narrow_in_req_i.w.last; - narrow_w_data.axi_ch = NarrowInW; - narrow_w_data.w = narrow_in_req_i.w; + floo_narrow_w = '0; + floo_narrow_w.hdr.rob_req = narrow_aw_rob_req_out; + floo_narrow_w.hdr.rob_idx = rob_idx_t'(narrow_aw_rob_idx_out); + floo_narrow_w.hdr.dst_id = dst_id[NarrowW]; + floo_narrow_w.hdr.src_id = src_id; + floo_narrow_w.hdr.last = axi_narrow_in_req_i.w.last; + floo_narrow_w.hdr.axi_ch = NarrowW; + floo_narrow_w.w = axi_narrow_in_req_i.w; end always_comb begin - narrow_ar_data = '0; - narrow_ar_data.rob_req = narrow_ar_rob_req_out; - narrow_ar_data.rob_idx = rob_idx_t'(narrow_ar_rob_idx_out); - narrow_ar_data.dst_id = dst_id[NarrowInAr]; - narrow_ar_data.src_id = src_id; - narrow_ar_data.last = 1'b1; - narrow_ar_data.axi_ch = NarrowInAr; - narrow_ar_data.ar = narrow_ar_queue; + floo_narrow_ar = '0; + floo_narrow_ar.hdr.rob_req = narrow_ar_rob_req_out; + floo_narrow_ar.hdr.rob_idx = rob_idx_t'(narrow_ar_rob_idx_out); + floo_narrow_ar.hdr.dst_id = dst_id[NarrowAr]; + floo_narrow_ar.hdr.src_id = src_id; + floo_narrow_ar.hdr.last = 1'b1; + floo_narrow_ar.hdr.axi_ch = NarrowAr; + floo_narrow_ar.ar = axi_narrow_ar_queue; end always_comb begin - narrow_b_data = '0; - narrow_b_data.rob_req = narrow_aw_out_data_out.rob_req; - narrow_b_data.rob_idx = rob_idx_t'(narrow_aw_out_data_out.rob_idx); - narrow_b_data.dst_id = narrow_aw_out_data_out.src_id; - narrow_b_data.src_id = src_id; - narrow_b_data.last = 1'b1; - narrow_b_data.axi_ch = NarrowInB; - narrow_b_data.b = narrow_out_rsp_id_mapped.b; - narrow_b_data.b.id = narrow_aw_out_data_out.id; - narrow_b_data.atop = narrow_aw_out_data_out.atop; + floo_narrow_b = '0; + floo_narrow_b.hdr.rob_req = narrow_aw_out_data_out.rob_req; + floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_out_data_out.rob_idx); + floo_narrow_b.hdr.dst_id = narrow_aw_out_data_out.src_id; + floo_narrow_b.hdr.src_id = src_id; + floo_narrow_b.hdr.last = 1'b1; + floo_narrow_b.hdr.axi_ch = NarrowB; + floo_narrow_b.hdr.atop = narrow_aw_out_data_out.atop; + floo_narrow_b.b = axi_narrow_out_rsp_id_mapped.b; + floo_narrow_b.b.id = narrow_aw_out_data_out.id; end always_comb begin - narrow_r_data = '0; - narrow_r_data.rob_req = narrow_ar_out_data_out.rob_req; - narrow_r_data.rob_idx = rob_idx_t'(narrow_ar_out_data_out.rob_idx); - narrow_r_data.dst_id = narrow_ar_out_data_out.src_id; - narrow_r_data.src_id = src_id; - narrow_r_data.axi_ch = NarrowInR; - narrow_r_data.last = narrow_out_rsp_i.r.last; - narrow_r_data.r = narrow_out_rsp_id_mapped.r; - narrow_r_data.r.id = narrow_ar_out_data_out.id; - narrow_r_data.atop = narrow_ar_out_data_out.atop; + floo_narrow_r = '0; + floo_narrow_r.hdr.rob_req = narrow_ar_out_data_out.rob_req; + floo_narrow_r.hdr.rob_idx = rob_idx_t'(narrow_ar_out_data_out.rob_idx); + floo_narrow_r.hdr.dst_id = narrow_ar_out_data_out.src_id; + floo_narrow_r.hdr.src_id = src_id; + floo_narrow_r.hdr.axi_ch = NarrowR; + floo_narrow_r.hdr.last = axi_narrow_out_rsp_i.r.last; + floo_narrow_r.hdr.atop = narrow_ar_out_data_out.atop; + floo_narrow_r.r = axi_narrow_out_rsp_id_mapped.r; + floo_narrow_r.r.id = narrow_ar_out_data_out.id; end always_comb begin - wide_aw_data = '0; - wide_aw_data.rob_req = wide_aw_rob_req_out; - wide_aw_data.rob_idx = rob_idx_t'(wide_aw_rob_idx_out); - wide_aw_data.dst_id = dst_id[WideInAw]; - wide_aw_data.src_id = src_id; - wide_aw_data.last = 1'b1; - wide_aw_data.axi_ch = WideInAw; - wide_aw_data.aw = wide_aw_queue; + floo_wide_aw = '0; + floo_wide_aw.hdr.rob_req = wide_aw_rob_req_out; + floo_wide_aw.hdr.rob_idx = rob_idx_t'(wide_aw_rob_idx_out); + floo_wide_aw.hdr.dst_id = dst_id[WideAw]; + floo_wide_aw.hdr.src_id = src_id; + floo_wide_aw.hdr.last = 1'b1; + floo_wide_aw.hdr.axi_ch = WideAw; + floo_wide_aw.aw = axi_wide_aw_queue; end always_comb begin - wide_w_data = '0; - wide_w_data.rob_req = wide_aw_rob_req_out; - wide_w_data.rob_idx = rob_idx_t'(wide_aw_rob_idx_out); - wide_w_data.dst_id = dst_id[WideInW]; - wide_w_data.src_id = src_id; - wide_w_data.last = wide_in_req_i.w.last; - wide_w_data.axi_ch = WideInW; - wide_w_data.w = wide_in_req_i.w; + floo_wide_w = '0; + floo_wide_w.hdr.rob_req = wide_aw_rob_req_out; + floo_wide_w.hdr.rob_idx = rob_idx_t'(wide_aw_rob_idx_out); + floo_wide_w.hdr.dst_id = dst_id[WideW]; + floo_wide_w.hdr.src_id = src_id; + floo_wide_w.hdr.last = axi_wide_in_req_i.w.last; + floo_wide_w.hdr.axi_ch = WideW; + floo_wide_w.w = axi_wide_in_req_i.w; end always_comb begin - wide_ar_data = '0; - wide_ar_data.rob_req = wide_ar_rob_req_out; - wide_ar_data.rob_idx = rob_idx_t'(wide_ar_rob_idx_out); - wide_ar_data.dst_id = dst_id[WideInAr]; - wide_ar_data.src_id = src_id; - wide_ar_data.last = 1'b1; - wide_ar_data.axi_ch = WideInAr; - wide_ar_data.ar = wide_ar_queue; + floo_wide_ar = '0; + floo_wide_ar.hdr.rob_req = wide_ar_rob_req_out; + floo_wide_ar.hdr.rob_idx = rob_idx_t'(wide_ar_rob_idx_out); + floo_wide_ar.hdr.dst_id = dst_id[WideAr]; + floo_wide_ar.hdr.src_id = src_id; + floo_wide_ar.hdr.last = 1'b1; + floo_wide_ar.hdr.axi_ch = WideAr; + floo_wide_ar.ar = axi_wide_ar_queue; end always_comb begin - wide_b_data = '0; - wide_b_data.rob_req = wide_aw_out_data_out.rob_req; - wide_b_data.rob_idx = rob_idx_t'(wide_aw_out_data_out.rob_idx); - wide_b_data.dst_id = wide_aw_out_data_out.src_id; - wide_b_data.src_id = src_id; - wide_b_data.last = 1'b1; - wide_b_data.axi_ch = WideInB; - wide_b_data.b = wide_out_rsp_id_mapped.b; - wide_b_data.b.id = wide_aw_out_data_out.id; + floo_wide_b = '0; + floo_wide_b.hdr.rob_req = wide_aw_out_data_out.rob_req; + floo_wide_b.hdr.rob_idx = rob_idx_t'(wide_aw_out_data_out.rob_idx); + floo_wide_b.hdr.dst_id = wide_aw_out_data_out.src_id; + floo_wide_b.hdr.src_id = src_id; + floo_wide_b.hdr.last = 1'b1; + floo_wide_b.hdr.axi_ch = WideB; + floo_wide_b.b = axi_wide_out_rsp_id_mapped.b; + floo_wide_b.b.id = wide_aw_out_data_out.id; end always_comb begin - wide_r_data = '0; - wide_r_data.rob_req = wide_ar_out_data_out.rob_req; - wide_r_data.rob_idx = rob_idx_t'(wide_ar_out_data_out.rob_idx); - wide_r_data.dst_id = wide_ar_out_data_out.src_id; - wide_r_data.src_id = src_id; - wide_r_data.axi_ch = WideInR; - wide_r_data.last = wide_out_rsp_i.r.last; - wide_r_data.r = wide_out_rsp_id_mapped.r; - wide_r_data.r.id = wide_ar_out_data_out.id; + floo_wide_r = '0; + floo_wide_r.hdr.rob_req = wide_ar_out_data_out.rob_req; + floo_wide_r.hdr.rob_idx = rob_idx_t'(wide_ar_out_data_out.rob_idx); + floo_wide_r.hdr.dst_id = wide_ar_out_data_out.src_id; + floo_wide_r.hdr.src_id = src_id; + floo_wide_r.hdr.axi_ch = WideR; + floo_wide_r.hdr.last = axi_wide_out_rsp_i.r.last; + floo_wide_r.r = axi_wide_out_rsp_id_mapped.r; + floo_wide_r.r.id = wide_ar_out_data_out.id; end always_comb begin narrow_aw_w_sel_d = narrow_aw_w_sel_q; wide_aw_w_sel_d = wide_aw_w_sel_q; - if (narrow_aw_queue_valid_out && narrow_aw_queue_ready_in) begin + if (axi_narrow_aw_queue_valid_out && axi_narrow_aw_queue_ready_in) begin narrow_aw_w_sel_d = SelW; end - if (narrow_in_req_i.w_valid && narrow_in_rsp_o.w_ready && narrow_in_req_i.w.last) begin + if (axi_narrow_in_req_i.w_valid && axi_narrow_in_rsp_o.w_ready && + axi_narrow_in_req_i.w.last) begin narrow_aw_w_sel_d = SelAw; end - if (wide_aw_queue_valid_out && wide_aw_queue_ready_in) begin + if (axi_wide_aw_queue_valid_out && axi_wide_aw_queue_ready_in) begin wide_aw_w_sel_d = SelW; end - if (wide_in_req_i.w_valid && wide_in_rsp_o.w_ready && wide_in_req_i.w.last) begin + if (axi_wide_in_req_i.w_valid && axi_wide_in_rsp_o.w_ready && axi_wide_in_req_i.w.last) begin wide_aw_w_sel_d = SelAw; end end @@ -807,93 +842,93 @@ module floo_narrow_wide_chimney `FF(narrow_aw_w_sel_q, narrow_aw_w_sel_d, SelAw) `FF(wide_aw_w_sel_q, wide_aw_w_sel_d, SelAw) - assign narrow_req_data_arb_req_in[NarrowInAw] = (narrow_aw_w_sel_q == SelAw) && - (narrow_aw_rob_valid_out || - ((narrow_aw_queue.atop != axi_pkg::ATOP_NONE) && - narrow_aw_queue_valid_out)); - assign narrow_req_data_arb_req_in[NarrowInW] = (narrow_aw_w_sel_q == SelW) && - narrow_in_req_i.w_valid; - assign narrow_req_data_arb_req_in[NarrowInAr] = narrow_ar_rob_valid_out; - assign narrow_req_data_arb_req_in[WideInAw] = (wide_aw_w_sel_q == SelAw) && - wide_aw_rob_valid_out; - assign narrow_req_data_arb_req_in[WideInAr] = wide_ar_rob_valid_out; - assign narrow_rsp_data_arb_req_in[NarrowInB] = narrow_out_rsp_i.b_valid; - assign narrow_rsp_data_arb_req_in[NarrowInR] = narrow_out_rsp_i.r_valid; - assign narrow_rsp_data_arb_req_in[WideInB] = wide_out_rsp_i.b_valid; - assign wide_data_arb_req_in[WideInW] = (wide_aw_w_sel_q == SelW) && - wide_in_req_i.w_valid; - assign wide_data_arb_req_in[WideInR] = wide_out_rsp_i.r_valid; - - assign narrow_aw_rob_ready_in = narrow_req_data_arb_gnt_out[NarrowInAw] && - (narrow_aw_w_sel_q == SelAw); - assign narrow_in_rsp_o.w_ready = narrow_req_data_arb_gnt_out[NarrowInW] && - (narrow_aw_w_sel_q == SelW); - assign narrow_ar_rob_ready_in = narrow_req_data_arb_gnt_out[NarrowInAr]; - assign narrow_out_req_id_mapped.b_ready = narrow_rsp_data_arb_gnt_out[NarrowInB]; - assign narrow_out_req_id_mapped.r_ready = narrow_rsp_data_arb_gnt_out[NarrowInR]; - assign wide_aw_rob_ready_in = narrow_req_data_arb_gnt_out[WideInAw] && - (wide_aw_w_sel_q == SelAw); - assign wide_in_rsp_o.w_ready = wide_data_arb_gnt_out[WideInW] && - (wide_aw_w_sel_q == SelW); - assign wide_ar_rob_ready_in = narrow_req_data_arb_gnt_out[WideInAr]; - assign wide_out_req_id_mapped.b_ready = narrow_rsp_data_arb_gnt_out[WideInB]; - assign wide_out_req_id_mapped.r_ready = wide_data_arb_gnt_out[WideInR]; - - assign narrow_req_data_arb_data_in[NarrowInAw].narrow_in_aw = narrow_aw_data; - assign narrow_req_data_arb_data_in[NarrowInW].narrow_in_w = narrow_w_data; - assign narrow_req_data_arb_data_in[NarrowInAr].narrow_in_ar = narrow_ar_data; - assign narrow_req_data_arb_data_in[WideInAw].wide_in_aw = wide_aw_data; - assign narrow_req_data_arb_data_in[WideInAr].wide_in_ar = wide_ar_data; - assign narrow_rsp_data_arb_data_in[NarrowInB].narrow_in_b = narrow_b_data; - assign narrow_rsp_data_arb_data_in[NarrowInR].narrow_in_r = narrow_r_data; - assign narrow_rsp_data_arb_data_in[WideInB].wide_in_b = wide_b_data; - assign wide_data_arb_data_in[WideInW].wide_in_w = wide_w_data; - assign wide_data_arb_data_in[WideInR].wide_in_r = wide_r_data; + assign floo_req_arb_req_in[NarrowAw] = (narrow_aw_w_sel_q == SelAw) && + (narrow_aw_rob_valid_out || + ((axi_narrow_aw_queue.atop != axi_pkg::ATOP_NONE) && + axi_narrow_aw_queue_valid_out)); + assign floo_req_arb_req_in[NarrowW] = (narrow_aw_w_sel_q == SelW) && + axi_narrow_in_req_i.w_valid; + assign floo_req_arb_req_in[NarrowAr] = narrow_ar_rob_valid_out; + assign floo_req_arb_req_in[WideAw] = (wide_aw_w_sel_q == SelAw) && + wide_aw_rob_valid_out; + assign floo_req_arb_req_in[WideAr] = wide_ar_rob_valid_out; + assign floo_rsp_arb_req_in[NarrowB] = axi_narrow_out_rsp_i.b_valid; + assign floo_rsp_arb_req_in[NarrowR] = axi_narrow_out_rsp_i.r_valid; + assign floo_rsp_arb_req_in[WideB] = axi_wide_out_rsp_i.b_valid; + assign floo_wide_arb_req_in[WideW] = (wide_aw_w_sel_q == SelW) && + axi_wide_in_req_i.w_valid; + assign floo_wide_arb_req_in[WideR] = axi_wide_out_rsp_i.r_valid; + + assign narrow_aw_rob_ready_in = floo_req_arb_gnt_out[NarrowAw] && + (narrow_aw_w_sel_q == SelAw); + assign axi_narrow_in_rsp_o.w_ready = floo_req_arb_gnt_out[NarrowW] && + (narrow_aw_w_sel_q == SelW); + assign narrow_ar_rob_ready_in = floo_req_arb_gnt_out[NarrowAr]; + assign axi_narrow_out_req_id_mapped.b_ready = floo_rsp_arb_gnt_out[NarrowB]; + assign axi_narrow_out_req_id_mapped.r_ready = floo_rsp_arb_gnt_out[NarrowR]; + assign wide_aw_rob_ready_in = floo_req_arb_gnt_out[WideAw] && + (wide_aw_w_sel_q == SelAw); + assign axi_wide_in_rsp_o.w_ready = floo_wide_arb_gnt_out[WideW] && + (wide_aw_w_sel_q == SelW); + assign wide_ar_rob_ready_in = floo_req_arb_gnt_out[WideAr]; + assign axi_wide_out_req_id_mapped.b_ready = floo_rsp_arb_gnt_out[WideB]; + assign axi_wide_out_req_id_mapped.r_ready = floo_wide_arb_gnt_out[WideR]; + + assign floo_req_arb_in[NarrowAw].narrow_aw = floo_narrow_aw; + assign floo_req_arb_in[NarrowW].narrow_w = floo_narrow_w; + assign floo_req_arb_in[NarrowAr].narrow_ar = floo_narrow_ar; + assign floo_req_arb_in[WideAw].wide_aw = floo_wide_aw; + assign floo_req_arb_in[WideAr].wide_ar = floo_wide_ar; + assign floo_rsp_arb_in[NarrowB].narrow_b = floo_narrow_b; + assign floo_rsp_arb_in[NarrowR].narrow_r = floo_narrow_r; + assign floo_rsp_arb_in[WideB].wide_b = floo_wide_b; + assign floo_wide_arb_in[WideW].wide_w = floo_wide_w; + assign floo_wide_arb_in[WideR].wide_r = floo_wide_r; /////////////////////// // FLIT ARBITRATION // /////////////////////// floo_wormhole_arbiter #( - .NumRoutes ( NumVirtPerPhys[PhysNarrowReq] ), - .flit_t ( narrow_req_generic_t ) - ) i_narrow_req_wormhole_arbiter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( narrow_req_data_arb_req_in ), - .data_i ( narrow_req_data_arb_data_in ), - .ready_o ( narrow_req_data_arb_gnt_out ), - .data_o ( narrow_req_o.data ), - .ready_i ( narrow_req_i.ready ), - .valid_o ( narrow_req_o.valid ) + .NumRoutes ( 5 ), + .flit_t ( floo_req_generic_flit_t ) + ) i_req_wormhole_arbiter ( + .clk_i, + .rst_ni, + .valid_i ( floo_req_arb_req_in ), + .data_i ( floo_req_arb_in ), + .ready_o ( floo_req_arb_gnt_out ), + .data_o ( floo_req_o.req ), + .ready_i ( floo_req_i.ready ), + .valid_o ( floo_req_o.valid ) ); floo_wormhole_arbiter #( - .NumRoutes ( NumVirtPerPhys[PhysNarrowRsp] ), - .flit_t ( narrow_rsp_generic_t ) - ) i_narrow_rsp_wormhole_arbiter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( narrow_rsp_data_arb_req_in ), - .data_i ( narrow_rsp_data_arb_data_in ), - .ready_o ( narrow_rsp_data_arb_gnt_out ), - .data_o ( narrow_rsp_o.data ), - .ready_i ( narrow_rsp_i.ready ), - .valid_o ( narrow_rsp_o.valid ) + .NumRoutes ( 3 ), + .flit_t ( floo_rsp_generic_flit_t ) + ) i_rsp_wormhole_arbiter ( + .clk_i, + .rst_ni, + .valid_i ( floo_rsp_arb_req_in ), + .data_i ( floo_rsp_arb_in ), + .ready_o ( floo_rsp_arb_gnt_out ), + .data_o ( floo_rsp_o.rsp ), + .ready_i ( floo_rsp_i.ready ), + .valid_o ( floo_rsp_o.valid ) ); floo_wormhole_arbiter #( - .NumRoutes ( NumVirtPerPhys[PhysWide] ), - .flit_t ( wide_generic_t ) + .NumRoutes ( 2 ), + .flit_t ( floo_wide_generic_flit_t ) ) i_wide_wormhole_arbiter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( wide_data_arb_req_in ), - .data_i ( wide_data_arb_data_in ), - .ready_o ( wide_data_arb_gnt_out ), - .data_o ( wide_o.data ), - .ready_i ( wide_i.ready ), - .valid_o ( wide_o.valid ) + .clk_i, + .rst_ni, + .valid_i ( floo_wide_arb_req_in ), + .data_i ( floo_wide_arb_in ), + .ready_o ( floo_wide_arb_gnt_out ), + .data_o ( floo_wide_o.wide ), + .ready_i ( floo_wide_i.ready ), + .valid_o ( floo_wide_o.valid ) ); //////////////////// @@ -904,148 +939,152 @@ module floo_narrow_wide_chimney logic b_sel_atop, r_sel_atop; logic b_rob_pending_q, r_rob_pending_q; - assign is_atop_b_rsp = AtopSupport && axi_valid_in[NarrowInB] && narrow_unpack_rsp_generic.atop; - assign is_atop_r_rsp = AtopSupport && axi_valid_in[NarrowInR] && narrow_unpack_rsp_generic.atop; + assign is_atop_b_rsp = AtopSupport && axi_valid_in[NarrowB] && + floo_narrow_unpack_rsp_generic.hdr.atop; + assign is_atop_r_rsp = AtopSupport && axi_valid_in[NarrowR] && + floo_narrow_unpack_rsp_generic.hdr.atop; assign b_sel_atop = is_atop_b_rsp && !b_rob_pending_q; assign r_sel_atop = is_atop_r_rsp && !r_rob_pending_q; - assign narrow_unpack_aw_data = narrow_req_in.data.narrow_in_aw.aw; - assign narrow_unpack_w_data = narrow_req_in.data.narrow_in_w.w; - assign narrow_unpack_ar_data = narrow_req_in.data.narrow_in_ar.ar; - assign narrow_unpack_r_data = narrow_rsp_in.data.narrow_in_r.r; - assign narrow_unpack_b_data = narrow_rsp_in.data.narrow_in_b.b; - assign wide_unpack_aw_data = narrow_req_in.data.wide_in_aw.aw; - assign wide_unpack_w_data = wide_in.data.wide_in_w.w; - assign wide_unpack_ar_data = narrow_req_in.data.wide_in_ar.ar; - assign wide_unpack_r_data = wide_in.data.wide_in_r.r; - assign wide_unpack_b_data = narrow_rsp_in.data.wide_in_b.b; - assign narrow_unpack_req_generic = narrow_req_in.data.gen; - assign narrow_unpack_rsp_generic = narrow_rsp_in.data.gen; - assign wide_unpack_generic = wide_in.data.gen; - - - assign axi_valid_in[NarrowInAw] = narrow_req_in.valid && - (narrow_unpack_req_generic.axi_ch == NarrowInAw); - assign axi_valid_in[NarrowInW] = narrow_req_in.valid && - (narrow_unpack_req_generic.axi_ch == NarrowInW); - assign axi_valid_in[NarrowInAr] = narrow_req_in.valid && - (narrow_unpack_req_generic.axi_ch == NarrowInAr); - assign axi_valid_in[WideInAw] = narrow_req_in.valid && - (narrow_unpack_req_generic.axi_ch == WideInAw); - assign axi_valid_in[WideInAr] = narrow_req_in.valid && - (narrow_unpack_req_generic.axi_ch == WideInAr); - assign axi_valid_in[NarrowInB] = narrow_rsp_in.valid && - (narrow_unpack_rsp_generic.axi_ch == NarrowInB); - assign axi_valid_in[NarrowInR] = narrow_rsp_in.valid && - (narrow_unpack_rsp_generic.axi_ch == NarrowInR); - assign axi_valid_in[WideInB] = narrow_rsp_in.valid && - (narrow_unpack_rsp_generic.axi_ch == WideInB); - assign axi_valid_in[WideInW] = wide_in.valid && - (wide_unpack_generic.axi_ch == WideInW); - assign axi_valid_in[WideInR] = wide_in.valid && - (wide_unpack_generic.axi_ch == WideInR); - - assign axi_ready_out[NarrowInAw] = narrow_out_rsp_i.aw_ready && !narrow_aw_out_full; - assign axi_ready_out[NarrowInW] = narrow_out_rsp_i.w_ready; - assign axi_ready_out[NarrowInAr] = narrow_out_rsp_i.ar_ready && !narrow_ar_out_full; - assign axi_ready_out[NarrowInB] = narrow_b_rob_ready_out || - b_sel_atop && narrow_in_req_i.b_ready; - assign axi_ready_out[NarrowInR] = narrow_r_rob_ready_out || - r_sel_atop && narrow_in_req_i.r_ready; - assign axi_ready_out[WideInAw] = wide_out_rsp_i.aw_ready && !wide_aw_out_full; - assign axi_ready_out[WideInW] = wide_out_rsp_i.w_ready; - assign axi_ready_out[WideInAr] = wide_out_rsp_i.ar_ready&& !wide_ar_out_full; - assign axi_ready_out[WideInB] = wide_b_rob_ready_out; - assign axi_ready_out[WideInR] = wide_r_rob_ready_out; - - assign narrow_req_ready_out = axi_ready_out[narrow_unpack_req_generic.axi_ch]; - assign narrow_rsp_ready_out = axi_ready_out[narrow_unpack_rsp_generic.axi_ch]; - assign wide_ready_out = axi_ready_out[wide_unpack_generic.axi_ch]; + assign axi_narrow_unpack_aw = floo_req_in.narrow_aw.aw; + assign axi_narrow_unpack_w = floo_req_in.narrow_w.w; + assign axi_narrow_unpack_ar = floo_req_in.narrow_ar.ar; + assign axi_narrow_unpack_r = floo_rsp_in.narrow_r.r; + assign axi_narrow_unpack_b = floo_rsp_in.narrow_b.b; + assign axi_wide_unpack_aw = floo_req_in.wide_aw.aw; + assign axi_wide_unpack_w = floo_wide_in.wide_w.w; + assign axi_wide_unpack_ar = floo_req_in.wide_ar.ar; + assign axi_wide_unpack_r = floo_wide_in.wide_r.r; + assign axi_wide_unpack_b = floo_rsp_in.wide_b.b; + assign floo_narrow_unpack_req_generic = floo_req_in.generic; + assign floo_narrow_unpack_rsp_generic = floo_rsp_in.generic; + assign floo_wide_unpack_generic = floo_wide_in.generic; + + + assign axi_valid_in[NarrowAw] = floo_req_in_valid && + (floo_narrow_unpack_req_generic.hdr.axi_ch == NarrowAw); + assign axi_valid_in[NarrowW] = floo_req_in_valid && + (floo_narrow_unpack_req_generic.hdr.axi_ch == NarrowW); + assign axi_valid_in[NarrowAr] = floo_req_in_valid && + (floo_narrow_unpack_req_generic.hdr.axi_ch == NarrowAr); + assign axi_valid_in[WideAw] = floo_req_in_valid && + (floo_narrow_unpack_req_generic.hdr.axi_ch == WideAw); + assign axi_valid_in[WideAr] = floo_req_in_valid && + (floo_narrow_unpack_req_generic.hdr.axi_ch == WideAr); + assign axi_valid_in[NarrowB] = floo_rsp_in_valid && + (floo_narrow_unpack_rsp_generic.hdr.axi_ch == NarrowB); + assign axi_valid_in[NarrowR] = floo_rsp_in_valid && + (floo_narrow_unpack_rsp_generic.hdr.axi_ch == NarrowR); + assign axi_valid_in[WideB] = floo_rsp_in_valid && + (floo_narrow_unpack_rsp_generic.hdr.axi_ch == WideB); + assign axi_valid_in[WideW] = floo_wide_in_valid && + (floo_wide_unpack_generic.hdr.axi_ch == WideW); + assign axi_valid_in[WideR] = floo_wide_in_valid && + (floo_wide_unpack_generic.hdr.axi_ch == WideR); + + assign axi_ready_out[NarrowAw] = axi_narrow_out_rsp_i.aw_ready && !narrow_aw_out_full; + assign axi_ready_out[NarrowW] = axi_narrow_out_rsp_i.w_ready; + assign axi_ready_out[NarrowAr] = axi_narrow_out_rsp_i.ar_ready && !narrow_ar_out_full; + assign axi_ready_out[NarrowB] = narrow_b_rob_ready_out || + b_sel_atop && axi_narrow_in_req_i.b_ready; + assign axi_ready_out[NarrowR] = narrow_r_rob_ready_out || + r_sel_atop && axi_narrow_in_req_i.r_ready; + assign axi_ready_out[WideAw] = axi_wide_out_rsp_i.aw_ready && !wide_aw_out_full; + assign axi_ready_out[WideW] = axi_wide_out_rsp_i.w_ready; + assign axi_ready_out[WideAr] = axi_wide_out_rsp_i.ar_ready&& !wide_ar_out_full; + assign axi_ready_out[WideB] = wide_b_rob_ready_out; + assign axi_ready_out[WideR] = wide_r_rob_ready_out; + + assign floo_req_out_ready = axi_ready_out[floo_narrow_unpack_req_generic.hdr.axi_ch]; + assign floo_rsp_out_ready = axi_ready_out[floo_narrow_unpack_rsp_generic.hdr.axi_ch]; + assign floo_wide_out_ready = axi_ready_out[floo_wide_unpack_generic.hdr.axi_ch]; ///////////////////////////// // AXI req/rsp generation // //////////////////////////// - assign narrow_out_req_id_mapped.aw_valid = axi_valid_in[NarrowInAw] && !narrow_aw_out_full; - assign narrow_out_req_id_mapped.w_valid = axi_valid_in[NarrowInW]; - assign narrow_out_req_id_mapped.ar_valid = axi_valid_in[NarrowInAr] && !narrow_ar_out_full; - assign narrow_b_rob_valid_in = axi_valid_in[NarrowInB] && !is_atop_b_rsp; - assign narrow_r_rob_valid_in = axi_valid_in[NarrowInR] && !is_atop_r_rsp; - assign narrow_in_rsp_o.b_valid = narrow_b_rob_valid_out || is_atop_b_rsp; - assign narrow_in_rsp_o.r_valid = narrow_r_rob_valid_out || is_atop_r_rsp; - assign narrow_b_rob_ready_in = narrow_in_req_i.b_ready && !b_sel_atop; - assign narrow_r_rob_ready_in = narrow_in_req_i.r_ready && !r_sel_atop; - assign wide_out_req_id_mapped.aw_valid = axi_valid_in[WideInAw] && !wide_aw_out_full; - assign wide_out_req_id_mapped.w_valid = axi_valid_in[WideInW]; - assign wide_out_req_id_mapped.ar_valid = axi_valid_in[WideInAr] && !wide_ar_out_full; - assign wide_b_rob_valid_in = axi_valid_in[WideInB]; - assign wide_r_rob_valid_in = axi_valid_in[WideInR]; - assign wide_in_rsp_o.b_valid = wide_b_rob_valid_out; - assign wide_in_rsp_o.r_valid = wide_r_rob_valid_out; - assign wide_b_rob_ready_in = wide_in_req_i.b_ready; - assign wide_r_rob_ready_in = wide_in_req_i.r_ready; - - assign narrow_out_req_id_mapped.aw = narrow_aw_id_mod; - assign narrow_out_req_id_mapped.w = narrow_unpack_w_data; - assign narrow_out_req_id_mapped.ar = narrow_ar_id_mod; - assign narrow_b_rob_in = narrow_unpack_b_data; - assign narrow_r_rob_in = narrow_unpack_r_data; - assign narrow_in_rsp_o.b = (b_sel_atop)? narrow_unpack_b_data : narrow_b_rob_out; - assign narrow_in_rsp_o.r = (r_sel_atop)? narrow_unpack_r_data : narrow_r_rob_out; - assign wide_out_req_id_mapped.aw = wide_aw_id_mod; - assign wide_out_req_id_mapped.w = wide_unpack_w_data; - assign wide_out_req_id_mapped.ar = wide_ar_id_mod; - assign wide_b_rob_in = wide_unpack_b_data; - assign wide_r_rob_in = wide_unpack_r_data; - assign wide_in_rsp_o.b = wide_b_rob_out; - assign wide_in_rsp_o.r = wide_r_rob_out; + assign axi_narrow_out_req_id_mapped.aw_valid = axi_valid_in[NarrowAw] && !narrow_aw_out_full; + assign axi_narrow_out_req_id_mapped.w_valid = axi_valid_in[NarrowW]; + assign axi_narrow_out_req_id_mapped.ar_valid = axi_valid_in[NarrowAr] && !narrow_ar_out_full; + assign narrow_b_rob_valid_in = axi_valid_in[NarrowB] && !is_atop_b_rsp; + assign narrow_r_rob_valid_in = axi_valid_in[NarrowR] && !is_atop_r_rsp; + assign axi_narrow_in_rsp_o.b_valid = narrow_b_rob_valid_out || is_atop_b_rsp; + assign axi_narrow_in_rsp_o.r_valid = narrow_r_rob_valid_out || is_atop_r_rsp; + assign narrow_b_rob_ready_in = axi_narrow_in_req_i.b_ready && !b_sel_atop; + assign narrow_r_rob_ready_in = axi_narrow_in_req_i.r_ready && !r_sel_atop; + assign axi_wide_out_req_id_mapped.aw_valid = axi_valid_in[WideAw] && !wide_aw_out_full; + assign axi_wide_out_req_id_mapped.w_valid = axi_valid_in[WideW]; + assign axi_wide_out_req_id_mapped.ar_valid = axi_valid_in[WideAr] && !wide_ar_out_full; + assign wide_b_rob_valid_in = axi_valid_in[WideB]; + assign wide_r_rob_valid_in = axi_valid_in[WideR]; + assign axi_wide_in_rsp_o.b_valid = wide_b_rob_valid_out; + assign axi_wide_in_rsp_o.r_valid = wide_r_rob_valid_out; + assign wide_b_rob_ready_in = axi_wide_in_req_i.b_ready; + assign wide_r_rob_ready_in = axi_wide_in_req_i.r_ready; + + assign axi_narrow_out_req_id_mapped.aw = axi_narrow_aw_id_mod; + assign axi_narrow_out_req_id_mapped.w = axi_narrow_unpack_w; + assign axi_narrow_out_req_id_mapped.ar = axi_narrow_ar_id_mod; + assign axi_narrow_b_rob_in = axi_narrow_unpack_b; + assign axi_narrow_r_rob_in = axi_narrow_unpack_r; + assign axi_narrow_in_rsp_o.b = (b_sel_atop)? axi_narrow_unpack_b + : axi_narrow_b_rob_out; + assign axi_narrow_in_rsp_o.r = (r_sel_atop)? axi_narrow_unpack_r + : axi_narrow_r_rob_out; + assign axi_wide_out_req_id_mapped.aw = axi_wide_aw_id_mod; + assign axi_wide_out_req_id_mapped.w = axi_wide_unpack_w; + assign axi_wide_out_req_id_mapped.ar = axi_wide_ar_id_mod; + assign axi_wide_b_rob_in = axi_wide_unpack_b; + assign axi_wide_r_rob_in = axi_wide_unpack_r; + assign axi_wide_in_rsp_o.b = axi_wide_b_rob_out; + assign axi_wide_in_rsp_o.r = axi_wide_r_rob_out; logic is_atop, atop_has_r_rsp; - assign is_atop = AtopSupport && axi_valid_in[NarrowInAw] && - (narrow_unpack_aw_data.atop != axi_pkg::ATOP_NONE); - assign atop_has_r_rsp = AtopSupport && axi_valid_in[NarrowInAw] && - narrow_unpack_aw_data.atop[axi_pkg::ATOP_R_RESP]; - - assign narrow_aw_out_push = narrow_out_req_o.aw_valid && narrow_out_rsp_i.aw_ready; - assign narrow_ar_out_push = narrow_out_req_o.ar_valid && narrow_out_rsp_i.ar_ready || - narrow_out_req_o.aw_valid && narrow_out_rsp_i.aw_ready && + assign is_atop = AtopSupport && axi_valid_in[NarrowAw] && + (axi_narrow_unpack_aw.atop != axi_pkg::ATOP_NONE); + assign atop_has_r_rsp = AtopSupport && axi_valid_in[NarrowAw] && + axi_narrow_unpack_aw.atop[axi_pkg::ATOP_R_RESP]; + + assign narrow_aw_out_push = axi_narrow_out_req_o.aw_valid && axi_narrow_out_rsp_i.aw_ready; + assign narrow_ar_out_push = axi_narrow_out_req_o.ar_valid && axi_narrow_out_rsp_i.ar_ready || + axi_narrow_out_req_o.aw_valid && axi_narrow_out_rsp_i.aw_ready && is_atop && atop_has_r_rsp; - assign narrow_aw_out_pop = narrow_out_rsp_i.b_valid && narrow_out_req_o.b_ready; - assign narrow_ar_out_pop = narrow_out_rsp_i.r_valid && narrow_out_req_o.r_ready & - narrow_out_rsp_i.r.last; + assign narrow_aw_out_pop = axi_narrow_out_rsp_i.b_valid && axi_narrow_out_req_o.b_ready; + assign narrow_ar_out_pop = axi_narrow_out_rsp_i.r_valid && axi_narrow_out_req_o.r_ready & + axi_narrow_out_rsp_i.r.last; - assign wide_aw_out_push = wide_out_req_o.aw_valid && wide_out_rsp_i.aw_ready; - assign wide_ar_out_push = wide_out_req_o.ar_valid && wide_out_rsp_i.ar_ready; - assign wide_aw_out_pop = wide_out_rsp_i.b_valid && wide_out_req_o.b_ready; - assign wide_ar_out_pop = wide_out_rsp_i.r_valid && wide_out_req_o.r_ready && - wide_out_rsp_i.r.last; + assign wide_aw_out_push = axi_wide_out_req_o.aw_valid && axi_wide_out_rsp_i.aw_ready; + assign wide_ar_out_push = axi_wide_out_req_o.ar_valid && axi_wide_out_rsp_i.ar_ready; + assign wide_aw_out_pop = axi_wide_out_rsp_i.b_valid && axi_wide_out_req_o.b_ready; + assign wide_ar_out_pop = axi_wide_out_rsp_i.r_valid && axi_wide_out_req_o.r_ready && + axi_wide_out_rsp_i.r.last; assign narrow_aw_out_data_in = '{ - id: narrow_unpack_aw_data.id, - rob_req: narrow_unpack_req_generic.rob_req, - rob_idx: narrow_unpack_req_generic.rob_idx, - src_id: narrow_unpack_req_generic.src_id, - atop: narrow_unpack_req_generic.atop + id: axi_narrow_unpack_aw.id, + rob_req: floo_narrow_unpack_req_generic.hdr.rob_req, + rob_idx: floo_narrow_unpack_req_generic.hdr.rob_idx, + src_id: floo_narrow_unpack_req_generic.hdr.src_id, + atop: floo_narrow_unpack_req_generic.hdr.atop }; assign narrow_ar_out_data_in = '{ - id: narrow_unpack_ar_data.id, - rob_req: narrow_unpack_req_generic.rob_req, - rob_idx: narrow_unpack_req_generic.rob_idx, - src_id: narrow_unpack_req_generic.src_id, - atop: narrow_unpack_req_generic.atop + id: axi_narrow_unpack_ar.id, + rob_req: floo_narrow_unpack_req_generic.hdr.rob_req, + rob_idx: floo_narrow_unpack_req_generic.hdr.rob_idx, + src_id: floo_narrow_unpack_req_generic.hdr.src_id, + atop: floo_narrow_unpack_req_generic.hdr.atop }; assign wide_aw_out_data_in = '{ - id: wide_unpack_aw_data.id, - rob_req: narrow_unpack_req_generic.rob_req, - rob_idx: narrow_unpack_req_generic.rob_idx, - src_id: narrow_unpack_req_generic.src_id + id: axi_wide_unpack_aw.id, + rob_req: floo_narrow_unpack_req_generic.hdr.rob_req, + rob_idx: floo_narrow_unpack_req_generic.hdr.rob_idx, + src_id: floo_narrow_unpack_req_generic.hdr.src_id }; assign wide_ar_out_data_in = '{ - id: wide_unpack_ar_data.id, - rob_req: narrow_unpack_req_generic.rob_req, - rob_idx: narrow_unpack_req_generic.rob_idx, - src_id: narrow_unpack_req_generic.src_id + id: axi_wide_unpack_ar.id, + rob_req: floo_narrow_unpack_req_generic.hdr.rob_req, + rob_idx: floo_narrow_unpack_req_generic.hdr.rob_idx, + src_id: floo_narrow_unpack_req_generic.hdr.src_id }; floo_meta_buffer #( @@ -1053,21 +1092,21 @@ module floo_narrow_wide_chimney .AtopSupport ( AtopSupport ), .MaxAtomicTxns ( MaxAtomicTxns ), .buf_t ( narrow_id_out_buf_t ), - .id_t ( narrow_out_id_t ) + .id_t ( axi_narrow_out_id_t ) ) i_narrow_aw_meta_buffer ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_enable_i ( test_enable_i ), - .req_push_i ( narrow_aw_out_push ), - .req_valid_i ( narrow_out_req_o.aw_valid ), - .req_buf_i ( narrow_aw_out_data_in ), - .req_is_atop_i ( is_atop ), - .req_atop_id_i ( '0 ), - .req_full_o ( narrow_aw_out_full ), - .req_id_o ( narrow_aw_out_id ), - .rsp_pop_i ( narrow_aw_out_pop ), - .rsp_id_i ( narrow_out_rsp_i.b.id ), - .rsp_buf_o ( narrow_aw_out_data_out ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_enable_i ), + .req_push_i ( narrow_aw_out_push ), + .req_valid_i ( axi_narrow_out_req_o.aw_valid ), + .req_buf_i ( narrow_aw_out_data_in ), + .req_is_atop_i ( is_atop ), + .req_atop_id_i ( '0 ), + .req_full_o ( narrow_aw_out_full ), + .req_id_o ( narrow_aw_out_id ), + .rsp_pop_i ( narrow_aw_out_pop ), + .rsp_id_i ( axi_narrow_out_rsp_i.b.id ), + .rsp_buf_o ( narrow_aw_out_data_out ) ); @@ -1077,75 +1116,75 @@ module floo_narrow_wide_chimney .MaxAtomicTxns ( MaxAtomicTxns ), .ExtAtomicId ( 1'b1 ), // Use ID from AW channel .buf_t ( narrow_id_out_buf_t ), - .id_t ( narrow_out_id_t ) + .id_t ( axi_narrow_out_id_t ) ) i_narrow_ar_meta_buffer ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_enable_i ( test_enable_i ), - .req_push_i ( narrow_ar_out_push ), - .req_valid_i ( narrow_out_req_o.ar_valid ), - .req_buf_i ( narrow_ar_out_data_in ), - .req_is_atop_i ( is_atop ), - .req_atop_id_i ( narrow_aw_out_id ), // Use ID from AW channel - .req_full_o ( narrow_ar_out_full ), - .req_id_o ( narrow_ar_out_id ), - .rsp_pop_i ( narrow_ar_out_pop ), - .rsp_id_i ( narrow_out_rsp_i.r.id ), - .rsp_buf_o ( narrow_ar_out_data_out ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_enable_i ), + .req_push_i ( narrow_ar_out_push ), + .req_valid_i ( axi_narrow_out_req_o.ar_valid ), + .req_buf_i ( narrow_ar_out_data_in ), + .req_is_atop_i ( is_atop ), + .req_atop_id_i ( narrow_aw_out_id ), // Use ID from AW channel + .req_full_o ( narrow_ar_out_full ), + .req_id_o ( narrow_ar_out_id ), + .rsp_pop_i ( narrow_ar_out_pop ), + .rsp_id_i ( axi_narrow_out_rsp_i.r.id ), + .rsp_buf_o ( narrow_ar_out_data_out ) ); floo_meta_buffer #( .MaxTxns ( NarrowMaxTxns ), .AtopSupport ( 1'b0 ), .buf_t ( wide_id_out_buf_t ), - .id_t ( wide_out_id_t ) + .id_t ( axi_wide_out_id_t ) ) i_wide_aw_meta_buffer ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_enable_i ( test_enable_i ), - .req_push_i ( wide_aw_out_push ), - .req_valid_i ( wide_out_req_o.aw_valid ), - .req_buf_i ( wide_aw_out_data_in ), - .req_is_atop_i ( 1'b0 ), - .req_atop_id_i ( '0 ), - .req_full_o ( wide_aw_out_full ), - .req_id_o ( wide_aw_out_id ), - .rsp_pop_i ( wide_aw_out_pop ), - .rsp_id_i ( wide_out_rsp_i.b.id ), - .rsp_buf_o ( wide_aw_out_data_out ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_enable_i ), + .req_push_i ( wide_aw_out_push ), + .req_valid_i ( axi_wide_out_req_o.aw_valid ), + .req_buf_i ( wide_aw_out_data_in ), + .req_is_atop_i ( 1'b0 ), + .req_atop_id_i ( '0 ), + .req_full_o ( wide_aw_out_full ), + .req_id_o ( wide_aw_out_id ), + .rsp_pop_i ( wide_aw_out_pop ), + .rsp_id_i ( axi_wide_out_rsp_i.b.id ), + .rsp_buf_o ( wide_aw_out_data_out ) ); floo_meta_buffer #( .MaxTxns ( NarrowMaxTxns ), .AtopSupport ( 1'b0 ), .buf_t ( wide_id_out_buf_t ), - .id_t ( wide_out_id_t ) + .id_t ( axi_wide_out_id_t ) ) i_wide_ar_meta_buffer ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_enable_i ( test_enable_i ), - .req_push_i ( wide_ar_out_push ), - .req_valid_i ( wide_out_req_o.ar_valid ), - .req_buf_i ( wide_ar_out_data_in ), - .req_is_atop_i ( 1'b0 ), - .req_atop_id_i ( '0 ), - .req_full_o ( wide_ar_out_full ), - .req_id_o ( wide_ar_out_id ), - .rsp_pop_i ( wide_ar_out_pop ), - .rsp_id_i ( wide_out_rsp_i.r.id ), - .rsp_buf_o ( wide_ar_out_data_out ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_enable_i ), + .req_push_i ( wide_ar_out_push ), + .req_valid_i ( axi_wide_out_req_o.ar_valid ), + .req_buf_i ( wide_ar_out_data_in ), + .req_is_atop_i ( 1'b0 ), + .req_atop_id_i ( '0 ), + .req_full_o ( wide_ar_out_full ), + .req_id_o ( wide_ar_out_id ), + .rsp_pop_i ( wide_ar_out_pop ), + .rsp_id_i ( axi_wide_out_rsp_i.r.id ), + .rsp_buf_o ( wide_ar_out_data_out ) ); always_comb begin // Assign the outgoing AX an unique ID - narrow_aw_id_mod = narrow_unpack_aw_data; - narrow_ar_id_mod = narrow_unpack_ar_data; - wide_aw_id_mod = wide_unpack_aw_data; - wide_ar_id_mod = wide_unpack_ar_data; - narrow_aw_id_mod.id = narrow_aw_out_id; - narrow_ar_id_mod.id = narrow_ar_out_id; - wide_aw_id_mod.id = wide_aw_out_id; - wide_ar_id_mod.id = wide_ar_out_id; + axi_narrow_aw_id_mod = axi_narrow_unpack_aw; + axi_narrow_ar_id_mod = axi_narrow_unpack_ar; + axi_wide_aw_id_mod = axi_wide_unpack_aw; + axi_wide_ar_id_mod = axi_wide_unpack_ar; + axi_narrow_aw_id_mod.id = narrow_aw_out_id; + axi_narrow_ar_id_mod.id = narrow_ar_out_id; + axi_wide_aw_id_mod.id = wide_aw_out_id; + axi_wide_ar_id_mod.id = wide_ar_out_id; end // Registers @@ -1162,20 +1201,26 @@ module floo_narrow_wide_chimney `ASSERT_INIT(ToSmallIdWidth, 1 + AtopSupport * MaxAtomicTxns <= 2**NarrowOutIdWidth) // Data and valid signals must be stable/asserted when ready is low - // `ASSERT(NarrowReqOutStableData, narrow_req_o.valid && !narrow_req_i.ready - // |=> $stable(narrow_req_o.data)) - // `ASSERT(NarrowReqInStableData, narrow_req_i.valid && !narrow_req_o.ready - // |=> $stable(narrow_req_i.data)) - // `ASSERT(NarrowRspOutStableData, narrow_rsp_o.valid && !narrow_rsp_i.ready - // |=> $stable(narrow_rsp_o.data)) - // `ASSERT(NarrowRspInStableData, narrow_rsp_i.valid && !narrow_rsp_o.ready - // |=> $stable(narrow_rsp_i.data)) + // `ASSERT(NarrowReqOutStableData, req_o.valid && !req_i.ready + // |=> $stable(req_o.data)) + // `ASSERT(NarrowReqInStableData, req_i.valid && !req_o.ready + // |=> $stable(req_i.data)) + // `ASSERT(NarrowRspOutStableData, rsp_o.valid && !rsp_i.ready + // |=> $stable(rsp_o.data)) + // `ASSERT(NarrowRspInStableData, rsp_i.valid && !rsp_o.ready + // |=> $stable(rsp_i.data)) // `ASSERT(WideOutStableData, wide_o.valid && !wide_i.ready |=> $stable(wide_o.data)) - // `ASSERT(WideInStableData, wide_i.valid && !wide_o.ready |=> $stable(wide_i.data)) - `ASSERT(NarrowReqOutStableValid, narrow_req_o.valid && !narrow_req_i.ready |=> narrow_req_o.valid) - `ASSERT(NarrowReqInStableValid, narrow_req_i.valid && !narrow_req_o.ready |=> narrow_req_i.valid) - `ASSERT(NarrowRspOutStableValid, narrow_rsp_o.valid && !narrow_rsp_i.ready |=> narrow_rsp_o.valid) - `ASSERT(NarrowRspInStableValid, narrow_rsp_i.valid && !narrow_rsp_o.ready |=> narrow_rsp_i.valid) - `ASSERT(WideOutStableValid, wide_o.valid && !wide_i.ready |=> wide_o.valid) - `ASSERT(WideInStableValid, wide_i.valid && !wide_o.ready |=> wide_i.valid) + // `ASSERT(WideStableData, wide_i.valid && !wide_o.ready |=> $stable(wide_i.data)) + `ASSERT(NarrowReqOutStableValid, floo_req_o.valid && + !floo_req_i.ready |=> floo_req_o.valid) + `ASSERT(NarrowReqInStableValid, floo_req_i.valid && + !floo_req_o.ready |=> floo_req_i.valid) + `ASSERT(NarrowRspOutStableValid, floo_rsp_o.valid && + !floo_rsp_i.ready |=> floo_rsp_o.valid) + `ASSERT(NarrowRspInStableValid, floo_rsp_i.valid && + !floo_rsp_o.ready |=> floo_rsp_i.valid) + `ASSERT(WideOutStableValid, floo_wide_o.valid && + !floo_wide_i.ready |=> floo_wide_o.valid) + `ASSERT(WideStableValid, floo_wide_i.valid && + !floo_wide_o.ready |=> floo_wide_i.valid) endmodule diff --git a/src/floo_narrow_wide_flit_pkg.sv b/src/floo_narrow_wide_flit_pkg.sv deleted file mode 100644 index 8a71e208..00000000 --- a/src/floo_narrow_wide_flit_pkg.sv +++ /dev/null @@ -1,355 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// This file is auto-generated. Do not edit! Edit the template file instead - - -`include "axi/typedef.svh" - -package floo_narrow_wide_flit_pkg; - - localparam int unsigned NumPhysChannels = 3; - localparam int unsigned NumAxiChannels = 10; - - //////////////////////// - // AXI Parameters // - //////////////////////// - - localparam int unsigned NarrowInAddrWidth = 48; - localparam int unsigned NarrowInDataWidth = 64; - localparam int unsigned NarrowInIdWidth = 4; - localparam int unsigned NarrowInUserWidth = 5; - - localparam int unsigned NarrowOutAddrWidth = 48; - localparam int unsigned NarrowOutDataWidth = 64; - localparam int unsigned NarrowOutIdWidth = 2; - localparam int unsigned NarrowOutUserWidth = 5; - - localparam int unsigned WideInAddrWidth = 48; - localparam int unsigned WideInDataWidth = 512; - localparam int unsigned WideInIdWidth = 3; - localparam int unsigned WideInUserWidth = 1; - - localparam int unsigned WideOutAddrWidth = 48; - localparam int unsigned WideOutDataWidth = 512; - localparam int unsigned WideOutIdWidth = 1; - localparam int unsigned WideOutUserWidth = 1; - - - typedef logic [47:0] narrow_in_addr_t; - typedef logic [63:0] narrow_in_data_t; - typedef logic [7:0] narrow_in_strb_t; - typedef logic [3:0] narrow_in_id_t; - typedef logic [4:0] narrow_in_user_t; - - typedef logic [47:0] narrow_out_addr_t; - typedef logic [63:0] narrow_out_data_t; - typedef logic [7:0] narrow_out_strb_t; - typedef logic [1:0] narrow_out_id_t; - typedef logic [4:0] narrow_out_user_t; - - typedef logic [47:0] wide_in_addr_t; - typedef logic [511:0] wide_in_data_t; - typedef logic [63:0] wide_in_strb_t; - typedef logic [2:0] wide_in_id_t; - typedef logic [0:0] wide_in_user_t; - - typedef logic [47:0] wide_out_addr_t; - typedef logic [511:0] wide_out_data_t; - typedef logic [63:0] wide_out_strb_t; - typedef logic [0:0] wide_out_id_t; - typedef logic [0:0] wide_out_user_t; - - - `AXI_TYPEDEF_ALL(narrow_in, narrow_in_addr_t, narrow_in_id_t, narrow_in_data_t, narrow_in_strb_t, - narrow_in_user_t) - `AXI_TYPEDEF_ALL(narrow_out, narrow_out_addr_t, narrow_out_id_t, narrow_out_data_t, - narrow_out_strb_t, narrow_out_user_t) - `AXI_TYPEDEF_ALL(wide_in, wide_in_addr_t, wide_in_id_t, wide_in_data_t, wide_in_strb_t, - wide_in_user_t) - `AXI_TYPEDEF_ALL(wide_out, wide_out_addr_t, wide_out_id_t, wide_out_data_t, wide_out_strb_t, - wide_out_user_t) - - ////////////////////// - // AXI Channels // - ////////////////////// - - typedef enum logic [3:0] { - NarrowInAw, - NarrowInW, - NarrowInAr, - WideInAr, - WideInAw, - NarrowInB, - NarrowInR, - WideInB, - WideInW, - WideInR - } axi_ch_e; - - /////////////////////////// - // Physical Channels // - /////////////////////////// - - typedef enum int { - PhysNarrowReq, - PhysNarrowRsp, - PhysWide - } phys_chan_e; - - ///////////////////////// - // Channel Mapping // - ///////////////////////// - - localparam int NumVirtPerPhys[NumPhysChannels] = '{5, 3, 2}; - - localparam int PhysChanMapping[NumAxiChannels] = '{ - PhysNarrowReq, - PhysNarrowReq, - PhysNarrowReq, - PhysNarrowReq, - PhysNarrowReq, - PhysNarrowRsp, - PhysNarrowRsp, - PhysNarrowRsp, - PhysWide, - PhysWide - }; - - localparam int VirtChanMapping[NumPhysChannels][5] = '{ - '{NarrowInAw, NarrowInW, NarrowInAr, WideInAr, WideInAw}, - '{NarrowInB, NarrowInR, WideInB, 0, 0}, - '{WideInW, WideInR, 0, 0, 0} - }; - - /////////////////////// - // Meta Typedefs // - /////////////////////// - - typedef logic [0:0] rob_req_t; - typedef logic [7:0] rob_idx_t; - typedef logic [5:0] dst_id_t; - typedef logic [5:0] src_id_t; - typedef logic [0:0] last_t; - typedef logic [0:0] atop_t; - typedef logic [3:0] axi_ch_t; - - //////////////////////////// - // AXI Packet Structs // - //////////////////////////// - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - narrow_in_aw_chan_t aw; - } narrow_in_aw_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - narrow_in_w_chan_t w; - logic [13:0] rsvd; - } narrow_in_w_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - narrow_in_ar_chan_t ar; - logic [5:0] rsvd; - } narrow_in_ar_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - wide_in_ar_chan_t ar; - logic [10:0] rsvd; - } wide_in_ar_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - wide_in_aw_chan_t aw; - logic [4:0] rsvd; - } wide_in_aw_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - logic [91:0] rsvd; - } narrow_req_generic_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - narrow_in_b_chan_t b; - logic [64:0] rsvd; - } narrow_in_b_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - narrow_in_r_chan_t r; - } narrow_in_r_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - wide_in_b_chan_t b; - logic [69:0] rsvd; - } wide_in_b_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - logic [75:0] rsvd; - } narrow_rsp_generic_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - wide_in_w_chan_t w; - } wide_in_w_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - wide_in_r_chan_t r; - logic [58:0] rsvd; - } wide_in_r_data_t; - - typedef struct packed { - rob_req_t rob_req; - rob_idx_t rob_idx; - dst_id_t dst_id; - src_id_t src_id; - last_t last; - atop_t atop; - axi_ch_t axi_ch; - logic [577:0] rsvd; - } wide_generic_t; - - - - /////////////////////////// - // AXI Packet Unions // - /////////////////////////// - - typedef union packed { - narrow_in_aw_data_t narrow_in_aw; - narrow_in_w_data_t narrow_in_w; - narrow_in_ar_data_t narrow_in_ar; - wide_in_ar_data_t wide_in_ar; - wide_in_aw_data_t wide_in_aw; - narrow_req_generic_t gen; - } narrow_req_data_t; - - typedef union packed { - narrow_in_b_data_t narrow_in_b; - narrow_in_r_data_t narrow_in_r; - wide_in_b_data_t wide_in_b; - narrow_rsp_generic_t gen; - } narrow_rsp_data_t; - - typedef union packed { - wide_in_w_data_t wide_in_w; - wide_in_r_data_t wide_in_r; - wide_generic_t gen; - } wide_data_t; - - - /////////////////////////////// - // Physical Flit Structs // - /////////////////////////////// - - typedef struct packed { - logic valid; - logic ready; - narrow_req_data_t data; - } narrow_req_flit_t; - - typedef struct packed { - logic valid; - logic ready; - narrow_rsp_data_t data; - } narrow_rsp_flit_t; - - typedef struct packed { - logic valid; - logic ready; - wide_data_t data; - } wide_flit_t; - - - ////////////////////////////// - // Phys Packeed Structs // - ////////////////////////////// - - typedef struct packed { - narrow_req_flit_t narrow_req; - narrow_rsp_flit_t narrow_rsp; - wide_flit_t wide; - } flit_t; - -endpackage - diff --git a/src/floo_narrow_wide_pkg.sv b/src/floo_narrow_wide_pkg.sv new file mode 100644 index 00000000..86fa4129 --- /dev/null +++ b/src/floo_narrow_wide_pkg.sv @@ -0,0 +1,223 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// This file is auto-generated. Do not edit! Edit the template file instead + + +`include "axi/typedef.svh" + +package floo_narrow_wide_pkg; + + //////////////////////// + // AXI Parameters // + //////////////////////// + + localparam int unsigned NarrowInAddrWidth = 48; + localparam int unsigned NarrowInDataWidth = 64; + localparam int unsigned NarrowInIdWidth = 4; + localparam int unsigned NarrowInUserWidth = 5; + + localparam int unsigned NarrowOutAddrWidth = 48; + localparam int unsigned NarrowOutDataWidth = 64; + localparam int unsigned NarrowOutIdWidth = 2; + localparam int unsigned NarrowOutUserWidth = 5; + + localparam int unsigned WideInAddrWidth = 48; + localparam int unsigned WideInDataWidth = 512; + localparam int unsigned WideInIdWidth = 3; + localparam int unsigned WideInUserWidth = 1; + + localparam int unsigned WideOutAddrWidth = 48; + localparam int unsigned WideOutDataWidth = 512; + localparam int unsigned WideOutIdWidth = 1; + localparam int unsigned WideOutUserWidth = 1; + + typedef logic [NarrowInAddrWidth-1:0] axi_narrow_in_addr_t; + typedef logic [NarrowInDataWidth-1:0] axi_narrow_in_data_t; + typedef logic [NarrowInDataWidth/8-1:0] axi_narrow_in_strb_t; + typedef logic [NarrowInIdWidth-1:0] axi_narrow_in_id_t; + typedef logic [NarrowInUserWidth-1:0] axi_narrow_in_user_t; + + typedef logic [NarrowOutAddrWidth-1:0] axi_narrow_out_addr_t; + typedef logic [NarrowOutDataWidth-1:0] axi_narrow_out_data_t; + typedef logic [NarrowOutDataWidth/8-1:0] axi_narrow_out_strb_t; + typedef logic [NarrowOutIdWidth-1:0] axi_narrow_out_id_t; + typedef logic [NarrowOutUserWidth-1:0] axi_narrow_out_user_t; + + typedef logic [WideInAddrWidth-1:0] axi_wide_in_addr_t; + typedef logic [WideInDataWidth-1:0] axi_wide_in_data_t; + typedef logic [WideInDataWidth/8-1:0] axi_wide_in_strb_t; + typedef logic [WideInIdWidth-1:0] axi_wide_in_id_t; + typedef logic [WideInUserWidth-1:0] axi_wide_in_user_t; + + typedef logic [WideOutAddrWidth-1:0] axi_wide_out_addr_t; + typedef logic [WideOutDataWidth-1:0] axi_wide_out_data_t; + typedef logic [WideOutDataWidth/8-1:0] axi_wide_out_strb_t; + typedef logic [WideOutIdWidth-1:0] axi_wide_out_id_t; + typedef logic [WideOutUserWidth-1:0] axi_wide_out_user_t; + + `AXI_TYPEDEF_ALL_CT(axi_narrow_in, axi_narrow_in_req_t, axi_narrow_in_rsp_t, axi_narrow_in_addr_t, + axi_narrow_in_id_t, axi_narrow_in_data_t, axi_narrow_in_strb_t, + axi_narrow_in_user_t) + `AXI_TYPEDEF_ALL_CT(axi_narrow_out, axi_narrow_out_req_t, axi_narrow_out_rsp_t, + axi_narrow_out_addr_t, axi_narrow_out_id_t, axi_narrow_out_data_t, + axi_narrow_out_strb_t, axi_narrow_out_user_t) + `AXI_TYPEDEF_ALL_CT(axi_wide_in, axi_wide_in_req_t, axi_wide_in_rsp_t, axi_wide_in_addr_t, + axi_wide_in_id_t, axi_wide_in_data_t, axi_wide_in_strb_t, axi_wide_in_user_t) + `AXI_TYPEDEF_ALL_CT(axi_wide_out, axi_wide_out_req_t, axi_wide_out_rsp_t, axi_wide_out_addr_t, + axi_wide_out_id_t, axi_wide_out_data_t, axi_wide_out_strb_t, + axi_wide_out_user_t) + + ///////////////////////// + // Header Typedefs // + ///////////////////////// + + typedef logic [7:0] rob_idx_t; + typedef logic [5:0] dst_id_t; + typedef logic [5:0] src_id_t; + typedef logic [3:0] axi_ch_t; + + typedef struct packed { + logic rob_req; + rob_idx_t rob_idx; + dst_id_t dst_id; + src_id_t src_id; + logic last; + logic atop; + axi_ch_t axi_ch; + } hdr_t; + + + //////////////////////////// + // AXI Flits Typedefs // + //////////////////////////// + + typedef struct packed { + hdr_t hdr; + axi_narrow_in_aw_chan_t aw; + } floo_narrow_aw_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_narrow_in_w_chan_t w; + logic [13:0] rsvd; + } floo_narrow_w_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_narrow_in_b_chan_t b; + logic [64:0] rsvd; + } floo_narrow_b_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_narrow_in_ar_chan_t ar; + logic [5:0] rsvd; + } floo_narrow_ar_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_narrow_in_r_chan_t r; + } floo_narrow_r_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_wide_in_aw_chan_t aw; + logic [4:0] rsvd; + } floo_wide_aw_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_wide_in_w_chan_t w; + } floo_wide_w_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_wide_in_b_chan_t b; + logic [69:0] rsvd; + } floo_wide_b_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_wide_in_ar_chan_t ar; + logic [10:0] rsvd; + } floo_wide_ar_flit_t; + + typedef struct packed { + hdr_t hdr; + axi_wide_in_r_chan_t r; + logic [58:0] rsvd; + } floo_wide_r_flit_t; + + + //////////////////////////////// + // Generic Flits Typedefs // + //////////////////////////////// + + typedef struct packed { + hdr_t hdr; + logic [91:0] rsvd; + } floo_req_generic_flit_t; + + typedef struct packed { + hdr_t hdr; + logic [75:0] rsvd; + } floo_rsp_generic_flit_t; + + typedef struct packed { + hdr_t hdr; + logic [577:0] rsvd; + } floo_wide_generic_flit_t; + + + ////////////////////////// + // Channel Typedefs // + ////////////////////////// + + typedef union packed { + floo_narrow_aw_flit_t narrow_aw; + floo_narrow_w_flit_t narrow_w; + floo_narrow_ar_flit_t narrow_ar; + floo_wide_aw_flit_t wide_aw; + floo_wide_ar_flit_t wide_ar; + floo_req_generic_flit_t generic; + } floo_req_chan_t; + + typedef union packed { + floo_narrow_b_flit_t narrow_b; + floo_narrow_r_flit_t narrow_r; + floo_wide_b_flit_t wide_b; + floo_rsp_generic_flit_t generic; + } floo_rsp_chan_t; + + typedef union packed { + floo_wide_w_flit_t wide_w; + floo_wide_r_flit_t wide_r; + floo_wide_generic_flit_t generic; + } floo_wide_chan_t; + + /////////////////////// + // Link Typedefs // + /////////////////////// + + typedef struct packed { + logic valid; + logic ready; + floo_req_chan_t req; + } floo_req_t; + + typedef struct packed { + logic valid; + logic ready; + floo_rsp_chan_t rsp; + } floo_rsp_t; + + typedef struct packed { + logic valid; + logic ready; + floo_wide_chan_t wide; + } floo_wide_t; + +endpackage + diff --git a/src/floo_narrow_wide_router.sv b/src/floo_narrow_wide_router.sv index b0cacab9..24e9f40c 100644 --- a/src/floo_narrow_wide_router.sv +++ b/src/floo_narrow_wide_router.sv @@ -7,9 +7,11 @@ /// Wrapper of a multi-link router for narrow and wide links module floo_narrow_wide_router import floo_pkg::*; - import floo_narrow_wide_flit_pkg::*; + import floo_narrow_wide_pkg::*; #( parameter int unsigned NumRoutes = NumDirections, + parameter int unsigned NumInputs = NumRoutes, + parameter int unsigned NumOutputs = NumRoutes, parameter int unsigned ChannelFifoDepth = 0, parameter int unsigned OutputFifoDepth = 0, parameter route_algo_e RouteAlgo = XYRouting, @@ -27,110 +29,121 @@ module floo_narrow_wide_router input id_t xy_id_i, input addr_rule_t [NumAddrRules-1:0] id_route_map_i, - input narrow_req_flit_t [NumRoutes-1:0] narrow_req_i, - input narrow_rsp_flit_t [NumRoutes-1:0] narrow_rsp_i, - output narrow_req_flit_t [NumRoutes-1:0] narrow_req_o, - output narrow_rsp_flit_t [NumRoutes-1:0] narrow_rsp_o, - input wide_flit_t [NumRoutes-1:0] wide_i, - output wide_flit_t [NumRoutes-1:0] wide_o + input floo_req_t [NumInputs-1:0] floo_req_i, + input floo_rsp_t [NumOutputs-1:0] floo_rsp_i, + output floo_req_t [NumOutputs-1:0] floo_req_o, + output floo_rsp_t [NumInputs-1:0] floo_rsp_o, + input floo_wide_t [NumRoutes-1:0] floo_wide_i, + output floo_wide_t [NumRoutes-1:0] floo_wide_o ); - narrow_req_data_t [NumRoutes-1:0] narrow_req_in, narrow_req_out; - narrow_rsp_data_t [NumRoutes-1:0] narrow_rsp_in, narrow_rsp_out; - logic [NumRoutes-1:0] narrow_req_valid_in, narrow_req_valid_out; - logic [NumRoutes-1:0] narrow_rsp_valid_in, narrow_rsp_valid_out; - logic [NumRoutes-1:0] narrow_req_ready_in, narrow_rsp_ready_in; - logic [NumRoutes-1:0] narrow_req_ready_out, narrow_rsp_ready_out; - wide_data_t [NumRoutes-1:0] wide_in, wide_out; - logic [NumRoutes-1:0] wide_valid_in, wide_valid_out; - logic [NumRoutes-1:0] wide_ready_in, wide_ready_out; + floo_req_chan_t [NumInputs-1:0] req_in; + floo_rsp_chan_t [NumInputs-1:0] rsp_out; + floo_req_chan_t [NumOutputs-1:0] req_out; + floo_rsp_chan_t [NumOutputs-1:0] rsp_in; + floo_wide_chan_t [NumRoutes-1:0] wide_in, wide_out; + logic [NumInputs-1:0] req_valid_in, req_ready_out; + logic [NumInputs-1:0] rsp_valid_out, rsp_ready_in; + logic [NumOutputs-1:0] req_valid_out, req_ready_in; + logic [NumOutputs-1:0] rsp_valid_in, rsp_ready_out; + logic [NumRoutes-1:0] wide_valid_in, wide_valid_out; + logic [NumRoutes-1:0] wide_ready_in, wide_ready_out; - for (genvar i = 0; i < NumRoutes; i++) begin : gen_chimney_req - assign narrow_req_o[i].data = narrow_req_out[i]; - assign narrow_rsp_o[i].data = narrow_rsp_out[i]; - assign narrow_req_in[i] = narrow_req_i[i].data; - assign narrow_rsp_in[i] = narrow_rsp_i[i].data; - assign narrow_req_valid_in[i] = narrow_req_i[i].valid; - assign narrow_rsp_valid_in[i] = narrow_rsp_i[i].valid; - assign narrow_req_ready_in[i] = narrow_req_i[i].ready; - assign narrow_rsp_ready_in[i] = narrow_rsp_i[i].ready; - assign narrow_req_o[i].valid = narrow_req_valid_out[i]; - assign narrow_rsp_o[i].valid = narrow_rsp_valid_out[i]; - assign narrow_req_o[i].ready = narrow_req_ready_out[i]; - assign narrow_rsp_o[i].ready = narrow_rsp_ready_out[i]; - assign wide_o[i].data = wide_out[i]; - assign wide_in[i] = wide_i[i].data; - assign wide_valid_in[i] = wide_i[i].valid; - assign wide_ready_in[i] = wide_i[i].ready; - assign wide_o[i].valid = wide_valid_out[i]; - assign wide_o[i].ready = wide_ready_out[i]; + for (genvar i = 0; i < NumInputs; i++) begin : gen_chimney_req + assign req_valid_in[i] = floo_req_i[i].valid; + assign floo_req_o[i].ready = req_ready_out[i]; + assign req_in[i] = floo_req_i[i].req; + assign floo_rsp_o[i].valid = rsp_valid_out[i]; + assign rsp_ready_in[i] = floo_rsp_i[i].ready; + assign floo_rsp_o[i].rsp = rsp_out[i]; end + for (genvar i = 0; i < NumOutputs; i++) begin : gen_chimney_rsp + assign floo_req_o[i].valid = req_valid_out[i]; + assign req_ready_in[i] = floo_req_i[i].ready; + assign floo_req_o[i].req = req_out[i]; + assign rsp_valid_in[i] = floo_rsp_i[i].valid; + assign floo_rsp_o[i].ready = rsp_ready_out[i]; + assign rsp_in[i] = floo_rsp_i[i].rsp; + end + for (genvar i = 0; i < NumRoutes; i++) begin : gen_chimney_wide + assign wide_valid_in[i] = floo_wide_i[i].valid; + assign floo_wide_o[i].ready = wide_ready_out[i]; + assign wide_in[i] = floo_wide_i[i].wide; + assign floo_wide_o[i].valid = wide_valid_out[i]; + assign wide_ready_in[i] = floo_wide_i[i].ready; + assign floo_wide_o[i].wide = wide_out[i]; + end floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( narrow_req_generic_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .OutputFifoDepth ( OutputFifoDepth ), - .RouteAlgo ( RouteAlgo ), - .IdWidth ( IdWidth ), - .id_t ( id_t ), - .NumAddrRules ( NumAddrRules ) - ) i_narrow_req_floo_router ( + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), + .NumInput ( NumInputs ), + .NumOutput ( NumOutputs ), + .flit_t ( floo_req_generic_flit_t ), + .ChannelFifoDepth ( ChannelFifoDepth ), + .OutputFifoDepth ( OutputFifoDepth ), + .RouteAlgo ( RouteAlgo ), + .IdWidth ( IdWidth ), + .id_t ( id_t ), + .NumAddrRules ( NumAddrRules ), + .addr_rule_t ( addr_rule_t ) + ) i_req_floo_router ( .clk_i, .rst_ni, .test_enable_i, .xy_id_i, .id_route_map_i, - .valid_i ( narrow_req_valid_in ), - .ready_o ( narrow_req_ready_out ), - .data_i ( narrow_req_in ), - .valid_o ( narrow_req_valid_out ), - .ready_i ( narrow_req_ready_in ), - .data_o ( narrow_req_out ) + .valid_i ( req_valid_in ), + .ready_o ( req_ready_out ), + .data_i ( req_in ), + .valid_o ( req_valid_out ), + .ready_i ( req_ready_in ), + .data_o ( req_out ) ); floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( narrow_rsp_generic_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .OutputFifoDepth ( OutputFifoDepth ), - .RouteAlgo ( RouteAlgo ), - .IdWidth ( IdWidth ), - .id_t ( id_t ), - .NumAddrRules ( NumAddrRules ) - ) i_narrow_rsp_floo_router ( + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), + .NumInput ( NumInputs ), + .NumOutput ( NumOutputs ), + .ChannelFifoDepth ( ChannelFifoDepth ), + .OutputFifoDepth ( OutputFifoDepth ), + .RouteAlgo ( RouteAlgo ), + .IdWidth ( IdWidth ), + .flit_t ( floo_rsp_generic_flit_t ), + .id_t ( id_t ), + .NumAddrRules ( NumAddrRules ), + .addr_rule_t ( addr_rule_t ) + ) i_rsp_floo_router ( .clk_i, .rst_ni, .test_enable_i, .xy_id_i, .id_route_map_i, - .valid_i ( narrow_rsp_valid_in ), - .ready_o ( narrow_rsp_ready_out ), - .data_i ( narrow_rsp_in ), - .valid_o ( narrow_rsp_valid_out ), - .ready_i ( narrow_rsp_ready_in ), - .data_o ( narrow_rsp_out ) + .valid_i ( rsp_valid_in ), + .ready_o ( rsp_ready_out ), + .data_i ( rsp_in ), + .valid_o ( rsp_valid_out ), + .ready_i ( rsp_ready_in ), + .data_o ( rsp_out ) ); floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( wide_generic_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .OutputFifoDepth ( OutputFifoDepth ), - .RouteAlgo ( RouteAlgo ), - .IdWidth ( IdWidth ), - .id_t ( id_t ), - .NumAddrRules ( NumAddrRules ) + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), + .NumRoutes ( NumRoutes ), + .flit_t ( floo_wide_generic_flit_t ), + .ChannelFifoDepth ( ChannelFifoDepth ), + .OutputFifoDepth ( OutputFifoDepth ), + .RouteAlgo ( RouteAlgo ), + .IdWidth ( IdWidth ), + .id_t ( id_t ), + .NumAddrRules ( NumAddrRules ), + .addr_rule_t ( addr_rule_t ) ) i_wide_req_floo_router ( .clk_i, .rst_ni, diff --git a/src/floo_param_pkg.sv b/src/floo_param_pkg.sv deleted file mode 100644 index 2aa07fe6..00000000 --- a/src/floo_param_pkg.sv +++ /dev/null @@ -1,41 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Tim Fischer - -`include "axi/typedef.svh" -`include "floo_noc/typedef.svh" - -package floo_param_pkg; - - import floo_pkg::*; - - localparam int unsigned NumX = 5; // Number of tiles in X direction - localparam int unsigned NumY = 5; // Number of tiles in Y direction - - // Already defined in floo_pkg - localparam int unsigned RucheFactor = 0; - localparam int unsigned NumRoutes = 5 + (RucheFactor > 0) * 4; - localparam int unsigned ChannelFifoDepth = 2; - localparam int unsigned OutputFifoDepth = 2; - localparam route_algo_e RouteAlgo = XYRouting; - - - // Chimney parameters - localparam bit CutAx = 1'b1; - localparam bit CutRsp = 1'b0; - localparam int unsigned MaxTxnsPerId = 16; - localparam bit RoBSimple = 1'b0; - localparam int unsigned ReorderBufferSize = 32'd64; - // Narrow Wide Chimney parameters - localparam bit NarrowRoBSimple = 1'b1; - localparam int unsigned NarrowMaxTxnsPerId = 4; - localparam int unsigned NarrowReorderBufferSize = 32'd256; - localparam bit WideRoBSimple = 1'b0; - localparam int unsigned WideMaxTxnsPerId = 32; - localparam int unsigned WideReorderBufferSize = 32'd128; - - `FLOO_NOC_TYPEDEF_XY_ID_T(xy_id_t, NumX, NumY) - -endpackage diff --git a/src/floo_pkg.sv b/src/floo_pkg.sv index 065a453e..f8c2c604 100644 --- a/src/floo_pkg.sv +++ b/src/floo_pkg.sv @@ -9,6 +9,29 @@ /// Currently only contains useful functions and some constants and typedefs package floo_pkg; + typedef enum logic [3:0] { + NarrowAw, + NarrowW, + NarrowAr, + WideAw, + WideAr, + NarrowB, + NarrowR, + WideB, + WideW, + WideR, + NumNarrowWideAxiChannels + } narrow_wide_axi_ch_e; + + typedef enum logic [2:0] { + AxiAw, + AxiW, + AxiAr, + AxiB, + AxiR, + NumAxiChannels + } axi_ch_e; + typedef enum logic[1:0] { IdIsPort, IdTable, diff --git a/src/floo_rob.sv b/src/floo_rob.sv index af3f6508..e99f65f1 100644 --- a/src/floo_rob.sv +++ b/src/floo_rob.sv @@ -22,12 +22,10 @@ module floo_rob #( parameter type rsp_chan_t = logic, parameter type rsp_data_t = logic, parameter type rsp_meta_t = logic, - parameter type rob_idx_t = logic[$clog2(ReorderBufferSize)-1:0], + parameter type rob_idx_t = logic, parameter type dest_t = logic, // Type for implementation inputs and outputs - parameter type sram_cfg_t = logic, - // Dependent parameters, DO NOT OVERRIDE! - localparam type rob_flag_t = logic[ReorderBufferSize-1:0] + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -56,6 +54,7 @@ module floo_rob #( localparam int unsigned NumIds = 2**AxiIdWidth; typedef logic[AxiIdWidth-1:0] axi_id_t; typedef logic[$clog2(NumIds)-1:0] num_id_t; + typedef logic[ReorderBufferSize-1:0] rob_flag_t; ///////////////////////// // Transaction Table // diff --git a/src/floo_route_select.sv b/src/floo_route_select.sv index c26f408d..7ccf62d8 100644 --- a/src/floo_route_select.sv +++ b/src/floo_route_select.sv @@ -45,7 +45,7 @@ module floo_route_select import floo_pkg::*; // One-hot encoding of the decoded route always_comb begin : proc_route_sel route_sel = '0; - route_sel[channel_i.dst_id] = 1'b1; + route_sel[channel_i.hdr.dst_id] = 1'b1; end end else if (RouteAlgo == IdTable) begin : gen_id_table @@ -64,7 +64,7 @@ module floo_route_select import floo_pkg::*; .rule_t ( addr_rule_t ), .Napot ( 0 ) ) i_id_decode ( - .addr_i ( channel_i.dst_id ), + .addr_i ( channel_i.hdr.dst_id ), .addr_map_i ( id_route_map_i ), .idx_o ( out_id ), .dec_valid_o (), @@ -102,7 +102,7 @@ module floo_route_select import floo_pkg::*; // One-hot encoding of the decoded route id_t id_in; - assign id_in = id_t'(channel_i.dst_id); + assign id_in = id_t'(channel_i.hdr.dst_id); always_comb begin : proc_route_sel route_sel = '0; @@ -142,7 +142,7 @@ module floo_route_select import floo_pkg::*; locked_route_d = locked_route_q; if (ready_i && valid_i) begin - locked_route_d = ~channel_i.last; + locked_route_d = ~channel_i.hdr.last; end end diff --git a/src/floo_wormhole_arbiter.sv b/src/floo_wormhole_arbiter.sv index ceff58b7..2d264f1e 100644 --- a/src/floo_wormhole_arbiter.sv +++ b/src/floo_wormhole_arbiter.sv @@ -62,7 +62,7 @@ module floo_wormhole_arbiter import floo_pkg::*; ready_o[valid_selected_idx] = ready_i; end - assign last_out = data_o.last & valid_o; + assign last_out = data_o.hdr.last & valid_o; always_comb begin : proc_valid valid_d = valid_q; diff --git a/src/synth/floo_synth_axi_chimney.sv b/src/synth/floo_synth_axi_chimney.sv index be2b1e66..ba6097e8 100644 --- a/src/synth/floo_synth_axi_chimney.sv +++ b/src/synth/floo_synth_axi_chimney.sv @@ -6,20 +6,20 @@ module floo_synth_axi_chimney import floo_pkg::*; - import floo_axi_flit_pkg::*; - import floo_param_pkg::*; + import floo_axi_pkg::*; + import floo_test_pkg::*; ( input logic clk_i, input logic rst_ni, input axi_in_req_t axi_in_req_i, - output axi_in_resp_t axi_in_rsp_o, - output axi_out_req_t axi_out_req_o, - input axi_out_resp_t axi_out_rsp_i, + output axi_in_rsp_t axi_in_rsp_o, + output axi_out_req_t axi_out_req_o, + input axi_out_rsp_t axi_out_rsp_i, input xy_id_t xy_id_i, - output req_flit_t req_o, - output rsp_flit_t rsp_o, - input req_flit_t req_i, - input rsp_flit_t rsp_i + output floo_req_t floo_req_o, + output floo_rsp_t floo_rsp_o, + input floo_req_t floo_req_i, + input floo_rsp_t floo_rsp_i ); @@ -41,10 +41,10 @@ module floo_synth_axi_chimney .axi_out_rsp_i, .id_i('0), .xy_id_i, - .req_o, - .rsp_o, - .req_i, - .rsp_i + .floo_req_o, + .floo_rsp_o, + .floo_req_i, + .floo_rsp_i ); endmodule diff --git a/src/synth/floo_synth_endpoint.sv b/src/synth/floo_synth_endpoint.sv index b8d936e6..05802a05 100644 --- a/src/synth/floo_synth_endpoint.sv +++ b/src/synth/floo_synth_endpoint.sv @@ -6,27 +6,27 @@ module floo_synth_endpoint import floo_pkg::*; - import floo_axi_flit_pkg::*; - import floo_param_pkg::*; + import floo_axi_pkg::*; + import floo_test_pkg::*; ( input logic clk_i, input logic rst_ni, input logic test_enable_i, input axi_in_req_t axi_in_req_i, - output axi_in_resp_t axi_in_rsp_o, - output axi_out_req_t axi_out_req_o, - input axi_out_resp_t axi_out_rsp_i, + output axi_in_rsp_t axi_in_rsp_o, + output axi_out_req_t axi_out_req_o, + input axi_out_rsp_t axi_out_rsp_i, input xy_id_t xy_id_i, - output req_flit_t [NumRoutes-1:1] req_o, - output rsp_flit_t [NumRoutes-1:1] rsp_o, - input req_flit_t [NumRoutes-1:1] req_i, - input rsp_flit_t [NumRoutes-1:1] rsp_i + output floo_req_t [NumRoutes-1:1] floo_req_o, + output floo_rsp_t [NumRoutes-1:1] floo_rsp_o, + input floo_req_t [NumRoutes-1:1] floo_req_i, + input floo_rsp_t [NumRoutes-1:1] floo_rsp_i ); - req_flit_t chimney_req_in, chimney_req_out; - rsp_flit_t chimney_rsp_in, chimney_rsp_out; - req_data_t [NumRoutes-1:1] req_in, req_out; - rsp_data_t [NumRoutes-1:1] rsp_in, rsp_out; + floo_req_t chimney_req_in, chimney_req_out; + floo_rsp_t chimney_rsp_in, chimney_rsp_out; + floo_req_chan_t [NumRoutes-1:1] req_in, req_out; + floo_rsp_chan_t [NumRoutes-1:1] rsp_in, rsp_out; logic [NumRoutes-1:1] req_valid_in, req_valid_out; logic [NumRoutes-1:1] rsp_valid_in, rsp_valid_out; logic [NumRoutes-1:1] req_ready_in, rsp_ready_in; @@ -34,18 +34,18 @@ module floo_synth_endpoint for (genvar i = 1; i < NumRoutes; i++) begin : gen_chimney_req - assign req_o[i].data = req_out[i]; - assign rsp_o[i].data = rsp_out[i]; - assign req_in[i] = req_i[i].data; - assign rsp_in[i] = rsp_i[i].data; - assign req_valid_in[i] = req_i[i].valid; - assign rsp_valid_in[i] = rsp_i[i].valid; - assign req_ready_in[i] = req_i[i].ready; - assign rsp_ready_in[i] = rsp_i[i].ready; - assign req_o[i].valid = req_valid_out[i]; - assign rsp_o[i].valid = rsp_valid_out[i]; - assign req_o[i].ready = req_ready_out[i]; - assign rsp_o[i].ready = rsp_ready_out[i]; + assign floo_req_o[i].req = req_out[i]; + assign floo_rsp_o[i].rsp = rsp_out[i]; + assign req_in[i] = floo_req_i[i].req; + assign rsp_in[i] = floo_rsp_i[i].rsp; + assign req_valid_in[i] = floo_req_i[i].valid; + assign rsp_valid_in[i] = floo_rsp_i[i].valid; + assign req_ready_in[i] = floo_req_i[i].ready; + assign rsp_ready_in[i] = floo_rsp_i[i].ready; + assign floo_req_o[i].valid = req_valid_out[i]; + assign floo_rsp_o[i].valid = rsp_valid_out[i]; + assign floo_req_o[i].ready = req_ready_out[i]; + assign floo_rsp_o[i].ready = rsp_ready_out[i]; end floo_axi_chimney #( @@ -61,28 +61,29 @@ module floo_synth_endpoint .clk_i, .rst_ni, .test_enable_i, + .sram_cfg_i('0), .axi_in_req_i, .axi_in_rsp_o, .axi_out_req_o, .axi_out_rsp_i, .id_i('0), .xy_id_i, - .req_o(chimney_req_out), - .rsp_o(chimney_rsp_out), - .req_i(chimney_req_in), - .rsp_i(chimney_rsp_in) - ); + .floo_req_o(chimney_req_out), + .floo_rsp_o(chimney_rsp_out), + .floo_req_i(chimney_req_in), + .floo_rsp_i(chimney_rsp_in) + ); floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( req_generic_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .RouteAlgo ( XYRouting ), - .IdWidth ( 4 ), - .id_t ( xy_id_t ), - .NumAddrRules ( 1 ) + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), + .NumRoutes ( NumRoutes ), + .flit_t ( floo_req_generic_flit_t ), + .ChannelFifoDepth ( ChannelFifoDepth ), + .RouteAlgo ( XYRouting ), + .IdWidth ( 4 ), + .id_t ( xy_id_t ), + .NumAddrRules ( 1 ) ) i_req_floo_router ( .clk_i, .rst_ni, @@ -91,22 +92,22 @@ module floo_synth_endpoint .id_route_map_i ('0 ), .valid_i ( {req_valid_in, chimney_req_out.valid} ), .ready_o ( {req_ready_out, chimney_req_in.ready} ), - .data_i ( {req_in, chimney_req_out.data} ), + .data_i ( {req_in, chimney_req_out.req} ), .valid_o ( {req_valid_out, chimney_req_in.valid} ), .ready_i ( {req_ready_in, chimney_req_out.ready} ), - .data_o ( {req_out, chimney_req_in.data} ) + .data_o ( {req_out, chimney_req_in.req} ) ); floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( rsp_generic_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .RouteAlgo ( XYRouting ), - .IdWidth ( 4 ), - .id_t ( xy_id_t ), - .NumAddrRules ( 1 ) + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), + .NumRoutes ( NumRoutes ), + .flit_t ( floo_rsp_generic_flit_t ), + .ChannelFifoDepth ( ChannelFifoDepth ), + .RouteAlgo ( XYRouting ), + .IdWidth ( 4 ), + .id_t ( xy_id_t ), + .NumAddrRules ( 1 ) ) i_rsp_floo_router ( .clk_i, .rst_ni, @@ -115,10 +116,10 @@ module floo_synth_endpoint .id_route_map_i ('0 ), .valid_i ( {rsp_valid_in, chimney_rsp_out.valid} ), .ready_o ( {rsp_ready_out, chimney_rsp_in.ready} ), - .data_i ( {rsp_in, chimney_rsp_out.data} ), + .data_i ( {rsp_in, chimney_rsp_out.rsp} ), .valid_o ( {rsp_valid_out, chimney_rsp_in.valid} ), .ready_i ( {rsp_ready_in, chimney_rsp_out.ready} ), - .data_o ( {rsp_out, chimney_rsp_in.data} ) + .data_o ( {rsp_out, chimney_rsp_in.rsp} ) ); endmodule diff --git a/src/synth/floo_synth_narrow_wide_chimney.sv b/src/synth/floo_synth_narrow_wide_chimney.sv index 75936ffc..52a0e230 100644 --- a/src/synth/floo_synth_narrow_wide_chimney.sv +++ b/src/synth/floo_synth_narrow_wide_chimney.sv @@ -6,28 +6,37 @@ module floo_synth_narrow_wide_chimney import floo_pkg::*; - import floo_narrow_wide_flit_pkg::*; - import floo_param_pkg::*; + import floo_narrow_wide_pkg::*; + import floo_test_pkg::*; ( input logic clk_i, input logic rst_ni, - input narrow_in_req_t narrow_in_req_i, - output narrow_in_resp_t narrow_in_rsp_o, - output narrow_out_req_t narrow_out_req_o, - input narrow_out_resp_t narrow_out_rsp_i, - input wide_in_req_t wide_in_req_i, - output wide_in_resp_t wide_in_rsp_o, - output wide_out_req_t wide_out_req_o, - input wide_out_resp_t wide_out_rsp_i, + input axi_narrow_in_req_t axi_narrow_in_req_i, + output axi_narrow_in_rsp_t axi_narrow_in_rsp_o, + output axi_narrow_out_req_t axi_narrow_out_req_o, + input axi_narrow_out_rsp_t axi_narrow_out_rsp_i, + input axi_wide_in_req_t axi_wide_in_req_i, + output axi_wide_in_rsp_t axi_wide_in_rsp_o, + output axi_wide_out_req_t axi_wide_out_req_o, + input axi_wide_out_rsp_t axi_wide_out_rsp_i, input xy_id_t xy_id_i, - output narrow_req_flit_t narrow_req_o, - output narrow_rsp_flit_t narrow_rsp_o, - input narrow_req_flit_t narrow_req_i, - input narrow_rsp_flit_t narrow_rsp_i, - output wide_flit_t wide_o, - input wide_flit_t wide_i + output floo_req_t floo_req_o, + output floo_rsp_t floo_rsp_o, + input floo_req_t floo_req_i, + input floo_rsp_t floo_rsp_i, + output floo_wide_t floo_wide_o, + input floo_wide_t floo_wide_i ); +`ifdef TARGET_GF12 + typedef struct packed { + logic [2:0] ema; + logic [1:0] emaw; + logic [0:0] emas; + } sram_cfg_t; +`else + typedef logic sram_cfg_t; +`endif floo_narrow_wide_chimney #( .RouteAlgo ( floo_pkg::XYRouting ), @@ -43,28 +52,30 @@ floo_narrow_wide_chimney #( .WideRoBSimple ( WideRoBSimple ), .CutAx ( CutAx ), .CutRsp ( CutRsp ), - .xy_id_t ( xy_id_t ) + .xy_id_t ( xy_id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_floo_narrow_wide_chimney ( .clk_i, .rst_ni, .test_enable_i(1'b0), .sram_cfg_i('0), .id_i('0), + .id_map_i ('0), .xy_id_i, - .narrow_in_req_i, - .narrow_in_rsp_o, - .narrow_out_req_o, - .narrow_out_rsp_i, - .wide_in_req_i, - .wide_in_rsp_o, - .wide_out_req_o, - .wide_out_rsp_i, - .narrow_req_i, - .narrow_rsp_o, - .narrow_req_o, - .narrow_rsp_i, - .wide_o, - .wide_i + .axi_narrow_in_req_i, + .axi_narrow_in_rsp_o, + .axi_narrow_out_req_o, + .axi_narrow_out_rsp_i, + .axi_wide_in_req_i, + .axi_wide_in_rsp_o, + .axi_wide_out_req_o, + .axi_wide_out_rsp_i, + .floo_req_i, + .floo_rsp_o, + .floo_req_o, + .floo_rsp_i, + .floo_wide_o, + .floo_wide_i ); endmodule diff --git a/src/synth/floo_synth_narrow_wide_router.sv b/src/synth/floo_synth_narrow_wide_router.sv index 8f6e79e7..92dc0769 100644 --- a/src/synth/floo_synth_narrow_wide_router.sv +++ b/src/synth/floo_synth_narrow_wide_router.sv @@ -6,8 +6,8 @@ module floo_synth_narrow_wide_router import floo_pkg::*; - import floo_narrow_wide_flit_pkg::*; - import floo_param_pkg::*; + import floo_narrow_wide_pkg::*; + import floo_test_pkg::*; ( input logic clk_i, input logic rst_ni, @@ -15,19 +15,19 @@ module floo_synth_narrow_wide_router input xy_id_t xy_id_i, - input narrow_req_flit_t [NumRoutes-1:0] narrow_req_i, - input narrow_rsp_flit_t [NumRoutes-1:0] narrow_rsp_i, - output narrow_req_flit_t [NumRoutes-1:0] narrow_req_o, - output narrow_rsp_flit_t [NumRoutes-1:0] narrow_rsp_o, - input wide_flit_t [NumRoutes-1:0] wide_i, - output wide_flit_t [NumRoutes-1:0] wide_o + input floo_req_t [NumRoutes-1:0] floo_req_i, + input floo_rsp_t [NumRoutes-1:0] floo_rsp_i, + output floo_req_t [NumRoutes-1:0] floo_req_o, + output floo_rsp_t [NumRoutes-1:0] floo_rsp_o, + input floo_wide_t [NumRoutes-1:0] floo_wide_i, + output floo_wide_t [NumRoutes-1:0] floo_wide_o ); floo_narrow_wide_router #( .NumRoutes ( NumRoutes ), .ChannelFifoDepth ( ChannelFifoDepth ), .OutputFifoDepth ( OutputFifoDepth ), - .RouteAlgo ( RouteAlgo ), + .RouteAlgo ( XYRouting ), .id_t ( xy_id_t ) ) i_floo_narrow_wide_router ( .clk_i, @@ -35,12 +35,12 @@ module floo_synth_narrow_wide_router .test_enable_i, .xy_id_i, .id_route_map_i ('0), - .narrow_req_i, - .narrow_req_o, - .narrow_rsp_i, - .narrow_rsp_o, - .wide_i, - .wide_o + .floo_req_i, + .floo_req_o, + .floo_rsp_i, + .floo_rsp_o, + .floo_wide_i, + .floo_wide_o ); endmodule diff --git a/src/synth/floo_synth_router.sv b/src/synth/floo_synth_router.sv index 5ef1dfa1..57caef9d 100644 --- a/src/synth/floo_synth_router.sv +++ b/src/synth/floo_synth_router.sv @@ -6,8 +6,8 @@ module floo_synth_router import floo_pkg::*; - import floo_axi_flit_pkg::*; - import floo_param_pkg::*; + import floo_axi_pkg::*; + import floo_test_pkg::*; ( input logic clk_i, input logic rst_ni, @@ -15,24 +15,24 @@ module floo_synth_router input xy_id_t xy_id_i, - input req_flit_t [NumRoutes-1:0] req_i, - input rsp_flit_t [NumRoutes-1:0] rsp_i, - output req_flit_t [NumRoutes-1:0] req_o, - output rsp_flit_t [NumRoutes-1:0] rsp_o + input floo_req_t [NumRoutes-1:0] req_i, + input floo_rsp_t [NumRoutes-1:0] rsp_i, + output floo_req_t [NumRoutes-1:0] req_o, + output floo_rsp_t [NumRoutes-1:0] rsp_o ); - req_data_t [NumRoutes-1:0] req_in, req_out; - rsp_data_t [NumRoutes-1:0] rsp_in, rsp_out; + floo_req_chan_t [NumRoutes-1:0] req_in, req_out; + floo_rsp_chan_t [NumRoutes-1:0] rsp_in, rsp_out; logic [NumRoutes-1:0] req_valid_in, req_valid_out; logic [NumRoutes-1:0] rsp_valid_in, rsp_valid_out; logic [NumRoutes-1:0] req_ready_in, rsp_ready_in; logic [NumRoutes-1:0] req_ready_out, rsp_ready_out; for (genvar i = 0; i < NumRoutes; i++) begin : gen_chimney_req - assign req_o[i].data = req_out[i]; - assign rsp_o[i].data = rsp_out[i]; - assign req_in[i] = req_i[i].data; - assign rsp_in[i] = rsp_i[i].data; + assign req_o[i].req = req_out[i]; + assign rsp_o[i].rsp = rsp_out[i]; + assign req_in[i] = req_i[i].req; + assign rsp_in[i] = rsp_i[i].rsp; assign req_valid_in[i] = req_i[i].valid; assign rsp_valid_in[i] = rsp_i[i].valid; assign req_ready_in[i] = req_i[i].ready; @@ -44,15 +44,15 @@ module floo_synth_router end floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( req_generic_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .RouteAlgo ( XYRouting ), - .IdWidth ( 4 ), - .id_t ( xy_id_t ), - .NumAddrRules ( 1 ) + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), + .NumRoutes ( NumRoutes ), + .flit_t ( floo_req_generic_flit_t ), + .ChannelFifoDepth ( 2 ), + .RouteAlgo ( XYRouting ), + .IdWidth ( 4 ), + .id_t ( xy_id_t ), + .NumAddrRules ( 1 ) ) i_req_floo_router ( .clk_i, .rst_ni, @@ -69,15 +69,15 @@ module floo_synth_router floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( rsp_generic_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .RouteAlgo ( XYRouting ), - .IdWidth ( 4 ), - .id_t ( xy_id_t ), - .NumAddrRules ( 1 ) + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), + .NumRoutes ( NumRoutes ), + .flit_t ( floo_rsp_generic_flit_t ), + .ChannelFifoDepth ( ChannelFifoDepth ), + .RouteAlgo ( XYRouting ), + .IdWidth ( 4 ), + .id_t ( xy_id_t ), + .NumAddrRules ( 1 ) ) i_rsp_floo_router ( .clk_i, .rst_ni, diff --git a/test/floo_axi_rand_slave.sv b/test/floo_axi_rand_slave.sv index 6ae639e1..d30d6aa9 100644 --- a/test/floo_axi_rand_slave.sv +++ b/test/floo_axi_rand_slave.sv @@ -22,11 +22,11 @@ module floo_axi_rand_slave // TB Parameters parameter time ApplTime = 2ns, parameter time TestTime = 8ns, - parameter int unsigned DstStartAddr = 0, - parameter int unsigned DstEndAddr = 0, + parameter logic[AxiAddrWidth-1:0] DstStartAddr = '0, + parameter logic[AxiAddrWidth-1:0] DstEndAddr = '0, parameter slave_type_e SlaveType = MixedSlave, - localparam int unsigned NumSlaves = 4, - localparam int unsigned SlvAddrSpace = (DstEndAddr - DstStartAddr) / NumSlaves + parameter int unsigned NumSlaves = 4, + localparam logic[AxiAddrWidth-1:0] SlvAddrSpace = (DstEndAddr - DstStartAddr) / NumSlaves ) ( input logic clk_i, input logic rst_ni, @@ -59,13 +59,14 @@ module floo_axi_rand_slave logic [AxiAddrWidth-1:0] end_addr; } xbar_rule_t; - xbar_rule_t [3:0] XbarAddrMap; - assign XbarAddrMap = '{ - '{ idx: 0, start_addr: DstStartAddr + 0 * SlvAddrSpace, end_addr: DstStartAddr + 1 * SlvAddrSpace }, - '{ idx: 1, start_addr: DstStartAddr + 1 * SlvAddrSpace, end_addr: DstStartAddr + 2 * SlvAddrSpace }, - '{ idx: 2, start_addr: DstStartAddr + 2 * SlvAddrSpace, end_addr: DstStartAddr + 3 * SlvAddrSpace }, - '{ idx: 3, start_addr: DstStartAddr + 3 * SlvAddrSpace, end_addr: DstStartAddr + 4 * SlvAddrSpace } - }; + xbar_rule_t [NumSlaves-1:0] XbarAddrMap; + for (genvar i = 0; i < NumSlaves; i++) begin : gen_addr_rules + assign XbarAddrMap[i] = '{ + idx: i, + start_addr: DstStartAddr + i * SlvAddrSpace, + end_addr: DstStartAddr + (i+1) * SlvAddrSpace + }; + end localparam axi_pkg::xbar_cfg_t XbarCfg = '{ NoSlvPorts: 1, diff --git a/test/floo_dma_test_node.sv b/test/floo_dma_test_node.sv index dabaa5de..436a24e7 100644 --- a/test/floo_dma_test_node.sv +++ b/test/floo_dma_test_node.sv @@ -29,8 +29,8 @@ module floo_dma_test_node #( parameter type axi_out_rsp_t = axi_rsp_t, parameter int unsigned TFLenWidth = 32, parameter int unsigned MemSysDepth = 0, - parameter int unsigned MemBaseAddr = 32'h0, - parameter int unsigned MemSize = 32'h10000, + parameter logic [AddrWidth-1:0] MemBaseAddr = 32'h0, + parameter logic [AddrWidth-1:0] MemSize = 32'h10000, parameter bit MaskInvalidData = 1, parameter bit RAWCouplingAvail = 1, parameter bit HardwareLegalizer = 1, @@ -142,7 +142,8 @@ module floo_dma_test_node #( UniqueIds: 0, AxiAddrWidth: AddrWidth, AxiDataWidth: DataWidth, - NoAddrRules: 1 + NoAddrRules: 1, + PipelineStages: 0 }; //-------------------------------------- diff --git a/test/floo_test_pkg.sv b/test/floo_test_pkg.sv index 9526d5fc..cae694ce 100644 --- a/test/floo_test_pkg.sv +++ b/test/floo_test_pkg.sv @@ -4,6 +4,8 @@ // // Tim Fischer +`include "floo_noc/typedef.svh" + package floo_test_pkg; typedef enum { @@ -12,4 +14,30 @@ package floo_test_pkg; MixedSlave } slave_type_e; + // System parameters + localparam int unsigned NumX = 4; + localparam int unsigned NumY = 4; + + // Router parameters + localparam int unsigned NumRoutes = 5; + localparam int unsigned ChannelFifoDepth = 2; + localparam int unsigned OutputFifoDepth = 2; + + // Chimney parameters + localparam bit CutAx = 1'b1; + localparam bit CutRsp = 1'b0; + localparam int unsigned MaxTxnsPerId = 16; + localparam bit RoBSimple = 1'b0; + localparam int unsigned ReorderBufferSize = 32'd64; + + // Narrow Wide Chimney parameters + localparam bit NarrowRoBSimple = 1'b1; + localparam int unsigned NarrowMaxTxnsPerId = 4; + localparam int unsigned NarrowReorderBufferSize = 32'd256; + localparam bit WideRoBSimple = 1'b0; + localparam int unsigned WideMaxTxnsPerId = 32; + localparam int unsigned WideReorderBufferSize = 32'd128; + + `FLOO_NOC_TYPEDEF_XY_ID_T(xy_id_t, NumX, NumY) + endpackage diff --git a/test/tb_floo_axi_chimney.sv b/test/tb_floo_axi_chimney.sv index 31f6aa68..a9d85932 100644 --- a/test/tb_floo_axi_chimney.sv +++ b/test/tb_floo_axi_chimney.sv @@ -11,7 +11,7 @@ module tb_floo_axi_chimney; import floo_pkg::*; - import floo_axi_flit_pkg::*; + import floo_axi_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -31,21 +31,21 @@ module tb_floo_axi_chimney; logic clk, rst_n; axi_in_req_t [NumTargets-1:0] node_man_req; - axi_in_resp_t [NumTargets-1:0] node_man_rsp; + axi_in_rsp_t [NumTargets-1:0] node_man_rsp; axi_out_req_t [NumTargets-1:0] node_sub_req; - axi_out_resp_t [NumTargets-1:0] node_sub_rsp; + axi_out_rsp_t [NumTargets-1:0] node_sub_rsp; axi_in_req_t [NumTargets-1:0] sub_req_id_assign; - axi_in_resp_t [NumTargets-1:0] sub_rsp_id_assign; + axi_in_rsp_t [NumTargets-1:0] sub_rsp_id_assign; for (genvar i = 0; i < NumTargets; i++) begin : gen_axi_assign `AXI_ASSIGN_REQ_STRUCT(sub_req_id_assign[i], node_sub_req[i]) `AXI_ASSIGN_RESP_STRUCT(sub_rsp_id_assign[i], node_sub_rsp[i]) end - req_flit_t [NumTargets-1:0] chimney_req; - rsp_flit_t [NumTargets-1:0] chimney_rsp; + floo_req_t [NumTargets-1:0] chimney_req; + floo_rsp_t [NumTargets-1:0] chimney_rsp; logic [NumTargets*2-1:0] end_of_sim; @@ -74,9 +74,9 @@ module tb_floo_axi_chimney; .AxiIdInWidth ( AxiOutIdWidth ), .AxiUserWidth ( AxiInUserWidth ), .mst_req_t ( axi_in_req_t ), - .mst_rsp_t ( axi_in_resp_t ), + .mst_rsp_t ( axi_in_rsp_t ), .slv_req_t ( axi_out_req_t ), - .slv_rsp_t ( axi_out_resp_t ), + .slv_rsp_t ( axi_out_rsp_t ), .ApplTime ( ApplTime ), .TestTime ( TestTime ), .Atops ( 1'b1 ), @@ -105,7 +105,7 @@ module tb_floo_axi_chimney; .ar_chan_t ( axi_in_ar_chan_t ), .r_chan_t ( axi_in_r_chan_t ), .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_resp_t ) + .rsp_t ( axi_in_rsp_t ) ) i_axi_chan_compare_0 ( .clk_i ( clk ), .mon_mst_req_i ( node_man_req[0] ), @@ -133,10 +133,10 @@ module tb_floo_axi_chimney; .axi_out_rsp_i ( node_sub_rsp[0] ), .xy_id_i ( '0 ), .id_i ( '0 ), - .req_o ( chimney_req[0] ), - .rsp_o ( chimney_rsp[0] ), - .req_i ( chimney_req[1] ), - .rsp_i ( chimney_rsp[1] ) + .floo_req_o ( chimney_req[0] ), + .floo_rsp_o ( chimney_rsp[0] ), + .floo_req_i ( chimney_req[1] ), + .floo_rsp_i ( chimney_rsp[1] ) ); floo_axi_chimney #( @@ -157,10 +157,10 @@ module tb_floo_axi_chimney; .axi_out_rsp_i ( node_sub_rsp[1] ), .xy_id_i ( '0 ), .id_i ( '0 ), - .req_o ( chimney_req[1] ), - .rsp_o ( chimney_rsp[1] ), - .req_i ( chimney_req[0] ), - .rsp_i ( chimney_rsp[0] ) + .floo_req_o ( chimney_req[1] ), + .floo_rsp_o ( chimney_rsp[1] ), + .floo_req_i ( chimney_req[0] ), + .floo_rsp_i ( chimney_rsp[0] ) ); axi_reorder_remap_compare #( @@ -172,7 +172,7 @@ module tb_floo_axi_chimney; .ar_chan_t ( axi_in_ar_chan_t ), .r_chan_t ( axi_in_r_chan_t ), .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_resp_t ) + .rsp_t ( axi_in_rsp_t ) ) i_axi_chan_compare_1 ( .clk_i ( clk ), .mon_mst_req_i ( node_man_req[1] ), @@ -189,9 +189,9 @@ module tb_floo_axi_chimney; .AxiIdOutWidth ( AxiInIdWidth ), .AxiUserWidth ( AxiInUserWidth ), .mst_req_t ( axi_in_req_t ), - .mst_rsp_t ( axi_in_resp_t ), + .mst_rsp_t ( axi_in_rsp_t ), .slv_req_t ( axi_out_req_t ), - .slv_rsp_t ( axi_out_resp_t ), + .slv_rsp_t ( axi_out_rsp_t ), .ApplTime ( ApplTime ), .TestTime ( TestTime ), .Atops ( 1'b1 ), @@ -213,7 +213,7 @@ module tb_floo_axi_chimney; axi_bw_monitor #( .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_resp_t ), + .rsp_t ( axi_in_rsp_t ), .AxiIdWidth ( AxiInIdWidth ) ) i_axi_bw_monitor ( .clk_i ( clk ), diff --git a/test/tb_floo_axi_chimney.wave.tcl b/test/tb_floo_axi_chimney.wave.tcl index 72c4780b..bf071cbe 100644 --- a/test/tb_floo_axi_chimney.wave.tcl +++ b/test/tb_floo_axi_chimney.wave.tcl @@ -21,17 +21,17 @@ for {set i 0} {$i < 2} {incr i} { add wave -noupdate -expand -group $group_name -group Arbiter tb_floo_axi_chimney/i_floo_axi_chimney_${i}/aw_w_sel_q add wave -noupdate -expand -group $group_name -group Arbiter tb_floo_axi_chimney/i_floo_axi_chimney_${i}/aw_w_sel_d - add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/aw_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/w_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/b_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/ar_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/r_data + add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/floo_axi_aw + add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/floo_axi_w + add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/floo_axi_b + add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/floo_axi_ar + add wave -noupdate -expand -group $group_name -group Packer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/floo_axi_r - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/unpack_aw_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/unpack_w_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/unpack_ar_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/unpack_b_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/unpack_r_data + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/axi_unpack_aw + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/axi_unpack_w + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/axi_unpack_ar + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/axi_unpack_b + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_axi_chimney/i_floo_axi_chimney_${i}/axi_unpack_r add wave -noupdate -expand -group $group_name -group AwMetaBuffer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/i_aw_meta_buffer/* add wave -noupdate -expand -group $group_name -group ArMetaBuffer tb_floo_axi_chimney/i_floo_axi_chimney_${i}/i_ar_meta_buffer/* diff --git a/test/tb_floo_dma_chimney.sv b/test/tb_floo_dma_chimney.sv index 94b6fbed..1d4c9709 100644 --- a/test/tb_floo_dma_chimney.sv +++ b/test/tb_floo_dma_chimney.sv @@ -11,7 +11,7 @@ module tb_floo_dma_chimney; import floo_pkg::*; - import floo_axi_flit_pkg::*; + import floo_axi_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 0ns; @@ -26,21 +26,21 @@ module tb_floo_dma_chimney; logic clk, rst_n; axi_in_req_t [NumTargets-1:0] node_man_req; - axi_in_resp_t [NumTargets-1:0] node_man_rsp; + axi_in_rsp_t [NumTargets-1:0] node_man_rsp; axi_in_req_t [NumTargets-1:0] node_sub_req; - axi_in_resp_t [NumTargets-1:0] node_sub_rsp; + axi_in_rsp_t [NumTargets-1:0] node_sub_rsp; axi_in_req_t [NumTargets-1:0] sub_req_id_mapped; - axi_in_resp_t [NumTargets-1:0] sub_rsp_id_mapped; + axi_in_rsp_t [NumTargets-1:0] sub_rsp_id_mapped; for (genvar i = 0; i < NumTargets; i++) begin : gen_axi_assign `AXI_ASSIGN_REQ_STRUCT(sub_req_id_mapped[i], node_sub_req[i]) `AXI_ASSIGN_RESP_STRUCT(sub_rsp_id_mapped[i], node_sub_rsp[i]) end - req_flit_t [NumTargets-1:0] chimney_req; - rsp_flit_t [NumTargets-1:0] chimney_rsp; + floo_req_t [NumTargets-1:0] chimney_req; + floo_rsp_t [NumTargets-1:0] chimney_rsp; logic [NumTargets-1:0] end_of_sim; @@ -71,7 +71,7 @@ module tb_floo_dma_chimney; .MemBaseAddr ( MemBaseAddr ), .MemSize ( MemSize ), .axi_req_t ( axi_in_req_t ), - .axi_rsp_t ( axi_in_resp_t ), + .axi_rsp_t ( axi_in_rsp_t ), .JobId ( 0 ) ) i_floo_dma_test_node_0 ( .clk_i ( clk ), @@ -90,7 +90,7 @@ module tb_floo_dma_chimney; .ar_chan_t ( axi_in_ar_chan_t ), .r_chan_t ( axi_in_r_chan_t ), .req_t ( axi_in_req_t ), - .resp_t ( axi_in_resp_t ) + .resp_t ( axi_in_rsp_t ) ) i_axi_channel_compare_0 ( .clk_i ( clk ), .axi_a_req ( node_man_req[0] ), @@ -100,6 +100,7 @@ module tb_floo_dma_chimney; ); floo_axi_chimney #( + .AtopSupport ( 1'b0 ), .RouteAlgo ( floo_pkg::IdTable ), .MaxTxns ( MaxTxns ), .MaxTxnsPerId ( MaxTxnsPerId ), @@ -115,13 +116,14 @@ module tb_floo_dma_chimney; .axi_out_rsp_i ( node_sub_rsp[0] ), .xy_id_i ( '0 ), .id_i ( '0 ), - .req_o ( chimney_req[0] ), - .rsp_o ( chimney_rsp[0] ), - .req_i ( chimney_req[1] ), - .rsp_i ( chimney_rsp[1] ) + .floo_req_o ( chimney_req[0] ), + .floo_rsp_o ( chimney_rsp[0] ), + .floo_req_i ( chimney_req[1] ), + .floo_rsp_i ( chimney_rsp[1] ) ); floo_axi_chimney #( + .AtopSupport ( 1'b0 ), .RouteAlgo ( floo_pkg::IdTable ), .MaxTxns ( MaxTxns ), .MaxTxnsPerId ( MaxTxnsPerId ), @@ -137,10 +139,10 @@ module tb_floo_dma_chimney; .axi_out_rsp_i ( node_sub_rsp[1] ), .xy_id_i ( '0 ), .id_i ( '0 ), - .req_o ( chimney_req[1] ), - .rsp_o ( chimney_rsp[1] ), - .req_i ( chimney_req[0] ), - .rsp_i ( chimney_rsp[0] ) + .floo_req_o ( chimney_req[1] ), + .floo_rsp_o ( chimney_rsp[1] ), + .floo_req_i ( chimney_req[0] ), + .floo_rsp_i ( chimney_rsp[0] ) ); axi_channel_compare #( @@ -150,7 +152,7 @@ module tb_floo_dma_chimney; .ar_chan_t ( axi_in_ar_chan_t ), .r_chan_t ( axi_in_r_chan_t ), .req_t ( axi_in_req_t ), - .resp_t ( axi_in_resp_t ) + .resp_t ( axi_in_rsp_t ) ) i_axi_channel_compare_1 ( .clk_i(clk), .axi_a_req ( node_man_req[1] ), @@ -170,7 +172,7 @@ module tb_floo_dma_chimney; .MemBaseAddr ( MemBaseAddr ), .MemSize ( MemSize ), .axi_req_t ( axi_in_req_t ), - .axi_rsp_t ( axi_in_resp_t ), + .axi_rsp_t ( axi_in_rsp_t ), .JobId ( 1 ) ) i_floo_dma_test_node_1 ( .clk_i ( clk ), @@ -184,7 +186,7 @@ module tb_floo_dma_chimney; axi_bw_monitor #( .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_resp_t ), + .rsp_t ( axi_in_rsp_t ), .AxiIdWidth ( AxiInIdWidth ) ) i_axi_bw_monitor ( .clk_i ( clk ), diff --git a/test/tb_floo_dma_mesh.sv b/test/tb_floo_dma_mesh.sv index 6d98c12e..fbee5fba 100644 --- a/test/tb_floo_dma_mesh.sv +++ b/test/tb_floo_dma_mesh.sv @@ -9,7 +9,7 @@ module tb_floo_dma_mesh; import floo_pkg::*; - import floo_narrow_wide_flit_pkg::*; + import floo_narrow_wide_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -49,42 +49,42 @@ module tb_floo_dma_mesh; // AXI Signals // ///////////////////// - narrow_in_req_t [NumX-1:0][NumY-1:0] narrow_man_req; - narrow_in_resp_t [NumX-1:0][NumY-1:0] narrow_man_rsp; - wide_in_req_t [NumX-1:0][NumY-1:0] wide_man_req; - wide_in_resp_t [NumX-1:0][NumY-1:0] wide_man_rsp; + axi_narrow_in_req_t [NumX-1:0][NumY-1:0] narrow_man_req; + axi_narrow_in_rsp_t [NumX-1:0][NumY-1:0] narrow_man_rsp; + axi_wide_in_req_t [NumX-1:0][NumY-1:0] wide_man_req; + axi_wide_in_rsp_t [NumX-1:0][NumY-1:0] wide_man_rsp; - narrow_out_req_t [NumX-1:0][NumY-1:0] narrow_sub_req; - narrow_out_resp_t [NumX-1:0][NumY-1:0] narrow_sub_rsp; - wide_out_req_t [NumX-1:0][NumY-1:0] wide_sub_req; - wide_out_resp_t [NumX-1:0][NumY-1:0] wide_sub_rsp; + axi_narrow_out_req_t [NumX-1:0][NumY-1:0] narrow_sub_req; + axi_narrow_out_rsp_t [NumX-1:0][NumY-1:0] narrow_sub_rsp; + axi_wide_out_req_t [NumX-1:0][NumY-1:0] wide_sub_req; + axi_wide_out_rsp_t [NumX-1:0][NumY-1:0] wide_sub_rsp; - narrow_out_req_t [West:North][NumMax-1:0] narrow_hbm_req; - narrow_out_resp_t [West:North][NumMax-1:0] narrow_hbm_rsp; - wide_out_req_t [West:North][NumMax-1:0] wide_hbm_req; - wide_out_resp_t [West:North][NumMax-1:0] wide_hbm_rsp; + axi_narrow_out_req_t [West:North][NumMax-1:0] narrow_hbm_req; + axi_narrow_out_rsp_t [West:North][NumMax-1:0] narrow_hbm_rsp; + axi_wide_out_req_t [West:North][NumMax-1:0] wide_hbm_req; + axi_wide_out_rsp_t [West:North][NumMax-1:0] wide_hbm_rsp; ///////////////////// // NoC Signals // ///////////////////// - narrow_req_flit_t [NumX-1:0][NumY-1:0] narrow_chimney_man_req, narrow_chimney_sub_req; - narrow_rsp_flit_t [NumX-1:0][NumY-1:0] narrow_chimney_man_rsp, narrow_chimney_sub_rsp; - wide_flit_t [NumX-1:0][NumY-1:0] wide_chimney_man, wide_chimney_sub; + floo_req_t [NumX-1:0][NumY-1:0] narrow_chimney_man_req, narrow_chimney_sub_req; + floo_rsp_t [NumX-1:0][NumY-1:0] narrow_chimney_man_rsp, narrow_chimney_sub_rsp; + floo_wide_t [NumX-1:0][NumY-1:0] wide_chimney_man, wide_chimney_sub; - narrow_req_flit_t [NumX:0][NumY-1:0] narrow_req_hor_pos; - narrow_req_flit_t [NumX:0][NumY-1:0] narrow_req_hor_neg; - narrow_req_flit_t [NumY:0][NumX-1:0] narrow_req_ver_pos; - narrow_req_flit_t [NumY:0][NumX-1:0] narrow_req_ver_neg; - narrow_rsp_flit_t [NumX:0][NumY-1:0] narrow_rsp_hor_pos; - narrow_rsp_flit_t [NumX:0][NumY-1:0] narrow_rsp_hor_neg; - narrow_rsp_flit_t [NumY:0][NumX-1:0] narrow_rsp_ver_pos; - narrow_rsp_flit_t [NumY:0][NumX-1:0] narrow_rsp_ver_neg; - wide_flit_t [NumX:0][NumY-1:0] wide_hor_pos; - wide_flit_t [NumX:0][NumY-1:0] wide_hor_neg; - wide_flit_t [NumY:0][NumX-1:0] wide_ver_pos; - wide_flit_t [NumY:0][NumX-1:0] wide_ver_neg; + floo_req_t [NumX:0][NumY-1:0] req_hor_pos; + floo_req_t [NumX:0][NumY-1:0] req_hor_neg; + floo_req_t [NumY:0][NumX-1:0] req_ver_pos; + floo_req_t [NumY:0][NumX-1:0] req_ver_neg; + floo_rsp_t [NumX:0][NumY-1:0] rsp_hor_pos; + floo_rsp_t [NumX:0][NumY-1:0] rsp_hor_neg; + floo_rsp_t [NumY:0][NumX-1:0] rsp_ver_pos; + floo_rsp_t [NumY:0][NumX-1:0] rsp_ver_neg; + floo_wide_t [NumX:0][NumY-1:0] wide_hor_pos; + floo_wide_t [NumX:0][NumY-1:0] wide_hor_neg; + floo_wide_t [NumY:0][NumX-1:0] wide_ver_pos; + floo_wide_t [NumY:0][NumX-1:0] wide_ver_neg; logic [NumX-1:0][NumY-1:0][1:0] end_of_sim; @@ -102,22 +102,22 @@ module tb_floo_dma_mesh; //////////////////////////////// floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .MemSize ( HBMSize ), - .DataWidth ( WideOutDataWidth ), - .UserWidth ( WideOutUserWidth ), - .IdWidth ( WideOutIdWidth ), - .axi_req_t ( wide_out_req_t ), - .axi_rsp_t ( wide_out_resp_t ), - .aw_chan_t ( wide_out_aw_chan_t ), - .w_chan_t ( wide_out_w_chan_t ), - .b_chan_t ( wide_out_b_chan_t ), - .ar_chan_t ( wide_out_ar_chan_t ), - .r_chan_t ( wide_out_r_chan_t ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .Latency ( HBMLatency ), + .NumChannels ( 1 ), + .MemSize ( HBMSize ), + .DataWidth ( WideOutDataWidth ), + .UserWidth ( WideOutUserWidth ), + .IdWidth ( WideOutIdWidth ), + .axi_req_t ( axi_wide_out_req_t ), + .axi_rsp_t ( axi_wide_out_rsp_t ), + .aw_chan_t ( axi_wide_out_aw_chan_t ), + .w_chan_t ( axi_wide_out_w_chan_t ), + .b_chan_t ( axi_wide_out_b_chan_t ), + .ar_chan_t ( axi_wide_out_ar_chan_t ), + .r_chan_t ( axi_wide_out_r_chan_t ) ) i_floo_wide_hbm_model [West:North][NumMax-1:0] ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -126,22 +126,22 @@ module tb_floo_dma_mesh; ); floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .MemSize ( HBMSize ), - .DataWidth ( NarrowOutDataWidth ), - .UserWidth ( NarrowOutUserWidth ), - .IdWidth ( NarrowOutIdWidth ), - .axi_req_t ( narrow_out_req_t ), - .axi_rsp_t ( narrow_out_resp_t ), - .aw_chan_t ( narrow_out_aw_chan_t ), - .w_chan_t ( narrow_out_w_chan_t ), - .b_chan_t ( narrow_out_b_chan_t ), - .ar_chan_t ( narrow_out_ar_chan_t ), - .r_chan_t ( narrow_out_r_chan_t ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .Latency ( HBMLatency ), + .NumChannels ( 1 ), + .MemSize ( HBMSize ), + .DataWidth ( NarrowOutDataWidth ), + .UserWidth ( NarrowOutUserWidth ), + .IdWidth ( NarrowOutIdWidth ), + .axi_req_t ( axi_narrow_out_req_t ), + .axi_rsp_t ( axi_narrow_out_rsp_t ), + .aw_chan_t ( axi_narrow_out_aw_chan_t ), + .w_chan_t ( axi_narrow_out_w_chan_t ), + .b_chan_t ( axi_narrow_out_b_chan_t ), + .ar_chan_t ( axi_narrow_out_ar_chan_t ), + .r_chan_t ( axi_narrow_out_r_chan_t ) ) i_floo_narrow_hbm_model [West:North][NumMax-1:0] ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -153,53 +153,53 @@ module tb_floo_dma_mesh; localparam int unsigned NumChimneys = (i == North || i == South) ? NumX : NumY; - narrow_req_flit_t [NumChimneys-1:0] narrow_req_hbm_in, narrow_req_hbm_out; - narrow_rsp_flit_t [NumChimneys-1:0] narrow_rsp_hbm_in, narrow_rsp_hbm_out; - wide_flit_t [NumChimneys-1:0] wide_hbm_in, wide_hbm_out; + floo_req_t [NumChimneys-1:0] req_hbm_in, req_hbm_out; + floo_rsp_t [NumChimneys-1:0] rsp_hbm_in, rsp_hbm_out; + floo_wide_t [NumChimneys-1:0] wide_hbm_in, wide_hbm_out; xy_id_t [NumChimneys-1:0] xy_id_hbm; if (i == North) begin : gen_north_hbm_chimneys for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id assign xy_id_hbm[j] = '{x: j+1, y: NumY+1}; end - assign narrow_req_hbm_in = narrow_req_ver_pos[NumY]; - assign narrow_rsp_hbm_in = narrow_rsp_ver_pos[NumY]; + assign req_hbm_in = req_ver_pos[NumY]; + assign rsp_hbm_in = rsp_ver_pos[NumY]; assign wide_hbm_in = wide_ver_pos[NumY]; - assign narrow_req_ver_neg[NumY] = narrow_req_hbm_out; - assign narrow_rsp_ver_neg[NumY] = narrow_rsp_hbm_out; + assign req_ver_neg[NumY] = req_hbm_out; + assign rsp_ver_neg[NumY] = rsp_hbm_out; assign wide_ver_neg[NumY] = wide_hbm_out; end else if (i == South) begin : gen_south_hbm_chimneys for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id assign xy_id_hbm[j] = '{x: j+1, y: 0}; end - assign narrow_req_hbm_in = narrow_req_ver_neg[0]; - assign narrow_rsp_hbm_in = narrow_rsp_ver_neg[0]; + assign req_hbm_in = req_ver_neg[0]; + assign rsp_hbm_in = rsp_ver_neg[0]; assign wide_hbm_in = wide_ver_neg[0]; - assign narrow_req_ver_pos[0] = narrow_req_hbm_out; - assign narrow_rsp_ver_pos[0] = narrow_rsp_hbm_out; + assign req_ver_pos[0] = req_hbm_out; + assign rsp_ver_pos[0] = rsp_hbm_out; assign wide_ver_pos[0] = wide_hbm_out; end else if (i == East) begin : gen_east_hbm_chimneys for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id assign xy_id_hbm[j] = '{x: NumX, y: j+1}; end - assign narrow_req_hbm_in = narrow_req_hor_pos[NumX]; - assign narrow_rsp_hbm_in = narrow_rsp_hor_pos[NumX]; + assign req_hbm_in = req_hor_pos[NumX]; + assign rsp_hbm_in = rsp_hor_pos[NumX]; assign wide_hbm_in = wide_hor_pos[NumX]; - assign narrow_req_hor_neg[NumX] = narrow_req_hbm_out; - assign narrow_rsp_hor_neg[NumX] = narrow_rsp_hbm_out; + assign req_hor_neg[NumX] = req_hbm_out; + assign rsp_hor_neg[NumX] = rsp_hbm_out; assign wide_hor_neg[NumX] = wide_hbm_out; end else if (i == West) begin : gen_west_hbm_chimneys for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id assign xy_id_hbm[j] = '{x: 0, y: j+1}; end - assign narrow_req_hbm_in = narrow_req_hor_neg[0]; - assign narrow_rsp_hbm_in = narrow_rsp_hor_neg[0]; + assign req_hbm_in = req_hor_neg[0]; + assign rsp_hbm_in = rsp_hor_neg[0]; assign wide_hbm_in = wide_hor_neg[0]; - assign narrow_req_hor_pos[0] = narrow_req_hbm_out; - assign narrow_rsp_hor_pos[0] = narrow_rsp_hbm_out; + assign req_hor_pos[0] = req_hbm_out; + assign rsp_hor_pos[0] = rsp_hbm_out; assign wide_hor_pos[0] = wide_hbm_out; end @@ -217,26 +217,26 @@ module tb_floo_dma_mesh; .CutRsp ( CutRsp ), .xy_id_t ( xy_id_t ) ) i_hbm_chimney [NumChimneys-1:0] ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .id_i ( '0 ), - .xy_id_i ( xy_id_hbm ), - .narrow_in_req_i ( '0 ), - .narrow_in_rsp_o ( ), - .narrow_out_req_o ( narrow_hbm_req[i] ), - .narrow_out_rsp_i ( narrow_hbm_rsp[i] ), - .wide_in_req_i ( '0 ), - .wide_in_rsp_o ( ), - .wide_out_req_o ( wide_hbm_req[i] ), - .wide_out_rsp_i ( wide_hbm_rsp[i] ), - .narrow_req_i ( narrow_req_hbm_in ), - .narrow_req_o ( narrow_req_hbm_out ), - .narrow_rsp_i ( narrow_rsp_hbm_in ), - .narrow_rsp_o ( narrow_rsp_hbm_out ), - .wide_i ( wide_hbm_in ), - .wide_o ( wide_hbm_out ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .id_i ( '0 ), + .xy_id_i ( xy_id_hbm ), + .axi_narrow_in_req_i ( '0 ), + .axi_narrow_in_rsp_o ( ), + .axi_narrow_out_req_o ( narrow_hbm_req[i] ), + .axi_narrow_out_rsp_i ( narrow_hbm_rsp[i] ), + .axi_wide_in_req_i ( '0 ), + .axi_wide_in_rsp_o ( ), + .axi_wide_out_req_o ( wide_hbm_req[i] ), + .axi_wide_out_rsp_i ( wide_hbm_rsp[i] ), + .floo_req_i ( req_hbm_in ), + .floo_req_o ( req_hbm_out ), + .floo_rsp_i ( rsp_hbm_in ), + .floo_rsp_o ( rsp_hbm_out ), + .floo_wide_i ( wide_hbm_in ), + .floo_wide_o ( wide_hbm_out ) ); end @@ -251,9 +251,9 @@ module tb_floo_dma_mesh; xy_id_t current_id; localparam string narrow_dma_name = $sformatf("narrow_dma_%0d_%0d", x, y); localparam string wide_dma_name = $sformatf("wide_dma_%0d_%0d", x, y); - narrow_req_flit_t [NumDirections-1:0] narrow_req_out, narrow_req_in; - narrow_rsp_flit_t [NumDirections-1:0] narrow_rsp_out, narrow_rsp_in; - wide_flit_t [NumDirections-1:0] wide_out, wide_in; + floo_req_t [NumDirections-1:0] req_out, req_in; + floo_rsp_t [NumDirections-1:0] rsp_out, rsp_in; + floo_wide_t [NumDirections-1:0] wide_out, wide_in; localparam int unsigned index = y * NumX + x+1; localparam MemBaseAddr = (x+1) << XYAddrOffsetX | (y+1) << XYAddrOffsetY; @@ -271,11 +271,11 @@ module tb_floo_dma_mesh; .MemBaseAddr ( MemBaseAddr ), .MemSize ( MemSize ), .NumAxInFlight ( 2*NarrowMaxTxnsPerId ), - .axi_in_req_t ( narrow_out_req_t ), - .axi_in_rsp_t ( narrow_out_resp_t ), - .axi_out_req_t ( narrow_in_req_t ), - .axi_out_rsp_t ( narrow_in_resp_t ), - .JobId ( 100 + index ) + .axi_in_req_t ( axi_narrow_out_req_t ), + .axi_in_rsp_t ( axi_narrow_out_rsp_t ), + .axi_out_req_t ( axi_narrow_in_req_t ), + .axi_out_rsp_t ( axi_narrow_in_rsp_t ), + .JobId ( 100 + index ) ) i_narrow_dma_node ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -298,10 +298,10 @@ module tb_floo_dma_mesh; .MemBaseAddr ( MemBaseAddr ), .MemSize ( MemSize ), .NumAxInFlight ( 2*WideMaxTxnsPerId ), - .axi_in_req_t ( wide_out_req_t ), - .axi_in_rsp_t ( wide_out_resp_t ), - .axi_out_req_t ( wide_in_req_t ), - .axi_out_rsp_t ( wide_in_resp_t ), + .axi_in_req_t ( axi_wide_out_req_t ), + .axi_in_rsp_t ( axi_wide_out_rsp_t ), + .axi_out_req_t ( axi_wide_in_req_t ), + .axi_out_rsp_t ( axi_wide_in_rsp_t ), .JobId ( index ) ) i_wide_dma_node ( .clk_i ( clk ), @@ -314,10 +314,10 @@ module tb_floo_dma_mesh; ); axi_bw_monitor #( - .req_t ( narrow_in_req_t ), - .rsp_t ( narrow_in_resp_t ), - .AxiIdWidth ( NarrowInIdWidth ), - .name ( narrow_dma_name ) + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ), + .AxiIdWidth ( NarrowInIdWidth ), + .name ( narrow_dma_name ) ) i_axi_narrow_bw_monitor ( .clk_i ( clk ), .en_i ( rst_n ), @@ -329,10 +329,10 @@ module tb_floo_dma_mesh; ); axi_bw_monitor #( - .req_t ( wide_in_req_t ), - .rsp_t ( wide_in_resp_t ), - .AxiIdWidth ( WideInIdWidth ), - .name ( wide_dma_name ) + .req_t ( axi_wide_in_req_t ), + .rsp_t ( axi_wide_in_rsp_t ), + .AxiIdWidth ( WideInIdWidth ), + .name ( wide_dma_name ) ) i_axi_wide_bw_monitor ( .clk_i ( clk ), .en_i ( rst_n ), @@ -357,26 +357,26 @@ module tb_floo_dma_mesh; .CutRsp ( CutRsp ), .xy_id_t ( xy_id_t ) ) i_dma_chimney ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .id_i ( '0 ), - .xy_id_i ( current_id ), - .narrow_in_req_i ( narrow_man_req[x][y] ), - .narrow_in_rsp_o ( narrow_man_rsp[x][y] ), - .narrow_out_req_o ( narrow_sub_req[x][y] ), - .narrow_out_rsp_i ( narrow_sub_rsp[x][y] ), - .wide_in_req_i ( wide_man_req[x][y] ), - .wide_in_rsp_o ( wide_man_rsp[x][y] ), - .wide_out_req_o ( wide_sub_req[x][y] ), - .wide_out_rsp_i ( wide_sub_rsp[x][y] ), - .narrow_req_i ( narrow_chimney_sub_req[x][y] ), - .narrow_req_o ( narrow_chimney_man_req[x][y] ), - .narrow_rsp_i ( narrow_chimney_man_rsp[x][y] ), - .narrow_rsp_o ( narrow_chimney_sub_rsp[x][y] ), - .wide_i ( wide_chimney_sub[x][y] ), - .wide_o ( wide_chimney_man[x][y] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .id_i ( '0 ), + .xy_id_i ( current_id ), + .axi_narrow_in_req_i ( narrow_man_req[x][y] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[x][y] ), + .axi_narrow_out_req_o ( narrow_sub_req[x][y] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[x][y] ), + .axi_wide_in_req_i ( wide_man_req[x][y] ), + .axi_wide_in_rsp_o ( wide_man_rsp[x][y] ), + .axi_wide_out_req_o ( wide_sub_req[x][y] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[x][y] ), + .floo_req_i ( narrow_chimney_sub_req[x][y] ), + .floo_req_o ( narrow_chimney_man_req[x][y] ), + .floo_rsp_i ( narrow_chimney_man_rsp[x][y] ), + .floo_rsp_o ( narrow_chimney_sub_rsp[x][y] ), + .floo_wide_i ( wide_chimney_sub[x][y] ), + .floo_wide_o ( wide_chimney_man[x][y] ) ); floo_narrow_wide_router #( @@ -386,56 +386,56 @@ module tb_floo_dma_mesh; .RouteAlgo ( RouteAlgo ), .id_t ( xy_id_t ) ) i_router ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_enable_i ( 1'b0 ), - .xy_id_i ( current_id ), - .id_route_map_i ( '0 ), - .narrow_req_i ( narrow_req_in ), - .narrow_req_o ( narrow_req_out ), - .narrow_rsp_i ( narrow_rsp_in ), - .narrow_rsp_o ( narrow_rsp_out ), - .wide_i ( wide_in ), - .wide_o ( wide_out ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .xy_id_i ( current_id ), + .id_route_map_i ( '0 ), + .floo_req_i ( req_in ), + .floo_req_o ( req_out ), + .floo_rsp_i ( rsp_in ), + .floo_rsp_o ( rsp_out ), + .floo_wide_i ( wide_in ), + .floo_wide_o ( wide_out ) ); // Eject - assign narrow_req_in[Eject] = narrow_chimney_man_req[x][y]; - assign narrow_chimney_sub_req[x][y] = narrow_req_out[Eject]; - assign narrow_rsp_in[Eject] = narrow_chimney_sub_rsp[x][y]; - assign narrow_chimney_man_rsp[x][y] = narrow_rsp_out[Eject]; + assign req_in[Eject] = narrow_chimney_man_req[x][y]; + assign narrow_chimney_sub_req[x][y] = req_out[Eject]; + assign rsp_in[Eject] = narrow_chimney_sub_rsp[x][y]; + assign narrow_chimney_man_rsp[x][y] = rsp_out[Eject]; assign wide_in[Eject] = wide_chimney_man[x][y]; assign wide_chimney_sub[x][y] = wide_out[Eject]; // East - assign narrow_req_in[East] = narrow_req_hor_neg[x+1][y]; - assign narrow_req_hor_pos[x+1][y] = narrow_req_out[East]; - assign narrow_rsp_in[East] = narrow_rsp_hor_neg[x+1][y]; - assign narrow_rsp_hor_pos[x+1][y] = narrow_rsp_out[East]; + assign req_in[East] = req_hor_neg[x+1][y]; + assign req_hor_pos[x+1][y] = req_out[East]; + assign rsp_in[East] = rsp_hor_neg[x+1][y]; + assign rsp_hor_pos[x+1][y] = rsp_out[East]; assign wide_in[East] = wide_hor_neg[x+1][y]; assign wide_hor_pos[x+1][y] = wide_out[East]; // West - assign narrow_req_in[West] = narrow_req_hor_pos[x][y]; - assign narrow_req_hor_neg[x][y] = narrow_req_out[West]; - assign narrow_rsp_in[West] = narrow_rsp_hor_pos[x][y]; - assign narrow_rsp_hor_neg[x][y] = narrow_rsp_out[West]; + assign req_in[West] = req_hor_pos[x][y]; + assign req_hor_neg[x][y] = req_out[West]; + assign rsp_in[West] = rsp_hor_pos[x][y]; + assign rsp_hor_neg[x][y] = rsp_out[West]; assign wide_in[West] = wide_hor_pos[x][y]; assign wide_hor_neg[x][y] = wide_out[West]; // North - assign narrow_req_in[North] = narrow_req_ver_neg[y+1][x]; - assign narrow_req_ver_pos[y+1][x] = narrow_req_out[North]; - assign narrow_rsp_in[North] = narrow_rsp_ver_neg[y+1][x]; - assign narrow_rsp_ver_pos[y+1][x] = narrow_rsp_out[North]; + assign req_in[North] = req_ver_neg[y+1][x]; + assign req_ver_pos[y+1][x] = req_out[North]; + assign rsp_in[North] = rsp_ver_neg[y+1][x]; + assign rsp_ver_pos[y+1][x] = rsp_out[North]; assign wide_in[North] = wide_ver_neg[y+1][x]; assign wide_ver_pos[y+1][x] = wide_out[North]; // South - assign narrow_req_in[South] = narrow_req_ver_pos[y][x]; - assign narrow_req_ver_neg[y][x] = narrow_req_out[South]; - assign narrow_rsp_in[South] = narrow_rsp_ver_pos[y][x]; - assign narrow_rsp_ver_neg[y][x] = narrow_rsp_out[South]; + assign req_in[South] = req_ver_pos[y][x]; + assign req_ver_neg[y][x] = req_out[South]; + assign rsp_in[South] = rsp_ver_pos[y][x]; + assign rsp_ver_neg[y][x] = rsp_out[South]; assign wide_in[South] = wide_ver_pos[y][x]; assign wide_ver_neg[y][x] = wide_out[South]; diff --git a/test/tb_floo_dma_nw_chimney.sv b/test/tb_floo_dma_nw_chimney.sv index be16e9ec..e04520ae 100644 --- a/test/tb_floo_dma_nw_chimney.sv +++ b/test/tb_floo_dma_nw_chimney.sv @@ -11,7 +11,7 @@ module tb_floo_dma_nw_chimney; import floo_pkg::*; - import floo_narrow_wide_flit_pkg::*; + import floo_narrow_wide_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -25,20 +25,20 @@ module tb_floo_dma_nw_chimney; logic clk, rst_n; - narrow_in_req_t [NumTargets-1:0] narrow_man_req; - narrow_in_resp_t [NumTargets-1:0] narrow_man_rsp; - wide_in_req_t [NumTargets-1:0] wide_man_req; - wide_in_resp_t [NumTargets-1:0] wide_man_rsp; + axi_narrow_in_req_t [NumTargets-1:0] narrow_man_req; + axi_narrow_in_rsp_t [NumTargets-1:0] narrow_man_rsp; + axi_wide_in_req_t [NumTargets-1:0] wide_man_req; + axi_wide_in_rsp_t [NumTargets-1:0] wide_man_rsp; - narrow_out_req_t [NumTargets-1:0] narrow_sub_req; - narrow_out_resp_t [NumTargets-1:0] narrow_sub_rsp; - wide_out_req_t [NumTargets-1:0] wide_sub_req; - wide_out_resp_t [NumTargets-1:0] wide_sub_rsp; + axi_narrow_out_req_t [NumTargets-1:0] narrow_sub_req; + axi_narrow_out_rsp_t [NumTargets-1:0] narrow_sub_rsp; + axi_wide_out_req_t [NumTargets-1:0] wide_sub_req; + axi_wide_out_rsp_t [NumTargets-1:0] wide_sub_rsp; - narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; - narrow_in_resp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; - wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; - wide_in_resp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; + axi_narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; + axi_narrow_in_rsp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; + axi_wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; + axi_wide_in_rsp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; for (genvar i = 0; i < NumDirections; i++) begin : gen_dir `AXI_ASSIGN_REQ_STRUCT(narrow_sub_req_id_mapped[i], narrow_sub_req[i]) @@ -47,9 +47,9 @@ module tb_floo_dma_nw_chimney; `AXI_ASSIGN_RESP_STRUCT(wide_sub_rsp_id_mapped[i], wide_sub_rsp[i]) end - narrow_req_flit_t [NumTargets-1:0] narrow_chimney_req, narrow_chimney_req_cut; - narrow_rsp_flit_t [NumTargets-1:0] narrow_chimney_rsp, narrow_chimney_rsp_cut; - wide_flit_t [NumTargets-1:0] wide_chimney, wide_chimney_cut; + floo_req_t [NumTargets-1:0] chimney_req, chimney_req_cut; + floo_rsp_t [NumTargets-1:0] chimney_rsp, chimney_rsp_cut; + floo_wide_t [NumTargets-1:0] chimney_wide, chimney_wide_cut; logic [NumTargets*2-1:0] end_of_sim; @@ -70,21 +70,21 @@ module tb_floo_dma_nw_chimney; localparam int unsigned MemSize = 32'h0001_0000; floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .DataWidth ( NarrowInDataWidth ), - .AddrWidth ( NarrowInAddrWidth ), - .UserWidth ( NarrowInUserWidth ), - .AxiIdInWidth ( NarrowOutIdWidth ), - .AxiIdOutWidth ( NarrowInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( narrow_out_req_t ), - .axi_in_rsp_t ( narrow_out_resp_t ), - .axi_out_req_t ( narrow_in_req_t ), - .axi_out_rsp_t ( narrow_in_resp_t ), - .JobId ( 100 ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .DataWidth ( NarrowInDataWidth ), + .AddrWidth ( NarrowInAddrWidth ), + .UserWidth ( NarrowInUserWidth ), + .AxiIdInWidth ( NarrowOutIdWidth ), + .AxiIdOutWidth ( NarrowInIdWidth ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .axi_in_req_t ( axi_narrow_out_req_t ), + .axi_in_rsp_t ( axi_narrow_out_rsp_t ), + .axi_out_req_t ( axi_narrow_in_req_t ), + .axi_out_rsp_t ( axi_narrow_in_rsp_t ), + .JobId ( 100 ) ) i_narrow_dma_node_0 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -96,21 +96,21 @@ module tb_floo_dma_nw_chimney; ); floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .DataWidth ( WideInDataWidth ), - .AddrWidth ( WideInAddrWidth ), - .UserWidth ( WideInUserWidth ), - .AxiIdInWidth ( WideOutIdWidth ), - .AxiIdOutWidth ( WideInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( wide_out_req_t ), - .axi_in_rsp_t ( wide_out_resp_t ), - .axi_out_req_t ( wide_in_req_t ), - .axi_out_rsp_t ( wide_in_resp_t ), - .JobId ( 0 ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .DataWidth ( WideInDataWidth ), + .AddrWidth ( WideInAddrWidth ), + .UserWidth ( WideInUserWidth ), + .AxiIdInWidth ( WideOutIdWidth ), + .AxiIdOutWidth ( WideInIdWidth ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .axi_in_req_t ( axi_wide_out_req_t ), + .axi_in_rsp_t ( axi_wide_out_rsp_t ), + .axi_out_req_t ( axi_wide_in_req_t ), + .axi_out_rsp_t ( axi_wide_in_rsp_t ), + .JobId ( 0 ) ) i_wide_dma_node_0 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -122,13 +122,13 @@ module tb_floo_dma_nw_chimney; ); axi_channel_compare #( - .aw_chan_t ( narrow_in_aw_chan_t ), - .w_chan_t ( narrow_in_w_chan_t ), - .b_chan_t ( narrow_in_b_chan_t ), - .ar_chan_t ( narrow_in_ar_chan_t ), - .r_chan_t ( narrow_in_r_chan_t ), - .req_t ( narrow_in_req_t ), - .resp_t ( narrow_in_resp_t ) + .aw_chan_t ( axi_narrow_in_aw_chan_t ), + .w_chan_t ( axi_narrow_in_w_chan_t ), + .b_chan_t ( axi_narrow_in_b_chan_t ), + .ar_chan_t ( axi_narrow_in_ar_chan_t ), + .r_chan_t ( axi_narrow_in_r_chan_t ), + .req_t ( axi_narrow_in_req_t ), + .resp_t ( axi_narrow_in_rsp_t ) ) i_narrow_channel_compare_0 ( .clk_i ( clk ), .axi_a_req ( narrow_man_req[0] ), @@ -138,13 +138,13 @@ module tb_floo_dma_nw_chimney; ); axi_channel_compare #( - .aw_chan_t ( wide_in_aw_chan_t ), - .w_chan_t ( wide_in_w_chan_t ), - .b_chan_t ( wide_in_b_chan_t ), - .ar_chan_t ( wide_in_ar_chan_t ), - .r_chan_t ( wide_in_r_chan_t ), - .req_t ( wide_in_req_t ), - .resp_t ( wide_in_resp_t ) + .aw_chan_t ( axi_wide_in_aw_chan_t ), + .w_chan_t ( axi_wide_in_w_chan_t ), + .b_chan_t ( axi_wide_in_b_chan_t ), + .ar_chan_t ( axi_wide_in_ar_chan_t ), + .r_chan_t ( axi_wide_in_r_chan_t ), + .req_t ( axi_wide_in_req_t ), + .resp_t ( axi_wide_in_rsp_t ) ) i_wide_channel_compare_0 ( .clk_i ( clk ), .axi_a_req ( wide_man_req[0] ), @@ -162,71 +162,71 @@ module tb_floo_dma_nw_chimney; .WideMaxTxnsPerId ( MaxTxnsPerId ), .WideReorderBufferSize ( ReorderBufferSize ) ) i_floo_narrow_wide_chimney_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .narrow_in_req_i ( narrow_man_req[0] ), - .narrow_in_rsp_o ( narrow_man_rsp[0] ), - .narrow_out_req_o ( narrow_sub_req[0] ), - .narrow_out_rsp_i ( narrow_sub_rsp[0] ), - .wide_in_req_i ( wide_man_req[0] ), - .wide_in_rsp_o ( wide_man_rsp[0] ), - .wide_out_req_o ( wide_sub_req[0] ), - .wide_out_rsp_i ( wide_sub_rsp[0] ), - .xy_id_i ( '0 ), - .id_i ( '0 ), - .narrow_req_o ( narrow_chimney_req[0] ), - .narrow_rsp_o ( narrow_chimney_rsp[0] ), - .wide_o ( wide_chimney[0] ), - .narrow_req_i ( narrow_chimney_req_cut[1] ), - .narrow_rsp_i ( narrow_chimney_rsp_cut[1] ), - .wide_i ( wide_chimney_cut[1] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_narrow_in_req_i ( narrow_man_req[0] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[0] ), + .axi_narrow_out_req_o ( narrow_sub_req[0] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[0] ), + .axi_wide_in_req_i ( wide_man_req[0] ), + .axi_wide_in_rsp_o ( wide_man_rsp[0] ), + .axi_wide_out_req_o ( wide_sub_req[0] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[0] ), + .xy_id_i ( '0 ), + .id_i ( '0 ), + .floo_req_o ( chimney_req[0] ), + .floo_rsp_o ( chimney_rsp[0] ), + .floo_wide_o ( chimney_wide[0] ), + .floo_req_i ( chimney_req_cut[1] ), + .floo_rsp_i ( chimney_rsp_cut[1] ), + .floo_wide_i ( chimney_wide_cut[1] ) ); floo_cut #( - .NumChannels ( 2 ), - .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers - .flit_t ( narrow_req_data_t ) + .NumChannels ( 2 ), + .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers + .flit_t ( floo_req_t ) ) i_floo_req_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {narrow_chimney_req[1].valid, narrow_chimney_req[0].valid} ), - .ready_o ( {narrow_chimney_req_cut[1].ready, narrow_chimney_req_cut[0].ready} ), - .data_i ( {narrow_chimney_req[1].data, narrow_chimney_req[0].data} ), - .valid_o ( {narrow_chimney_req_cut[1].valid, narrow_chimney_req_cut[0].valid} ), - .ready_i ( {narrow_chimney_req[1].ready, narrow_chimney_req[0].ready} ), - .data_o ( {narrow_chimney_req_cut[1].data, narrow_chimney_req_cut[0].data} ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .valid_i ( {chimney_req[1].valid, chimney_req[0].valid} ), + .ready_o ( {chimney_req_cut[1].ready, chimney_req_cut[0].ready} ), + .data_i ( {chimney_req[1], chimney_req[0]} ), + .valid_o ( {chimney_req_cut[1].valid, chimney_req_cut[0].valid} ), + .ready_i ( {chimney_req[1].ready, chimney_req[0].ready} ), + .data_o ( {chimney_req_cut[1], chimney_req_cut[0]} ) ); floo_cut #( - .NumChannels ( 2 ), - .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers - .flit_t ( narrow_rsp_data_t ) + .NumChannels ( 2 ), + .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers + .flit_t ( floo_rsp_t ) ) i_floo_rsp_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {narrow_chimney_rsp[1].valid, narrow_chimney_rsp[0].valid} ), - .ready_o ( {narrow_chimney_rsp_cut[1].ready, narrow_chimney_rsp_cut[0].ready} ), - .data_i ( {narrow_chimney_rsp[1].data, narrow_chimney_rsp[0].data} ), - .valid_o ( {narrow_chimney_rsp_cut[1].valid, narrow_chimney_rsp_cut[0].valid} ), - .ready_i ( {narrow_chimney_rsp[1].ready, narrow_chimney_rsp[0].ready} ), - .data_o ( {narrow_chimney_rsp_cut[1].data, narrow_chimney_rsp_cut[0].data} ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .valid_i ( {chimney_rsp[1].valid, chimney_rsp[0].valid} ), + .ready_o ( {chimney_rsp_cut[1].ready, chimney_rsp_cut[0].ready} ), + .data_i ( {chimney_rsp[1], chimney_rsp[0]} ), + .valid_o ( {chimney_rsp_cut[1].valid, chimney_rsp_cut[0].valid} ), + .ready_i ( {chimney_rsp[1].ready, chimney_rsp[0].ready} ), + .data_o ( {chimney_rsp_cut[1], chimney_rsp_cut[0]} ) ); floo_cut #( .NumChannels ( 2 ), .NumCuts ( 32'd4 ), // should simulate a hop with 2 routers - .flit_t ( wide_data_t ) + .flit_t ( floo_wide_t ) ) i_floo_wide_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {wide_chimney[1].valid, wide_chimney[0].valid} ), - .ready_o ( {wide_chimney_cut[1].ready, wide_chimney_cut[0].ready} ), - .data_i ( {wide_chimney[1].data, wide_chimney[0].data} ), - .valid_o ( {wide_chimney_cut[1].valid, wide_chimney_cut[0].valid} ), - .ready_i ( {wide_chimney[1].ready, wide_chimney[0].ready} ), - .data_o ( {wide_chimney_cut[1].data, wide_chimney_cut[0].data} ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .valid_i ( {chimney_wide[1].valid, chimney_wide[0].valid} ), + .ready_o ( {chimney_wide_cut[1].ready, chimney_wide_cut[0].ready} ), + .data_i ( {chimney_wide[1], chimney_wide[0]} ), + .valid_o ( {chimney_wide_cut[1].valid, chimney_wide_cut[0].valid} ), + .ready_i ( {chimney_wide[1].ready, chimney_wide[0].ready} ), + .data_o ( {chimney_wide_cut[1], chimney_wide_cut[0]} ) ); floo_narrow_wide_chimney #( @@ -238,76 +238,76 @@ module tb_floo_dma_nw_chimney; .WideMaxTxnsPerId ( MaxTxnsPerId ), .WideReorderBufferSize ( ReorderBufferSize ) ) i_floo_narrow_wide_chimney_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .narrow_in_req_i ( narrow_man_req[1] ), - .narrow_in_rsp_o ( narrow_man_rsp[1] ), - .narrow_out_req_o ( narrow_sub_req[1] ), - .narrow_out_rsp_i ( narrow_sub_rsp[1] ), - .wide_in_req_i ( wide_man_req[1] ), - .wide_in_rsp_o ( wide_man_rsp[1] ), - .wide_out_req_o ( wide_sub_req[1] ), - .wide_out_rsp_i ( wide_sub_rsp[1] ), - .xy_id_i ( '0 ), - .id_i ( '0 ), - .narrow_req_o ( narrow_chimney_req[1] ), - .narrow_rsp_o ( narrow_chimney_rsp[1] ), - .wide_o ( wide_chimney[1] ), - .narrow_req_i ( narrow_chimney_req_cut[0] ), - .narrow_rsp_i ( narrow_chimney_rsp_cut[0] ), - .wide_i ( wide_chimney_cut[0] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_narrow_in_req_i ( narrow_man_req[1] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[1] ), + .axi_narrow_out_req_o ( narrow_sub_req[1] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[1] ), + .axi_wide_in_req_i ( wide_man_req[1] ), + .axi_wide_in_rsp_o ( wide_man_rsp[1] ), + .axi_wide_out_req_o ( wide_sub_req[1] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[1] ), + .xy_id_i ( '0 ), + .id_i ( '0 ), + .floo_req_o ( chimney_req[1] ), + .floo_rsp_o ( chimney_rsp[1] ), + .floo_wide_o ( chimney_wide[1] ), + .floo_req_i ( chimney_req_cut[0] ), + .floo_rsp_i ( chimney_rsp_cut[0] ), + .floo_wide_i ( chimney_wide_cut[0] ) ); axi_channel_compare #( - .aw_chan_t ( narrow_in_aw_chan_t ), - .w_chan_t ( narrow_in_w_chan_t ), - .b_chan_t ( narrow_in_b_chan_t ), - .ar_chan_t ( narrow_in_ar_chan_t ), - .r_chan_t ( narrow_in_r_chan_t ), - .req_t ( narrow_in_req_t ), - .resp_t ( narrow_in_resp_t ) + .aw_chan_t ( axi_narrow_in_aw_chan_t ), + .w_chan_t ( axi_narrow_in_w_chan_t ), + .b_chan_t ( axi_narrow_in_b_chan_t ), + .ar_chan_t ( axi_narrow_in_ar_chan_t ), + .r_chan_t ( axi_narrow_in_r_chan_t ), + .req_t ( axi_narrow_in_req_t ), + .resp_t ( axi_narrow_in_rsp_t ) ) i_narrow_channel_compare_1 ( - .clk_i ( clk ), - .axi_a_req ( narrow_man_req[1] ), - .axi_a_res ( narrow_man_rsp[1] ), + .clk_i ( clk ), + .axi_a_req ( narrow_man_req[1] ), + .axi_a_res ( narrow_man_rsp[1] ), .axi_b_req ( narrow_sub_req_id_mapped[0] ), .axi_b_res ( narrow_sub_rsp_id_mapped[0] ) ); axi_channel_compare #( - .aw_chan_t ( wide_in_aw_chan_t ), - .w_chan_t ( wide_in_w_chan_t ), - .b_chan_t ( wide_in_b_chan_t ), - .ar_chan_t ( wide_in_ar_chan_t ), - .r_chan_t ( wide_in_r_chan_t ), - .req_t ( wide_in_req_t ), - .resp_t ( wide_in_resp_t ) + .aw_chan_t ( axi_wide_in_aw_chan_t ), + .w_chan_t ( axi_wide_in_w_chan_t ), + .b_chan_t ( axi_wide_in_b_chan_t ), + .ar_chan_t ( axi_wide_in_ar_chan_t ), + .r_chan_t ( axi_wide_in_r_chan_t ), + .req_t ( axi_wide_in_req_t ), + .resp_t ( axi_wide_in_rsp_t ) ) i_wide_channel_compare_1 ( - .clk_i ( clk ), - .axi_a_req ( wide_man_req[1] ), - .axi_a_res ( wide_man_rsp[1] ), + .clk_i ( clk ), + .axi_a_req ( wide_man_req[1] ), + .axi_a_res ( wide_man_rsp[1] ), .axi_b_req ( wide_sub_req_id_mapped[0] ), .axi_b_res ( wide_sub_rsp_id_mapped[0] ) ); floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .DataWidth ( NarrowInDataWidth ), - .AddrWidth ( NarrowInAddrWidth ), - .UserWidth ( NarrowInUserWidth ), - .AxiIdInWidth ( NarrowOutIdWidth ), - .AxiIdOutWidth ( NarrowInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( narrow_out_req_t ), - .axi_in_rsp_t ( narrow_out_resp_t ), - .axi_out_req_t ( narrow_in_req_t ), - .axi_out_rsp_t ( narrow_in_resp_t ), - .JobId ( 101 ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .DataWidth ( NarrowInDataWidth ), + .AddrWidth ( NarrowInAddrWidth ), + .UserWidth ( NarrowInUserWidth ), + .AxiIdInWidth ( NarrowOutIdWidth ), + .AxiIdOutWidth ( NarrowInIdWidth ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .axi_in_req_t ( axi_narrow_out_req_t ), + .axi_in_rsp_t ( axi_narrow_out_rsp_t ), + .axi_out_req_t ( axi_narrow_in_req_t ), + .axi_out_rsp_t ( axi_narrow_in_rsp_t ), + .JobId ( 101 ) ) i_narrow_dma_node_1 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -319,21 +319,21 @@ module tb_floo_dma_nw_chimney; ); floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .DataWidth ( WideInDataWidth ), - .AddrWidth ( WideInAddrWidth ), - .UserWidth ( WideInUserWidth ), - .AxiIdInWidth ( WideOutIdWidth ), - .AxiIdOutWidth ( WideInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( wide_out_req_t ), - .axi_in_rsp_t ( wide_out_resp_t ), - .axi_out_req_t ( wide_in_req_t ), - .axi_out_rsp_t ( wide_in_resp_t ), - .JobId ( 1 ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .DataWidth ( WideInDataWidth ), + .AddrWidth ( WideInAddrWidth ), + .UserWidth ( WideInUserWidth ), + .AxiIdInWidth ( WideOutIdWidth ), + .AxiIdOutWidth ( WideInIdWidth ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .axi_in_req_t ( axi_wide_out_req_t ), + .axi_in_rsp_t ( axi_wide_out_rsp_t ), + .axi_out_req_t ( axi_wide_in_req_t ), + .axi_out_rsp_t ( axi_wide_in_rsp_t ), + .JobId ( 1 ) ) i_wide_dma_node_1 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -345,10 +345,10 @@ module tb_floo_dma_nw_chimney; ); axi_bw_monitor #( - .req_t ( narrow_in_req_t ), - .rsp_t ( narrow_in_resp_t ), - .AxiIdWidth ( NarrowInIdWidth ), - .name ( "narrow 0" ) + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ), + .AxiIdWidth ( NarrowInIdWidth ), + .name ( "narrow 0" ) ) i_axi_narrow_bw_monitor_0 ( .clk_i ( clk ), .en_i ( rst_n ), @@ -358,10 +358,10 @@ module tb_floo_dma_nw_chimney; ); axi_bw_monitor #( - .req_t ( narrow_in_req_t ), - .rsp_t ( narrow_in_resp_t ), - .AxiIdWidth ( NarrowInIdWidth ), - .name ( "narrow 1" ) + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ), + .AxiIdWidth ( NarrowInIdWidth ), + .name ( "narrow 1" ) ) i_axi_narrow_bw_monitor_1 ( .clk_i ( clk ), .en_i ( rst_n ), @@ -371,10 +371,10 @@ module tb_floo_dma_nw_chimney; ); axi_bw_monitor #( - .req_t ( wide_in_req_t ), - .rsp_t ( wide_in_resp_t ), - .AxiIdWidth ( WideInIdWidth ), - .name ( "wide 0" ) + .req_t ( axi_wide_in_req_t ), + .rsp_t ( axi_wide_in_rsp_t ), + .AxiIdWidth ( WideInIdWidth ), + .name ( "wide 0" ) ) i_axi_wide_bw_monitor_0 ( .clk_i ( clk ), .en_i ( rst_n ), @@ -384,10 +384,10 @@ module tb_floo_dma_nw_chimney; ); axi_bw_monitor #( - .req_t ( wide_in_req_t ), - .rsp_t ( wide_in_resp_t ), - .AxiIdWidth ( WideInIdWidth ), - .name ( "wide 1" ) + .req_t ( axi_wide_in_req_t ), + .rsp_t ( axi_wide_in_rsp_t ), + .AxiIdWidth ( WideInIdWidth ), + .name ( "wide 1" ) ) i_axi_wide_bw_monitor_1 ( .clk_i ( clk ), .en_i ( rst_n ), diff --git a/test/tb_floo_narrow_wide_chimney.sv b/test/tb_floo_narrow_wide_chimney.sv index 055174f4..6c4320fd 100644 --- a/test/tb_floo_narrow_wide_chimney.sv +++ b/test/tb_floo_narrow_wide_chimney.sv @@ -11,16 +11,16 @@ module tb_floo_narrow_wide_chimney; import floo_pkg::*; - import floo_narrow_wide_flit_pkg::*; + import floo_narrow_wide_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; localparam time TestTime = 8ns; - localparam NarrowNumReads = 1000; - localparam NarrowNumWrites = 1000; - localparam WideNumReads = 1000; - localparam WideNumWrites = 1000; + localparam NarrowNumReads = 100; + localparam NarrowNumWrites = 100; + localparam WideNumReads = 100; + localparam WideNumWrites = 100; localparam NumTargets = 2; @@ -30,20 +30,20 @@ module tb_floo_narrow_wide_chimney; logic clk, rst_n; - narrow_in_req_t [NumTargets-1:0] narrow_man_req; - narrow_in_resp_t [NumTargets-1:0] narrow_man_rsp; - wide_in_req_t [NumTargets-1:0] wide_man_req; - wide_in_resp_t [NumTargets-1:0] wide_man_rsp; + axi_narrow_in_req_t [NumTargets-1:0] narrow_man_req; + axi_narrow_in_rsp_t [NumTargets-1:0] narrow_man_rsp; + axi_wide_in_req_t [NumTargets-1:0] wide_man_req; + axi_wide_in_rsp_t [NumTargets-1:0] wide_man_rsp; - narrow_out_req_t [NumTargets-1:0] narrow_sub_req; - narrow_out_resp_t [NumTargets-1:0] narrow_sub_rsp; - wide_out_req_t [NumTargets-1:0] wide_sub_req; - wide_out_resp_t [NumTargets-1:0] wide_sub_rsp; + axi_narrow_out_req_t [NumTargets-1:0] narrow_sub_req; + axi_narrow_out_rsp_t [NumTargets-1:0] narrow_sub_rsp; + axi_wide_out_req_t [NumTargets-1:0] wide_sub_req; + axi_wide_out_rsp_t [NumTargets-1:0] wide_sub_rsp; - narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; - narrow_in_resp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; - wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; - wide_in_resp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; + axi_narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; + axi_narrow_in_rsp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; + axi_wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; + axi_wide_in_rsp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; for (genvar i = 0; i < NumDirections; i++) begin : gen_dir `AXI_ASSIGN_REQ_STRUCT(narrow_sub_req_id_mapped[i], narrow_sub_req[i]) @@ -52,9 +52,9 @@ module tb_floo_narrow_wide_chimney; `AXI_ASSIGN_RESP_STRUCT(wide_sub_rsp_id_mapped[i], wide_sub_rsp[i]) end - narrow_req_flit_t [NumTargets-1:0] narrow_chimney_req; - narrow_rsp_flit_t [NumTargets-1:0] narrow_chimney_rsp; - wide_flit_t [NumTargets-1:0] wide_chimney; + floo_req_t [NumTargets-1:0] chimney_req; + floo_rsp_t [NumTargets-1:0] chimney_rsp; + floo_wide_t [NumTargets-1:0] chimney_wide; logic [NumTargets*3-1:0] end_of_sim; @@ -76,25 +76,37 @@ module tb_floo_narrow_wide_chimney; '{start_addr: 48'h000_0000_0000, end_addr: 48'h000_0000_8000} }; + typedef struct packed { + int unsigned idx; + logic [NarrowInAddrWidth-1:0] start_addr; + logic [NarrowInAddrWidth-1:0] end_addr; + } node_addr_region_id_t; + + node_addr_region_id_t [NumTargets-1:0] node_addr_regions; + assign node_addr_regions = '{ + '{idx: 0, start_addr: 48'h000_0000_0000, end_addr: 48'h000_0000_4000}, + '{idx: 1, start_addr: 48'h000_0000_4000, end_addr: 48'h000_0000_8000} + }; + floo_axi_test_node #( - .AxiAddrWidth ( NarrowInAddrWidth ), - .AxiDataWidth ( NarrowInDataWidth ), - .AxiIdInWidth ( NarrowOutIdWidth ), - .AxiIdOutWidth ( NarrowInIdWidth ), - .AxiUserWidth ( NarrowInUserWidth ), - .mst_req_t ( narrow_in_req_t ), - .mst_rsp_t ( narrow_in_resp_t ), - .slv_req_t ( narrow_out_req_t ), - .slv_rsp_t ( narrow_out_resp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .Atops ( 1'b1 ), - .AxiMaxBurstLen ( ReorderBufferSize ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( NarrowNumReads ), - .NumWrites ( NarrowNumWrites ) + .AxiAddrWidth ( NarrowInAddrWidth ), + .AxiDataWidth ( NarrowInDataWidth ), + .AxiIdInWidth ( NarrowOutIdWidth ), + .AxiIdOutWidth ( NarrowInIdWidth ), + .AxiUserWidth ( NarrowInUserWidth ), + .mst_req_t ( axi_narrow_in_req_t ), + .mst_rsp_t ( axi_narrow_in_rsp_t ), + .slv_req_t ( axi_narrow_out_req_t ), + .slv_rsp_t ( axi_narrow_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .Atops ( 1'b1 ), + .AxiMaxBurstLen ( ReorderBufferSize ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .NumReads ( NarrowNumReads ), + .NumWrites ( NarrowNumWrites ) ) i_narrow_test_node_0 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -111,10 +123,10 @@ module tb_floo_narrow_wide_chimney; .AxiIdInWidth ( WideOutIdWidth ), .AxiIdOutWidth ( WideInIdWidth ), .AxiUserWidth ( WideInUserWidth ), - .mst_req_t ( wide_in_req_t ), - .mst_rsp_t ( wide_in_resp_t ), - .slv_req_t ( wide_out_req_t ), - .slv_rsp_t ( wide_out_resp_t ), + .mst_req_t ( axi_wide_in_req_t ), + .mst_rsp_t ( axi_wide_in_rsp_t ), + .slv_req_t ( axi_wide_out_req_t ), + .slv_rsp_t ( axi_wide_out_rsp_t ), .Atops ( 1'b0 ), .ApplTime ( ApplTime ), .TestTime ( TestTime ), @@ -135,15 +147,15 @@ module tb_floo_narrow_wide_chimney; ); axi_reorder_remap_compare #( - .AxiInIdWidth ( NarrowInIdWidth ), - .AxiOutIdWidth ( NarrowOutIdWidth ), - .aw_chan_t ( narrow_in_aw_chan_t ), - .w_chan_t ( narrow_in_w_chan_t ), - .b_chan_t ( narrow_in_b_chan_t ), - .ar_chan_t ( narrow_in_ar_chan_t ), - .r_chan_t ( narrow_in_r_chan_t ), - .req_t ( narrow_in_req_t ), - .rsp_t ( narrow_in_resp_t ) + .AxiInIdWidth ( NarrowInIdWidth ), + .AxiOutIdWidth ( NarrowOutIdWidth ), + .aw_chan_t ( axi_narrow_in_aw_chan_t ), + .w_chan_t ( axi_narrow_in_w_chan_t ), + .b_chan_t ( axi_narrow_in_b_chan_t ), + .ar_chan_t ( axi_narrow_in_ar_chan_t ), + .r_chan_t ( axi_narrow_in_r_chan_t ), + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ) ) i_narrow_channel_compare_0 ( .clk_i ( clk ), .mon_mst_req_i ( narrow_man_req[0] ), @@ -154,97 +166,105 @@ module tb_floo_narrow_wide_chimney; ); axi_channel_compare #( - .aw_chan_t ( wide_in_aw_chan_t ), - .w_chan_t ( wide_in_w_chan_t ), - .b_chan_t ( wide_in_b_chan_t ), - .ar_chan_t ( wide_in_ar_chan_t ), - .r_chan_t ( wide_in_r_chan_t ), - .req_t ( wide_in_req_t ), - .resp_t ( wide_in_resp_t ) + .aw_chan_t ( axi_wide_in_aw_chan_t ), + .w_chan_t ( axi_wide_in_w_chan_t ), + .b_chan_t ( axi_wide_in_b_chan_t ), + .ar_chan_t ( axi_wide_in_ar_chan_t ), + .r_chan_t ( axi_wide_in_r_chan_t ), + .req_t ( axi_wide_in_req_t ), + .resp_t ( axi_wide_in_rsp_t ) ) i_wide_channel_compare_0 ( - .clk_i ( clk ), - .axi_a_req ( wide_man_req[0] ), - .axi_a_res ( wide_man_rsp[0] ), + .clk_i ( clk ), + .axi_a_req ( wide_man_req[0] ), + .axi_a_res ( wide_man_rsp[0] ), .axi_b_req ( wide_sub_req_id_mapped[1] ), .axi_b_res ( wide_sub_rsp_id_mapped[1] ) ); floo_narrow_wide_chimney #( - .AtopSupport ( 1'b1 ), - .MaxAtomicTxns ( 1 ), - .RouteAlgo ( floo_pkg::IdTable ), - .NarrowMaxTxns ( MaxTxns ), - .NarrowMaxTxnsPerId ( MaxTxnsPerId ), - .NarrowReorderBufferSize ( ReorderBufferSize ), - .WideMaxTxns ( MaxTxns ), - .WideMaxTxnsPerId ( MaxTxnsPerId ), - .WideReorderBufferSize ( ReorderBufferSize ) + .AtopSupport ( 1'b1 ), + .MaxAtomicTxns ( 1 ), + .RouteAlgo ( floo_pkg::IdTable ), + .NumIDs ( NumTargets ), + .NumRules ( NumTargets ), + .id_rule_t ( node_addr_region_id_t ), + .NarrowMaxTxns ( MaxTxns ), + .NarrowMaxTxnsPerId ( MaxTxnsPerId ), + .NarrowReorderBufferSize ( ReorderBufferSize ), + .WideMaxTxns ( MaxTxns ), + .WideMaxTxnsPerId ( MaxTxnsPerId ), + .WideReorderBufferSize ( ReorderBufferSize ) ) i_floo_narrow_wide_chimney_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .narrow_in_req_i ( narrow_man_req[0] ), - .narrow_in_rsp_o ( narrow_man_rsp[0] ), - .narrow_out_req_o ( narrow_sub_req[0] ), - .narrow_out_rsp_i ( narrow_sub_rsp[0] ), - .wide_in_req_i ( wide_man_req[0] ), - .wide_in_rsp_o ( wide_man_rsp[0] ), - .wide_out_req_o ( wide_sub_req[0] ), - .wide_out_rsp_i ( wide_sub_rsp[0] ), - .xy_id_i ( '0 ), - .id_i ( '0 ), - .narrow_req_o ( narrow_chimney_req[0] ), - .narrow_rsp_o ( narrow_chimney_rsp[0] ), - .wide_o ( wide_chimney[0] ), - .narrow_req_i ( narrow_chimney_req[1] ), - .narrow_rsp_i ( narrow_chimney_rsp[1] ), - .wide_i ( wide_chimney[1] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_narrow_in_req_i ( narrow_man_req[0] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[0] ), + .axi_narrow_out_req_o ( narrow_sub_req[0] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[0] ), + .axi_wide_in_req_i ( wide_man_req[0] ), + .axi_wide_in_rsp_o ( wide_man_rsp[0] ), + .axi_wide_out_req_o ( wide_sub_req[0] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[0] ), + .xy_id_i ( '0 ), + .id_i ( '0 ), + .id_map_i ( node_addr_regions ), + .floo_req_o ( chimney_req[0] ), + .floo_rsp_o ( chimney_rsp[0] ), + .floo_wide_o ( chimney_wide[0] ), + .floo_req_i ( chimney_req[1] ), + .floo_rsp_i ( chimney_rsp[1] ), + .floo_wide_i ( chimney_wide[1] ) ); floo_narrow_wide_chimney #( - .AtopSupport ( 1'b1 ), - .MaxAtomicTxns ( 1 ), - .RouteAlgo ( floo_pkg::IdTable ), - .NarrowMaxTxns ( MaxTxns ), - .NarrowMaxTxnsPerId ( MaxTxnsPerId ), - .NarrowReorderBufferSize ( ReorderBufferSize ), - .WideMaxTxns ( MaxTxns ), - .WideMaxTxnsPerId ( MaxTxnsPerId ), - .WideReorderBufferSize ( ReorderBufferSize ) + .AtopSupport ( 1'b1 ), + .MaxAtomicTxns ( 1 ), + .RouteAlgo ( floo_pkg::IdTable ), + .NumIDs ( NumTargets ), + .NumRules ( NumTargets ), + .id_rule_t ( node_addr_region_id_t ), + .NarrowMaxTxns ( MaxTxns ), + .NarrowMaxTxnsPerId ( MaxTxnsPerId ), + .NarrowReorderBufferSize ( ReorderBufferSize ), + .WideMaxTxns ( MaxTxns ), + .WideMaxTxnsPerId ( MaxTxnsPerId ), + .WideReorderBufferSize ( ReorderBufferSize ) ) i_floo_narrow_wide_chimney_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .narrow_in_req_i ( narrow_man_req[1] ), - .narrow_in_rsp_o ( narrow_man_rsp[1] ), - .narrow_out_req_o ( narrow_sub_req[1] ), - .narrow_out_rsp_i ( narrow_sub_rsp[1] ), - .wide_in_req_i ( wide_man_req[1] ), - .wide_in_rsp_o ( wide_man_rsp[1] ), - .wide_out_req_o ( wide_sub_req[1] ), - .wide_out_rsp_i ( wide_sub_rsp[1] ), - .xy_id_i ( '0 ), - .id_i ( '0 ), - .narrow_req_o ( narrow_chimney_req[1] ), - .narrow_rsp_o ( narrow_chimney_rsp[1] ), - .wide_o ( wide_chimney[1] ), - .narrow_req_i ( narrow_chimney_req[0] ), - .narrow_rsp_i ( narrow_chimney_rsp[0] ), - .wide_i ( wide_chimney[0] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_narrow_in_req_i ( narrow_man_req[1] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[1] ), + .axi_narrow_out_req_o ( narrow_sub_req[1] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[1] ), + .axi_wide_in_req_i ( wide_man_req[1] ), + .axi_wide_in_rsp_o ( wide_man_rsp[1] ), + .axi_wide_out_req_o ( wide_sub_req[1] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[1] ), + .xy_id_i ( '0 ), + .id_i ( '0 ), + .id_map_i ( node_addr_regions ), + .floo_req_o ( chimney_req[1] ), + .floo_rsp_o ( chimney_rsp[1] ), + .floo_wide_o ( chimney_wide[1] ), + .floo_req_i ( chimney_req[0] ), + .floo_rsp_i ( chimney_rsp[0] ), + .floo_wide_i ( chimney_wide[0] ) ); axi_reorder_remap_compare #( - .AxiInIdWidth ( NarrowInIdWidth ), - .AxiOutIdWidth ( NarrowOutIdWidth ), - .aw_chan_t ( narrow_in_aw_chan_t ), - .w_chan_t ( narrow_in_w_chan_t ), - .b_chan_t ( narrow_in_b_chan_t ), - .ar_chan_t ( narrow_in_ar_chan_t ), - .r_chan_t ( narrow_in_r_chan_t ), - .req_t ( narrow_in_req_t ), - .rsp_t ( narrow_in_resp_t ) + .AxiInIdWidth ( NarrowInIdWidth ), + .AxiOutIdWidth ( NarrowOutIdWidth ), + .aw_chan_t ( axi_narrow_in_aw_chan_t ), + .w_chan_t ( axi_narrow_in_w_chan_t ), + .b_chan_t ( axi_narrow_in_b_chan_t ), + .ar_chan_t ( axi_narrow_in_ar_chan_t ), + .r_chan_t ( axi_narrow_in_r_chan_t ), + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ) ) i_narrow_channel_compare_1 ( .clk_i ( clk ), .mon_mst_req_i ( narrow_man_req[1] ), @@ -255,13 +275,13 @@ module tb_floo_narrow_wide_chimney; ); axi_channel_compare #( - .aw_chan_t ( wide_in_aw_chan_t ), - .w_chan_t ( wide_in_w_chan_t ), - .b_chan_t ( wide_in_b_chan_t ), - .ar_chan_t ( wide_in_ar_chan_t ), - .r_chan_t ( wide_in_r_chan_t ), - .req_t ( wide_in_req_t ), - .resp_t ( wide_in_resp_t ) + .aw_chan_t ( axi_wide_in_aw_chan_t ), + .w_chan_t ( axi_wide_in_w_chan_t ), + .b_chan_t ( axi_wide_in_b_chan_t ), + .ar_chan_t ( axi_wide_in_ar_chan_t ), + .r_chan_t ( axi_wide_in_r_chan_t ), + .req_t ( axi_wide_in_req_t ), + .resp_t ( axi_wide_in_rsp_t ) ) i_wide_channel_compare_1 ( .clk_i ( clk ), .axi_a_req ( wide_man_req[1] ), @@ -271,24 +291,24 @@ module tb_floo_narrow_wide_chimney; ); floo_axi_test_node #( - .AxiAddrWidth ( NarrowInAddrWidth ), - .AxiDataWidth ( NarrowInDataWidth ), - .AxiIdOutWidth ( NarrowInIdWidth ), - .AxiIdInWidth ( NarrowOutIdWidth ), - .AxiUserWidth ( NarrowInUserWidth ), - .mst_req_t ( narrow_in_req_t ), - .mst_rsp_t ( narrow_in_resp_t ), - .slv_req_t ( narrow_out_req_t ), - .slv_rsp_t ( narrow_out_resp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .Atops ( 1'b1 ), - .AxiMaxBurstLen ( ReorderBufferSize ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( NarrowNumReads ), - .NumWrites ( NarrowNumWrites ) + .AxiAddrWidth ( NarrowInAddrWidth ), + .AxiDataWidth ( NarrowInDataWidth ), + .AxiIdOutWidth ( NarrowInIdWidth ), + .AxiIdInWidth ( NarrowOutIdWidth ), + .AxiUserWidth ( NarrowInUserWidth ), + .mst_req_t ( axi_narrow_in_req_t ), + .mst_rsp_t ( axi_narrow_in_rsp_t ), + .slv_req_t ( axi_narrow_out_req_t ), + .slv_rsp_t ( axi_narrow_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .Atops ( 1'b1 ), + .AxiMaxBurstLen ( ReorderBufferSize ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .NumReads ( NarrowNumReads ), + .NumWrites ( NarrowNumWrites ) ) i_narrow_test_node_1 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -305,12 +325,13 @@ module tb_floo_narrow_wide_chimney; .AxiIdInWidth ( WideOutIdWidth ), .AxiIdOutWidth ( WideInIdWidth ), .AxiUserWidth ( WideInUserWidth ), - .mst_req_t ( wide_in_req_t ), - .mst_rsp_t ( wide_in_resp_t ), - .slv_req_t ( wide_out_req_t ), - .slv_rsp_t ( wide_out_resp_t ), + .mst_req_t ( axi_wide_in_req_t ), + .mst_rsp_t ( axi_wide_in_rsp_t ), + .slv_req_t ( axi_wide_out_req_t ), + .slv_rsp_t ( axi_wide_out_rsp_t ), .ApplTime ( ApplTime ), .TestTime ( TestTime ), + .Atops ( 1'b0 ), .AxiMaxBurstLen ( ReorderBufferSize ), .NumAddrRegions ( NumAddrRegions ), .rule_t ( node_addr_region_t ), diff --git a/test/tb_floo_narrow_wide_chimney.wave.tcl b/test/tb_floo_narrow_wide_chimney.wave.tcl index 0931dd63..59d52b21 100644 --- a/test/tb_floo_narrow_wide_chimney.wave.tcl +++ b/test/tb_floo_narrow_wide_chimney.wave.tcl @@ -15,31 +15,31 @@ for {set i 0} {$i < 2} {incr i} { add wave -noupdate -expand -group $group_name -ports tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/* - add wave -noupdate -expand -group $group_name -group Arbiter -group ArbiterNarrowReq -ports tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/i_narrow_req_wormhole_arbiter/* - add wave -noupdate -expand -group $group_name -group Arbiter -group ArbiterNarrowRsp -ports tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/i_narrow_rsp_wormhole_arbiter/* + add wave -noupdate -expand -group $group_name -group Arbiter -group ArbiterNarrowReq -ports tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/i_req_wormhole_arbiter/* + add wave -noupdate -expand -group $group_name -group Arbiter -group ArbiterNarrowRsp -ports tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/i_rsp_wormhole_arbiter/* add wave -noupdate -expand -group $group_name -group Arbiter -group ArbiterWideReq -ports tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/i_wide_wormhole_arbiter/* - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_aw_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_w_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_b_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_ar_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_r_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_aw_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_w_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_b_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_ar_data - add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_r_data + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_narrow_aw + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_narrow_w + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_narrow_b + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_narrow_ar + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_narrow_r + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_wide_aw + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_wide_w + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_wide_b + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_wide_ar + add wave -noupdate -expand -group $group_name -group Packer tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/floo_wide_r - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_unpack_aw_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_unpack_w_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_unpack_ar_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_unpack_b_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/narrow_unpack_r_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_unpack_aw_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_unpack_w_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_unpack_ar_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_unpack_b_data - add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/wide_unpack_r_data + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_narrow_unpack_aw + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_narrow_unpack_w + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_narrow_unpack_ar + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_narrow_unpack_b + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_narrow_unpack_r + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_wide_unpack_aw + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_wide_unpack_w + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_wide_unpack_ar + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_wide_unpack_b + add wave -noupdate -expand -group $group_name -group Unpacker tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/axi_wide_unpack_r if {!$simple_rob} { add wave -noupdate -expand -group $group_name -group NarrowR_RoB -group StatusTable tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i}/gen_narrow_rob/i_narrow_r_rob/i_floo_rob_status_table/* diff --git a/test/tb_floo_rob.sv b/test/tb_floo_rob.sv index 814bce2b..3d3fbe66 100644 --- a/test/tb_floo_rob.sv +++ b/test/tb_floo_rob.sv @@ -12,7 +12,7 @@ module tb_floo_rob; import floo_pkg::*; import floo_test_pkg::*; - import floo_axi_flit_pkg::*; + import floo_axi_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -33,32 +33,33 @@ module tb_floo_rob; logic clk, rst_n; axi_in_req_t node_mst_req; - axi_in_resp_t node_mst_rsp; + axi_in_rsp_t node_mst_rsp; axi_out_req_t [NumDirections-1:0] node_slv_req; - axi_out_resp_t [NumDirections-1:0] node_slv_rsp; + axi_out_rsp_t [NumDirections-1:0] node_slv_rsp; axi_in_req_t [NumDirections-1:0] node_slv_req_id_mapped; - axi_in_resp_t [NumDirections-1:0] node_slv_rsp_id_mapped; + axi_in_rsp_t [NumDirections-1:0] node_slv_rsp_id_mapped; for (genvar i = 0; i < NumDirections; i++) begin : gen_dir `AXI_ASSIGN_REQ_STRUCT(node_slv_req_id_mapped[i], node_slv_req[i]) `AXI_ASSIGN_RESP_STRUCT(node_slv_rsp_id_mapped[i], node_slv_rsp[i]) end - req_flit_t [NumDirections-1:0] chimney_req_out, chimney_req_in; - rsp_flit_t [NumDirections-1:0] chimney_rsp_out, chimney_rsp_in; - req_data_t [NumDirections-1:0] chimney_req_data_out, chimney_req_data_in; - rsp_data_t [NumDirections-1:0] chimney_rsp_data_out, chimney_rsp_data_in; + floo_req_t [NumDirections-1:0] chimney_req_out, chimney_req_in; + floo_rsp_t [NumDirections-1:0] chimney_rsp_out, chimney_rsp_in; + floo_req_chan_t [NumDirections-1:0] chimney_req_out_chan, chimney_req_in_chan; + floo_rsp_chan_t [NumDirections-1:0] chimney_rsp_out_chan, chimney_rsp_in_chan; + logic [NumDirections-1:0] chimney_req_out_valid, chimney_req_out_ready; logic [NumDirections-1:0] chimney_rsp_out_valid, chimney_rsp_out_ready; logic [NumDirections-1:0] chimney_req_in_valid, chimney_req_in_ready; logic [NumDirections-1:0] chimney_rsp_in_valid, chimney_rsp_in_ready; for (genvar i = 0; i < NumDirections; i++) begin : gen_directions - assign chimney_req_data_out[i] = chimney_req_out[i].data; - assign chimney_rsp_data_out[i] = chimney_rsp_out[i].data; - assign chimney_req_in[i].data = chimney_req_data_in[i]; - assign chimney_rsp_in[i].data = chimney_rsp_data_in[i]; + assign chimney_req_out_chan[i] = chimney_req_out[i].req; + assign chimney_rsp_out_chan[i] = chimney_rsp_out[i].rsp; + assign chimney_req_in[i].req = chimney_req_in_chan[i]; + assign chimney_rsp_in[i].rsp = chimney_rsp_in_chan[i]; assign chimney_req_out_valid[i] = chimney_req_out[i].valid; assign chimney_req_out_ready[i] = chimney_req_out[i].ready; assign chimney_rsp_out_valid[i] = chimney_rsp_out[i].valid; @@ -109,9 +110,9 @@ module tb_floo_rob; .AxiIdOutWidth ( AxiInIdWidth ), .AxiUserWidth ( AxiInUserWidth ), .mst_req_t ( axi_in_req_t ), - .mst_rsp_t ( axi_in_resp_t ), + .mst_rsp_t ( axi_in_rsp_t ), .slv_req_t ( axi_out_req_t ), - .slv_rsp_t ( axi_out_resp_t ), + .slv_rsp_t ( axi_out_rsp_t ), .ApplTime ( ApplTime ), .TestTime ( TestTime ), .AxiMaxBurstLen ( 4 ), @@ -149,54 +150,54 @@ module tb_floo_rob; .axi_out_rsp_i ( node_slv_rsp[Eject] ), .xy_id_i ( xy_id[Eject] ), .id_i ( '0 ), - .req_o ( chimney_req_out[Eject] ), - .rsp_o ( chimney_rsp_out[Eject] ), - .req_i ( chimney_req_in[Eject] ), - .rsp_i ( chimney_rsp_in[Eject] ) + .floo_req_o ( chimney_req_out[Eject] ), + .floo_rsp_o ( chimney_rsp_out[Eject] ), + .floo_req_i ( chimney_req_in[Eject] ), + .floo_rsp_i ( chimney_rsp_in[Eject] ) ); floo_router #( - .NumRoutes ( NumDirections ), - .NumVirtChannels ( 1 ), - .NumPhysChannels ( 1 ), - .flit_t ( req_generic_t ), - .ChannelFifoDepth ( 4 ), - .RouteAlgo ( XYRouting ), - .id_t ( xy_id_t ) + .NumRoutes ( NumDirections ), + .NumVirtChannels ( 1 ), + .NumPhysChannels ( 1 ), + .flit_t ( floo_req_generic_flit_t ), + .ChannelFifoDepth ( 4 ), + .RouteAlgo ( XYRouting ), + .id_t ( xy_id_t ) ) i_floo_req_router ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_enable_i ( 1'b0 ), - .xy_id_i ( xy_id[Eject] ), - .id_route_map_i ( '0 ), - .valid_i ( chimney_req_out_valid ), - .ready_o ( chimney_req_in_ready ), - .data_i ( chimney_req_data_out ), - .valid_o ( chimney_req_in_valid ), - .ready_i ( chimney_req_out_ready ), - .data_o ( chimney_req_data_in ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .xy_id_i ( xy_id[Eject] ), + .id_route_map_i ( '0 ), + .valid_i ( chimney_req_out_valid ), + .ready_o ( chimney_req_in_ready ), + .data_i ( chimney_req_out_chan ), + .valid_o ( chimney_req_in_valid ), + .ready_i ( chimney_req_out_ready ), + .data_o ( chimney_req_in_chan ) ); floo_router #( - .NumRoutes ( NumDirections ), - .NumVirtChannels ( 1 ), - .NumPhysChannels ( 1 ), - .flit_t ( rsp_generic_t ), - .ChannelFifoDepth ( 4 ), - .RouteAlgo ( XYRouting ), - .id_t ( xy_id_t ) + .NumRoutes ( NumDirections ), + .NumVirtChannels ( 1 ), + .NumPhysChannels ( 1 ), + .flit_t ( floo_rsp_generic_flit_t ), + .ChannelFifoDepth ( 4 ), + .RouteAlgo ( XYRouting ), + .id_t ( xy_id_t ) ) i_floo_rsp_router ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_enable_i ( 1'b0 ), - .xy_id_i ( xy_id[Eject] ), - .id_route_map_i ( '0 ), - .valid_i ( chimney_rsp_out_valid ), - .ready_o ( chimney_rsp_in_ready ), - .data_i ( chimney_rsp_data_out ), - .valid_o ( chimney_rsp_in_valid ), - .ready_i ( chimney_rsp_out_ready ), - .data_o ( chimney_rsp_data_in ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .xy_id_i ( xy_id[Eject] ), + .id_route_map_i ( '0 ), + .valid_i ( chimney_rsp_out_valid ), + .ready_o ( chimney_rsp_in_ready ), + .data_i ( chimney_rsp_out_chan ), + .valid_o ( chimney_rsp_in_valid ), + .ready_i ( chimney_rsp_out_ready ), + .data_o ( chimney_rsp_in_chan ) ); localparam slave_type_e SlaveType[NumDirections-1] = '{FastSlave, FastSlave, SlowSlave, MixedSlave}; @@ -232,10 +233,10 @@ module tb_floo_rob; .axi_out_rsp_i ( node_slv_rsp[i] ), .xy_id_i ( xy_id[i] ), .id_i ( '0 ), - .req_o ( chimney_req_out[i] ), - .rsp_o ( chimney_rsp_out[i] ), - .req_i ( chimney_req_in[i] ), - .rsp_i ( chimney_rsp_in[i] ) + .floo_req_o ( chimney_req_out[i] ), + .floo_rsp_o ( chimney_rsp_out[i] ), + .floo_req_i ( chimney_req_in[i] ), + .floo_rsp_i ( chimney_rsp_in[i] ) ); floo_axi_rand_slave #( @@ -244,7 +245,7 @@ module tb_floo_rob; .AxiIdWidth ( AxiOutIdWidth ), .AxiUserWidth ( AxiOutUserWidth ), .axi_req_t ( axi_out_req_t ), - .axi_rsp_t ( axi_out_resp_t ), + .axi_rsp_t ( axi_out_rsp_t ), .ApplTime ( ApplTime ), .TestTime ( TestTime ), .SlaveType ( SlaveType[i] ), @@ -274,7 +275,7 @@ module tb_floo_rob; .ar_chan_t ( axi_in_ar_chan_t ), .r_chan_t ( axi_in_r_chan_t ), .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_resp_t ), + .rsp_t ( axi_in_rsp_t ), .Verbose ( 1'b0 ) ) i_axi_reorder_compare ( .clk_i ( clk ), diff --git a/test/tb_floo_router.sv b/test/tb_floo_router.sv index 8703dc6d..29688ab7 100644 --- a/test/tb_floo_router.sv +++ b/test/tb_floo_router.sv @@ -16,6 +16,7 @@ module tb_floo_router; import floo_pkg::*; + import floo_axi_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -41,8 +42,6 @@ module tb_floo_router; localparam int unsigned FlitWidth = 123; localparam int unsigned MaxPacketLength = 32; - `FLOO_NOC_TYPEDEF_ID_FLIT_T(full_flit_t, IdWidth, FlitWidth) - logic clk, rst_n; clk_rst_gen #( @@ -93,10 +92,10 @@ module tb_floo_router; endclass // Source Port Virtual Channel - full_flit_t stimuli_queue[NumPorts-1:0][NumVirtChannels-1:0] [$]; + floo_req_generic_flit_t stimuli_queue[NumPorts-1:0][NumVirtChannels-1:0] [$]; // Destination Virtual Channel Source Port - full_flit_t golden_queue [NumPorts-1:0][NumVirtChannels-1:0][NumPorts-1:0][$]; + floo_req_generic_flit_t golden_queue [NumPorts-1:0][NumVirtChannels-1:0][NumPorts-1:0][$]; function automatic void generate_stimuli(); for (int port = 0; port < NumPorts; port++) begin @@ -116,7 +115,11 @@ module tb_floo_router; automatic rand_data_t rand_data = new(port); rand_data.data_mod_id.constraint_mode(1); if (rand_data.randomize()) begin - automatic full_flit_t next_flit = '{data: rand_data.data, dst_id: stimuli.id, last: j == stimuli.len-1}; + automatic floo_req_generic_flit_t next_flit = '0; + next_flit.rsvd = rand_data.data; + next_flit.hdr.src_id = port; + next_flit.hdr.dst_id = stimuli.id; + next_flit.hdr.last = j == stimuli.len-1; stimuli_queue[port][virt_channel].push_back(next_flit); golden_queue[port][virt_channel][stimuli.id].push_back(next_flit); @@ -137,10 +140,10 @@ module tb_floo_router; // Apply Stimuli logic [NumPorts-1:0][NumVirtChannels-1:0] pre_valid_in, pre_ready_in; - full_flit_t [NumPorts-1:0][NumVirtChannels-1:0] pre_data_in; + floo_req_generic_flit_t [NumPorts-1:0][NumVirtChannels-1:0] pre_data_in; task automatic apply_stimuli(int unsigned port, int unsigned virt_channel); - automatic full_flit_t stimuli; + automatic floo_req_generic_flit_t stimuli; // pre_valid_in[port][virt_channel] = 1'b0; @@ -171,14 +174,14 @@ module tb_floo_router; logic [NumPorts-1:0][NumVirtChannels-1:0] delayed_valid_in; logic [NumPorts-1:0][NumVirtChannels-1:0] delayed_ready_in; - full_flit_t [NumPorts-1:0][NumVirtChannels-1:0] delayed_data_in; + floo_req_generic_flit_t [NumPorts-1:0][NumVirtChannels-1:0] delayed_data_in; for (genvar port = 0; port < NumPorts; port++) begin : gen_in_delay for (genvar virt_channel = 0; virt_channel < NumVirtChannels; virt_channel++) begin : gen_in_vc_delay stream_delay #( .StallRandom ( 1'b1 ), .FixedDelay ( 1 ), - .payload_t ( full_flit_t ), + .payload_t ( floo_req_generic_flit_t ), .Seed ( '0 ) ) i_in_delay ( .clk_i (clk), @@ -197,12 +200,12 @@ module tb_floo_router; logic [NumPorts-1:0][NumVirtChannels-1:0] valid_in, valid_out; logic [NumPorts-1:0][NumVirtChannels-1:0] ready_in, ready_out; - full_flit_t [NumPorts-1:0] data_in, data_out; + floo_req_generic_flit_t [NumPorts-1:0] data_in, data_out; for (genvar port = 0; port < NumPorts; port++) begin : gen_in_vc_arb floo_vc_arbiter #( .NumVirtChannels ( NumVirtChannels ), - .flit_t ( full_flit_t ) + .flit_t ( floo_req_generic_flit_t ) ) i_vc_arbiter ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -221,7 +224,7 @@ module tb_floo_router; floo_router #( .NumRoutes ( NumPorts ), .NumVirtChannels ( NumVirtChannels ), - .flit_t ( full_flit_t ), + .flit_t ( floo_req_generic_flit_t ), .ChannelFifoDepth( 4 ), .RouteAlgo ( IdIsPort ), .IdWidth ( IdWidth ) @@ -244,16 +247,16 @@ module tb_floo_router; logic [NumPorts-1:0][NumVirtChannels-1:0] fall_valid_out; logic [NumPorts-1:0][NumVirtChannels-1:0] fall_ready_out; - full_flit_t [NumPorts-1:0][NumVirtChannels-1:0] fall_data_out; + floo_req_generic_flit_t [NumPorts-1:0][NumVirtChannels-1:0] fall_data_out; logic [NumPorts-1:0][NumVirtChannels-1:0] delayed_valid_out; logic [NumPorts-1:0][NumVirtChannels-1:0] delayed_ready_out; - full_flit_t [NumPorts-1:0][NumVirtChannels-1:0] delayed_data_out; + floo_req_generic_flit_t [NumPorts-1:0][NumVirtChannels-1:0] delayed_data_out; for (genvar port = 0; port < NumPorts; port++) begin : gen_out_delay for (genvar virt_channel = 0; virt_channel < NumVirtChannels; virt_channel++) begin : gen_out_vc_delay fall_through_register #( - .T ( full_flit_t ) + .T ( floo_req_generic_flit_t ) ) i_fall ( .clk_i (clk), .rst_ni (rst_n), @@ -272,7 +275,7 @@ module tb_floo_router; stream_delay #( .StallRandom ( 1'b1 ), .FixedDelay ( 1 ), - .payload_t ( full_flit_t ), + .payload_t ( floo_req_generic_flit_t ), .Seed ( '0 ) ) i_in_delay ( .clk_i (clk), @@ -294,7 +297,7 @@ module tb_floo_router; ***********************/ // Destination Virtual Channel - full_flit_t result_queue[NumPorts-1:0][NumVirtChannels-1:0][$]; + floo_req_generic_flit_t result_queue[NumPorts-1:0][NumVirtChannels-1:0][$]; task automatic collect_result(int unsigned port, int unsigned virt_channel); @@ -322,18 +325,26 @@ module tb_floo_router; int unsigned last_physical_bin = 0; int unsigned all_golden_size = 0; - automatic full_flit_t result; - automatic full_flit_t golden; + automatic floo_req_generic_flit_t result; + automatic floo_req_generic_flit_t golden; do begin wait(result_queue[port][virt_channel].size() != 0); // Capture the result - result = result_queue[port][virt_channel].pop_front(); - golden = golden_queue[result.data%NumPorts][virt_channel][port].pop_front(); + if (result_queue[port][virt_channel].size() == 0) begin + $error("ERROR! Result queue is empty."); + end else begin + result = result_queue[port][virt_channel].pop_front(); + end + if (golden_queue[result.hdr.src_id][virt_channel][port].size() == 0) begin + $error("ERROR! Golden queue %d is empty.", result.hdr.src_id); + end else begin + golden = golden_queue[result.hdr.src_id][virt_channel][port].pop_front(); + end - if (result.data != golden.data) begin - $error("ERROR! Mismatch for port %d channel %d (from %d, target port %d).\n This was the data: %x, %x", port, virt_channel, result.data%NumPorts, result.dst_id, result.data, golden.data); + if (result.rsvd != golden.rsvd) begin + $error("ERROR! Mismatch for port %d channel %d (from %d, target port %d).\n This was the data: %x, %x", port, virt_channel, result.hdr.src_id, result.hdr.dst_id, result.rsvd, golden.rsvd); end all_golden_size = 0; diff --git a/util/axi_cfg.hjson b/util/axi_cfg.hjson index d2482e39..be2b57a9 100644 --- a/util/axi_cfg.hjson +++ b/util/axi_cfg.hjson @@ -6,19 +6,15 @@ { name: "axi", - axi_channels: [ - {name: 'axi_in', params: {dw: 64, aw: 32, iw: 3, uw: 1 }}, - {name: 'axi_out', params: {dw: 64, aw: 32, iw: 3, uw: 1 }}, + protocols: [ + {name: 'axi', direction: 'input', params: {dw: 64, aw: 32, iw: 3, uw: 1 }}, + {name: 'axi', direction: 'output', params: {dw: 64, aw: 32, iw: 3, uw: 1 }}, ] - phys_channels: [ - 'req', - 'rsp' - ], - map: { - req: ["axi_in_aw", "axi_in_w", "axi_in_ar"], - rsp: ["axi_in_b", "axi_in_r"] + channel_mapping: { + req: {axi: ['aw', 'w', 'ar']}, + rsp: {axi: ['b', 'r']} }, - meta: { + header: { rob_req: 1, rob_idx: 6, dst_id: 6, diff --git a/util/flit_gen.py b/util/flit_gen.py index 06f273e5..643abc53 100755 --- a/util/flit_gen.py +++ b/util/flit_gen.py @@ -19,12 +19,32 @@ output_encoding="utf-8") -def clog2(x): +def clog2(x: int) -> int: """Compute the ceil of the log2 of x.""" return int(math.ceil(math.log(x, 2))) -def calc_axi_ch_size(aw, dw, iw, uw): +def get_axi_chs(channel_mapping: dict, **kwargs) -> list: + """Return all the AXI channels.""" + channels = [] + for axi_chs in channel_mapping.values(): + for key, values in axi_chs.items(): + for v in values: + channels.append(f"{key}_{v}") + return channels + + +def get_inverted_mapping(channel_mapping: dict, **kwargs) -> dict: + """Return the mapping of the link.""" + mappings = {} + for phys_ch, ch_types in channel_mapping.items(): + for ch_type, axi_chs in ch_types.items(): + for axi_ch in axi_chs: + mappings.setdefault(ch_type, {})[axi_ch] = phys_ch + return mappings + + +def get_axi_channel_sizes(aw: int, dw: int, iw: int, uw: int) -> dict: """Compute the AXI channel size in bits.""" # Constant widths @@ -55,56 +75,27 @@ def calc_axi_ch_size(aw, dw, iw, uw): return axi_ch_size -def invert_map(map: list): - """Invert a list of lists.""" - inv_map = {} - for phys_chan, axi_chans in map.items(): - for axi_ch in axi_chans: - inv_map[axi_ch] = phys_chan - return inv_map - - -def axi_channel_ordering(map: list): - """Return the ordering of the AXI channels.""" - ordering = [] - for phys_chan, axi_chans in map.items(): - for axi_ch in axi_chans: - ordering.append(axi_ch) - return ordering - - -def calc_channel_size(cfg): - - rsvd_bits = {} - axi_ch_size = {} - phys_ch_size = {} - - for axi_ch in cfg['axi_channels']: - axi_ch_size[axi_ch['name']] = calc_axi_ch_size(**axi_ch['params']) - - for phys_ch, axi_chans in cfg['map'].items(): - axi_chans_size = [] - for axi_ch in axi_chans: - type = '_'.join(axi_ch.split('_')[:2]) - ch = axi_ch.split("_")[-1] - axi_chans_size.append(axi_ch_size[type][ch]) - phys_ch_size[phys_ch] = max(axi_chans_size) - - for axi_ch in cfg['axi_order']: - type = '_'.join(axi_ch.split('_')[:2]) - ch = axi_ch.split("_")[-1] - phys_ch = cfg['inv_map'][axi_ch] - rsvd_bits[axi_ch] = phys_ch_size[phys_ch] - axi_ch_size[type][ch] - - return phys_ch_size, rsvd_bits +def get_link_sizes(channel_mapping: dict, protocols: list, **kwargs) -> dict: + """Infer the link sizes AXI channels and the mapping.""" + link_sizes = {} + for phys_ch, axi_chs in channel_mapping.items(): + # Get all protocols that use this channel + used_protocols = [p for p in protocols if p['name'] in axi_chs and p['direction'] == 'input'] + # Get only the exact AXI channels that are used by the link + used_axi_chs = [axi_chs[p['name']] for p in used_protocols] + # Get the sizes of the AXI channels + axi_ch_sizes = [get_axi_channel_sizes(**p['params']) for p in used_protocols] + link_message_sizes = [] + for used_axi_ch, axi_ch_size in zip(used_axi_chs, axi_ch_sizes): + link_message_sizes += [axi_ch_size[ch] for ch in used_axi_ch] + # Get the maximum size of the link + link_sizes[phys_ch] = max(link_message_sizes) + return link_sizes def main(): """Generate a flit packet package.""" - # Path of the current script. - script_path = pathlib.Path(__file__).parent - parser = argparse.ArgumentParser( description="Generate flit files for a given configuration") parser.add_argument("--config", "-c", type=pathlib.Path, required=True, help="Path to the config file") @@ -115,16 +106,15 @@ def main(): with open(args.config, "r") as f: cfg = JsonRef.replace_refs(hjson.load(f)) - cfg['axi_order'] = axi_channel_ordering(cfg['map']) - cfg['meta']['axi_ch'] = clog2(len(cfg['axi_order'])) - cfg['meta_bits'] = sum(cfg['meta'].values()) - cfg['inv_map'] = invert_map(cfg['map']) - ch_sizes, rsvd_bits = calc_channel_size(cfg) - cfg['phys_ch_sizes'] = ch_sizes - cfg['rsvd_bits'] = rsvd_bits + kwargs = cfg + kwargs['axi_channels'] = get_axi_chs(**kwargs) + kwargs['header']['axi_ch'] = clog2(len(get_axi_chs(**kwargs))) + kwargs['inv_map'] = get_inverted_mapping(**kwargs) + kwargs['get_axi_channel_sizes'] = get_axi_channel_sizes + kwargs['link_sizes'] = get_link_sizes(**kwargs) - tpl = templates.get_template("floo_flit_pkg.sv.tpl") - print(tpl.render_unicode(cfg=cfg)) + tpl = templates.get_template("floo_flit_pkg.sv.mako") + print(tpl.render_unicode(**kwargs)) if __name__ == "__main__": diff --git a/util/floo_flit_pkg.sv.mako b/util/floo_flit_pkg.sv.mako new file mode 100644 index 00000000..1aa44026 --- /dev/null +++ b/util/floo_flit_pkg.sv.mako @@ -0,0 +1,137 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// This file is auto-generated. Do not edit! Edit the template file instead + +<% def list2array(values: list): + return '{' + ', '.join([str(a) for a in values]) + '}' +%> \ +<% def camelcase(word: str): + return ''.join([w.capitalize() for w in word.split('_')]) +%> \ +<% def clog2(value: int): + import math + return int(math.ceil(math.log(value, 2))) +%> \ +<%def zero_pad(values: list, length: int): + return values + [0] * (length - len(values)) +%> \ +<%def short_dir(direction: str): + return 'in' if direction == 'input' else 'out' +%> \ +<%def prot_full_name(name: str, direction: str, prefix: str="axi_", **kwargs): + prefix = '' if name in prefix else prefix + return prefix + name + '_' + short_dir(direction) +%> \ + +`include "axi/typedef.svh" + +package floo_${name}_pkg; + + //////////////////////// + // AXI Parameters // + //////////////////////// + +% for prot in protocols: + localparam int unsigned ${camelcase(prot_full_name(**prot, prefix=''))}AddrWidth = ${prot['params']['aw']}; + localparam int unsigned ${camelcase(prot_full_name(**prot, prefix=''))}DataWidth = ${prot['params']['dw']}; + localparam int unsigned ${camelcase(prot_full_name(**prot, prefix=''))}IdWidth = ${prot['params']['iw']}; + localparam int unsigned ${camelcase(prot_full_name(**prot, prefix=''))}UserWidth = ${prot['params']['uw']}; + +% endfor +% for prot in protocols: + typedef logic [${camelcase(prot_full_name(**prot, prefix=''))}AddrWidth-1:0] ${prot_full_name(**prot)}_addr_t; + typedef logic [${camelcase(prot_full_name(**prot, prefix=''))}DataWidth-1:0] ${prot_full_name(**prot)}_data_t; + typedef logic [${camelcase(prot_full_name(**prot, prefix=''))}DataWidth/8-1:0] ${prot_full_name(**prot)}_strb_t; + typedef logic [${camelcase(prot_full_name(**prot, prefix=''))}IdWidth-1:0] ${prot_full_name(**prot)}_id_t; + typedef logic [${camelcase(prot_full_name(**prot, prefix=''))}UserWidth-1:0] ${prot_full_name(**prot)}_user_t; + +% endfor +% for prot in protocols: + `AXI_TYPEDEF_ALL_CT(${prot_full_name(**prot)}, ${prot_full_name(**prot)}_req_t, ${prot_full_name(**prot)}_rsp_t, ${prot_full_name(**prot)}_addr_t, ${prot_full_name(**prot)}_id_t, ${prot_full_name(**prot)}_data_t, ${prot_full_name(**prot)}_strb_t, ${prot_full_name(**prot)}_user_t) +% endfor + + ///////////////////////// + // Header Typedefs // + ///////////////////////// + +% for m, l in header.items(): + % if l > 1: + typedef logic [${l-1}:0] ${m}_t; + % endif +% endfor + + typedef struct packed { + % for m, l in header.items(): + % if l == 1: + logic ${m}; + % else: + ${m}_t ${m}; + % endif + % endfor + } hdr_t; + + + //////////////////////////// + // AXI Flits Typedefs // + //////////////////////////// + + % for prot in protocols: + % if prot['direction'] == 'input': + % for axi_ch, size in get_axi_channel_sizes(**prot['params']).items(): +<% phys_ch = inv_map[prot['name']][axi_ch] %>\ +<% phys_ch_size = link_sizes[phys_ch] %>\ +<% rsvd_space = phys_ch_size - size %>\ + typedef struct packed { + hdr_t hdr; + ${prot_full_name(**prot)}_${axi_ch}_chan_t ${axi_ch}; + % if rsvd_space > 0: + logic [${rsvd_space-1}:0] rsvd; + % endif + } floo_${prot['name']}_${axi_ch}_flit_t; + + % endfor + % endif + % endfor + + //////////////////////////////// + // Generic Flits Typedefs // + //////////////////////////////// + + % for phys_ch in channel_mapping: + typedef struct packed { + hdr_t hdr; + logic [${link_sizes[phys_ch]-1}:0] rsvd; + } floo_${phys_ch}_generic_flit_t; + + % endfor + + ////////////////////////// + // Channel Typedefs // + ////////////////////////// + + % for phys_ch, mapping in channel_mapping.items(): + typedef union packed { + % for ch_type, axi_chs in mapping.items(): + % for axi_ch in axi_chs: + floo_${ch_type}_${axi_ch}_flit_t ${ch_type}_${axi_ch}; + % endfor + % endfor + floo_${phys_ch}_generic_flit_t generic; + } floo_${phys_ch}_chan_t; + + % endfor + /////////////////////// + // Link Typedefs // + /////////////////////// + + % for phys_ch in channel_mapping: + typedef struct packed { + logic valid; + logic ready; + floo_${phys_ch}_chan_t ${phys_ch}; + } floo_${phys_ch}_t; + + % endfor +endpackage diff --git a/util/floo_flit_pkg.sv.tpl b/util/floo_flit_pkg.sv.tpl deleted file mode 100644 index 6222d43e..00000000 --- a/util/floo_flit_pkg.sv.tpl +++ /dev/null @@ -1,166 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// This file is auto-generated. Do not edit! Edit the template file instead - -<% def list2array(values: list): - return '{' + ', '.join([str(a) for a in values]) + '}' -%> \ -<% def camelcase(word: str): - return ''.join([w.capitalize() for w in word.split('_')]) -%> \ -<% def clog2(value: int): - import math - return int(math.ceil(math.log(value, 2))) -%> \ -<%def zero_pad(values: list, length: int): - return values + [0] * (length - len(values)) -%> \ -<% - max_virt_ch_per_phys = max([len(i) for i in cfg['map'].values()]) -%> \ - -`include "axi/typedef.svh" - -package floo_${cfg['name']}_flit_pkg; - - localparam int unsigned NumPhysChannels = ${len(cfg['phys_channels'])}; - localparam int unsigned NumAxiChannels = ${len(cfg['axi_order'])}; - - //////////////////////// - // AXI Parameters // - //////////////////////// - -% for axi_ch in cfg['axi_channels']: - localparam int unsigned ${camelcase(axi_ch['name'])}AddrWidth = ${axi_ch['params']['aw']}; - localparam int unsigned ${camelcase(axi_ch['name'])}DataWidth = ${axi_ch['params']['dw']}; - localparam int unsigned ${camelcase(axi_ch['name'])}IdWidth = ${axi_ch['params']['iw']}; - localparam int unsigned ${camelcase(axi_ch['name'])}UserWidth = ${axi_ch['params']['uw']}; - -% endfor - -% for axi_ch in cfg['axi_channels']: - typedef logic [${axi_ch['params']['aw']-1}:0] ${axi_ch['name']}_addr_t; - typedef logic [${axi_ch['params']['dw']-1}:0] ${axi_ch['name']}_data_t; - typedef logic [${axi_ch['params']['dw']//8-1}:0] ${axi_ch['name']}_strb_t; - typedef logic [${axi_ch['params']['iw']-1}:0] ${axi_ch['name']}_id_t; - typedef logic [${axi_ch['params']['uw']-1}:0] ${axi_ch['name']}_user_t; - -% endfor - -% for axi_ch in cfg['axi_channels']: - `AXI_TYPEDEF_ALL(${axi_ch['name']}, ${axi_ch['name']}_addr_t, ${axi_ch['name']}_id_t, ${axi_ch['name']}_data_t, ${axi_ch['name']}_strb_t, ${axi_ch['name']}_user_t) -% endfor - - ////////////////////// - // AXI Channels // - ////////////////////// - - typedef enum logic[${clog2(len(cfg['axi_order']))-1}:0] { - % for axi_ch in cfg['axi_order']: - ${camelcase(axi_ch)}${'' if loop.last else ','} - % endfor - } axi_ch_e; - - /////////////////////////// - // Physical Channels // - /////////////////////////// - - typedef enum int { - % for phys_ch in cfg['phys_channels']: - Phys${camelcase(phys_ch)}${'' if loop.last else ','} - % endfor - } phys_chan_e; - - ///////////////////////// - // Channel Mapping // - ///////////////////////// - - localparam int NumVirtPerPhys[NumPhysChannels] = '${list2array([len(axi_chs) for axi_chs in cfg['map'].values()])}; - - localparam int PhysChanMapping[NumAxiChannels] = '{ - % for i in cfg['inv_map'].values(): - ${'Phys' + camelcase(i)}${'' if loop.last else ','} - % endfor - }; - - localparam int VirtChanMapping[NumPhysChannels][${max_virt_ch_per_phys}] = '{ - % for axi_chs in cfg['map'].values(): - '${list2array(zero_pad([camelcase(i) for i in axi_chs], max_virt_ch_per_phys))}${'' if loop.last else ','} - % endfor - }; - - /////////////////////// - // Meta Typedefs // - /////////////////////// - -% for m, l in cfg['meta'].items(): - typedef logic [${l-1}:0] ${m}_t; -% endfor - - //////////////////////////// - // AXI Packet Structs // - //////////////////////////// - -% for phys_ch, axi_chs in cfg['map'].items(): - % for axi_ch in axi_chs: - typedef struct packed { - % for m, l in cfg['meta'].items(): - ${m}_t ${m}; - % endfor - ${axi_ch}_chan_t ${axi_ch.split('_')[-1]}; - % if cfg['rsvd_bits'][axi_ch] != 0: - logic [${cfg['rsvd_bits'][axi_ch]-1}:0] rsvd; - % endif - } ${axi_ch}_data_t; - - % endfor - typedef struct packed { - % for m, l in cfg['meta'].items(): - ${m}_t ${m}; - % endfor - logic [${cfg['phys_ch_sizes'][phys_ch]-1}:0] rsvd; - } ${phys_ch}_generic_t; - -% endfor - - - /////////////////////////// - // AXI Packet Unions // - /////////////////////////// - -% for phys_ch, axi_chs in cfg['map'].items(): - typedef union packed { - % for axi_ch in axi_chs: - ${axi_ch}_data_t ${axi_ch}; - % endfor - ${phys_ch}_generic_t gen; - } ${phys_ch}_data_t; - -% endfor - - /////////////////////////////// - // Physical Flit Structs // - /////////////////////////////// - - % for phys_ch in cfg['phys_channels']: - typedef struct packed { - logic valid; - logic ready; - ${phys_ch}_data_t data; - } ${phys_ch}_flit_t; - - % endfor - - ////////////////////////////// - // Phys Packeed Structs // - ////////////////////////////// - - typedef struct packed { -% for phys_ch, axi_chs in cfg['map'].items(): - ${phys_ch}_flit_t ${phys_ch}; -% endfor - } flit_t; - -endpackage diff --git a/util/narrow_wide_cfg.hjson b/util/narrow_wide_cfg.hjson index 7d8871d0..5fb24ed6 100644 --- a/util/narrow_wide_cfg.hjson +++ b/util/narrow_wide_cfg.hjson @@ -6,23 +6,26 @@ { name: "narrow_wide", - axi_channels: [ - {name: 'narrow_in', params: {dw: 64, aw: 48, iw: 4, uw: 5 }}, - {name: 'narrow_out', params: {dw: 64, aw: 48, iw: 2, uw: 5 }}, - {name: 'wide_in', params: {dw: 512, aw: 48, iw: 3, uw: 1 }}, - {name: 'wide_out', params: {dw: 512, aw: 48, iw: 1, uw: 1 }}, + protocols: [ + {name: 'narrow', direction: 'input', params: {dw: 64, aw: 48, iw: 4, uw: 5 }}, + {name: 'narrow', direction: 'output', params: {dw: 64, aw: 48, iw: 2, uw: 5 }}, + {name: 'wide', direction: 'input', params: {dw: 512, aw: 48, iw: 3, uw: 1 }}, + {name: 'wide', direction: 'output', params: {dw: 512, aw: 48, iw: 1, uw: 1 }}, ] - phys_channels: [ - "narrow_req", - "narrow_rsp", - "wide", - ], - map: { - narrow_req: ["narrow_in_aw", "narrow_in_w", "narrow_in_ar", "wide_in_ar", "wide_in_aw"], - narrow_rsp: ["narrow_in_b", "narrow_in_r", "wide_in_b"] - wide: ["wide_in_w", "wide_in_r"] + channel_mapping: { + req: { + narrow: ['aw', 'w', 'ar'], + wide: ['aw', 'ar'] + }, + rsp: { + narrow: ['b', 'r'], + wide: ['b'] + }, + wide: { + wide: ['w', 'r'] + } }, - meta: { + header: { rob_req: 1, rob_idx: 8, dst_id: 6,