From aa5c168d7a6edd25cf006bc8c3b0fe037bfd7c65 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Wed, 24 Apr 2024 11:43:28 +0200 Subject: [PATCH 1/5] fpga: Testing hyperram in block design --- carfield.mk | 2 +- target/xilinx/flavor_bd/.gitignore | 15 +++++++++------ .../flavor_bd/constraints/vcu128_hyperbus.xdc | 12 ++++++------ .../flavor_bd/scripts/carfield_bd_hyperbus.tcl | 17 +++++++++++++++++ .../flavor_bd/scripts/carfield_bd_vcu128.tcl | 5 ----- target/xilinx/flavor_bd/scripts/run.tcl | 3 +-- 6 files changed, 34 insertions(+), 20 deletions(-) create mode 100644 target/xilinx/flavor_bd/scripts/carfield_bd_hyperbus.tcl diff --git a/carfield.mk b/carfield.mk index 3fadc7f3..93b32098 100644 --- a/carfield.mk +++ b/carfield.mk @@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk ###################### CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:carfield/carfield-nonfree.git -CAR_NONFREE_COMMIT ?= 59e53134 +CAR_NONFREE_COMMIT ?= 7d227bc7 ## @section Carfield platform nonfree components ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC diff --git a/target/xilinx/flavor_bd/.gitignore b/target/xilinx/flavor_bd/.gitignore index c9a0ab54..4b4f41e1 100644 --- a/target/xilinx/flavor_bd/.gitignore +++ b/target/xilinx/flavor_bd/.gitignore @@ -1,6 +1,9 @@ -.Xil -carfield_* -scripts/add_sources.tcl* -scripts/add_includes.tcl -out/ -probes.ltx \ No newline at end of file +# Makefile +/out/ +# Bender +/scripts/add_sources.tcl* +/scripts/add_includes.tcl +# Vivado +/.Xil +/carfield_* +/probes.ltx diff --git a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc index c6967631..0024e79d 100644 --- a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc @@ -14,8 +14,8 @@ set_property PACKAGE_PIN A24 [get_ports "pad_hyper_csn[1]"] ;# (FMCP set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 set_property PACKAGE_PIN A25 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 -set_property PACKAGE_PIN C23 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 +set_property PACKAGE_PIN C23 [get_ports "pad_hyper_rwds"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 set_property PACKAGE_PIN D26 [get_ports "pad_hyper_dq[2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 set_property PACKAGE_PIN A23 [get_ports pad_hyper_dq[3]] ;# (FMCP_HSPC_LA10_N) @@ -28,10 +28,10 @@ set_property PACKAGE_PIN D22 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 set_property PACKAGE_PIN E22 [get_ports "pad_hyper_dq[1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 -set_property PACKAGE_PIN F25 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 -set_property PACKAGE_PIN F26 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 +set_property PACKAGE_PIN F25 [get_ports "pad_hyper_ckn"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 +set_property PACKAGE_PIN F26 [get_ports "pad_hyper_ck"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 set_property PACKAGE_PIN G27 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 set_property PACKAGE_PIN H27 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_hyperbus.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_hyperbus.tcl new file mode 100644 index 00000000..c6fb15da --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_hyperbus.tcl @@ -0,0 +1,17 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set pad_hyper_ck [ create_bd_port -dir IO pad_hyper_ck ] +set pad_hyper_ckn [ create_bd_port -dir IO pad_hyper_ckn ] +set pad_hyper_csn [ create_bd_port -dir IO -from 1 -to 0 pad_hyper_csn ] +set pad_hyper_dq [ create_bd_port -dir IO -from 7 -to 0 pad_hyper_dq ] +set pad_hyper_rwds [ create_bd_port -dir IO pad_hyper_rwds ] + +connect_bd_net [get_bd_ports pad_hyper_csn] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn] +connect_bd_net [get_bd_ports pad_hyper_ck] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ck] +connect_bd_net [get_bd_ports pad_hyper_ckn] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ckn] +connect_bd_net [get_bd_ports pad_hyper_rwds] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_rwds] +connect_bd_net [get_bd_ports pad_hyper_dq] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_dq] diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl index 8557d77d..db9daa91 100644 --- a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl @@ -463,11 +463,6 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x1] [get_bd_intf_pins xdma_0/pcie_mgt] # Create port connections - connect_bd_net -net Net [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn] - connect_bd_net -net Net1 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ck] - connect_bd_net -net Net2 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ckn] - connect_bd_net -net Net3 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_rwds] - connect_bd_net -net Net4 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_dq] connect_bd_net -net axi_dma_0_mm2s_cntrl_reset_out_n [get_bd_pins axi_dma_0/mm2s_cntrl_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txc_arstn] connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins concat_irq/In2] connect_bd_net -net axi_dma_0_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_0/mm2s_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txd_arstn] diff --git a/target/xilinx/flavor_bd/scripts/run.tcl b/target/xilinx/flavor_bd/scripts/run.tcl index 9a529a06..3700bfb0 100644 --- a/target/xilinx/flavor_bd/scripts/run.tcl +++ b/target/xilinx/flavor_bd/scripts/run.tcl @@ -34,9 +34,8 @@ if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} { # Add the hyperbus pins to block design if {![info exists ::env(GEN_NO_HYPERBUS)] || ($::env(GEN_NO_HYPERBUS)==0)} { + source scripts/carfield_bd_hyperbus.tcl import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_hyperbus.xdc -} else { - delete_bd_objs [get_bd_ports pad_hyper*] } make_wrapper -files [get_files $project/$project.srcs/sources_1/bd/design_1/design_1.bd] -top From 5ee14d7c66ed8272544f09c98ae62fbc41022cae Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Wed, 24 Apr 2024 11:57:40 +0200 Subject: [PATCH 2/5] fpga: Testing hyperram in vanilla --- .../flavor_bd/constraints/vcu128_ext_jtag.xdc | 6 + .../flavor_bd/constraints/vcu128_hyperbus.xdc | 60 +- .../flavor_vanilla/constraints/vcu128.xdc | 233 +--- .../constraints/vcu128_ext_jtag.xdc | 23 + .../constraints/vcu128_hyperbus.xdc | 48 + .../flavor_vanilla/constraints/zcu102.xdc | 1096 ----------------- target/xilinx/flavor_vanilla/scripts/run.tcl | 9 + 7 files changed, 120 insertions(+), 1355 deletions(-) create mode 100644 target/xilinx/flavor_vanilla/constraints/vcu128_ext_jtag.xdc create mode 100644 target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc delete mode 100644 target/xilinx/flavor_vanilla/constraints/zcu102.xdc diff --git a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc index 38bb4b50..69dc4e1a 100644 --- a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc @@ -1,3 +1,9 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; diff --git a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc index 0024e79d..daffcb34 100644 --- a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc @@ -1,5 +1,10 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O}] #set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 @@ -10,35 +15,36 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/carfield_xilinx_ip #set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA20_P) Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 #set_property PACKAGE_PIN D20 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 #set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 -set_property PACKAGE_PIN A24 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 -set_property PACKAGE_PIN A25 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 -set_property PACKAGE_PIN C23 [get_ports "pad_hyper_rwds"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 -set_property PACKAGE_PIN D26 [get_ports "pad_hyper_dq[2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 -set_property PACKAGE_PIN A23 [get_ports pad_hyper_dq[3]] ;# (FMCP_HSPC_LA10_N) -set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_dq[3]] ;# (FMCP_HSPC_LA10_N) -set_property PACKAGE_PIN B23 [get_ports pad_hyper_dq[0]] ;# (FMCP_HSPC_LA10_P) -set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_dq[0]] ;# (FMCP_HSPC_LA10_P) -set_property PACKAGE_PIN E26 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA09_P) Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA09_P) Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 -set_property PACKAGE_PIN D22 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 -set_property PACKAGE_PIN E22 [get_ports "pad_hyper_dq[1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 -set_property PACKAGE_PIN F25 [get_ports "pad_hyper_ckn"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 -set_property PACKAGE_PIN F26 [get_ports "pad_hyper_ck"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 -set_property PACKAGE_PIN G27 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 -set_property PACKAGE_PIN H27 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 +set_property PACKAGE_PIN A24 [get_ports {pad_hyper_csn[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_csn[1]}] +set_property PACKAGE_PIN A25 [get_ports {pad_hyper_csn[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_csn[0]}] +set_property PACKAGE_PIN C23 [get_ports pad_hyper_rwds] +set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_rwds] +set_property PACKAGE_PIN D26 [get_ports {pad_hyper_dq[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[2]}] +set_property PACKAGE_PIN A23 [get_ports {pad_hyper_dq[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[3]}] +set_property PACKAGE_PIN B23 [get_ports {pad_hyper_dq[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[0]}] +set_property PACKAGE_PIN E26 [get_ports {pad_hyper_dq[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[4]}] +set_property PACKAGE_PIN D22 [get_ports {pad_hyper_dq[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[7]}] +set_property PACKAGE_PIN E22 [get_ports {pad_hyper_dq[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[1]}] +set_property PACKAGE_PIN F25 [get_ports pad_hyper_ckn] +set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_ckn] +set_property PACKAGE_PIN F26 [get_ports pad_hyper_ck] +set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_ck] +set_property PACKAGE_PIN G27 [get_ports {pad_hyper_dq[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[5]}] +set_property PACKAGE_PIN H27 [get_ports {pad_hyper_dq[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[6]}] #set_property PACKAGE_PIN L23 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 #set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 #set_property PACKAGE_PIN K23 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 #set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 #set_property PACKAGE_PIN K24 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 #set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 + diff --git a/target/xilinx/flavor_vanilla/constraints/vcu128.xdc b/target/xilinx/flavor_vanilla/constraints/vcu128.xdc index d810d1d6..be0cde30 100644 --- a/target/xilinx/flavor_vanilla/constraints/vcu128.xdc +++ b/target/xilinx/flavor_vanilla/constraints/vcu128.xdc @@ -1196,240 +1196,9 @@ set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] #set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK4_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_73 #set_property PACKAGE_PIN K41 [get_ports "RLD3_72B_QK4_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_73 #set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK4_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_73 -#set_property PACKAGE_PIN A24 [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 -#set_property PACKAGE_PIN A25 [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 -#set_property PACKAGE_PIN A26 [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 72 VCCO - VADJ - IO_L23N_T3U_N9_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 72 VCCO - VADJ - IO_L23N_T3U_N9_72 -#set_property PACKAGE_PIN B27 [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 72 VCCO - VADJ - IO_L23P_T3U_N8_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 72 VCCO - VADJ - IO_L23P_T3U_N8_72 -set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND -set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; +# FMC moved in vcu128_ext_jtag.xdc -set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD -set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; - -set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] - -set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; - -#set_property PACKAGE_PIN C24 [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 72 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 72 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_72 -#set_property PACKAGE_PIN C25 [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 72 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 72 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_72 -#set_property PACKAGE_PIN B22 [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 72 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 72 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_72 -#set_property PACKAGE_PIN C23 [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 -#set_property PACKAGE_PIN C22 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T3U_N12_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T3U_N12_72 -#set_property PACKAGE_PIN C27 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T2U_N12_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T2U_N12_72 -#set_property PACKAGE_PIN D27 [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 72 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 72 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_72 -#set_property PACKAGE_PIN E27 [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 72 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 72 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_72 -#set_property PACKAGE_PIN D26 [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 -#set_property PACKAGE_PIN E26 [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 -#set_property PACKAGE_PIN D24 [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_72 -#set_property PACKAGE_PIN D25 [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_72 -#set_property PACKAGE_PIN D22 [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 -#set_property PACKAGE_PIN E22 [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 -#set_property PACKAGE_PIN F25 [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 -#set_property PACKAGE_PIN F26 [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 -#set_property PACKAGE_PIN E23 [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_72 -#set_property PACKAGE_PIN E24 [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_72 -#set_property PACKAGE_PIN G25 [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L12N_T1U_N11_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L12N_T1U_N11_GC_72 -#set_property PACKAGE_PIN G26 [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L12P_T1U_N10_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L12P_T1U_N10_GC_72 -#set_property PACKAGE_PIN F23 [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L11N_T1U_N9_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L11N_T1U_N9_GC_72 -#set_property PACKAGE_PIN F24 [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L11P_T1U_N8_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L11P_T1U_N8_GC_72 -#set_property PACKAGE_PIN G22 [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_72 -#set_property PACKAGE_PIN G23 [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_72 -#set_property PACKAGE_PIN G27 [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 -#set_property PACKAGE_PIN H27 [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 - -set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; - -set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] - -#set_property PACKAGE_PIN H23 [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_72 -#set_property PACKAGE_PIN H24 [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_72 -#set_property PACKAGE_PIN H25 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T1U_N12_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T1U_N12_72 -#set_property PACKAGE_PIN J24 [get_ports "VRP_72"] ;# Bank 72 VCCO - VADJ - IO_T0U_N12_VRP_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_72"] ;# Bank 72 VCCO - VADJ - IO_T0U_N12_VRP_72 -#set_property PACKAGE_PIN J25 [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 72 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 72 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_72 -#set_property PACKAGE_PIN J26 [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 72 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 72 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_72 -#set_property PACKAGE_PIN J27 [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 72 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 72 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_72 -#set_property PACKAGE_PIN K27 [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 72 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 72 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_72 -#set_property PACKAGE_PIN K22 [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 72 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 72 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_72 -#set_property PACKAGE_PIN L23 [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 -#set_property PACKAGE_PIN K23 [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 -#set_property PACKAGE_PIN K24 [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 -#set_property PACKAGE_PIN K26 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2N_T0L_N3_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2N_T0L_N3_72 -#set_property PACKAGE_PIN L26 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2P_T0L_N2_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2P_T0L_N2_72 -#set_property PACKAGE_PIN L24 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1N_T0L_N1_DBC_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1N_T0L_N1_DBC_72 -#set_property PACKAGE_PIN L25 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1P_T0L_N0_DBC_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1P_T0L_N0_DBC_72 -#set_property PACKAGE_PIN AV43 [get_ports "FMCP_HSPC_GBTCLK0_M2C_N"] ;# Bank 124 - MGTREFCLK0N_124 -#set_property PACKAGE_PIN AV42 [get_ports "FMCP_HSPC_GBTCLK0_M2C_P"] ;# Bank 124 - MGTREFCLK0P_124 -#set_property PACKAGE_PIN AT43 [get_ports "No Connect"] ;# Bank 124 - MGTREFCLK1N_124 -#set_property PACKAGE_PIN AT42 [get_ports "No Connect"] ;# Bank 124 - MGTREFCLK1P_124 -#set_property PACKAGE_PIN BC54 [get_ports "FMCP_HSPC_DP0_M2C_N"] ;# Bank 124 - MGTYRXN0_124 -#set_property PACKAGE_PIN BB52 [get_ports "FMCP_HSPC_DP1_M2C_N"] ;# Bank 124 - MGTYRXN1_124 -#set_property PACKAGE_PIN BA54 [get_ports "FMCP_HSPC_DP2_M2C_N"] ;# Bank 124 - MGTYRXN2_124 -#set_property PACKAGE_PIN BA50 [get_ports "FMCP_HSPC_DP3_M2C_N"] ;# Bank 124 - MGTYRXN3_124 -#set_property PACKAGE_PIN BC53 [get_ports "FMCP_HSPC_DP0_M2C_P"] ;# Bank 124 - MGTYRXP0_124 -#set_property PACKAGE_PIN BB51 [get_ports "FMCP_HSPC_DP1_M2C_P"] ;# Bank 124 - MGTYRXP1_124 -#set_property PACKAGE_PIN BA53 [get_ports "FMCP_HSPC_DP2_M2C_P"] ;# Bank 124 - MGTYRXP2_124 -#set_property PACKAGE_PIN BA49 [get_ports "FMCP_HSPC_DP3_M2C_P"] ;# Bank 124 - MGTYRXP3_124 -#set_property PACKAGE_PIN BC49 [get_ports "FMCP_HSPC_DP0_C2M_N"] ;# Bank 124 - MGTYTXN0_124 -#set_property PACKAGE_PIN BC45 [get_ports "FMCP_HSPC_DP1_C2M_N"] ;# Bank 124 - MGTYTXN1_124 -#set_property PACKAGE_PIN BB47 [get_ports "FMCP_HSPC_DP2_C2M_N"] ;# Bank 124 - MGTYTXN2_124 -#set_property PACKAGE_PIN BA45 [get_ports "FMCP_HSPC_DP3_C2M_N"] ;# Bank 124 - MGTYTXN3_124 -#set_property PACKAGE_PIN BC48 [get_ports "FMCP_HSPC_DP0_C2M_P"] ;# Bank 124 - MGTYTXP0_124 -#set_property PACKAGE_PIN BC44 [get_ports "FMCP_HSPC_DP1_C2M_P"] ;# Bank 124 - MGTYTXP1_124 -#set_property PACKAGE_PIN BB46 [get_ports "FMCP_HSPC_DP2_C2M_P"] ;# Bank 124 - MGTYTXP2_124 -#set_property PACKAGE_PIN BA44 [get_ports "FMCP_HSPC_DP3_C2M_P"] ;# Bank 124 - MGTYTXP3_124 -#set_property PACKAGE_PIN AR41 [get_ports "FMCP_HSPC_GBTCLK1_M2C_N"] ;# Bank 125 - MGTREFCLK0N_125 -#set_property PACKAGE_PIN AR40 [get_ports "FMCP_HSPC_GBTCLK1_M2C_P"] ;# Bank 125 - MGTREFCLK0P_125 -#set_property PACKAGE_PIN AP43 [get_ports "No Connect"] ;# Bank 125 - MGTREFCLK1N_125 -#set_property PACKAGE_PIN AP42 [get_ports "No Connect"] ;# Bank 125 - MGTREFCLK1P_125 -#set_property PACKAGE_PIN AU41 [get_ports "N22117206"] ;# Bank 125 - MGTRREF_LS -#set_property PACKAGE_PIN AY52 [get_ports "FMCP_HSPC_DP4_M2C_N"] ;# Bank 125 - MGTYRXN0_125 -#set_property PACKAGE_PIN AW54 [get_ports "FMCP_HSPC_DP5_M2C_N"] ;# Bank 125 - MGTYRXN1_125 -#set_property PACKAGE_PIN AW50 [get_ports "FMCP_HSPC_DP6_M2C_N"] ;# Bank 125 - MGTYRXN2_125 -#set_property PACKAGE_PIN AV52 [get_ports "FMCP_HSPC_DP7_M2C_N"] ;# Bank 125 - MGTYRXN3_125 -#set_property PACKAGE_PIN AY51 [get_ports "FMCP_HSPC_DP4_M2C_P"] ;# Bank 125 - MGTYRXP0_125 -#set_property PACKAGE_PIN AW53 [get_ports "FMCP_HSPC_DP5_M2C_P"] ;# Bank 125 - MGTYRXP1_125 -#set_property PACKAGE_PIN AW49 [get_ports "FMCP_HSPC_DP6_M2C_P"] ;# Bank 125 - MGTYRXP2_125 -#set_property PACKAGE_PIN AV51 [get_ports "FMCP_HSPC_DP7_M2C_P"] ;# Bank 125 - MGTYRXP3_125 -#set_property PACKAGE_PIN AY47 [get_ports "FMCP_HSPC_DP4_C2M_N"] ;# Bank 125 - MGTYTXN0_125 -#set_property PACKAGE_PIN AW45 [get_ports "FMCP_HSPC_DP5_C2M_N"] ;# Bank 125 - MGTYTXN1_125 -#set_property PACKAGE_PIN AV47 [get_ports "FMCP_HSPC_DP6_C2M_N"] ;# Bank 125 - MGTYTXN2_125 -#set_property PACKAGE_PIN AU45 [get_ports "FMCP_HSPC_DP7_C2M_N"] ;# Bank 125 - MGTYTXN3_125 -#set_property PACKAGE_PIN AY46 [get_ports "FMCP_HSPC_DP4_C2M_P"] ;# Bank 125 - MGTYTXP0_125 -#set_property PACKAGE_PIN AW44 [get_ports "FMCP_HSPC_DP5_C2M_P"] ;# Bank 125 - MGTYTXP1_125 -#set_property PACKAGE_PIN AV46 [get_ports "FMCP_HSPC_DP6_C2M_P"] ;# Bank 125 - MGTYTXP2_125 -#set_property PACKAGE_PIN AU44 [get_ports "FMCP_HSPC_DP7_C2M_P"] ;# Bank 125 - MGTYTXP3_125 -#set_property PACKAGE_PIN AN41 [get_ports "FMCP_HSPC_GBTCLK2_M2C_N"] ;# Bank 126 - MGTREFCLK0N_126 -#set_property PACKAGE_PIN AN40 [get_ports "FMCP_HSPC_GBTCLK2_M2C_P"] ;# Bank 126 - MGTREFCLK0P_126 -#set_property PACKAGE_PIN AM43 [get_ports "No Connect"] ;# Bank 126 - MGTREFCLK1N_126 -#set_property PACKAGE_PIN AM42 [get_ports "No Connect"] ;# Bank 126 - MGTREFCLK1P_126 -#set_property PACKAGE_PIN AU54 [get_ports "FMCP_HSPC_DP8_M2C_N"] ;# Bank 126 - MGTYRXN0_126 -#set_property PACKAGE_PIN AT52 [get_ports "FMCP_HSPC_DP9_M2C_N"] ;# Bank 126 - MGTYRXN1_126 -#set_property PACKAGE_PIN AR54 [get_ports "FMCP_HSPC_DP10_M2C_N"] ;# Bank 126 - MGTYRXN2_126 -#set_property PACKAGE_PIN AP52 [get_ports "FMCP_HSPC_DP11_M2C_N"] ;# Bank 126 - MGTYRXN3_126 -#set_property PACKAGE_PIN AU53 [get_ports "FMCP_HSPC_DP8_M2C_P"] ;# Bank 126 - MGTYRXP0_126 -#set_property PACKAGE_PIN AT51 [get_ports "FMCP_HSPC_DP9_M2C_P"] ;# Bank 126 - MGTYRXP1_126 -#set_property PACKAGE_PIN AR53 [get_ports "FMCP_HSPC_DP10_M2C_P"] ;# Bank 126 - MGTYRXP2_126 -#set_property PACKAGE_PIN AP51 [get_ports "FMCP_HSPC_DP11_M2C_P"] ;# Bank 126 - MGTYRXP3_126 -#set_property PACKAGE_PIN AU49 [get_ports "FMCP_HSPC_DP8_C2M_N"] ;# Bank 126 - MGTYTXN0_126 -#set_property PACKAGE_PIN AT47 [get_ports "FMCP_HSPC_DP9_C2M_N"] ;# Bank 126 - MGTYTXN1_126 -#set_property PACKAGE_PIN AR49 [get_ports "FMCP_HSPC_DP10_C2M_N"] ;# Bank 126 - MGTYTXN2_126 -#set_property PACKAGE_PIN AR45 [get_ports "FMCP_HSPC_DP11_C2M_N"] ;# Bank 126 - MGTYTXN3_126 -#set_property PACKAGE_PIN AU48 [get_ports "FMCP_HSPC_DP8_C2M_P"] ;# Bank 126 - MGTYTXP0_126 -#set_property PACKAGE_PIN AT46 [get_ports "FMCP_HSPC_DP9_C2M_P"] ;# Bank 126 - MGTYTXP1_126 -#set_property PACKAGE_PIN AR48 [get_ports "FMCP_HSPC_DP10_C2M_P"] ;# Bank 126 - MGTYTXP2_126 -#set_property PACKAGE_PIN AR44 [get_ports "FMCP_HSPC_DP11_C2M_P"] ;# Bank 126 - MGTYTXP3_126 -#set_property PACKAGE_PIN AL41 [get_ports "FMCP_HSPC_GBTCLK3_M2C_N"] ;# Bank 127 - MGTREFCLK0N_127 -#set_property PACKAGE_PIN AL40 [get_ports "FMCP_HSPC_GBTCLK3_M2C_P"] ;# Bank 127 - MGTREFCLK0P_127 -#set_property PACKAGE_PIN AK43 [get_ports "No Connect"] ;# Bank 127 - MGTREFCLK1N_127 -#set_property PACKAGE_PIN AK42 [get_ports "No Connect"] ;# Bank 127 - MGTREFCLK1P_127 -#set_property PACKAGE_PIN AN54 [get_ports "FMCP_HSPC_DP12_M2C_N"] ;# Bank 127 - MGTYRXN0_127 -#set_property PACKAGE_PIN AN50 [get_ports "FMCP_HSPC_DP13_M2C_N"] ;# Bank 127 - MGTYRXN1_127 -#set_property PACKAGE_PIN AM52 [get_ports "FMCP_HSPC_DP14_M2C_N"] ;# Bank 127 - MGTYRXN2_127 -#set_property PACKAGE_PIN AL54 [get_ports "FMCP_HSPC_DP15_M2C_N"] ;# Bank 127 - MGTYRXN3_127 -#set_property PACKAGE_PIN AN53 [get_ports "FMCP_HSPC_DP12_M2C_P"] ;# Bank 127 - MGTYRXP0_127 -#set_property PACKAGE_PIN AN49 [get_ports "FMCP_HSPC_DP13_M2C_P"] ;# Bank 127 - MGTYRXP1_127 -#set_property PACKAGE_PIN AM51 [get_ports "FMCP_HSPC_DP14_M2C_P"] ;# Bank 127 - MGTYRXP2_127 -#set_property PACKAGE_PIN AL53 [get_ports "FMCP_HSPC_DP15_M2C_P"] ;# Bank 127 - MGTYRXP3_127 -#set_property PACKAGE_PIN AP47 [get_ports "FMCP_HSPC_DP12_C2M_N"] ;# Bank 127 - MGTYTXN0_127 -#set_property PACKAGE_PIN AN45 [get_ports "FMCP_HSPC_DP13_C2M_N"] ;# Bank 127 - MGTYTXN1_127 -#set_property PACKAGE_PIN AM47 [get_ports "FMCP_HSPC_DP14_C2M_N"] ;# Bank 127 - MGTYTXN2_127 -#set_property PACKAGE_PIN AL45 [get_ports "FMCP_HSPC_DP15_C2M_N"] ;# Bank 127 - MGTYTXN3_127 -#set_property PACKAGE_PIN AP46 [get_ports "FMCP_HSPC_DP12_C2M_P"] ;# Bank 127 - MGTYTXP0_127 -#set_property PACKAGE_PIN AN44 [get_ports "FMCP_HSPC_DP13_C2M_P"] ;# Bank 127 - MGTYTXP1_127 -#set_property PACKAGE_PIN AM46 [get_ports "FMCP_HSPC_DP14_C2M_P"] ;# Bank 127 - MGTYTXP2_127 -#set_property PACKAGE_PIN AL44 [get_ports "FMCP_HSPC_DP15_C2M_P"] ;# Bank 127 - MGTYTXP3_127 -#set_property PACKAGE_PIN AJ41 [get_ports "FMCP_HSPC_GBTCLK4_M2C_N"] ;# Bank 128 - MGTREFCLK0N_128 -#set_property PACKAGE_PIN AJ40 [get_ports "FMCP_HSPC_GBTCLK4_M2C_P"] ;# Bank 128 - MGTREFCLK0P_128 -#set_property PACKAGE_PIN AH43 [get_ports "No Connect"] ;# Bank 128 - MGTREFCLK1N_128 -#set_property PACKAGE_PIN AH42 [get_ports "No Connect"] ;# Bank 128 - MGTREFCLK1P_128 -#set_property PACKAGE_PIN AL50 [get_ports "FMCP_HSPC_DP16_M2C_N"] ;# Bank 128 - MGTYRXN0_128 -#set_property PACKAGE_PIN AK52 [get_ports "FMCP_HSPC_DP17_M2C_N"] ;# Bank 128 - MGTYRXN1_128 -#set_property PACKAGE_PIN AJ54 [get_ports "FMCP_HSPC_DP18_M2C_N"] ;# Bank 128 - MGTYRXN2_128 -#set_property PACKAGE_PIN AH52 [get_ports "FMCP_HSPC_DP19_M2C_N"] ;# Bank 128 - MGTYRXN3_128 -#set_property PACKAGE_PIN AL49 [get_ports "FMCP_HSPC_DP16_M2C_P"] ;# Bank 128 - MGTYRXP0_128 -#set_property PACKAGE_PIN AK51 [get_ports "FMCP_HSPC_DP17_M2C_P"] ;# Bank 128 - MGTYRXP1_128 -#set_property PACKAGE_PIN AJ53 [get_ports "FMCP_HSPC_DP18_M2C_P"] ;# Bank 128 - MGTYRXP2_128 -#set_property PACKAGE_PIN AH51 [get_ports "FMCP_HSPC_DP19_M2C_P"] ;# Bank 128 - MGTYRXP3_128 -#set_property PACKAGE_PIN AK47 [get_ports "FMCP_HSPC_DP16_C2M_N"] ;# Bank 128 - MGTYTXN0_128 -#set_property PACKAGE_PIN AJ49 [get_ports "FMCP_HSPC_DP17_C2M_N"] ;# Bank 128 - MGTYTXN1_128 -#set_property PACKAGE_PIN AJ45 [get_ports "FMCP_HSPC_DP18_C2M_N"] ;# Bank 128 - MGTYTXN2_128 -#set_property PACKAGE_PIN AH47 [get_ports "FMCP_HSPC_DP19_C2M_N"] ;# Bank 128 - MGTYTXN3_128 -#set_property PACKAGE_PIN AK46 [get_ports "FMCP_HSPC_DP16_C2M_P"] ;# Bank 128 - MGTYTXP0_128 -#set_property PACKAGE_PIN AJ48 [get_ports "FMCP_HSPC_DP17_C2M_P"] ;# Bank 128 - MGTYTXP1_128 -#set_property PACKAGE_PIN AJ44 [get_ports "FMCP_HSPC_DP18_C2M_P"] ;# Bank 128 - MGTYTXP2_128 -#set_property PACKAGE_PIN AH46 [get_ports "FMCP_HSPC_DP19_C2M_P"] ;# Bank 128 - MGTYTXP3_128 -#set_property PACKAGE_PIN AG41 [get_ports "FMCP_HSPC_GBTCLK5_M2C_N"] ;# Bank 129 - MGTREFCLK0N_129 -#set_property PACKAGE_PIN AG40 [get_ports "FMCP_HSPC_GBTCLK5_M2C_P"] ;# Bank 129 - MGTREFCLK0P_129 -#set_property PACKAGE_PIN AF43 [get_ports "No Connect"] ;# Bank 129 - MGTREFCLK1N_129 -#set_property PACKAGE_PIN AF42 [get_ports "No Connect"] ;# Bank 129 - MGTREFCLK1P_129 -#set_property PACKAGE_PIN AE41 [get_ports "N21075880"] ;# Bank 129 - MGTRREF_LC -#set_property PACKAGE_PIN AG54 [get_ports "FMCP_HSPC_DP20_M2C_N"] ;# Bank 129 - MGTYRXN0_129 -#set_property PACKAGE_PIN AF52 [get_ports "FMCP_HSPC_DP21_M2C_N"] ;# Bank 129 - MGTYRXN1_129 -#set_property PACKAGE_PIN AE54 [get_ports "FMCP_HSPC_DP22_M2C_N"] ;# Bank 129 - MGTYRXN2_129 -#set_property PACKAGE_PIN AE50 [get_ports "FMCP_HSPC_DP23_M2C_N"] ;# Bank 129 - MGTYRXN3_129 -#set_property PACKAGE_PIN AG53 [get_ports "FMCP_HSPC_DP20_M2C_P"] ;# Bank 129 - MGTYRXP0_129 -#set_property PACKAGE_PIN AF51 [get_ports "FMCP_HSPC_DP21_M2C_P"] ;# Bank 129 - MGTYRXP1_129 -#set_property PACKAGE_PIN AE53 [get_ports "FMCP_HSPC_DP22_M2C_P"] ;# Bank 129 - MGTYRXP2_129 -#set_property PACKAGE_PIN AE49 [get_ports "FMCP_HSPC_DP23_M2C_P"] ;# Bank 129 - MGTYRXP3_129 -#set_property PACKAGE_PIN AG49 [get_ports "FMCP_HSPC_DP20_C2M_N"] ;# Bank 129 - MGTYTXN0_129 -#set_property PACKAGE_PIN AG45 [get_ports "FMCP_HSPC_DP21_C2M_N"] ;# Bank 129 - MGTYTXN1_129 -#set_property PACKAGE_PIN AF47 [get_ports "FMCP_HSPC_DP22_C2M_N"] ;# Bank 129 - MGTYTXN2_129 -#set_property PACKAGE_PIN AE45 [get_ports "FMCP_HSPC_DP23_C2M_N"] ;# Bank 129 - MGTYTXN3_129 -#set_property PACKAGE_PIN AG48 [get_ports "FMCP_HSPC_DP20_C2M_P"] ;# Bank 129 - MGTYTXP0_129 -#set_property PACKAGE_PIN AG44 [get_ports "FMCP_HSPC_DP21_C2M_P"] ;# Bank 129 - MGTYTXP1_129 -#set_property PACKAGE_PIN AF46 [get_ports "FMCP_HSPC_DP22_C2M_P"] ;# Bank 129 - MGTYTXP2_129 -#set_property PACKAGE_PIN AE44 [get_ports "FMCP_HSPC_DP23_C2M_P"] ;# Bank 129 - MGTYTXP3_129 #set_property PACKAGE_PIN AD43 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK0N_130 #set_property PACKAGE_PIN AD42 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK0P_130 #set_property PACKAGE_PIN AC41 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK1N_130 diff --git a/target/xilinx/flavor_vanilla/constraints/vcu128_ext_jtag.xdc b/target/xilinx/flavor_vanilla/constraints/vcu128_ext_jtag.xdc new file mode 100644 index 00000000..69dc4e1a --- /dev/null +++ b/target/xilinx/flavor_vanilla/constraints/vcu128_ext_jtag.xdc @@ -0,0 +1,23 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND +set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; + +set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD +set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; + +set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] + +set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; + +set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; + +set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] diff --git a/target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc b/target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc new file mode 100644 index 00000000..65cb267a --- /dev/null +++ b/target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc @@ -0,0 +1,48 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_ports pad_hyper_rwds[0]] + +#set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 +#set_property PACKAGE_PIN A20 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA20_N) Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA20_N) Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71 +#set_property PACKAGE_PIN A21 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA20_P) Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA20_P) Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 +#set_property PACKAGE_PIN D20 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 +set_property PACKAGE_PIN A24 [get_ports "pad_hyper_csn[0][1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0][1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 +set_property PACKAGE_PIN A25 [get_ports "pad_hyper_csn[0][0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0][0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 +set_property PACKAGE_PIN C23 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 +set_property PACKAGE_PIN D26 [get_ports "pad_hyper_dq[0][2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 +set_property PACKAGE_PIN A23 [get_ports pad_hyper_dq[0][3]] ;# (FMCP_HSPC_LA10_N) +set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_dq[0][3]] ;# (FMCP_HSPC_LA10_N) +set_property PACKAGE_PIN B23 [get_ports pad_hyper_dq[0][0]] ;# (FMCP_HSPC_LA10_P) +set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_dq[0][0]] ;# (FMCP_HSPC_LA10_P) +set_property PACKAGE_PIN E26 [get_ports "pad_hyper_dq[0][4]"] ;# (FMCP_HSPC_LA09_P) Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][4]"] ;# (FMCP_HSPC_LA09_P) Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 +set_property PACKAGE_PIN D22 [get_ports "pad_hyper_dq[0][7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 +set_property PACKAGE_PIN E22 [get_ports "pad_hyper_dq[0][1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 +set_property PACKAGE_PIN F25 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 +set_property PACKAGE_PIN F26 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 +set_property PACKAGE_PIN G27 [get_ports "pad_hyper_dq[0][5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 +set_property PACKAGE_PIN H27 [get_ports "pad_hyper_dq[0][6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 +#set_property PACKAGE_PIN L23 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 +#set_property PACKAGE_PIN K23 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 +#set_property PACKAGE_PIN K24 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 diff --git a/target/xilinx/flavor_vanilla/constraints/zcu102.xdc b/target/xilinx/flavor_vanilla/constraints/zcu102.xdc deleted file mode 100644 index c27d0f18..00000000 --- a/target/xilinx/flavor_vanilla/constraints/zcu102.xdc +++ /dev/null @@ -1,1096 +0,0 @@ -############################## -# BOARD SPECIFIC CONSTRAINTS # -############################## - -# JTAG - -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] - -# Hyperbus -# 10MHz -set period_hyperbus 100 -create_clock -period [expr $period_hyperbus] -name rwds0_clk [get_ports pad_hyper_rwds[0]] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O] - - -set clk_rwds_delayed_pin [get_pins -of_objects [get_cells i_iguana/i_hyperbus/i_phy/i_phy/i_trx/i_delay_rx_rwds_90/i_delay] -filter {DIRECTION =~ OUT}] -set clk_rwds_delayed_inv_pin [get_pins i_iguana/i_hyperbus/i_phy/i_phy/i_trx/i_rx_rwds_cdc_fifo/src_clk_i] - - -set clk_rx_shift [expr $period_hyperbus/10] -set rwds_input_delay [expr $period_hyperbus/4] -create_generated_clock -name clk_rwds_delayed0 -edges {1 2 3} -edge_shift "$clk_rx_shift $clk_rx_shift $clk_rx_shift" \ - -source [get_ports FMC_hyper0_rwds] $clk_rwds_delayed_pin -set_clock_latency [expr ${rwds_input_delay}] clk_rwds_delayed0 - -create_generated_clock -name clk_rwds_sample0 -invert -divide_by 1 -source $clk_rwds_delayed_pin $clk_rwds_delayed_inv_pin -set_clock_latency [expr ${rwds_input_delay}] clk_rwds_sample0 - - -################################################################################# - -############### -# ASSIGN PINS # -############### - - -################################################# -### ZCU102 Rev1.0 Master XDC file 09-15-2016 #### -################################################# -#Other net PACKAGE_PIN W17 - SYSMON_DXN Bank 0 - DXN -#Other net PACKAGE_PIN T18 - FPGA_SYSMON_AVCC Bank 0 - VCCADC -#Other net PACKAGE_PIN T17 - SYSMON_AGND Bank 0 - GNDADC -#Other net PACKAGE_PIN W18 - SYSMON_DXP Bank 0 - DXP -#Other net PACKAGE_PIN V18 - SYSMON_VREFP Bank 0 - VREFP -#Other net PACKAGE_PIN U17 - SYSMON_AGND Bank 0 - VREFN -#Other net PACKAGE_PIN U18 - SYSMON_VP_R Bank 0 - VP -#Other net PACKAGE_PIN V17 - SYSMON_VN_R Bank 0 - VN -#Other net PACKAGE_PIN AD15 - 3N5822 Bank 0 - PUDC_B_0 -#Other net PACKAGE_PIN AD14 - 3N5824 Bank 0 - POR_OVERRIDE -#set_property PACKAGE_PIN J15 [get_ports "L12N_AD8N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L12N_AD8N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L12N_AD8N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L12N_AD8N_50 -#set_property PACKAGE_PIN J16 [get_ports "L12P_AD8P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L12P_AD8P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L12P_AD8P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L12P_AD8P_50 -#set_property PACKAGE_PIN G16 [get_ports "L11N_AD9N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L11N_AD9N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L11N_AD9N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L11N_AD9N_50 -#set_property PACKAGE_PIN H16 [get_ports "L11P_AD9P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L11P_AD9P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L11P_AD9P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L11P_AD9P_50 -#set_property PACKAGE_PIN H14 [get_ports "L10N_AD10N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L10N_AD10N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L10N_AD10N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L10N_AD10N_50 -#set_property PACKAGE_PIN J14 [get_ports "L10P_AD10P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L10P_AD10P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L10P_AD10P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L10P_AD10P_50 -#set_property PACKAGE_PIN G14 [get_ports "L9N_AD11N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L9N_AD11N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L9N_AD11N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L9N_AD11N_50 -#set_property PACKAGE_PIN G15 [get_ports "L9P_AD11P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L9P_AD11P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L9P_AD11P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L9P_AD11P_50 -#set_property PACKAGE_PIN G13 [get_ports "L8N_HDGC_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L8N_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L8N_HDGC_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L8N_HDGC_50 -#set_property PACKAGE_PIN H13 [get_ports "L8P_HDGC_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L8P_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L8P_HDGC_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L8P_HDGC_50 -#set_property PACKAGE_PIN H12 [get_ports "HDMI_SI5324_LOL"] ;# Bank 50 VCCO - VCC3V3 - IO_L7N_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_LOL"] ;# Bank 50 VCCO - VCC3V3 - IO_L7N_HDGC_50 -#set_property PACKAGE_PIN J12 [get_ports "HDMI_SI5324_RST"] ;# Bank 50 VCCO - VCC3V3 - IO_L7P_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_RST"] ;# Bank 50 VCCO - VCC3V3 - IO_L7P_HDGC_50 -#set_property PACKAGE_PIN F11 [get_ports "HDMI_SI5324_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L6N_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L6N_HDGC_50 -#set_property PACKAGE_PIN F12 [get_ports "34N8121"] ;# Bank 50 VCCO - VCC3V3 - IO_L6P_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "34N8121"] ;# Bank 50 VCCO - VCC3V3 - IO_L6P_HDGC_50 -#set_property PACKAGE_PIN G11 [get_ports "34N8125"] ;# Bank 50 VCCO - VCC3V3 - IO_L5N_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "34N8125"] ;# Bank 50 VCCO - VCC3V3 - IO_L5N_HDGC_50 -#set_property PACKAGE_PIN H11 [get_ports "34N8129"] ;# Bank 50 VCCO - VCC3V3 - IO_L5P_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "34N8129"] ;# Bank 50 VCCO - VCC3V3 - IO_L5P_HDGC_50 -#set_property PACKAGE_PIN D10 [get_ports "34N8133"] ;# Bank 50 VCCO - VCC3V3 - IO_L4N_AD12N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "34N8133"] ;# Bank 50 VCCO - VCC3V3 - IO_L4N_AD12N_50 -#set_property PACKAGE_PIN D11 [get_ports "MSP430_GPIO_PL_0"] ;# Bank 50 VCCO - VCC3V3 - IO_L4P_AD12P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_0"] ;# Bank 50 VCCO - VCC3V3 - IO_L4P_AD12P_50 -#set_property PACKAGE_PIN E10 [get_ports "MSP430_GPIO_PL_1"] ;# Bank 50 VCCO - VCC3V3 - IO_L3N_AD13N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_1"] ;# Bank 50 VCCO - VCC3V3 - IO_L3N_AD13N_50 -#set_property PACKAGE_PIN F10 [get_ports "MSP430_GPIO_PL_2"] ;# Bank 50 VCCO - VCC3V3 - IO_L3P_AD13P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_2"] ;# Bank 50 VCCO - VCC3V3 - IO_L3P_AD13P_50 -#set_property PACKAGE_PIN G10 [get_ports "MSP430_GPIO_PL_3"] ;# Bank 50 VCCO - VCC3V3 - IO_L2N_AD14N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_3"] ;# Bank 50 VCCO - VCC3V3 - IO_L2N_AD14N_50 -#set_property PACKAGE_PIN H10 [get_ports "SFP_SI5328_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L2P_AD14P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP_SI5328_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L2P_AD14P_50 -#set_property PACKAGE_PIN J10 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1N_AD15N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1N_AD15N_50 -#set_property PACKAGE_PIN J11 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1P_AD15P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1P_AD15P_50 -set_property PACKAGE_PIN E13 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 -set_property IOSTANDARD LVCMOS33 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 -set_property PACKAGE_PIN F13 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 -set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 -#set_property PACKAGE_PIN D12 [get_ports "UART2_RTS_O_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "UART2_RTS_O_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 -#set_property PACKAGE_PIN E12 [get_ports "UART2_CTS_I_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "UART2_CTS_I_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 -#set_property PACKAGE_PIN B12 [get_ports "MSP430_UCA1_TXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10N_AD10N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_UCA1_TXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10N_AD10N_49 -#set_property PACKAGE_PIN C12 [get_ports "MSP430_UCA1_RXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10P_AD10P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_UCA1_RXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10P_AD10P_49 -#set_property PACKAGE_PIN A12 [get_ports "SFP0_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9N_AD11N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP0_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9N_AD11N_49 -#set_property PACKAGE_PIN A13 [get_ports "SFP1_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9P_AD11P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP1_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9P_AD11P_49 -#set_property PACKAGE_PIN B13 [get_ports "SFP2_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8N_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP2_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8N_HDGC_49 -#set_property PACKAGE_PIN C13 [get_ports "SFP3_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8P_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP3_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8P_HDGC_49 -#set_property PACKAGE_PIN B14 [get_ports "SYSMON_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L7N_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SYSMON_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L7N_HDGC_49 -#set_property PACKAGE_PIN C14 [get_ports "SYSMON_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L7P_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SYSMON_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L7P_HDGC_49 -#set_property PACKAGE_PIN D14 [get_ports "HDMI_RX_PWR_DET"] ;# Bank 49 VCCO - VCC3V3 - IO_L6N_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_PWR_DET"] ;# Bank 49 VCCO - VCC3V3 - IO_L6N_HDGC_49 -#set_property PACKAGE_PIN E14 [get_ports "HDMI_RX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L6P_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L6P_HDGC_49 -#set_property PACKAGE_PIN D15 [get_ports "HDMI_RX_CEC_SINK"] ;# Bank 49 VCCO - VCC3V3 - IO_L5N_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_CEC_SINK"] ;# Bank 49 VCCO - VCC3V3 - IO_L5N_HDGC_49 -#set_property PACKAGE_PIN E15 [get_ports "HDMI_RX_SNK_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L5P_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_SNK_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L5P_HDGC_49 -#set_property PACKAGE_PIN A15 [get_ports "HDMI_RX_SNK_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L4N_AD12N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_SNK_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L4N_AD12N_49 -#set_property PACKAGE_PIN B15 [get_ports "HDMI_TX_EN"] ;# Bank 49 VCCO - VCC3V3 - IO_L4P_AD12P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_EN"] ;# Bank 49 VCCO - VCC3V3 - IO_L4P_AD12P_49 -#set_property PACKAGE_PIN A16 [get_ports "HDMI_TX_CEC"] ;# Bank 49 VCCO - VCC3V3 - IO_L3N_AD13N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_CEC"] ;# Bank 49 VCCO - VCC3V3 - IO_L3N_AD13N_49 -#set_property PACKAGE_PIN B16 [get_ports "HDMI_TX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L3P_AD13P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L3P_AD13P_49 -#set_property PACKAGE_PIN C16 [get_ports "HDMI_TX_SRC_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L2N_AD14N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_SRC_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L2N_AD14N_49 -#set_property PACKAGE_PIN D16 [get_ports "HDMI_TX_SRC_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L2P_AD14P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_SRC_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L2P_AD14P_49 -#set_property PACKAGE_PIN F15 [get_ports "HDMI_CTL_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L1N_AD15N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_CTL_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L1N_AD15N_49 -#set_property PACKAGE_PIN F16 [get_ports "HDMI_CTL_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L1P_AD15P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_CTL_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L1P_AD15P_49 -#set_property PACKAGE_PIN A18 [get_ports "TRACEDBGRQ"] ;# Bank 48 VCCO - VCC3V3 - IO_L12N_AD8N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDBGRQ"] ;# Bank 48 VCCO - VCC3V3 - IO_L12N_AD8N_48 -#set_property PACKAGE_PIN A17 [get_ports "TRACESRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L12P_AD8P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACESRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L12P_AD8P_48 -#set_property PACKAGE_PIN C19 [get_ports "TRACETDO"] ;# Bank 48 VCCO - VCC3V3 - IO_L11N_AD9N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETDO"] ;# Bank 48 VCCO - VCC3V3 - IO_L11N_AD9N_48 -#set_property PACKAGE_PIN C18 [get_ports "TRACERTCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L11P_AD9P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACERTCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L11P_AD9P_48 -#set_property PACKAGE_PIN B19 [get_ports "TRACETCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L10N_AD10N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L10N_AD10N_48 -#set_property PACKAGE_PIN B18 [get_ports "TRACETMS"] ;# Bank 48 VCCO - VCC3V3 - IO_L10P_AD10P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETMS"] ;# Bank 48 VCCO - VCC3V3 - IO_L10P_AD10P_48 -#set_property PACKAGE_PIN C17 [get_ports "TRACETDI"] ;# Bank 48 VCCO - VCC3V3 - IO_L9N_AD11N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETDI"] ;# Bank 48 VCCO - VCC3V3 - IO_L9N_AD11N_48 -#set_property PACKAGE_PIN D17 [get_ports "TRACETRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L9P_AD11P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L9P_AD11P_48 -#set_property PACKAGE_PIN E18 [get_ports "TRACEDATA15"] ;# Bank 48 VCCO - VCC3V3 - IO_L8N_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA15"] ;# Bank 48 VCCO - VCC3V3 - IO_L8N_HDGC_48 -#set_property PACKAGE_PIN E17 [get_ports "TRACEDATA14"] ;# Bank 48 VCCO - VCC3V3 - IO_L8P_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA14"] ;# Bank 48 VCCO - VCC3V3 - IO_L8P_HDGC_48 -#set_property PACKAGE_PIN D19 [get_ports "TRACEDATA13"] ;# Bank 48 VCCO - VCC3V3 - IO_L7N_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA13"] ;# Bank 48 VCCO - VCC3V3 - IO_L7N_HDGC_48 -#set_property PACKAGE_PIN E19 [get_ports "TRACEDATA12"] ;# Bank 48 VCCO - VCC3V3 - IO_L7P_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA12"] ;# Bank 48 VCCO - VCC3V3 - IO_L7P_HDGC_48 -#set_property PACKAGE_PIN F18 [get_ports "TRACEDATA11"] ;# Bank 48 VCCO - VCC3V3 - IO_L6N_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA11"] ;# Bank 48 VCCO - VCC3V3 - IO_L6N_HDGC_48 -#set_property PACKAGE_PIN F17 [get_ports "TRACEDATA10"] ;# Bank 48 VCCO - VCC3V3 - IO_L6P_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA10"] ;# Bank 48 VCCO - VCC3V3 - IO_L6P_HDGC_48 -#set_property PACKAGE_PIN G19 [get_ports "TRACEDATA9"] ;# Bank 48 VCCO - VCC3V3 - IO_L5N_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA9"] ;# Bank 48 VCCO - VCC3V3 - IO_L5N_HDGC_48 -#set_property PACKAGE_PIN G18 [get_ports "TRACEDATA8"] ;# Bank 48 VCCO - VCC3V3 - IO_L5P_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA8"] ;# Bank 48 VCCO - VCC3V3 - IO_L5P_HDGC_48 -#set_property PACKAGE_PIN K17 [get_ports "TRACECLKA"] ;# Bank 48 VCCO - VCC3V3 - IO_L4N_AD12N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACECLKA"] ;# Bank 48 VCCO - VCC3V3 - IO_L4N_AD12N_48 -#set_property PACKAGE_PIN L17 [get_ports "TRACEDBGACK"] ;# Bank 48 VCCO - VCC3V3 - IO_L4P_AD12P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDBGACK"] ;# Bank 48 VCCO - VCC3V3 - IO_L4P_AD12P_48 -#set_property PACKAGE_PIN K18 [get_ports "TRACEEXTTRIG"] ;# Bank 48 VCCO - VCC3V3 - IO_L3N_AD13N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEEXTTRIG"] ;# Bank 48 VCCO - VCC3V3 - IO_L3N_AD13N_48 -#set_property PACKAGE_PIN L18 [get_ports "TRACEDATA7"] ;# Bank 48 VCCO - VCC3V3 - IO_L3P_AD13P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA7"] ;# Bank 48 VCCO - VCC3V3 - IO_L3P_AD13P_48 -#set_property PACKAGE_PIN H17 [get_ports "TRACEDATA6"] ;# Bank 48 VCCO - VCC3V3 - IO_L2N_AD14N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA6"] ;# Bank 48 VCCO - VCC3V3 - IO_L2N_AD14N_48 -#set_property PACKAGE_PIN J17 [get_ports "TRACEDATA5"] ;# Bank 48 VCCO - VCC3V3 - IO_L2P_AD14P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA5"] ;# Bank 48 VCCO - VCC3V3 - IO_L2P_AD14P_48 -#set_property PACKAGE_PIN H19 [get_ports "TRACEDATA4"] ;# Bank 48 VCCO - VCC3V3 - IO_L1N_AD15N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA4"] ;# Bank 48 VCCO - VCC3V3 - IO_L1N_AD15N_48 -#set_property PACKAGE_PIN H18 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 -#set_property PACKAGE_PIN A20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 -#set_property PACKAGE_PIN B20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 -#set_property PACKAGE_PIN A22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 -#set_property PACKAGE_PIN A21 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 -#set_property PACKAGE_PIN B21 [get_ports "PMOD0_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 -#set_property PACKAGE_PIN C21 [get_ports "PMOD0_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 -#set_property PACKAGE_PIN C22 [get_ports "PMOD0_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 -#set_property PACKAGE_PIN D21 [get_ports "PMOD0_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 -set_property PACKAGE_PIN D20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 -set_property PACKAGE_PIN E20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 -set_property PACKAGE_PIN D22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 -set_property PACKAGE_PIN E22 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 -#set_property PACKAGE_PIN F20 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 -#set_property PACKAGE_PIN G20 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 -#set_property PACKAGE_PIN F21 [get_ports "CLK_125_N"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_125_N"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -#set_property PACKAGE_PIN G21 [get_ports "CLK_125_P"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_125_P"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -#set_property PACKAGE_PIN J20 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 -#set_property PACKAGE_PIN J19 [get_ports "PMOD1_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L4P_AD8P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L4P_AD8P_47 -#set_property PACKAGE_PIN H21 [get_ports "TRACEDATA2"] ;# Bank 47 VCCO - VCC3V3 - IO_L3N_AD9N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA2"] ;# Bank 47 VCCO - VCC3V3 - IO_L3N_AD9N_47 -#set_property PACKAGE_PIN J21 [get_ports "TRACEDATA1"] ;# Bank 47 VCCO - VCC3V3 - IO_L3P_AD9P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA1"] ;# Bank 47 VCCO - VCC3V3 - IO_L3P_AD9P_47 -#set_property PACKAGE_PIN K19 [get_ports "TRACECTL"] ;# Bank 47 VCCO - VCC3V3 - IO_L2N_AD10N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACECTL"] ;# Bank 47 VCCO - VCC3V3 - IO_L2N_AD10N_47 -#set_property PACKAGE_PIN L19 [get_ports "TRACEDATA0"] ;# Bank 47 VCCO - VCC3V3 - IO_L2P_AD10P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA0"] ;# Bank 47 VCCO - VCC3V3 - IO_L2P_AD10P_47 -#set_property PACKAGE_PIN K20 [get_ports "PL_I2C1_SCL_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1N_AD11N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C1_SCL_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1N_AD11N_47 -#set_property PACKAGE_PIN L20 [get_ports "PL_I2C1_SDA_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1P_AD11P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C1_SDA_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1P_AD11P_47 -#set_property PACKAGE_PIN AE14 [get_ports "GPIO_SW_E"] ;# Bank 44 VCCO - VCC3V3 - IO_L12N_AD0N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_E"] ;# Bank 44 VCCO - VCC3V3 - IO_L12N_AD0N_44 -#set_property PACKAGE_PIN AE15 [get_ports "GPIO_SW_S"] ;# Bank 44 VCCO - VCC3V3 - IO_L12P_AD0P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_S"] ;# Bank 44 VCCO - VCC3V3 - IO_L12P_AD0P_44 -#set_property PACKAGE_PIN AG15 [get_ports "GPIO_SW_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L11N_AD1N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L11N_AD1N_44 -#set_property PACKAGE_PIN AF15 [get_ports "GPIO_SW_W"] ;# Bank 44 VCCO - VCC3V3 - IO_L11P_AD1P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_W"] ;# Bank 44 VCCO - VCC3V3 - IO_L11P_AD1P_44 -#set_property PACKAGE_PIN AG13 [get_ports "GPIO_SW_C"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_C"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 -#set_property PACKAGE_PIN AG14 [get_ports "GPIO_LED_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 -#set_property PACKAGE_PIN AF13 [get_ports "GPIO_LED_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 -#set_property PACKAGE_PIN AE13 [get_ports "GPIO_LED_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 -#set_property PACKAGE_PIN AJ14 [get_ports "GPIO_LED_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 -#set_property PACKAGE_PIN AJ15 [get_ports "GPIO_LED_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 -#set_property PACKAGE_PIN AH13 [get_ports "GPIO_LED_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44 -#set_property PACKAGE_PIN AH14 [get_ports "GPIO_LED_6"] ;# Bank 44 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_6"] ;# Bank 44 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_44 -#set_property PACKAGE_PIN AL12 [get_ports "GPIO_LED_7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_44 -#set_property PACKAGE_PIN AK13 [get_ports "GPIO_DIP_SW7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_44 -#set_property PACKAGE_PIN AK14 [get_ports "CLK_74_25_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_44 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_74_25_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_44 -#set_property PACKAGE_PIN AK15 [get_ports "CLK_74_25_P"] ;# Bank 44 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_44 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_74_25_P"] ;# Bank 44 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_44 -set_property PACKAGE_PIN AM13 [get_ports "cpu_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L4N_AD8N_44 -set_property IOSTANDARD LVCMOS33 [get_ports "cpu_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L4N_AD8N_44 -#set_property PACKAGE_PIN AL13 [get_ports "GPIO_DIP_SW6"] ;# Bank 44 VCCO - VCC3V3 - IO_L4P_AD8P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW6"] ;# Bank 44 VCCO - VCC3V3 - IO_L4P_AD8P_44 -#set_property PACKAGE_PIN AP12 [get_ports "GPIO_DIP_SW5"] ;# Bank 44 VCCO - VCC3V3 - IO_L3N_AD9N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW5"] ;# Bank 44 VCCO - VCC3V3 - IO_L3N_AD9N_44 -#set_property PACKAGE_PIN AN12 [get_ports "GPIO_DIP_SW4"] ;# Bank 44 VCCO - VCC3V3 - IO_L3P_AD9P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW4"] ;# Bank 44 VCCO - VCC3V3 - IO_L3P_AD9P_44 -#set_property PACKAGE_PIN AN13 [get_ports "GPIO_DIP_SW3"] ;# Bank 44 VCCO - VCC3V3 - IO_L2N_AD10N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW3"] ;# Bank 44 VCCO - VCC3V3 - IO_L2N_AD10N_44 -#set_property PACKAGE_PIN AM14 [get_ports "GPIO_DIP_SW2"] ;# Bank 44 VCCO - VCC3V3 - IO_L2P_AD10P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW2"] ;# Bank 44 VCCO - VCC3V3 - IO_L2P_AD10P_44 -#set_property PACKAGE_PIN AP14 [get_ports "GPIO_DIP_SW1"] ;# Bank 44 VCCO - VCC3V3 - IO_L1N_AD11N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW1"] ;# Bank 44 VCCO - VCC3V3 - IO_L1N_AD11N_44 -#set_property PACKAGE_PIN AN14 [get_ports "GPIO_DIP_SW0"] ;# Bank 44 VCCO - VCC3V3 - IO_L1P_AD11P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW0"] ;# Bank 44 VCCO - VCC3V3 - IO_L1P_AD11P_44 -#set_property PACKAGE_PIN K15 [get_ports "FMC_HPC0_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24N_T3U_N11_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24N_T3U_N11_67 -#set_property PACKAGE_PIN L15 [get_ports "FMC_HPC0_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24P_T3U_N10_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24P_T3U_N10_67 -#set_property PACKAGE_PIN K13 [get_ports "FMC_HPC0_LA19_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23N_T3U_N9_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA19_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23N_T3U_N9_67 -#set_property PACKAGE_PIN L13 [get_ports "FMC_HPC0_LA19_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23P_T3U_N8_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA19_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23P_T3U_N8_67 -set_property PACKAGE_PIN M13 [get_ports "pad_hyper_dq[0][7]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_67 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][7]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_67 -set_property PACKAGE_PIN N13 [get_ports "pad_hyper_dq[0][6]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_67 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][6]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_67 -#set_property PACKAGE_PIN N12 [get_ports "FMC_HPC0_LA21_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA21_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_67 -#set_property PACKAGE_PIN P12 [get_ports "FMC_HPC0_LA21_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA21_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_67 -set_property PACKAGE_PIN M14 [get_ports "pad_hyper_csn[0][0]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_67 # J20 - 9 = gray -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0][0]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_67 -#set_property PACKAGE_PIN M15 [get_ports "FMC_HPC0_LA22_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA22_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_67 -#set_property PACKAGE_PIN K16 [get_ports "FMC_HPC0_LA23_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA23_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_67 -#set_property PACKAGE_PIN L16 [get_ports "FMC_HPC0_LA23_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA23_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_67 -#set_property PACKAGE_PIN K14 [get_ports "7N8557"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8557"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67 -#set_property PACKAGE_PIN K10 [get_ports "7N8560"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8560"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67 -#set_property PACKAGE_PIN K12 [get_ports "FMC_HPC0_LA24_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA24_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67 -#set_property PACKAGE_PIN L12 [get_ports "FMC_HPC0_LA24_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA24_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_67 -#set_property PACKAGE_PIN L11 [get_ports "FMC_HPC0_LA25_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA25_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_67 -set_property PACKAGE_PIN M11 [get_ports "pad_hyper_reset[0]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_67 # J20 - 6 = violet -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_reset[0]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_67 -#set_property PACKAGE_PIN N8 [get_ports "FMC_HPC0_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_67 -#set_property PACKAGE_PIN N9 [get_ports "FMC_HPC0_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_67 -#set_property PACKAGE_PIN L10 [get_ports "FMC_HPC0_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_67 -#set_property PACKAGE_PIN M10 [get_ports "FMC_HPC0_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_67 -#set_property PACKAGE_PIN P9 [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_67 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_67 -#set_property PACKAGE_PIN P10 [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_67 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_67 -#set_property PACKAGE_PIN N11 [get_ports "FMC_HPC0_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_67 -#set_property PACKAGE_PIN P11 [get_ports "FMC_HPC0_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_67 -#set_property PACKAGE_PIN R8 [get_ports "FMC_HPC0_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_67 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_67 -#set_property PACKAGE_PIN T8 [get_ports "FMC_HPC0_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_67 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_67 -#set_property PACKAGE_PIN R9 [get_ports "SFP_REC_CLOCK_C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67 -#set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67 -#set_property PACKAGE_PIN R10 [get_ports "SFP_REC_CLOCK_C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67 -#set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67 -#set_property PACKAGE_PIN T6 [get_ports "FMC_HPC0_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67 -#set_property PACKAGE_PIN T7 [get_ports "FMC_HPC0_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67 -#set_property PACKAGE_PIN U8 [get_ports "FMC_HPC0_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_67 -#set_property PACKAGE_PIN U9 [get_ports "FMC_HPC0_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_67 -#set_property PACKAGE_PIN U6 [get_ports "FMC_HPC0_LA30_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA30_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_67 -#set_property PACKAGE_PIN V6 [get_ports "FMC_HPC0_LA30_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA30_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_67 -#set_property PACKAGE_PIN V7 [get_ports "FMC_HPC0_LA31_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA31_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_67 -#set_property PACKAGE_PIN V8 [get_ports "FMC_HPC0_LA31_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA31_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_67 -#set_property PACKAGE_PIN V9 [get_ports "7N8563"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8563"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67 -#set_property PACKAGE_PIN W10 [get_ports "7N8566"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8566"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67 -#set_property PACKAGE_PIN T11 [get_ports "FMC_HPC0_LA32_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA32_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67 -#set_property PACKAGE_PIN U11 [get_ports "FMC_HPC0_LA32_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA32_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_67 -#set_property PACKAGE_PIN V11 [get_ports "FMC_HPC0_LA33_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA33_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_67 -#set_property PACKAGE_PIN V12 [get_ports "FMC_HPC0_LA33_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA33_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_67 -#set_property PACKAGE_PIN R12 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67 -#set_property PACKAGE_PIN T12 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67 -#set_property PACKAGE_PIN T10 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67 -#set_property PACKAGE_PIN U10 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67 -#set_property PACKAGE_PIN R13 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67 -#set_property PACKAGE_PIN T13 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67 -#set_property PACKAGE_PIN W11 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67 -#set_property PACKAGE_PIN W12 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67 -#Other net PACKAGE_PIN N14 - 7N8332 Bank 67 - VREF_67 -set_property PACKAGE_PIN W1 [get_ports "pad_hyper_dq[0][3]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24N_T3U_N11_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][3]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24N_T3U_N11_66 -set_property PACKAGE_PIN W2 [get_ports "pad_hyper_dq[0][2]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24P_T3U_N10_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][2]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24P_T3U_N10_66 -#set_property PACKAGE_PIN V1 [get_ports "FMC_HPC0_LA02_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23N_T3U_N9_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA02_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23N_T3U_N9_66 -set_property PACKAGE_PIN V2 [get_ports "pad_hyper_csn[0][1]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23P_T3U_N8_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0][1]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23P_T3U_N8_66 -#set_property PACKAGE_PIN Y1 [get_ports "FMC_HPC0_LA03_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA03_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_66 -#set_property PACKAGE_PIN Y2 [get_ports "FMC_HPC0_LA03_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA03_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_66 -#set_property PACKAGE_PIN AA1 [get_ports "FMC_HPC0_LA04_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA04_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_66 -#set_property PACKAGE_PIN AA2 [get_ports "FMC_HPC0_LA04_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA04_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_66 -set_property PACKAGE_PIN AC3 [get_ports "pad_hyper_dq[0][1]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][1]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_66 -set_property PACKAGE_PIN AB3 [get_ports "pad_hyper_dq[0][0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_66 -#set_property PACKAGE_PIN AC1 [get_ports "FMC_HPC0_LA06_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA06_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_66 -#set_property PACKAGE_PIN AC2 [get_ports "FMC_HPC0_LA06_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA06_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_66 -#set_property PACKAGE_PIN AB1 [get_ports "7N8545"] ;# Bank 66 VCCO - VADJ_FMC - IO_T3U_N12_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8545"] ;# Bank 66 VCCO - VADJ_FMC - IO_T3U_N12_66 -#set_property PACKAGE_PIN AA3 [get_ports "7N8548"] ;# Bank 66 VCCO - VADJ_FMC - IO_T2U_N12_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8548"] ;# Bank 66 VCCO - VADJ_FMC - IO_T2U_N12_66 -#set_property PACKAGE_PIN U4 [get_ports "FMC_HPC0_LA07_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA07_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_66 -#set_property PACKAGE_PIN U5 [get_ports "FMC_HPC0_LA07_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA07_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_66 -#set_property PACKAGE_PIN V3 [get_ports "FMC_HPC0_LA08_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA08_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_66 -#set_property PACKAGE_PIN V4 [get_ports "FMC_HPC0_LA08_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA08_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_66 -set_property PACKAGE_PIN AC4 [get_ports "pad_hyper_ckn[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_66 -set_property PACKAGE_PIN AB4 [get_ports "pad_hyper_ck[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_66 -#set_property PACKAGE_PIN W4 [get_ports "FMC_HPC0_LA10_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA10_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_66 -#set_property PACKAGE_PIN W5 [get_ports "FMC_HPC0_LA10_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA10_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_66 -#set_property PACKAGE_PIN AA5 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_66 -#set_property PACKAGE_PIN Y5 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_66 -#set_property PACKAGE_PIN Y3 [get_ports "FMC_HPC0_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_66 -#set_property PACKAGE_PIN Y4 [get_ports "FMC_HPC0_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_66 -#set_property PACKAGE_PIN AA6 [get_ports "FMC_HPC0_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_66 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_66 -#set_property PACKAGE_PIN AA7 [get_ports "FMC_HPC0_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_66 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_66 -#set_property PACKAGE_PIN Y7 [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_66 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_66 -#set_property PACKAGE_PIN Y8 [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_66 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_66 -#set_property PACKAGE_PIN AB5 [get_ports "FMC_HPC0_LA11_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA11_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_66 -#set_property PACKAGE_PIN AB6 [get_ports "FMC_HPC0_LA11_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA11_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_66 -#set_property PACKAGE_PIN W6 [get_ports "FMC_HPC0_LA12_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA12_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_66 -#set_property PACKAGE_PIN W7 [get_ports "FMC_HPC0_LA12_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA12_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_66 -#set_property PACKAGE_PIN AC8 [get_ports "FMC_HPC0_LA13_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA13_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_66 -set_property PACKAGE_PIN AB8 [get_ports "pad_hyper_rwds[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_66 -#set_property PACKAGE_PIN AC6 [get_ports "FMC_HPC0_LA14_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA14_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_66 -#set_property PACKAGE_PIN AC7 [get_ports "FMC_HPC0_LA14_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA14_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_66 -#set_property PACKAGE_PIN AA8 [get_ports "7N8551"] ;# Bank 66 VCCO - VADJ_FMC - IO_T1U_N12_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8551"] ;# Bank 66 VCCO - VADJ_FMC - IO_T1U_N12_66 -#set_property PACKAGE_PIN W9 [get_ports "7N8554"] ;# Bank 66 VCCO - VADJ_FMC - IO_T0U_N12_VRP_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8554"] ;# Bank 66 VCCO - VADJ_FMC - IO_T0U_N12_VRP_66 -#set_property PACKAGE_PIN Y9 [get_ports "FMC_HPC0_LA15_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA15_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_66 -#set_property PACKAGE_PIN Y10 [get_ports "FMC_HPC0_LA15_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA15_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_66 -set_property PACKAGE_PIN AA12 [get_ports "pad_hyper_dq[0][5]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][5]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_66 -set_property PACKAGE_PIN Y12 [get_ports "pad_hyper_dq[0][4]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][4]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_66 -#set_property PACKAGE_PIN AC9 [get_ports "7N8645"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "7N8645"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_66 -#set_property PACKAGE_PIN AB9 [get_ports "7N8643"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "7N8643"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_66 -#set_property PACKAGE_PIN AA10 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_66 -#set_property PACKAGE_PIN AA11 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_66 -#set_property PACKAGE_PIN AB10 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2N_T0L_N3_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2N_T0L_N3_66 -#set_property PACKAGE_PIN AB11 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2P_T0L_N2_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2P_T0L_N2_66 -#set_property PACKAGE_PIN AC11 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_66 -#set_property PACKAGE_PIN AC12 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_66 -#Other net PACKAGE_PIN AD12 - 7N8282 Bank 66 - VREF_66 -#set_property PACKAGE_PIN AE1 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24N_T3U_N11_PERSTN0_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24N_T3U_N11_PERSTN0_65 -#set_property PACKAGE_PIN AE2 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 -#set_property PACKAGE_PIN AD1 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23N_T3U_N9_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23N_T3U_N9_65 -#set_property PACKAGE_PIN AD2 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23P_T3U_N8_I2C_SCLK_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23P_T3U_N8_I2C_SCLK_65 -#set_property PACKAGE_PIN AJ1 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_65 -#set_property PACKAGE_PIN AH1 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_65 -#set_property PACKAGE_PIN AF1 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_65 -#set_property PACKAGE_PIN AF2 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 -#set_property PACKAGE_PIN AH3 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_65 -#set_property PACKAGE_PIN AG3 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_65 -#set_property PACKAGE_PIN AJ2 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_65 -#set_property PACKAGE_PIN AH2 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_65 -#set_property PACKAGE_PIN AG1 [get_ports "6N9904"] ;# Bank 65 VCCO - VADJ_FMC - IO_T3U_N12_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "6N9904"] ;# Bank 65 VCCO - VADJ_FMC - IO_T3U_N12_65 -#set_property PACKAGE_PIN AD5 [get_ports "6N9901"] ;# Bank 65 VCCO - VADJ_FMC - IO_T2U_N12_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "6N9901"] ;# Bank 65 VCCO - VADJ_FMC - IO_T2U_N12_65 -#set_property PACKAGE_PIN AE4 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_65 -#set_property PACKAGE_PIN AD4 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_65 -#set_property PACKAGE_PIN AF3 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_65 -#set_property PACKAGE_PIN AE3 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_65 -#set_property PACKAGE_PIN AJ5 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_65 -#set_property PACKAGE_PIN AJ6 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_65 -#set_property PACKAGE_PIN AJ4 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_65 -#set_property PACKAGE_PIN AH4 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_65 -#set_property PACKAGE_PIN AG4 [get_ports "HDMI_REC_CLOCK_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "HDMI_REC_CLOCK_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 -#set_property PACKAGE_PIN AG5 [get_ports "HDMI_REC_CLOCK_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "HDMI_REC_CLOCK_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 -#set_property PACKAGE_PIN AF5 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_65 -#set_property PACKAGE_PIN AE5 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 -#set_property PACKAGE_PIN AF7 [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_65 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_65 -#set_property PACKAGE_PIN AE7 [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_65 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_65 -#set_property PACKAGE_PIN AG6 [get_ports "HDMI_TX_LVDS_OUT_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_65 -#set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_65 -#set_property PACKAGE_PIN AF6 [get_ports "HDMI_TX_LVDS_OUT_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_65 -#set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_65 -#set_property PACKAGE_PIN AF8 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_65 -#set_property PACKAGE_PIN AE8 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_65 -#set_property PACKAGE_PIN AD6 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_65 -#set_property PACKAGE_PIN AD7 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_65 -#set_property PACKAGE_PIN AH8 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_65 -#set_property PACKAGE_PIN AG8 [get_ports "pad_hyper_rwds[0]"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_65 -#set_property PACKAGE_PIN AH6 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_65 -#set_property PACKAGE_PIN AH7 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_65 -#set_property PACKAGE_PIN AH9 [get_ports "DDR4_RESET_B_LS"] ;# Bank 65 VCCO - VADJ_FMC - IO_T1U_N12_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "DDR4_RESET_B_LS"] ;# Bank 65 VCCO - VADJ_FMC - IO_T1U_N12_65 -#set_property PACKAGE_PIN AD9 [get_ports "VRP_65"] ;# Bank 65 VCCO - VADJ_FMC - IO_T0U_N12_VRP_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VADJ_FMC - IO_T0U_N12_VRP_65 -#set_property PACKAGE_PIN AE9 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_65 -#set_property PACKAGE_PIN AD10 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_65 -#set_property PACKAGE_PIN AG9 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_65 -#set_property PACKAGE_PIN AG10 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_65 -#set_property PACKAGE_PIN AG11 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_65 -#set_property PACKAGE_PIN AF11 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 -#set_property PACKAGE_PIN AF12 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_65 -#set_property PACKAGE_PIN AE12 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_65 -#set_property PACKAGE_PIN AH11 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2N_T0L_N3_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2N_T0L_N3_65 -#set_property PACKAGE_PIN AH12 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2P_T0L_N2_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2P_T0L_N2_65 -#set_property PACKAGE_PIN AF10 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_65 -#set_property PACKAGE_PIN AE10 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_65 -#Other net PACKAGE_PIN AD11 - 6N9689 Bank 65 - VREF_65 -#set_property PACKAGE_PIN AK2 [get_ports "DDR4_DQ8"] ;# Bank 64 VCCO - VCC1V2 - IO_L24N_T3U_N11_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ8"] ;# Bank 64 VCCO - VCC1V2 - IO_L24N_T3U_N11_64 -#set_property PACKAGE_PIN AK3 [get_ports "DDR4_DQ9"] ;# Bank 64 VCCO - VCC1V2 - IO_L24P_T3U_N10_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ9"] ;# Bank 64 VCCO - VCC1V2 - IO_L24P_T3U_N10_64 -#set_property PACKAGE_PIN AL1 [get_ports "DDR4_DQ10"] ;# Bank 64 VCCO - VCC1V2 - IO_L23N_T3U_N9_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ10"] ;# Bank 64 VCCO - VCC1V2 - IO_L23N_T3U_N9_64 -#set_property PACKAGE_PIN AK1 [get_ports "DDR4_DQ11"] ;# Bank 64 VCCO - VCC1V2 - IO_L23P_T3U_N8_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ11"] ;# Bank 64 VCCO - VCC1V2 - IO_L23P_T3U_N8_64 -#set_property PACKAGE_PIN AL2 [get_ports "DDR4_DQS1_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 -#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 -#set_property PACKAGE_PIN AL3 [get_ports "DDR4_DQS1_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 -#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 -#set_property PACKAGE_PIN AN1 [get_ports "DDR4_DQ12"] ;# Bank 64 VCCO - VCC1V2 - IO_L21N_T3L_N5_AD8N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ12"] ;# Bank 64 VCCO - VCC1V2 - IO_L21N_T3L_N5_AD8N_64 -#set_property PACKAGE_PIN AM1 [get_ports "DDR4_DQ13"] ;# Bank 64 VCCO - VCC1V2 - IO_L21P_T3L_N4_AD8P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ13"] ;# Bank 64 VCCO - VCC1V2 - IO_L21P_T3L_N4_AD8P_64 -#set_property PACKAGE_PIN AP3 [get_ports "DDR4_DQ14"] ;# Bank 64 VCCO - VCC1V2 - IO_L20N_T3L_N3_AD1N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ14"] ;# Bank 64 VCCO - VCC1V2 - IO_L20N_T3L_N3_AD1N_64 -#set_property PACKAGE_PIN AN3 [get_ports "DDR4_DQ15"] ;# Bank 64 VCCO - VCC1V2 - IO_L20P_T3L_N2_AD1P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ15"] ;# Bank 64 VCCO - VCC1V2 - IO_L20P_T3L_N2_AD1P_64 -#set_property PACKAGE_PIN AP2 [get_ports "DDR4_CS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 -#set_property PACKAGE_PIN AN2 [get_ports "DDR4_DM1"] ;# Bank 64 VCCO - VCC1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM1"] ;# Bank 64 VCCO - VCC1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 -#set_property PACKAGE_PIN AP1 [get_ports "DDR4_PAR"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_PAR"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64 -#set_property PACKAGE_PIN AM3 [get_ports "DDR4_CKE"] ;# Bank 64 VCCO - VCC1V2 - IO_T2U_N12_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CKE"] ;# Bank 64 VCCO - VCC1V2 - IO_T2U_N12_64 -#set_property PACKAGE_PIN AK4 [get_ports "DDR4_DQ0"] ;# Bank 64 VCCO - VCC1V2 - IO_L18N_T2U_N11_AD2N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ0"] ;# Bank 64 VCCO - VCC1V2 - IO_L18N_T2U_N11_AD2N_64 -#set_property PACKAGE_PIN AK5 [get_ports "DDR4_DQ1"] ;# Bank 64 VCCO - VCC1V2 - IO_L18P_T2U_N10_AD2P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ1"] ;# Bank 64 VCCO - VCC1V2 - IO_L18P_T2U_N10_AD2P_64 -#set_property PACKAGE_PIN AN4 [get_ports "DDR4_DQ2"] ;# Bank 64 VCCO - VCC1V2 - IO_L17N_T2U_N9_AD10N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ2"] ;# Bank 64 VCCO - VCC1V2 - IO_L17N_T2U_N9_AD10N_64 -#set_property PACKAGE_PIN AM4 [get_ports "DDR4_DQ3"] ;# Bank 64 VCCO - VCC1V2 - IO_L17P_T2U_N8_AD10P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ3"] ;# Bank 64 VCCO - VCC1V2 - IO_L17P_T2U_N8_AD10P_64 -#set_property PACKAGE_PIN AP6 [get_ports "DDR4_DQS0_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 -#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 -#set_property PACKAGE_PIN AN6 [get_ports "DDR4_DQS0_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 -#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 -#set_property PACKAGE_PIN AP4 [get_ports "DDR4_DQ4"] ;# Bank 64 VCCO - VCC1V2 - IO_L15N_T2L_N5_AD11N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ4"] ;# Bank 64 VCCO - VCC1V2 - IO_L15N_T2L_N5_AD11N_64 -#set_property PACKAGE_PIN AP5 [get_ports "DDR4_DQ5"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ5"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64 -#set_property PACKAGE_PIN AM5 [get_ports "DDR4_DQ6"] ;# Bank 64 VCCO - VCC1V2 - IO_L14N_T2L_N3_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ6"] ;# Bank 64 VCCO - VCC1V2 - IO_L14N_T2L_N3_GC_64 -#set_property PACKAGE_PIN AM6 [get_ports "DDR4_DQ7"] ;# Bank 64 VCCO - VCC1V2 - IO_L14P_T2L_N2_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ7"] ;# Bank 64 VCCO - VCC1V2 - IO_L14P_T2L_N2_GC_64 -#set_property PACKAGE_PIN AL5 [get_ports "DDR4_A15_CAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A15_CAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_64 -#set_property PACKAGE_PIN AL6 [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 -#set_property PACKAGE_PIN AL7 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 -#set_property PACKAGE_PIN AL8 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 -#set_property PACKAGE_PIN AK7 [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 -#set_property PACKAGE_PIN AK8 [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 -#set_property PACKAGE_PIN AP7 [get_ports "DDR4_CK_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 -#set_property PACKAGE_PIN AN7 [get_ports "DDR4_CK_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 -#set_property PACKAGE_PIN AK9 [get_ports "DDR4_ODT"] ;# Bank 64 VCCO - VCC1V2 - IO_L9N_T1L_N5_AD12N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ODT"] ;# Bank 64 VCCO - VCC1V2 - IO_L9N_T1L_N5_AD12N_64 -#set_property PACKAGE_PIN AJ9 [get_ports "DDR4_A16_RAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L9P_T1L_N4_AD12P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A16_RAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L9P_T1L_N4_AD12P_64 -#set_property PACKAGE_PIN AM8 [get_ports "DDR4_A0"] ;# Bank 64 VCCO - VCC1V2 - IO_L8N_T1L_N3_AD5N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A0"] ;# Bank 64 VCCO - VCC1V2 - IO_L8N_T1L_N3_AD5N_64 -#set_property PACKAGE_PIN AM9 [get_ports "DDR4_A1"] ;# Bank 64 VCCO - VCC1V2 - IO_L8P_T1L_N2_AD5P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A1"] ;# Bank 64 VCCO - VCC1V2 - IO_L8P_T1L_N2_AD5P_64 -#set_property PACKAGE_PIN AP8 [get_ports "DDR4_A2"] ;# Bank 64 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A2"] ;# Bank 64 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 -#set_property PACKAGE_PIN AN8 [get_ports "DDR4_A3"] ;# Bank 64 VCCO - VCC1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A3"] ;# Bank 64 VCCO - VCC1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 -#set_property PACKAGE_PIN AJ7 [get_ports "DDR4_A14_WE_B"] ;# Bank 64 VCCO - VCC1V2 - IO_T1U_N12_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A14_WE_B"] ;# Bank 64 VCCO - VCC1V2 - IO_T1U_N12_64 -#set_property PACKAGE_PIN AN11 [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64 -#set_property IOSTANDARD [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64 -#set_property PACKAGE_PIN AK10 [get_ports "DDR4_A4"] ;# Bank 64 VCCO - VCC1V2 - IO_L6N_T0U_N11_AD6N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A4"] ;# Bank 64 VCCO - VCC1V2 - IO_L6N_T0U_N11_AD6N_64 -#set_property PACKAGE_PIN AJ10 [get_ports "DDR4_A5"] ;# Bank 64 VCCO - VCC1V2 - IO_L6P_T0U_N10_AD6P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A5"] ;# Bank 64 VCCO - VCC1V2 - IO_L6P_T0U_N10_AD6P_64 -#set_property PACKAGE_PIN AP9 [get_ports "DDR4_A6"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A6"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64 -#set_property PACKAGE_PIN AN9 [get_ports "DDR4_A7"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A7"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64 -#set_property PACKAGE_PIN AP10 [get_ports "DDR4_A8"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A8"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 -#set_property PACKAGE_PIN AP11 [get_ports "DDR4_A9"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A9"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 -#set_property PACKAGE_PIN AM10 [get_ports "DDR4_A10"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A10"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64 -#set_property PACKAGE_PIN AL10 [get_ports "DDR4_A11"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A11"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64 -#set_property PACKAGE_PIN AM11 [get_ports "DDR4_A12"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A12"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64 -#set_property PACKAGE_PIN AL11 [get_ports "DDR4_A13"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A13"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64 -#set_property PACKAGE_PIN AK12 [get_ports "DDR4_BA0"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA0"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64 -#set_property PACKAGE_PIN AJ12 [get_ports "DDR4_BA1"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA1"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64 -#Other net PACKAGE_PIN AJ11 - 6N6772 Bank 64 - VREF_64 -#set_property PACKAGE_PIN T34 [get_ports "HDMI_RX0_C_N"] ;# Bank 128 - MGTHRXN0_128 -#set_property PACKAGE_PIN P34 [get_ports "HDMI_RX1_C_N"] ;# Bank 128 - MGTHRXN1_128 -#set_property PACKAGE_PIN N32 [get_ports "HDMI_RX2_C_N"] ;# Bank 128 - MGTHRXN2_128 -#set_property PACKAGE_PIN M34 [get_ports "SMA_MGT_RX_C_N"] ;# Bank 128 - MGTHRXN3_128 -#set_property PACKAGE_PIN T33 [get_ports "HDMI_RX0_C_P"] ;# Bank 128 - MGTHRXP0_128 -#set_property PACKAGE_PIN P33 [get_ports "HDMI_RX1_C_P"] ;# Bank 128 - MGTHRXP1_128 -#set_property PACKAGE_PIN N31 [get_ports "HDMI_RX2_C_P"] ;# Bank 128 - MGTHRXP2_128 -#set_property PACKAGE_PIN M33 [get_ports "SMA_MGT_RX_C_P"] ;# Bank 128 - MGTHRXP3_128 -#set_property PACKAGE_PIN T30 [get_ports "HDMI_TX0_N"] ;# Bank 128 - MGTHTXN0_128 -#set_property PACKAGE_PIN R32 [get_ports "HDMI_TX1_N"] ;# Bank 128 - MGTHTXN1_128 -#set_property PACKAGE_PIN P30 [get_ports "HDMI_TX2_N"] ;# Bank 128 - MGTHTXN2_128 -#set_property PACKAGE_PIN M30 [get_ports "SMA_MGT_TX_N"] ;# Bank 128 - MGTHTXN3_128 -#set_property PACKAGE_PIN T29 [get_ports "HDMI_TX0_P"] ;# Bank 128 - MGTHTXP0_128 -#set_property PACKAGE_PIN R31 [get_ports "HDMI_TX1_P"] ;# Bank 128 - MGTHTXP1_128 -#set_property PACKAGE_PIN P29 [get_ports "HDMI_TX2_P"] ;# Bank 128 - MGTHTXP2_128 -#set_property PACKAGE_PIN M29 [get_ports "SMA_MGT_TX_P"] ;# Bank 128 - MGTHTXP3_128 -#set_property PACKAGE_PIN N28 [get_ports "HDMI_RX_CLK_C_N"] ;# Bank 128 - MGTREFCLK1N_128 -#set_property PACKAGE_PIN N27 [get_ports "HDMI_RX_CLK_C_P"] ;# Bank 128 - MGTREFCLK1P_128 -#set_property PACKAGE_PIN R28 [get_ports "HDMI_SI5324_OUT_C_N"] ;# Bank 128 - MGTREFCLK0N_128 -#set_property PACKAGE_PIN R27 [get_ports "HDMI_SI5324_OUT_C_P"] ;# Bank 128 - MGTREFCLK0P_128 -#set_property PACKAGE_PIN A29 [get_ports "MGTRREF_128"] ;# Bank 128 - MGTRREF_L -#Other net PACKAGE_PIN A30 - MGTAVTT Bank 128 - MGTAVTTRCAL_L -#set_property PACKAGE_PIN L32 [get_ports "FMC_HPC1_DP4_M2C_N"] ;# Bank 129 - MGTHRXN0_129 -#set_property PACKAGE_PIN K34 [get_ports "FMC_HPC1_DP5_M2C_N"] ;# Bank 129 - MGTHRXN1_129 -#set_property PACKAGE_PIN H34 [get_ports "FMC_HPC1_DP6_M2C_N"] ;# Bank 129 - MGTHRXN2_129 -#set_property PACKAGE_PIN F34 [get_ports "FMC_HPC1_DP7_M2C_N"] ;# Bank 129 - MGTHRXN3_129 -#set_property PACKAGE_PIN L31 [get_ports "FMC_HPC1_DP4_M2C_P"] ;# Bank 129 - MGTHRXP0_129 -#set_property PACKAGE_PIN K33 [get_ports "FMC_HPC1_DP5_M2C_P"] ;# Bank 129 - MGTHRXP1_129 -#set_property PACKAGE_PIN H33 [get_ports "FMC_HPC1_DP6_M2C_P"] ;# Bank 129 - MGTHRXP2_129 -#set_property PACKAGE_PIN F33 [get_ports "FMC_HPC1_DP7_M2C_P"] ;# Bank 129 - MGTHRXP3_129 -#set_property PACKAGE_PIN K30 [get_ports "FMC_HPC1_DP4_C2M_N"] ;# Bank 129 - MGTHTXN0_129 -#set_property PACKAGE_PIN J32 [get_ports "FMC_HPC1_DP5_C2M_N"] ;# Bank 129 - MGTHTXN1_129 -#set_property PACKAGE_PIN H30 [get_ports "FMC_HPC1_DP6_C2M_N"] ;# Bank 129 - MGTHTXN2_129 -#set_property PACKAGE_PIN G32 [get_ports "FMC_HPC1_DP7_C2M_N"] ;# Bank 129 - MGTHTXN3_129 -#set_property PACKAGE_PIN K29 [get_ports "FMC_HPC1_DP4_C2M_P"] ;# Bank 129 - MGTHTXP0_129 -#set_property PACKAGE_PIN J31 [get_ports "FMC_HPC1_DP5_C2M_P"] ;# Bank 129 - MGTHTXP1_129 -#set_property PACKAGE_PIN H29 [get_ports "FMC_HPC1_DP6_C2M_P"] ;# Bank 129 - MGTHTXP2_129 -#set_property PACKAGE_PIN G31 [get_ports "FMC_HPC1_DP7_C2M_P"] ;# Bank 129 - MGTHTXP3_129 -#set_property PACKAGE_PIN J28 [get_ports "USER_SMA_MGT_CLOCK_C_N"] ;# Bank 129 - MGTREFCLK1N_129 -#set_property PACKAGE_PIN J27 [get_ports "USER_SMA_MGT_CLOCK_C_P"] ;# Bank 129 - MGTREFCLK1P_129 -#set_property PACKAGE_PIN L28 [get_ports "USER_MGT_SI570_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK0N_129 -#set_property PACKAGE_PIN L27 [get_ports "USER_MGT_SI570_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK0P_129 -#set_property PACKAGE_PIN E32 [get_ports "FMC_HPC1_DP0_M2C_N"] ;# Bank 130 - MGTHRXN0_130 -#set_property PACKAGE_PIN D34 [get_ports "FMC_HPC1_DP1_M2C_N"] ;# Bank 130 - MGTHRXN1_130 -#set_property PACKAGE_PIN C32 [get_ports "FMC_HPC1_DP2_M2C_N"] ;# Bank 130 - MGTHRXN2_130 -#set_property PACKAGE_PIN B34 [get_ports "FMC_HPC1_DP3_M2C_N"] ;# Bank 130 - MGTHRXN3_130 -#set_property PACKAGE_PIN E31 [get_ports "FMC_HPC1_DP0_M2C_P"] ;# Bank 130 - MGTHRXP0_130 -#set_property PACKAGE_PIN D33 [get_ports "FMC_HPC1_DP1_M2C_P"] ;# Bank 130 - MGTHRXP1_130 -#set_property PACKAGE_PIN C31 [get_ports "FMC_HPC1_DP2_M2C_P"] ;# Bank 130 - MGTHRXP2_130 -#set_property PACKAGE_PIN B33 [get_ports "FMC_HPC1_DP3_M2C_P"] ;# Bank 130 - MGTHRXP3_130 -#set_property PACKAGE_PIN F30 [get_ports "FMC_HPC1_DP0_C2M_N"] ;# Bank 130 - MGTHTXN0_130 -#set_property PACKAGE_PIN D30 [get_ports "FMC_HPC1_DP1_C2M_N"] ;# Bank 130 - MGTHTXN1_130 -#set_property PACKAGE_PIN B30 [get_ports "FMC_HPC1_DP2_C2M_N"] ;# Bank 130 - MGTHTXN2_130 -#set_property PACKAGE_PIN A32 [get_ports "FMC_HPC1_DP3_C2M_N"] ;# Bank 130 - MGTHTXN3_130 -#set_property PACKAGE_PIN F29 [get_ports "FMC_HPC1_DP0_C2M_P"] ;# Bank 130 - MGTHTXP0_130 -#set_property PACKAGE_PIN D29 [get_ports "FMC_HPC1_DP1_C2M_P"] ;# Bank 130 - MGTHTXP1_130 -#set_property PACKAGE_PIN B29 [get_ports "FMC_HPC1_DP2_C2M_P"] ;# Bank 130 - MGTHTXP2_130 -#set_property PACKAGE_PIN A31 [get_ports "FMC_HPC1_DP3_C2M_P"] ;# Bank 130 - MGTHTXP3_130 -#set_property PACKAGE_PIN G28 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"] ;# Bank 130 - MGTREFCLK0N_130 -#set_property PACKAGE_PIN G27 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"] ;# Bank 130 - MGTREFCLK0P_130 -#set_property PACKAGE_PIN E28 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_N"] ;# Bank 130 - MGTREFCLK1N_130 -#set_property PACKAGE_PIN E27 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_P"] ;# Bank 130 - MGTREFCLK1P_130 -#set_property PACKAGE_PIN T1 [get_ports "FMC_HPC0_DP6_M2C_N"] ;# Bank 228 - MGTHRXN0_228 -#set_property PACKAGE_PIN P1 [get_ports "FMC_HPC0_DP5_M2C_N"] ;# Bank 228 - MGTHRXN1_228 -#set_property PACKAGE_PIN M1 [get_ports "FMC_HPC0_DP7_M2C_N"] ;# Bank 228 - MGTHRXN2_228 -#set_property PACKAGE_PIN L3 [get_ports "FMC_HPC0_DP4_M2C_N"] ;# Bank 228 - MGTHRXN3_228 -#set_property PACKAGE_PIN T2 [get_ports "FMC_HPC0_DP6_M2C_P"] ;# Bank 228 - MGTHRXP0_228 -#set_property PACKAGE_PIN P2 [get_ports "FMC_HPC0_DP5_M2C_P"] ;# Bank 228 - MGTHRXP1_228 -#set_property PACKAGE_PIN M2 [get_ports "FMC_HPC0_DP7_M2C_P"] ;# Bank 228 - MGTHRXP2_228 -#set_property PACKAGE_PIN L4 [get_ports "FMC_HPC0_DP4_M2C_P"] ;# Bank 228 - MGTHRXP3_228 -#set_property PACKAGE_PIN R3 [get_ports "FMC_HPC0_DP6_C2M_N"] ;# Bank 228 - MGTHTXN0_228 -#set_property PACKAGE_PIN P5 [get_ports "FMC_HPC0_DP5_C2M_N"] ;# Bank 228 - MGTHTXN1_228 -#set_property PACKAGE_PIN N3 [get_ports "FMC_HPC0_DP7_C2M_N"] ;# Bank 228 - MGTHTXN2_228 -#set_property PACKAGE_PIN M5 [get_ports "FMC_HPC0_DP4_C2M_N"] ;# Bank 228 - MGTHTXN3_228 -#set_property PACKAGE_PIN R4 [get_ports "FMC_HPC0_DP6_C2M_P"] ;# Bank 228 - MGTHTXP0_228 -#set_property PACKAGE_PIN P6 [get_ports "FMC_HPC0_DP5_C2M_P"] ;# Bank 228 - MGTHTXP1_228 -#set_property PACKAGE_PIN N4 [get_ports "FMC_HPC0_DP7_C2M_P"] ;# Bank 228 - MGTHTXP2_228 -#set_property PACKAGE_PIN M6 [get_ports "FMC_HPC0_DP4_C2M_P"] ;# Bank 228 - MGTHTXP3_228 -#set_property PACKAGE_PIN J7 [get_ports "38N7145"] ;# Bank 228 - MGTREFCLK1N_228 -#set_property PACKAGE_PIN J8 [get_ports "38N7142"] ;# Bank 228 - MGTREFCLK1P_228 -#set_property PACKAGE_PIN L7 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"] ;# Bank 228 - MGTREFCLK0N_228 -#set_property PACKAGE_PIN L8 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"] ;# Bank 228 - MGTREFCLK0P_228 -#set_property PACKAGE_PIN A6 [get_ports "38N2099"] ;# Bank 228 - MGTRREF_R -#Other net PACKAGE_PIN A5 - MGTAVTT Bank 228 - MGTAVTTRCAL_R -#set_property PACKAGE_PIN K1 [get_ports "FMC_HPC0_DP3_M2C_N"] ;# Bank 229 - MGTHRXN0_229 -#set_property PACKAGE_PIN J3 [get_ports "FMC_HPC0_DP1_M2C_N"] ;# Bank 229 - MGTHRXN1_229 -#set_property PACKAGE_PIN H1 [get_ports "FMC_HPC0_DP0_M2C_N"] ;# Bank 229 - MGTHRXN2_229 -#set_property PACKAGE_PIN F1 [get_ports "FMC_HPC0_DP2_M2C_N"] ;# Bank 229 - MGTHRXN3_229 -#set_property PACKAGE_PIN K2 [get_ports "FMC_HPC0_DP3_M2C_P"] ;# Bank 229 - MGTHRXP0_229 -#set_property PACKAGE_PIN J4 [get_ports "FMC_HPC0_DP1_M2C_P"] ;# Bank 229 - MGTHRXP1_229 -#set_property PACKAGE_PIN H2 [get_ports "FMC_HPC0_DP0_M2C_P"] ;# Bank 229 - MGTHRXP2_229 -#set_property PACKAGE_PIN F2 [get_ports "FMC_HPC0_DP2_M2C_P"] ;# Bank 229 - MGTHRXP3_229 -#set_property PACKAGE_PIN K5 [get_ports "FMC_HPC0_DP3_C2M_N"] ;# Bank 229 - MGTHTXN0_229 -#set_property PACKAGE_PIN H5 [get_ports "FMC_HPC0_DP1_C2M_N"] ;# Bank 229 - MGTHTXN1_229 -#set_property PACKAGE_PIN G3 [get_ports "FMC_HPC0_DP0_C2M_N"] ;# Bank 229 - MGTHTXN2_229 -#set_property PACKAGE_PIN F5 [get_ports "FMC_HPC0_DP2_C2M_N"] ;# Bank 229 - MGTHTXN3_229 -#set_property PACKAGE_PIN K6 [get_ports "FMC_HPC0_DP3_C2M_P"] ;# Bank 229 - MGTHTXP0_229 -#set_property PACKAGE_PIN H6 [get_ports "FMC_HPC0_DP1_C2M_P"] ;# Bank 229 - MGTHTXP1_229 -#set_property PACKAGE_PIN G4 [get_ports "FMC_HPC0_DP0_C2M_P"] ;# Bank 229 - MGTHTXP2_229 -#set_property PACKAGE_PIN F6 [get_ports "FMC_HPC0_DP2_C2M_P"] ;# Bank 229 - MGTHTXP3_229 -#set_property PACKAGE_PIN E7 [get_ports "38N7165"] ;# Bank 229 - MGTREFCLK1N_229 -#set_property PACKAGE_PIN E8 [get_ports "38N7162"] ;# Bank 229 - MGTREFCLK1P_229 -#set_property PACKAGE_PIN G7 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"] ;# Bank 229 - MGTREFCLK0N_229 -#set_property PACKAGE_PIN G8 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"] ;# Bank 229 - MGTREFCLK0P_229 -#set_property PACKAGE_PIN D1 [get_ports "SFP0_RX_N"] ;# Bank 230 - MGTHRXN0_230 -#set_property PACKAGE_PIN C3 [get_ports "SFP1_RX_N"] ;# Bank 230 - MGTHRXN1_230 -#set_property PACKAGE_PIN B1 [get_ports "SFP2_RX_N"] ;# Bank 230 - MGTHRXN2_230 -#set_property PACKAGE_PIN A3 [get_ports "SFP3_RX_N"] ;# Bank 230 - MGTHRXN3_230 -#set_property PACKAGE_PIN D2 [get_ports "SFP0_RX_P"] ;# Bank 230 - MGTHRXP0_230 -#set_property PACKAGE_PIN C4 [get_ports "SFP1_RX_P"] ;# Bank 230 - MGTHRXP1_230 -#set_property PACKAGE_PIN B2 [get_ports "SFP2_RX_P"] ;# Bank 230 - MGTHRXP2_230 -#set_property PACKAGE_PIN A4 [get_ports "SFP3_RX_P"] ;# Bank 230 - MGTHRXP3_230 -#set_property PACKAGE_PIN E3 [get_ports "SFP0_TX_N"] ;# Bank 230 - MGTHTXN0_230 -#set_property PACKAGE_PIN D5 [get_ports "SFP1_TX_N"] ;# Bank 230 - MGTHTXN1_230 -#set_property PACKAGE_PIN B5 [get_ports "SFP2_TX_N"] ;# Bank 230 - MGTHTXN2_230 -#set_property PACKAGE_PIN A7 [get_ports "SFP3_TX_N"] ;# Bank 230 - MGTHTXN3_230 -#set_property PACKAGE_PIN E4 [get_ports "SFP0_TX_P"] ;# Bank 230 - MGTHTXP0_230 -#set_property PACKAGE_PIN D6 [get_ports "SFP1_TX_P"] ;# Bank 230 - MGTHTXP1_230 -#set_property PACKAGE_PIN B6 [get_ports "SFP2_TX_P"] ;# Bank 230 - MGTHTXP2_230 -#set_property PACKAGE_PIN A8 [get_ports "SFP3_TX_P"] ;# Bank 230 - MGTHTXP3_230 -#set_property PACKAGE_PIN C7 [get_ports "USER_MGT_SI570_CLOCK2_C_N"] ;# Bank 230 - MGTREFCLK0N_230 -#set_property PACKAGE_PIN C8 [get_ports "USER_MGT_SI570_CLOCK2_C_P"] ;# Bank 230 - MGTREFCLK0P_230 -#set_property PACKAGE_PIN B9 [get_ports "SFP_SI5328_OUT_C_N"] ;# Bank 230 - MGTREFCLK1N_230 -#set_property PACKAGE_PIN B10 [get_ports "SFP_SI5328_OUT_C_P"] ;# Bank 230 - MGTREFCLK1P_230 -################################################################################ -### PS Side -################################################################################ -#Other net PACKAGE_PIN AF16 - MIO0_QSPI_LWR_CLK Bank 500 - PS_MIO0 -#Other net PACKAGE_PIN AJ16 - MIO1_QSPI_LWR_DQ1 Bank 500 - PS_MIO1 -#Other net PACKAGE_PIN AD16 - MIO2_QSPI_LWR_DQ2 Bank 500 - PS_MIO2 -#Other net PACKAGE_PIN AG16 - MIO3_QSPI_LWR_DQ3 Bank 500 - PS_MIO3 -#Other net PACKAGE_PIN AH16 - MIO4_QSPI_LWR_DQ0 Bank 500 - PS_MIO4 -#Other net PACKAGE_PIN AM15 - MIO5_QSPI_LWR_CS_B Bank 500 - PS_MIO5 -#Other net PACKAGE_PIN AL15 - 53N6816 Bank 500 - PS_MIO6 -#Other net PACKAGE_PIN AD17 - MIO7_QSPI_UPR_CS_B Bank 500 - PS_MIO7 -#Other net PACKAGE_PIN AE17 - MIO8_QSPI_UPR_DQ0 Bank 500 - PS_MIO8 -#Other net PACKAGE_PIN AP15 - MIO9_QSPI_UPR_DQ1 Bank 500 - PS_MIO9 -#Other net PACKAGE_PIN AH17 - MIO10_QSPI_UPR_DQ2 Bank 500 - PS_MIO10 -#Other net PACKAGE_PIN AF17 - MIO11_QSPI_UPR_DQ3 Bank 500 - PS_MIO11 -#Other net PACKAGE_PIN AJ17 - MIO12_QSPI_UPR_CLK Bank 500 - PS_MIO12 -#Other net PACKAGE_PIN AK17 - MIO13PS_GPIO2 Bank 500 - PS_MIO13 -#Other net PACKAGE_PIN AL16 - MIO14_I2C0_SCL Bank 500 - PS_MIO14 -#Other net PACKAGE_PIN AN16 - MIO15_I2C0_SDA Bank 500 - PS_MIO15 -#Other net PACKAGE_PIN AM16 - MIO16_I2C1_SCL Bank 500 - PS_MIO16 -#Other net PACKAGE_PIN AP16 - MIO17_I2C1_SDA Bank 500 - PS_MIO17 -#Other net PACKAGE_PIN AE18 - MIO18_UART0_RXD Bank 500 - PS_MIO18 -#Other net PACKAGE_PIN AL17 - MIO19_UART0_TXD Bank 500 - PS_MIO19 -#Other net PACKAGE_PIN AD18 - MIO20_UART1_TXD Bank 500 - PS_MIO20 -#Other net PACKAGE_PIN AF18 - MIO21_UART1_RXD Bank 500 - PS_MIO21 -#Other net PACKAGE_PIN AD20 - MIO22_BUTTON Bank 500 - PS_MIO22 -#Other net PACKAGE_PIN AD19 - MIO23_LED Bank 500 - PS_MIO23 -#Other net PACKAGE_PIN AE20 - MIO24_CAN_TX Bank 500 - PS_MIO24 -#Other net PACKAGE_PIN AE19 - MIO25_CAN_RX Bank 500 - PS_MIO25 -#Other net PACKAGE_PIN P21 - MIO26_PMU_INPUT Bank 501 - PS_MIO26 -#Other net PACKAGE_PIN M21 - MIO27_DP_AUX_OUT Bank 501 - PS_MIO27 -#Other net PACKAGE_PIN N21 - MIO28_DP_HPD Bank 501 - PS_MIO28 -#Other net PACKAGE_PIN K22 - MIO29_DP_OE Bank 501 - PS_MIO29 -#Other net PACKAGE_PIN L21 - MIO30_DP_AUX_IN Bank 501 - PS_MIO30 -#Other net PACKAGE_PIN J22 - MIO31_PCIE_RESET_N Bank 501 - PS_MIO31 -#Other net PACKAGE_PIN H22 - MIO32_PMU_GPO0 Bank 501 - PS_MIO32 -#Other net PACKAGE_PIN H23 - MIO33_PMU_GPO1 Bank 501 - PS_MIO33 -#Other net PACKAGE_PIN L22 - MIO34_PMU_GPO2 Bank 501 - PS_MIO34 -#Other net PACKAGE_PIN P22 - MIO35_PMU_GPO3 Bank 501 - PS_MIO35 -#Other net PACKAGE_PIN K23 - MIO36_PMU_GPO4 Bank 501 - PS_MIO36 -#Other net PACKAGE_PIN N22 - MIO37_PMU_GPO5 Bank 501 - PS_MIO37 -#Other net PACKAGE_PIN L23 - MIO38_PS_GPIO1 Bank 501 - PS_MIO38 -#Other net PACKAGE_PIN N23 - MIO39_SDIO_SEL Bank 501 - PS_MIO39 -#Other net PACKAGE_PIN M23 - MIO40_SDIO_DIR_CMD Bank 501 - PS_MIO40 -#Other net PACKAGE_PIN J24 - MIO41_SDIO_DIR_DAT0 Bank 501 - PS_MIO41 -#Other net PACKAGE_PIN M24 - MIO42_SDIO_DIR_DAT1_3 Bank 501 - PS_MIO42 -#Other net PACKAGE_PIN K24 - 53N6798 Bank 501 - PS_MIO43 -#Other net PACKAGE_PIN N24 - MIO44_SDIO_PROTECT Bank 501 - PS_MIO44 -#Other net PACKAGE_PIN P24 - MIO45_SDIO_DETECT Bank 501 - PS_MIO45 -#Other net PACKAGE_PIN J25 - MIO46_SDIO_DAT0 Bank 501 - PS_MIO46 -#Other net PACKAGE_PIN L25 - MIO47_SDIO_DAT1 Bank 501 - PS_MIO47 -#Other net PACKAGE_PIN M25 - MIO48_SDIO_DAT2 Bank 501 - PS_MIO48 -#Other net PACKAGE_PIN K25 - MIO49_SDIO_DAT3 Bank 501 - PS_MIO49 -#Other net PACKAGE_PIN P25 - MIO50_SDIO_CMD Bank 501 - PS_MIO50 -#Other net PACKAGE_PIN N25 - MIO51_SDIO_CLK Bank 501 - PS_MIO51 -#Other net PACKAGE_PIN F22 - MIO52_USB_CLK Bank 502 - PS_MIO52 -#Other net PACKAGE_PIN E23 - MIO53_USB_DIR Bank 502 - PS_MIO53 -#Other net PACKAGE_PIN F23 - MIO54_USB_DATA2 Bank 502 - PS_MIO54 -#Other net PACKAGE_PIN B23 - MIO55_USB_NXT Bank 502 - PS_MIO55 -#Other net PACKAGE_PIN C23 - MIO56_USB_DATA0 Bank 502 - PS_MIO56 -#Other net PACKAGE_PIN A23 - MIO57_USB_DATA1 Bank 502 - PS_MIO57 -#Other net PACKAGE_PIN G23 - MIO58_USB_STP Bank 502 - PS_MIO58 -#Other net PACKAGE_PIN B24 - MIO59_USB_DATA3 Bank 502 - PS_MIO59 -#Other net PACKAGE_PIN E24 - MIO60_USB_DATA4 Bank 502 - PS_MIO60 -#Other net PACKAGE_PIN C24 - MIO61_USB_DATA5 Bank 502 - PS_MIO61 -#Other net PACKAGE_PIN G24 - MIO62_USB_DATA6 Bank 502 - PS_MIO62 -#Other net PACKAGE_PIN D24 - MIO63_USB_DATA7 Bank 502 - PS_MIO63 -#Other net PACKAGE_PIN A25 - MIO64_ENET_TX_CLK Bank 502 - PS_MIO64 -#Other net PACKAGE_PIN A26 - MIO65_ENET_TX_D0 Bank 502 - PS_MIO65 -#Other net PACKAGE_PIN A27 - MIO66_ENET_TX_D1 Bank 502 - PS_MIO66 -#Other net PACKAGE_PIN B25 - MIO67_ENET_TX_D2 Bank 502 - PS_MIO67 -#Other net PACKAGE_PIN B26 - MIO68_ENET_TX_D3 Bank 502 - PS_MIO68 -#Other net PACKAGE_PIN B27 - MIO69_ENET_TX_CTRL Bank 502 - PS_MIO69 -#Other net PACKAGE_PIN C26 - MIO70_ENET_RX_CLK Bank 502 - PS_MIO70 -#Other net PACKAGE_PIN C27 - MIO71_ENET_RX_D0 Bank 502 - PS_MIO71 -#Other net PACKAGE_PIN E25 - MIO72_ENET_RX_D1 Bank 502 - PS_MIO72 -#Other net PACKAGE_PIN H24 - MIO73_ENET_RX_D2 Bank 502 - PS_MIO73 -#Other net PACKAGE_PIN G25 - MIO74_ENET_RX_D3 Bank 502 - PS_MIO74 -#Other net PACKAGE_PIN D25 - MIO75_ENET_RX_CTRL Bank 502 - PS_MIO75 -#Other net PACKAGE_PIN H25 - MIO76_ENET_MDC Bank 502 - PS_MIO76 -#Other net PACKAGE_PIN F25 - MIO77_ENET_MDIO Bank 502 - PS_MIO77 -#Other net PACKAGE_PIN W21 - PS_DONE Bank 503 - PS_DONE -#Other net PACKAGE_PIN T21 - PS_ERR_OUT Bank 503 - PS_ERROR_OUT -#Other net PACKAGE_PIN R21 - PS_ERR_STATUS Bank 503 - PS_ERROR_STATUS -#Other net PACKAGE_PIN V24 - PS_INIT_B Bank 503 - PS_INIT_B -#Other net PACKAGE_PIN R25 - JTAG_TCK Bank 503 - PS_JTAG_TCK -#Other net PACKAGE_PIN U25 - JTAG_TDI Bank 503 - PS_JTAG_TDI -#Other net PACKAGE_PIN T25 - FPGA_TDO_FMC_TDI Bank 503 - PS_JTAG_TDO -#Other net PACKAGE_PIN R24 - JTAG_TMS Bank 503 - PS_JTAG_TMS -#Other net PACKAGE_PIN T22 - PS_MODE0 Bank 503 - PS_MODE0 -#Other net PACKAGE_PIN R22 - PS_MODE1 Bank 503 - PS_MODE1 -#Other net PACKAGE_PIN T23 - PS_MODE2 Bank 503 - PS_MODE2 -#Other net PACKAGE_PIN R23 - PS_MODE3 Bank 503 - PS_MODE3 -#Other net PACKAGE_PIN V21 - PS_PADI Bank 503 - PS_PADI -#Other net PACKAGE_PIN V22 - PS_PADO Bank 503 - PS_PADO -#Other net PACKAGE_PIN V23 - PS_POR_B Bank 503 - PS_POR_B -#Other net PACKAGE_PIN U21 - PS_PROG_B Bank 503 - PS_PROG_B -#Other net PACKAGE_PIN U24 - PS_REF_CLK Bank 503 - PS_REF_CLK -#Other net PACKAGE_PIN U23 - PS_SRST_B Bank 503 - PS_SRST_B -#Other net PACKAGE_PIN AP29 - DDR4_SODIMM_A0 Bank 504 - PS_DDR_A0 -#Other net PACKAGE_PIN AP30 - DDR4_SODIMM_A1 Bank 504 - PS_DDR_A1 -#Other net PACKAGE_PIN AL28 - DDR4_SODIMM_A10 Bank 504 - PS_DDR_A10 -#Other net PACKAGE_PIN AK27 - DDR4_SODIMM_A11 Bank 504 - PS_DDR_A11 -#Other net PACKAGE_PIN AJ25 - DDR4_SODIMM_A12 Bank 504 - PS_DDR_A12 -#Other net PACKAGE_PIN AL25 - DDR4_SODIMM_A13 Bank 504 - PS_DDR_A13 -#Other net PACKAGE_PIN AK25 - DDR4_SODIMM_WE_B Bank 504 - PS_DDR_A14 -#Other net PACKAGE_PIN AK24 - DDR4_SODIMM_CAS_B Bank 504 - PS_DDR_A15 -#Other net PACKAGE_PIN AM24 - DDR4_SODIMM_RAS_B Bank 504 - PS_DDR_A16 -#Other net PACKAGE_PIN AF25 - 68N6692 Bank 504 - PS_DDR_A17 -#Other net PACKAGE_PIN AP26 - DDR4_SODIMM_A2 Bank 504 - PS_DDR_A2 -#Other net PACKAGE_PIN AP27 - DDR4_SODIMM_A3 Bank 504 - PS_DDR_A3 -#Other net PACKAGE_PIN AP25 - DDR4_SODIMM_A4 Bank 504 - PS_DDR_A4 -#Other net PACKAGE_PIN AN24 - DDR4_SODIMM_A5 Bank 504 - PS_DDR_A5 -#Other net PACKAGE_PIN AM29 - DDR4_SODIMM_A6 Bank 504 - PS_DDR_A6 -#Other net PACKAGE_PIN AM28 - DDR4_SODIMM_A7 Bank 504 - PS_DDR_A7 -#Other net PACKAGE_PIN AM26 - DDR4_SODIMM_A8 Bank 504 - PS_DDR_A8 -#Other net PACKAGE_PIN AM25 - DDR4_SODIMM_A9 Bank 504 - PS_DDR_A9 -#Other net PACKAGE_PIN AG25 - DDR4_SODIMM_ACT_B Bank 504 - PS_DDR_ACT_N -#Other net PACKAGE_PIN AF22 - DDR4_SODIMM_ALERT_B Bank 504 - PS_DDR_ALERT_N -#Other net PACKAGE_PIN AH26 - DDR4_SODIMM_BA0 Bank 504 - PS_DDR_BA0 -#Other net PACKAGE_PIN AG26 - DDR4_SODIMM_BA1 Bank 504 - PS_DDR_BA1 -#Other net PACKAGE_PIN AK28 - DDR4_SODIMM_BG0 Bank 504 - PS_DDR_BG0 -#Other net PACKAGE_PIN AH27 - DDR4_SODIMM_BG1 Bank 504 - PS_DDR_BG1 -#Other net PACKAGE_PIN AN27 - DDR4_SODIMM_CK0_C Bank 504 - PS_DDR_CK_N0 -#Other net PACKAGE_PIN AL27 - DDR4_SODIMM_CK1_C Bank 504 - PS_DDR_CK_N1 -#Other net PACKAGE_PIN AN26 - DDR4_SODIMM_CK0_T Bank 504 - PS_DDR_CK0 -#Other net PACKAGE_PIN AL26 - DDR4_SODIMM_CK1_T Bank 504 - PS_DDR_CK1 -#Other net PACKAGE_PIN AN29 - DDR4_SODIMM_CKE0 Bank 504 - PS_DDR_CKE0 -#Other net PACKAGE_PIN AJ27 - DDR4_SODIMM_CKE1 Bank 504 - PS_DDR_CKE1 -#Other net PACKAGE_PIN AN28 - DDR4_SODIMM_CS0_B Bank 504 - PS_DDR_CS_N0 -#Other net PACKAGE_PIN AL30 - DDR4_SODIMM_CS1_B Bank 504 - PS_DDR_CS_N1 -#Other net PACKAGE_PIN AN17 - DDR4_SODIMM_DM0_B Bank 504 - PS_DDR_DM0 -#Other net PACKAGE_PIN AM21 - DDR4_SODIMM_DM1_B Bank 504 - PS_DDR_DM1 -#Other net PACKAGE_PIN AK19 - DDR4_SODIMM_DM2_B Bank 504 - PS_DDR_DM2 -#Other net PACKAGE_PIN AH24 - DDR4_SODIMM_DM3_B Bank 504 - PS_DDR_DM3 -#Other net PACKAGE_PIN AH31 - DDR4_SODIMM_DM4_B Bank 504 - PS_DDR_DM4 -#Other net PACKAGE_PIN AE30 - DDR4_SODIMM_DM5_B Bank 504 - PS_DDR_DM5 -#Other net PACKAGE_PIN AJ31 - DDR4_SODIMM_DM6_B Bank 504 - PS_DDR_DM6 -#Other net PACKAGE_PIN AE34 - DDR4_SODIMM_DM7_B Bank 504 - PS_DDR_DM7 -#Other net PACKAGE_PIN AN34 - DDR4_SODIMM_DM8_B Bank 504 - PS_DDR_DM8 -#Other net PACKAGE_PIN AP20 - DDR4_SODIMM_DQ0 Bank 504 - PS_DDR_DQ0 -#Other net PACKAGE_PIN AP18 - DDR4_SODIMM_DQ1 Bank 504 - PS_DDR_DQ1 -#Other net PACKAGE_PIN AP19 - DDR4_SODIMM_DQ2 Bank 504 - PS_DDR_DQ2 -#Other net PACKAGE_PIN AP17 - DDR4_SODIMM_DQ3 Bank 504 - PS_DDR_DQ3 -#Other net PACKAGE_PIN AM20 - DDR4_SODIMM_DQ4 Bank 504 - PS_DDR_DQ4 -#Other net PACKAGE_PIN AM19 - DDR4_SODIMM_DQ5 Bank 504 - PS_DDR_DQ5 -#Other net PACKAGE_PIN AM18 - DDR4_SODIMM_DQ6 Bank 504 - PS_DDR_DQ6 -#Other net PACKAGE_PIN AL18 - DDR4_SODIMM_DQ7 Bank 504 - PS_DDR_DQ7 -#Other net PACKAGE_PIN AP22 - DDR4_SODIMM_DQ8 Bank 504 - PS_DDR_DQ8 -#Other net PACKAGE_PIN AP21 - DDR4_SODIMM_DQ9 Bank 504 - PS_DDR_DQ9 -#Other net PACKAGE_PIN AP24 - DDR4_SODIMM_DQ10 Bank 504 - PS_DDR_DQ10 -#Other net PACKAGE_PIN AN23 - DDR4_SODIMM_DQ11 Bank 504 - PS_DDR_DQ11 -#Other net PACKAGE_PIN AL21 - DDR4_SODIMM_DQ12 Bank 504 - PS_DDR_DQ12 -#Other net PACKAGE_PIN AL22 - DDR4_SODIMM_DQ13 Bank 504 - PS_DDR_DQ13 -#Other net PACKAGE_PIN AM23 - DDR4_SODIMM_DQ14 Bank 504 - PS_DDR_DQ14 -#Other net PACKAGE_PIN AL23 - DDR4_SODIMM_DQ15 Bank 504 - PS_DDR_DQ15 -#Other net PACKAGE_PIN AL20 - DDR4_SODIMM_DQ16 Bank 504 - PS_DDR_DQ16 -#Other net PACKAGE_PIN AK20 - DDR4_SODIMM_DQ17 Bank 504 - PS_DDR_DQ17 -#Other net PACKAGE_PIN AJ20 - DDR4_SODIMM_DQ18 Bank 504 - PS_DDR_DQ18 -#Other net PACKAGE_PIN AK18 - DDR4_SODIMM_DQ19 Bank 504 - PS_DDR_DQ19 -#Other net PACKAGE_PIN AG20 - DDR4_SODIMM_DQ20 Bank 504 - PS_DDR_DQ20 -#Other net PACKAGE_PIN AH18 - DDR4_SODIMM_DQ21 Bank 504 - PS_DDR_DQ21 -#Other net PACKAGE_PIN AG19 - DDR4_SODIMM_DQ22 Bank 504 - PS_DDR_DQ22 -#Other net PACKAGE_PIN AG18 - DDR4_SODIMM_DQ23 Bank 504 - PS_DDR_DQ23 -#Other net PACKAGE_PIN AG21 - DDR4_SODIMM_DQ24 Bank 504 - PS_DDR_DQ24 -#Other net PACKAGE_PIN AH21 - DDR4_SODIMM_DQ25 Bank 504 - PS_DDR_DQ25 -#Other net PACKAGE_PIN AG24 - DDR4_SODIMM_DQ26 Bank 504 - PS_DDR_DQ26 -#Other net PACKAGE_PIN AG23 - DDR4_SODIMM_DQ27 Bank 504 - PS_DDR_DQ27 -#Other net PACKAGE_PIN AK22 - DDR4_SODIMM_DQ28 Bank 504 - PS_DDR_DQ28 -#Other net PACKAGE_PIN AJ21 - DDR4_SODIMM_DQ29 Bank 504 - PS_DDR_DQ29 -#Other net PACKAGE_PIN AJ22 - DDR4_SODIMM_DQ30 Bank 504 - PS_DDR_DQ30 -#Other net PACKAGE_PIN AK23 - DDR4_SODIMM_DQ31 Bank 504 - PS_DDR_DQ31 -#Other net PACKAGE_PIN AG31 - DDR4_SODIMM_DQ32 Bank 504 - PS_DDR_DQ32 -#Other net PACKAGE_PIN AG30 - DDR4_SODIMM_DQ33 Bank 504 - PS_DDR_DQ33 -#Other net PACKAGE_PIN AG29 - DDR4_SODIMM_DQ34 Bank 504 - PS_DDR_DQ34 -#Other net PACKAGE_PIN AG28 - DDR4_SODIMM_DQ35 Bank 504 - PS_DDR_DQ35 -#Other net PACKAGE_PIN AJ30 - DDR4_SODIMM_DQ36 Bank 504 - PS_DDR_DQ36 -#Other net PACKAGE_PIN AK29 - DDR4_SODIMM_DQ37 Bank 504 - PS_DDR_DQ37 -#Other net PACKAGE_PIN AK30 - DDR4_SODIMM_DQ38 Bank 504 - PS_DDR_DQ38 -#Other net PACKAGE_PIN AJ29 - DDR4_SODIMM_DQ39 Bank 504 - PS_DDR_DQ39 -#Other net PACKAGE_PIN AE27 - DDR4_SODIMM_DQ40 Bank 504 - PS_DDR_DQ40 -#Other net PACKAGE_PIN AF28 - DDR4_SODIMM_DQ41 Bank 504 - PS_DDR_DQ41 -#Other net PACKAGE_PIN AF30 - DDR4_SODIMM_DQ42 Bank 504 - PS_DDR_DQ42 -#Other net PACKAGE_PIN AF31 - DDR4_SODIMM_DQ43 Bank 504 - PS_DDR_DQ43 -#Other net PACKAGE_PIN AD28 - DDR4_SODIMM_DQ44 Bank 504 - PS_DDR_DQ44 -#Other net PACKAGE_PIN AD27 - DDR4_SODIMM_DQ45 Bank 504 - PS_DDR_DQ45 -#Other net PACKAGE_PIN AD29 - DDR4_SODIMM_DQ46 Bank 504 - PS_DDR_DQ46 -#Other net PACKAGE_PIN AD30 - DDR4_SODIMM_DQ47 Bank 504 - PS_DDR_DQ47 -#Other net PACKAGE_PIN AH33 - DDR4_SODIMM_DQ48 Bank 504 - PS_DDR_DQ48 -#Other net PACKAGE_PIN AJ34 - DDR4_SODIMM_DQ49 Bank 504 - PS_DDR_DQ49 -#Other net PACKAGE_PIN AH34 - DDR4_SODIMM_DQ50 Bank 504 - PS_DDR_DQ50 -#Other net PACKAGE_PIN AH32 - DDR4_SODIMM_DQ51 Bank 504 - PS_DDR_DQ51 -#Other net PACKAGE_PIN AK34 - DDR4_SODIMM_DQ52 Bank 504 - PS_DDR_DQ52 -#Other net PACKAGE_PIN AK33 - DDR4_SODIMM_DQ53 Bank 504 - PS_DDR_DQ53 -#Other net PACKAGE_PIN AL32 - DDR4_SODIMM_DQ54 Bank 504 - PS_DDR_DQ54 -#Other net PACKAGE_PIN AL31 - DDR4_SODIMM_DQ55 Bank 504 - PS_DDR_DQ55 -#Other net PACKAGE_PIN AG33 - DDR4_SODIMM_DQ56 Bank 504 - PS_DDR_DQ56 -#Other net PACKAGE_PIN AG34 - DDR4_SODIMM_DQ57 Bank 504 - PS_DDR_DQ57 -#Other net PACKAGE_PIN AF32 - DDR4_SODIMM_DQ58 Bank 504 - PS_DDR_DQ58 -#Other net PACKAGE_PIN AF33 - DDR4_SODIMM_DQ59 Bank 504 - PS_DDR_DQ59 -#Other net PACKAGE_PIN AD31 - DDR4_SODIMM_DQ60 Bank 504 - PS_DDR_DQ60 -#Other net PACKAGE_PIN AD32 - DDR4_SODIMM_DQ61 Bank 504 - PS_DDR_DQ61 -#Other net PACKAGE_PIN AD34 - DDR4_SODIMM_DQ62 Bank 504 - PS_DDR_DQ62 -#Other net PACKAGE_PIN AD33 - DDR4_SODIMM_DQ63 Bank 504 - PS_DDR_DQ63 -#Other net PACKAGE_PIN AN31 - DDR4_SODIMM_CB0 Bank 504 - PS_DDR_DQ64 -#Other net PACKAGE_PIN AP31 - DDR4_SODIMM_CB1 Bank 504 - PS_DDR_DQ65 -#Other net PACKAGE_PIN AP32 - DDR4_SODIMM_CB2 Bank 504 - PS_DDR_DQ66 -#Other net PACKAGE_PIN AP33 - DDR4_SODIMM_CB3 Bank 504 - PS_DDR_DQ67 -#Other net PACKAGE_PIN AM31 - DDR4_SODIMM_CB4 Bank 504 - PS_DDR_DQ68 -#Other net PACKAGE_PIN AM33 - DDR4_SODIMM_CB5 Bank 504 - PS_DDR_DQ69 -#Other net PACKAGE_PIN AM34 - DDR4_SODIMM_CB6 Bank 504 - PS_DDR_DQ70 -#Other net PACKAGE_PIN AL33 - DDR4_SODIMM_CB7 Bank 504 - PS_DDR_DQ71 -#Other net PACKAGE_PIN AN19 - DDR4_SODIMM_DQS0_C Bank 504 - PS_DDR_DQS_N0 -#Other net PACKAGE_PIN AN22 - DDR4_SODIMM_DQS1_C Bank 504 - PS_DDR_DQS_N1 -#Other net PACKAGE_PIN AJ19 - DDR4_SODIMM_DQS2_C Bank 504 - PS_DDR_DQS_N2 -#Other net PACKAGE_PIN AH23 - DDR4_SODIMM_DQS3_C Bank 504 - PS_DDR_DQS_N3 -#Other net PACKAGE_PIN AH29 - DDR4_SODIMM_DQS4_C Bank 504 - PS_DDR_DQS_N4 -#Other net PACKAGE_PIN AE29 - DDR4_SODIMM_DQS5_C Bank 504 - PS_DDR_DQS_N5 -#Other net PACKAGE_PIN AK32 - DDR4_SODIMM_DQS6_C Bank 504 - PS_DDR_DQS_N6 -#Other net PACKAGE_PIN AE33 - DDR4_SODIMM_DQS7_C Bank 504 - PS_DDR_DQS_N7 -#Other net PACKAGE_PIN AN33 - DDR4_SODIMM_DQS8_C Bank 504 - PS_DDR_DQS_N8 -#Other net PACKAGE_PIN AN18 - DDR4_SODIMM_DQS0_T Bank 504 - PS_DDR_DQS_P0 -#Other net PACKAGE_PIN AN21 - DDR4_SODIMM_DQS1_T Bank 504 - PS_DDR_DQS_P1 -#Other net PACKAGE_PIN AH19 - DDR4_SODIMM_DQS2_T Bank 504 - PS_DDR_DQS_P2 -#Other net PACKAGE_PIN AH22 - DDR4_SODIMM_DQS3_T Bank 504 - PS_DDR_DQS_P3 -#Other net PACKAGE_PIN AH28 - DDR4_SODIMM_DQS4_T Bank 504 - PS_DDR_DQS_P4 -#Other net PACKAGE_PIN AE28 - DDR4_SODIMM_DQS5_T Bank 504 - PS_DDR_DQS_P5 -#Other net PACKAGE_PIN AJ32 - DDR4_SODIMM_DQS6_T Bank 504 - PS_DDR_DQS_P6 -#Other net PACKAGE_PIN AE32 - DDR4_SODIMM_DQS7_T Bank 504 - PS_DDR_DQS_P7 -#Other net PACKAGE_PIN AN32 - DDR4_SODIMM_DQS8_T Bank 504 - PS_DDR_DQS_P8 -#Other net PACKAGE_PIN AM30 - DDR4_SODIMM_ODT0 Bank 504 - PS_DDR_ODT0 -#Other net PACKAGE_PIN AJ26 - DDR4_SODIMM_ODT1 Bank 504 - PS_DDR_ODT1 -#Other net PACKAGE_PIN AF20 - DDR4_SODIMM_PARITY Bank 504 - PS_DDR_PARITY -#Other net PACKAGE_PIN AF21 - ZYNQ_DDR4_SODIMM_RESET_B Bank 504 - PS_DDR_RAM_RST_N -#Other net PACKAGE_PIN AF23 - UDIMM_PS_ZQ Bank 504 - PS_DDR_ZQ -#Other net PACKAGE_PIN AF27 - 68N6670 Bank 504 - PS_SENSE_DDRPHY_VREF_N -#Other net PACKAGE_PIN AF26 - 68N6673 Bank 504 - PS_SENSE_DDRPHY_VREF_P -#Other net PACKAGE_PIN AB34 - GTR_LANE0_RX_N Bank 505 - PS_MGTRRXN0_505 -#Other net PACKAGE_PIN AA32 - GTR_LANE1_RX_N Bank 505 - PS_MGTRRXN1_505 -#Other net PACKAGE_PIN Y34 - GTR_LANE2_RX_N Bank 505 - PS_MGTRRXN2_505 -#Other net PACKAGE_PIN V34 - GTR_LANE3_RX_N Bank 505 - PS_MGTRRXN3_505 -#Other net PACKAGE_PIN AB33 - GTR_LANE0_RX_P Bank 505 - PS_MGTRRXP0_505 -#Other net PACKAGE_PIN AA31 - GTR_LANE1_RX_P Bank 505 - PS_MGTRRXP1_505 -#Other net PACKAGE_PIN Y33 - GTR_LANE2_RX_P Bank 505 - PS_MGTRRXP2_505 -#Other net PACKAGE_PIN V33 - GTR_LANE3_RX_P Bank 505 - PS_MGTRRXP3_505 -#Other net PACKAGE_PIN AB30 - GTR_LANE0_TX_N Bank 505 - PS_MGTRTXN0_505 -#Other net PACKAGE_PIN Y30 - GTR_LANE1_TX_N Bank 505 - PS_MGTRTXN1_505 -#Other net PACKAGE_PIN W32 - GTR_LANE2_TX_N Bank 505 - PS_MGTRTXN2_505 -#Other net PACKAGE_PIN V30 - GTR_LANE3_TX_N Bank 505 - PS_MGTRTXN3_505 -#Other net PACKAGE_PIN AB29 - GTR_LANE0_TX_P Bank 505 - PS_MGTRTXP0_505 -#Other net PACKAGE_PIN Y29 - GTR_LANE1_TX_P Bank 505 - PS_MGTRTXP1_505 -#Other net PACKAGE_PIN W31 - GTR_LANE2_TX_P Bank 505 - PS_MGTRTXP2_505 -#Other net PACKAGE_PIN V29 - GTR_LANE3_TX_P Bank 505 - PS_MGTRTXP3_505 -#Other net PACKAGE_PIN AA28 - GTR_REF_CLK_PCIE_C_N Bank 505 - PS_MGTREFCLK0N_505 -#Other net PACKAGE_PIN AA27 - GTR_REF_CLK_PCIE_C_P Bank 505 - PS_MGTREFCLK0P_505 -#Other net PACKAGE_PIN W28 - GTR_REF_CLK_SATA_C_N Bank 505 - PS_MGTREFCLK1N_505 -#Other net PACKAGE_PIN W27 - GTR_REF_CLK_SATA_C_P Bank 505 - PS_MGTREFCLK1P_505 -#Other net PACKAGE_PIN U28 - GTR_REF_CLK_USB3_C_N Bank 505 - PS_MGTREFCLK2N_505 -#Other net PACKAGE_PIN U27 - GTR_REF_CLK_USB3_C_P Bank 505 - PS_MGTREFCLK2P_505 -#Other net PACKAGE_PIN U32 - GTR_REF_CLK_DP_C_N Bank 505 - PS_MGTREFCLK3N_505 -#Other net PACKAGE_PIN U31 - GTR_REF_CLK_DP_C_P Bank 505 - PS_MGTREFCLK3P_505 -#Other net PACKAGE_PIN AB28 - 69N5804 Bank 505 - PS_MGTRREF_505 diff --git a/target/xilinx/flavor_vanilla/scripts/run.tcl b/target/xilinx/flavor_vanilla/scripts/run.tcl index c14efe8e..c40eb6de 100644 --- a/target/xilinx/flavor_vanilla/scripts/run.tcl +++ b/target/xilinx/flavor_vanilla/scripts/run.tcl @@ -15,7 +15,16 @@ set_param general.maxThreads 8 # Contraints files selection switch $::env(XILINX_BOARD) { "vcu128" { + # Board specific import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc + if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} { + import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_ext_jtag.xdc + } + if {![info exists ::env(GEN_NO_HYPERBUS)] || ($::env(GEN_NO_HYPERBUS)==0)} { + import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_hyperbus.xdc + } + + # Vanilla specific import_files -fileset constrs_1 -norecurse constraints/carfield_top_xilinx.xdc # General constraints import_files -fileset constrs_1 -norecurse ../constraints/carfield_islands.tcl From e4db6c6af9d129447fc6584ab18d79138c0216dd Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Mon, 17 Jun 2024 23:26:28 +0200 Subject: [PATCH 3/5] fpga: Correct Xilinx IP verilog to follow the standard --- .../carfield_ip/src/carfield_xilinx_ip.v | 236 +++++++++--------- 1 file changed, 118 insertions(+), 118 deletions(-) diff --git a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v index c21e4334..3f87e6b7 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v +++ b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v @@ -320,134 +320,134 @@ module carfield_xilinx_ip // Hyperram pads - .pad_hyper_csn, - .pad_hyper_ck, - .pad_hyper_ckn, - .pad_hyper_rwds, + .pad_hyper_csn(pad_hyper_csn), + .pad_hyper_ck(pad_hyper_ck), + .pad_hyper_ckn(pad_hyper_ckn), + .pad_hyper_rwds(pad_hyper_rwds), // .pad_hyper_reset, - .pad_hyper_dq, + .pad_hyper_dq(pad_hyper_dq), // Dram axi - .dram_axi_m_axi_awid, - .dram_axi_m_axi_awaddr, - .dram_axi_m_axi_awlen, - .dram_axi_m_axi_awsize, - .dram_axi_m_axi_awburst, - .dram_axi_m_axi_awlock, - .dram_axi_m_axi_awcache, - .dram_axi_m_axi_awprot, - .dram_axi_m_axi_awqos, - .dram_axi_m_axi_awvalid, - .dram_axi_m_axi_awready, - .dram_axi_m_axi_wdata, - .dram_axi_m_axi_wstrb, - .dram_axi_m_axi_wlast, - .dram_axi_m_axi_wvalid, - .dram_axi_m_axi_wready, - .dram_axi_m_axi_bready, - .dram_axi_m_axi_bid, - .dram_axi_m_axi_bresp, - .dram_axi_m_axi_bvalid, - .dram_axi_m_axi_arid, - .dram_axi_m_axi_araddr, - .dram_axi_m_axi_arlen, - .dram_axi_m_axi_arsize, - .dram_axi_m_axi_arburst, - .dram_axi_m_axi_arlock, - .dram_axi_m_axi_arcache, - .dram_axi_m_axi_arprot, - .dram_axi_m_axi_arqos, - .dram_axi_m_axi_arvalid, - .dram_axi_m_axi_arready, - .dram_axi_m_axi_rready, - .dram_axi_m_axi_rid, - .dram_axi_m_axi_rdata, - .dram_axi_m_axi_rresp, - .dram_axi_m_axi_rlast, - .dram_axi_m_axi_rvalid, + .dram_axi_m_axi_awid (dram_axi_m_axi_awid ), + .dram_axi_m_axi_awaddr (dram_axi_m_axi_awaddr ), + .dram_axi_m_axi_awlen (dram_axi_m_axi_awlen ), + .dram_axi_m_axi_awsize (dram_axi_m_axi_awsize ), + .dram_axi_m_axi_awburst (dram_axi_m_axi_awburst), + .dram_axi_m_axi_awlock (dram_axi_m_axi_awlock ), + .dram_axi_m_axi_awcache (dram_axi_m_axi_awcache), + .dram_axi_m_axi_awprot (dram_axi_m_axi_awprot ), + .dram_axi_m_axi_awqos (dram_axi_m_axi_awqos ), + .dram_axi_m_axi_awvalid (dram_axi_m_axi_awvalid), + .dram_axi_m_axi_awready (dram_axi_m_axi_awready), + .dram_axi_m_axi_wdata (dram_axi_m_axi_wdata ), + .dram_axi_m_axi_wstrb (dram_axi_m_axi_wstrb ), + .dram_axi_m_axi_wlast (dram_axi_m_axi_wlast ), + .dram_axi_m_axi_wvalid (dram_axi_m_axi_wvalid ), + .dram_axi_m_axi_wready (dram_axi_m_axi_wready ), + .dram_axi_m_axi_bready (dram_axi_m_axi_bready ), + .dram_axi_m_axi_bid (dram_axi_m_axi_bid ), + .dram_axi_m_axi_bresp (dram_axi_m_axi_bresp ), + .dram_axi_m_axi_bvalid (dram_axi_m_axi_bvalid ), + .dram_axi_m_axi_arid (dram_axi_m_axi_arid ), + .dram_axi_m_axi_araddr (dram_axi_m_axi_araddr ), + .dram_axi_m_axi_arlen (dram_axi_m_axi_arlen ), + .dram_axi_m_axi_arsize (dram_axi_m_axi_arsize ), + .dram_axi_m_axi_arburst (dram_axi_m_axi_arburst), + .dram_axi_m_axi_arlock (dram_axi_m_axi_arlock ), + .dram_axi_m_axi_arcache (dram_axi_m_axi_arcache), + .dram_axi_m_axi_arprot (dram_axi_m_axi_arprot ), + .dram_axi_m_axi_arqos (dram_axi_m_axi_arqos ), + .dram_axi_m_axi_arvalid (dram_axi_m_axi_arvalid), + .dram_axi_m_axi_arready (dram_axi_m_axi_arready), + .dram_axi_m_axi_rready (dram_axi_m_axi_rready ), + .dram_axi_m_axi_rid (dram_axi_m_axi_rid ), + .dram_axi_m_axi_rdata (dram_axi_m_axi_rdata ), + .dram_axi_m_axi_rresp (dram_axi_m_axi_rresp ), + .dram_axi_m_axi_rlast (dram_axi_m_axi_rlast ), + .dram_axi_m_axi_rvalid (dram_axi_m_axi_rvalid ), // Peripheral axi - .periph_axi_m_aclk, - .periph_axi_m_aresetn, - .periph_axi_m_axi_awid, - .periph_axi_m_axi_awaddr, - .periph_axi_m_axi_awlen, - .periph_axi_m_axi_awsize, - .periph_axi_m_axi_awburst, - .periph_axi_m_axi_awlock, - .periph_axi_m_axi_awcache, - .periph_axi_m_axi_awprot, - .periph_axi_m_axi_awqos, - .periph_axi_m_axi_awvalid, - .periph_axi_m_axi_awready, - .periph_axi_m_axi_wdata, - .periph_axi_m_axi_wstrb, - .periph_axi_m_axi_wlast, - .periph_axi_m_axi_wvalid, - .periph_axi_m_axi_wready, - .periph_axi_m_axi_bready, - .periph_axi_m_axi_bid, - .periph_axi_m_axi_bresp, - .periph_axi_m_axi_bvalid, - .periph_axi_m_axi_arid, - .periph_axi_m_axi_araddr, - .periph_axi_m_axi_arlen, - .periph_axi_m_axi_arsize, - .periph_axi_m_axi_arburst, - .periph_axi_m_axi_arlock, - .periph_axi_m_axi_arcache, - .periph_axi_m_axi_arprot, - .periph_axi_m_axi_arqos, - .periph_axi_m_axi_arvalid, - .periph_axi_m_axi_arready, - .periph_axi_m_axi_rready, - .periph_axi_m_axi_rid, - .periph_axi_m_axi_rdata, - .periph_axi_m_axi_rresp, - .periph_axi_m_axi_rlast, - .periph_axi_m_axi_rvalid, + .periph_axi_m_aclk (periph_axi_m_aclk ), + .periph_axi_m_aresetn (periph_axi_m_aresetn ), + .periph_axi_m_axi_awid (periph_axi_m_axi_awid ), + .periph_axi_m_axi_awaddr (periph_axi_m_axi_awaddr ), + .periph_axi_m_axi_awlen (periph_axi_m_axi_awlen ), + .periph_axi_m_axi_awsize (periph_axi_m_axi_awsize ), + .periph_axi_m_axi_awburst (periph_axi_m_axi_awburst), + .periph_axi_m_axi_awlock (periph_axi_m_axi_awlock ), + .periph_axi_m_axi_awcache (periph_axi_m_axi_awcache), + .periph_axi_m_axi_awprot (periph_axi_m_axi_awprot ), + .periph_axi_m_axi_awqos (periph_axi_m_axi_awqos ), + .periph_axi_m_axi_awvalid (periph_axi_m_axi_awvalid), + .periph_axi_m_axi_awready (periph_axi_m_axi_awready), + .periph_axi_m_axi_wdata (periph_axi_m_axi_wdata ), + .periph_axi_m_axi_wstrb (periph_axi_m_axi_wstrb ), + .periph_axi_m_axi_wlast (periph_axi_m_axi_wlast ), + .periph_axi_m_axi_wvalid (periph_axi_m_axi_wvalid ), + .periph_axi_m_axi_wready (periph_axi_m_axi_wready ), + .periph_axi_m_axi_bready (periph_axi_m_axi_bready ), + .periph_axi_m_axi_bid (periph_axi_m_axi_bid ), + .periph_axi_m_axi_bresp (periph_axi_m_axi_bresp ), + .periph_axi_m_axi_bvalid (periph_axi_m_axi_bvalid ), + .periph_axi_m_axi_arid (periph_axi_m_axi_arid ), + .periph_axi_m_axi_araddr (periph_axi_m_axi_araddr ), + .periph_axi_m_axi_arlen (periph_axi_m_axi_arlen ), + .periph_axi_m_axi_arsize (periph_axi_m_axi_arsize ), + .periph_axi_m_axi_arburst (periph_axi_m_axi_arburst), + .periph_axi_m_axi_arlock (periph_axi_m_axi_arlock ), + .periph_axi_m_axi_arcache (periph_axi_m_axi_arcache), + .periph_axi_m_axi_arprot (periph_axi_m_axi_arprot ), + .periph_axi_m_axi_arqos (periph_axi_m_axi_arqos ), + .periph_axi_m_axi_arvalid (periph_axi_m_axi_arvalid), + .periph_axi_m_axi_arready (periph_axi_m_axi_arready), + .periph_axi_m_axi_rready (periph_axi_m_axi_rready ), + .periph_axi_m_axi_rid (periph_axi_m_axi_rid ), + .periph_axi_m_axi_rdata (periph_axi_m_axi_rdata ), + .periph_axi_m_axi_rresp (periph_axi_m_axi_rresp ), + .periph_axi_m_axi_rlast (periph_axi_m_axi_rlast ), + .periph_axi_m_axi_rvalid (periph_axi_m_axi_rvalid ), // Peripheral axi - .periph_axi_s_axi_awid, - .periph_axi_s_axi_awaddr, - .periph_axi_s_axi_awlen, - .periph_axi_s_axi_awsize, - .periph_axi_s_axi_awburst, - .periph_axi_s_axi_awlock, - .periph_axi_s_axi_awcache, - .periph_axi_s_axi_awprot, - .periph_axi_s_axi_awqos, - .periph_axi_s_axi_awvalid, - .periph_axi_s_axi_awready, - .periph_axi_s_axi_wdata, - .periph_axi_s_axi_wstrb, - .periph_axi_s_axi_wlast, - .periph_axi_s_axi_wvalid, - .periph_axi_s_axi_wready, - .periph_axi_s_axi_bready, - .periph_axi_s_axi_bid, - .periph_axi_s_axi_bresp, - .periph_axi_s_axi_bvalid, - .periph_axi_s_axi_arid, - .periph_axi_s_axi_araddr, - .periph_axi_s_axi_arlen, - .periph_axi_s_axi_arsize, - .periph_axi_s_axi_arburst, - .periph_axi_s_axi_arlock, - .periph_axi_s_axi_arcache, - .periph_axi_s_axi_arprot, - .periph_axi_s_axi_arqos, - .periph_axi_s_axi_arvalid, - .periph_axi_s_axi_arready, - .periph_axi_s_axi_rready, - .periph_axi_s_axi_rid, - .periph_axi_s_axi_rdata, - .periph_axi_s_axi_rresp, - .periph_axi_s_axi_rlast, - .periph_axi_s_axi_rvalid + .periph_axi_s_axi_awid (periph_axi_s_axi_awid ), + .periph_axi_s_axi_awaddr (periph_axi_s_axi_awaddr ), + .periph_axi_s_axi_awlen (periph_axi_s_axi_awlen ), + .periph_axi_s_axi_awsize (periph_axi_s_axi_awsize ), + .periph_axi_s_axi_awburst (periph_axi_s_axi_awburst), + .periph_axi_s_axi_awlock (periph_axi_s_axi_awlock ), + .periph_axi_s_axi_awcache (periph_axi_s_axi_awcache), + .periph_axi_s_axi_awprot (periph_axi_s_axi_awprot ), + .periph_axi_s_axi_awqos (periph_axi_s_axi_awqos ), + .periph_axi_s_axi_awvalid (periph_axi_s_axi_awvalid), + .periph_axi_s_axi_awready (periph_axi_s_axi_awready), + .periph_axi_s_axi_wdata (periph_axi_s_axi_wdata ), + .periph_axi_s_axi_wstrb (periph_axi_s_axi_wstrb ), + .periph_axi_s_axi_wlast (periph_axi_s_axi_wlast ), + .periph_axi_s_axi_wvalid (periph_axi_s_axi_wvalid ), + .periph_axi_s_axi_wready (periph_axi_s_axi_wready ), + .periph_axi_s_axi_bready (periph_axi_s_axi_bready ), + .periph_axi_s_axi_bid (periph_axi_s_axi_bid ), + .periph_axi_s_axi_bresp (periph_axi_s_axi_bresp ), + .periph_axi_s_axi_bvalid (periph_axi_s_axi_bvalid ), + .periph_axi_s_axi_arid (periph_axi_s_axi_arid ), + .periph_axi_s_axi_araddr (periph_axi_s_axi_araddr ), + .periph_axi_s_axi_arlen (periph_axi_s_axi_arlen ), + .periph_axi_s_axi_arsize (periph_axi_s_axi_arsize ), + .periph_axi_s_axi_arburst (periph_axi_s_axi_arburst), + .periph_axi_s_axi_arlock (periph_axi_s_axi_arlock ), + .periph_axi_s_axi_arcache (periph_axi_s_axi_arcache), + .periph_axi_s_axi_arprot (periph_axi_s_axi_arprot ), + .periph_axi_s_axi_arqos (periph_axi_s_axi_arqos ), + .periph_axi_s_axi_arvalid (periph_axi_s_axi_arvalid), + .periph_axi_s_axi_arready (periph_axi_s_axi_arready), + .periph_axi_s_axi_rready (periph_axi_s_axi_rready ), + .periph_axi_s_axi_rid (periph_axi_s_axi_rid ), + .periph_axi_s_axi_rdata (periph_axi_s_axi_rdata ), + .periph_axi_s_axi_rresp (periph_axi_s_axi_rresp ), + .periph_axi_s_axi_rlast (periph_axi_s_axi_rlast ), + .periph_axi_s_axi_rvalid (periph_axi_s_axi_rvalid ) ); endmodule From a3b96bd679d2aabdd273764f6ade3e60422dcf14 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Tue, 18 Jun 2024 11:23:23 +0200 Subject: [PATCH 4/5] fpga: Adding hyperram CDC constraints --- .../xilinx/constraints/carfield_islands.tcl | 32 ++++++++++++++----- .../flavor_vanilla/src/carfield_top_xilinx.sv | 9 ++++++ .../flavor_vanilla/src/phy_definitions.svh | 16 +++------- 3 files changed, 37 insertions(+), 20 deletions(-) diff --git a/target/xilinx/constraints/carfield_islands.tcl b/target/xilinx/constraints/carfield_islands.tcl index bbd77c93..a123895b 100644 --- a/target/xilinx/constraints/carfield_islands.tcl +++ b/target/xilinx/constraints/carfield_islands.tcl @@ -41,13 +41,31 @@ handle_domain_clock_mux [get_cells -hier u_l2_clk_sel] 0 l2_domain_clk # Carfield CDCs # ################# -# Safety Island -################ +## Find the first parent cell of matching module from a list of object paths +## @param strs children objects paths +## @param ref_to_find the module type of the parent cell +proc find_parent_cell { strs ref_to_find } { + foreach str $strs { + set path "."; + foreach cell [split $str '/'] { + if {[get_cells -quiet $path] != ""} { + if { [get_property "ORIG_REF_NAME" [get_cell $path]] == $ref_to_find } { + return $path + } + if { [get_property "REF_NAME" [get_cell $path]] == $ref_to_find } { + return $path + } + } + set path $path/$cell; + } + } + return "" +} proc handle_slv_cdc { slv_cdc_path } { upvar SOC_TCK SOC_TCK # Start from a known slv cdc_dst and get fanout to find the mst cdc_src - set mst_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_slv_cdc_src|.*i_intcluster_slv_cdc} [lindex [filter [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] -filter {NAME =~ *gen_ext_slv_src_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0] + set mst_cdc_path [find_parent_cell [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] "axi_cdc_src"] if { $mst_cdc_path != "" } { set_max_delay -datapath \ -from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \ @@ -66,7 +84,6 @@ proc handle_slv_cdc { slv_cdc_path } { -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ "$SOC_TCK" } - } handle_slv_cdc [get_cells -hier gen_periph.i_cdc_dst_peripherals] @@ -76,12 +93,12 @@ handle_slv_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_in handle_slv_cdc [get_cells -hier gen_spatz_cluster.i_fp_cluster_wrapper]/i_spatz_cluster_cdc_dst handle_slv_cdc [get_cells -hier gen_pulp_cluster.i_integer_cluster]/axi_slave_cdc_i handle_slv_cdc [get_cells -hier gen_l2.i_reconfigurable_l2]/gen_cdc_fifos[0].i_dst_cdc +handle_slv_cdc [get_cells -hier i_hyperbus_wrap]/i_hyper_cdc_dst proc handle_mst_cdc { mst_cdc_path } { upvar SOC_TCK SOC_TCK - # Get the dst_cdc in cheshire - set slv_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_mst_cdc_dst|.*i_intcluster_mst_cdc} [lindex [filter [all_fanout -flat [get_pins $mst_cdc_path/*wptr*]] -filter {NAME =~ *gen_ext_mst_dst_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0] - + # Start from a known mst cdc_src and get fanout to find the slv cdc_dst + set slv_cdc_path [find_parent_cell [all_fanout -flat [get_pins $mst_cdc_path/*rptr*]] "axi_cdc_dst"] if { $slv_cdc_path != "" } { # From Safety Island master set_max_delay -datapath \ @@ -101,7 +118,6 @@ proc handle_mst_cdc { mst_cdc_path } { -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ "$SOC_TCK" } - } handle_mst_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_out diff --git a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv index 1d35fbd5..b16266de 100644 --- a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv @@ -151,6 +151,15 @@ module carfield_top_xilinx logic jtag_trst_ni; assign jtag_trst_ni = '1; `endif +`ifndef USE_JTAG + logic jtag_tck_i; + logic jtag_tms_i; + logic jtag_tdi_i; + logic jtag_tdo_o; + assign jtag_tck_i = '0; + assign jtag_tms_i = '0; + assign jtag_tdi_i = '0; +`endif ////////////////// // Clock Wizard // diff --git a/target/xilinx/flavor_vanilla/src/phy_definitions.svh b/target/xilinx/flavor_vanilla/src/phy_definitions.svh index 98ad955a..d2c76f98 100644 --- a/target/xilinx/flavor_vanilla/src/phy_definitions.svh +++ b/target/xilinx/flavor_vanilla/src/phy_definitions.svh @@ -6,8 +6,10 @@ `ifdef TARGET_VCU128 `define USE_RESET - `define USE_JTAG - `define USE_JTAG_VDDGND + `ifdef GEN_EXT_JTAG + `define USE_JTAG + `define USE_JTAG_VDDGND + `endif `define USE_QSPI `define USE_STARTUPE3 `define USE_VIO @@ -18,16 +20,6 @@ `endif `endif -`ifdef TARGET_ZCU102 - `define USE_RESET - `define USE_JTAG - `define HypNumChips 1 - `define HypNumPhys 1 - `ifdef GEN_NO_HYPERBUS - `define USE_DDR4 - `endif `define USE_VIO -`endif - ///////////////////// // DRAM INTERFACES // ///////////////////// From 44fb3e4cb81a36e7c39c9fd83872d5e211cb7eac Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Wed, 14 Aug 2024 11:14:54 +0200 Subject: [PATCH 5/5] fpga: Adding pads in vanilla --- .../flavor_bd/constraints/vcu128_hyperbus.xdc | 4 + .../constraints/vcu128_hyperbus.xdc | 42 +++++++ .../flavor_vanilla/src/carfield_top_xilinx.sv | 112 ++++++++++++++++-- 3 files changed, 146 insertions(+), 12 deletions(-) diff --git a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc index daffcb34..0b53777a 100644 --- a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc @@ -5,7 +5,11 @@ # Cyril Koenig set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O}] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O] +############ +# Hyperbus # +############ #set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 #set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 diff --git a/target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc b/target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc index 65cb267a..014675ac 100644 --- a/target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc +++ b/target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc @@ -5,6 +5,48 @@ # Cyril Koenig set_property CLOCK_DEDICATED_ROUTE FALSE [get_ports pad_hyper_rwds[0]] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O] + + +set period_hyperbus 100 + +create_clock -period [expr $period_hyperbus] -name hyper_rwds_clk [get_ports pad_hyper_rwds[0]] + +create_generated_clock -name hyper_clk_phy -source [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/CLK] -divide_by 2 [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/clock_generator.ddr_clk/r_clk0_o_reg/Q] +create_generated_clock -name hyper_clk_phy_90 -source [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/CLK] -edges {2 4 6} [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/clock_generator.ddr_clk/r_clk90_o_reg/Q] + +set clk_rwds_delayed_pin [get_pins -of_objects [get_cells i_carfield/i_hyperbus_wrap/i_hyperbus/i_phy/i_phy/i_trx/i_delay_rx_rwds_90/i_delay] -filter {DIRECTION =~ OUT}] +set clk_rwds_delayed_inv_pin [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/i_phy/i_phy/i_trx/i_rx_rwds_cdc_fifo/CLK] + +set clk_rx_shift [expr $period_hyperbus/10] +set rwds_input_delay [expr $period_hyperbus/4] +create_generated_clock -name hyper_clk_rwds_delayed0 -edges {1 2 3} -edge_shift "$clk_rx_shift $clk_rx_shift $clk_rx_shift" \ + -source [get_ports pad_hyper_rwds[0]] $clk_rwds_delayed_pin +set_clock_latency [expr ${rwds_input_delay}] hyper_clk_rwds_delayed0 + +create_generated_clock -name hyper_clk_rwds_sample0 -invert -divide_by 1 -source $clk_rwds_delayed_pin $clk_rwds_delayed_inv_pin +set_clock_latency [expr ${rwds_input_delay}] hyper_clk_rwds_sample0 + +set_false_path -from [get_ports pad_hyper_rwds[0]] -to [get_ports pad_hyper_rwds[0]] +# these are for clock domain crossing +set_false_path -from [get_clocks hyper_rwds_clk] -to [get_clocks hyper_clk_phy] +set_false_path -from [get_clocks hyper_clk_phy] -to [get_clocks hyper_rwds_clk] +set_false_path -from [get_clocks hyper_clk_phy_90] -to [get_clocks hyper_clk_phy] +set_false_path -from [get_clocks hyper_clk_phy_90] -to [get_clocks hyper_rwds_clk] + +# Todo correct build correct input / output constraints + +set hyper_output_ports [get_ports pad_hyper_dq*] +set_output_delay [expr $period_hyperbus/2 ] -clock hyper_clk_phy [get_ports $hyper_output_ports] -max +set_output_delay [expr $period_hyperbus/-2] -clock hyper_clk_phy [get_ports $hyper_output_ports] -min -add_delay +set_output_delay [expr $period_hyperbus/2 ] -clock hyper_clk_phy [get_ports $hyper_output_ports] -max -clock_fall -add_delay +set_output_delay [expr $period_hyperbus/-2] -clock hyper_clk_phy [get_ports $hyper_output_ports] -min -clock_fall -add_delay + +set hyper_input_ports [get_ports -regexp pad_hyper_dq.*] +set_input_delay -max [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] +set_input_delay -min [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay +set_input_delay -max [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay -clock_fall +set_input_delay -min [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay -clock_fall #set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 #set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 diff --git a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv index b16266de..5a679991 100644 --- a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv @@ -121,7 +121,7 @@ module carfield_top_xilinx `elsif USE_RESETN logic cpu_reset; assign cpu_reset = ~cpu_resetn; - `endif + `endif // USE_RESET logic sys_rst; wire clk_100, clk_50, clk_20; @@ -140,17 +140,17 @@ module carfield_top_xilinx assign testmode_i = '0; assign boot_mode_i = 2'b00; assign boot_mode_safety_i = 2'b00; -`endif +`endif // USE_SWITCHES // Give VDD and GND to JTAG `ifdef USE_JTAG_VDDGND assign jtag_vdd_o = '1; assign jtag_gnd_o = '0; -`endif +`endif // USE_JTAG_VDDGND `ifndef USE_JTAG_TRSTN logic jtag_trst_ni; assign jtag_trst_ni = '1; -`endif +`endif // USE_JTAG_TRSTN `ifndef USE_JTAG logic jtag_tck_i; logic jtag_tms_i; @@ -159,7 +159,7 @@ module carfield_top_xilinx assign jtag_tck_i = '0; assign jtag_tms_i = '0; assign jtag_tdi_i = '0; -`endif +`endif // USE_JTAG ////////////////// // Clock Wizard // @@ -227,11 +227,11 @@ module carfield_top_xilinx assign sys_rst = cpu_reset | vio_reset; assign boot_mode = boot_mode_i | vio_boot_mode; assign boot_mode_safety = boot_mode_safety_i | vio_boot_mode_safety; -`else +`else // USE_VIO assign sys_rst = cpu_reset; assign boot_mode = boot_mode_i; assign boot_mode_safety = boot_mode_safety_i; -`endif +`endif // USE_VIO ////////////////// // I2C Adaption // @@ -275,7 +275,7 @@ module carfield_top_xilinx .I ( i2c_sda_soc_out ), .T ( ~i2c_sda_en ) ); -`endif +`endif // USE_I2C ////////////////// @@ -403,7 +403,7 @@ module carfield_top_xilinx .pwm_setting_i ( fan_sw ), .fan_pwm_o ( fan_pwm ) ); -`endif +`endif // USE_FAN ////////////////// // Carfield Cfg // @@ -417,6 +417,7 @@ module carfield_top_xilinx /////////////////// `ifdef GEN_NO_HYPERBUS // bender-xilinx.mk + localparam axi_in_t AxiIn = gen_axi_in(Cfg); localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth+$clog2(AxiIn.num_in)+Cfg.LlcNotBypass; localparam int unsigned LlcArWidth = (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth,LlcIdWidth,Cfg.AxiUserWidth); @@ -475,6 +476,82 @@ module carfield_top_xilinx .dst_req_o ( llc_req ), .dst_resp_i ( llc_rsp ) ); +`endif // GEN_NO_HYPERBUS + + /////////////////// + // Hyperram PADS // + /////////////////// + +`ifndef GEN_NO_HYPERBUS + +logic [`HypNumPhys-1:0][`HypNumChips-1:0] hyper_cs_no; +logic [`HypNumPhys-1:0] hyper_ck_o; +logic [`HypNumPhys-1:0] hyper_ck_no; +logic [`HypNumPhys-1:0] hyper_rwds_o; +logic [`HypNumPhys-1:0] hyper_rwds_i; +logic [`HypNumPhys-1:0] hyper_rwds_oe_o; +logic [`HypNumPhys-1:0][7:0] hyper_dq_i; +logic [`HypNumPhys-1:0][7:0] hyper_dq_o; +logic [`HypNumPhys-1:0] hyper_dq_oe_o; +logic [`HypNumPhys-1:0] hyper_reset_no; + +for (genvar i = 0 ; i < `HypNumPhys; i++) begin : gen_hyper_phy + + for (genvar j = 0; j < `HypNumChips; j++) begin : gen_hyper_cs + pad_functional_pd padinst_hyper_csno ( + .OEN ( 1'b0 ), + .I ( hyper_cs_no[i][j] ), + .O ( ), + .PEN ( ), + .PAD ( pad_hyper_csn[i][j] ) + ); + end // gen_hyper_cs + + pad_functional_pd padinst_hyper_ck ( + .OEN ( 1'b0 ), + .I ( hyper_ck_o[i] ), + .O ( ), + .PEN ( ), + .PAD ( pad_hyper_ck[i] ) + ); + pad_functional_pd padinst_hyper_ckno ( + .OEN ( 1'b0 ), + .I ( hyper_ck_no[i] ), + .O ( ), + .PEN ( ), + .PAD ( pad_hyper_ckn[i] ) + ); + pad_functional_pd padinst_hyper_rwds0 ( + .OEN ( ~hyper_rwds_oe_o[i] ), + .I ( hyper_rwds_o[i] ), + .O ( hyper_rwds_i[i] ), + .PEN ( ), + .PAD ( pad_hyper_rwds[i] ) + ); + + for (genvar j = 0; j < 8; j++) begin : gen_hyper_dq + pad_functional_pd padinst_hyper_dqio0 ( + .OEN ( ~hyper_dq_oe_o[i] ), + .I ( hyper_dq_o[i][j] ), + .O ( hyper_dq_i[i][j] ), + .PEN ( ), + .PAD ( pad_hyper_dq[i][j] ) + ); + end // gen_hyper_dq + +end // gen_hyper_phy + + `ila(ila_hyper_cs_n , hyper_cs_no ) + `ila(ila_hyper_ck , hyper_ck_o ) + `ila(ila_hyper_ck_n , hyper_ck_no ) + `ila(ila_hyper_rwds_o , hyper_rwds_o ) + `ila(ila_hyper_rwds_i , hyper_rwds_i ) + `ila(ila_hyper_rwds_oe_o , hyper_rwds_oe_o ) + `ila(ila_hyper_dq_i , hyper_dq_i ) + `ila(ila_hyper_dq_o , hyper_dq_o ) + `ila(ila_hyper_dq_oe , hyper_dq_oe_o ) + `ila(ila_hyper_reset_n , hyper_reset_no ) + `endif // GEN_NO_HYPERBUS ////////////////// @@ -494,7 +571,7 @@ module carfield_top_xilinx .LlcBWidth ( LlcBWidth ), .LlcRWidth ( LlcRWidth ), .LlcWWidth ( LlcWWidth ), -`endif +`endif // GEN_NO_HYPERBUS .HypNumPhys (`HypNumPhys), .HypNumChips (`HypNumChips) ) i_carfield ( @@ -576,7 +653,18 @@ module carfield_top_xilinx .llc_w_data, .llc_w_wptr, .llc_w_rptr, -`endif +`else // GEN_NO_HYPERBUS + .hyper_cs_no, + .hyper_ck_o, + .hyper_ck_no, + .hyper_rwds_o, + .hyper_rwds_i, + .hyper_rwds_oe_o, + .hyper_dq_i, + .hyper_dq_o, + .hyper_dq_oe_o, + .hyper_reset_no, +`endif // GEN_NO_HYPERBUS // Serial link interface .slink_rcv_clk_i (), .slink_rcv_clk_o (), @@ -610,6 +698,6 @@ module carfield_top_xilinx // Phy .* ); -`endif +`endif // USE_DDR endmodule