From 9fe29b4ba53612ad7b2c01a018a9e5be932a57ad Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 9 Mar 2024 15:19:44 +0100 Subject: [PATCH 01/48] Integrate HMR unit for CVA6 redundancy. --- Bender.lock | 36 +- Bender.yml | 4 +- hw/bootrom/cheshire_bootrom.sv | 3574 ++++++++++++++++---------------- hw/cheshire_pkg.sv | 45 +- hw/cheshire_soc.sv | 175 +- hw/cva6_wrap.sv | 225 ++ hw/regs/cheshire_reg_pkg.sv | 19 +- hw/regs/cheshire_reg_top.sv | 46 +- hw/regs/cheshire_regs.hjson | 9 + sw/include/cheshire_io.h | 11 + sw/include/dif/uart.h | 4 +- sw/include/init.h | 7 + sw/include/params.h | 1 + sw/include/regs/axi_llc.h | 68 + sw/include/regs/cheshire.h | 3 + sw/include/smp.h | 18 +- sw/include/util.h | 30 + sw/lib/cheshire_io.c | 19 + sw/lib/crt0.S | 18 +- sw/lib/dif/uart.c | 13 +- sw/lib/init.c | 14 + sw/link/common.ldh | 1 + 22 files changed, 2453 insertions(+), 1887 deletions(-) create mode 100644 hw/cva6_wrap.sv create mode 100644 sw/include/cheshire_io.h create mode 100644 sw/include/init.h create mode 100644 sw/lib/cheshire_io.c create mode 100644 sw/lib/init.c diff --git a/Bender.lock b/Bender.lock index 293fc657..57b2db7e 100644 --- a/Bender.lock +++ b/Bender.lock @@ -18,16 +18,16 @@ packages: revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2 version: 0.39.2 source: - Git: https://github.com/pulp-platform/axi.git + Git: https://github.com/pulp-platform/axi dependencies: - common_cells - common_verification - tech_cells_generic axi_llc: - revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39 - version: 0.2.1 + revision: d79a00b8673b814efacbbe9bf106103407fc401b + version: null source: - Git: https://github.com/pulp-platform/axi_llc.git + Git: https://github.com/pulp-platform/axi_llc dependencies: - axi - common_cells @@ -62,8 +62,8 @@ packages: - common_cells - register_interface clic: - revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf - version: 2.0.0 + revision: bf6032e1ea30f3a502aa85906520dece53626eb9 + version: 3.0.0-rc4 source: Git: https://github.com/pulp-platform/clic.git dependencies: @@ -92,7 +92,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: - revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5 + revision: dbaecc59b99e3bb4d89fed546d75080f39bfe4f1 version: null source: Git: https://github.com/pulp-platform/cva6.git @@ -100,6 +100,7 @@ packages: - axi - common_cells - fpnew + - redundancy_cells - tech_cells_generic fpnew: revision: f231041c610f270ffc03cbdac38739ddb6426572 @@ -144,6 +145,16 @@ packages: - common_cells - register_interface - tech_cells_generic + redundancy_cells: + revision: c37bdb47339bf70e8323de8df14ea8bbeafb6583 + version: null + source: + Git: https://github.com/pulp-platform/redundancy_cells.git + dependencies: + - common_cells + - common_verification + - register_interface + - tech_cells_generic register_interface: revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19 version: 0.4.3 @@ -171,6 +182,17 @@ packages: - axi - common_cells - register_interface + tagger: + revision: b288376b65b6bbd5feea196bb3c220f783d96e29 + version: null + source: + Git: https://github.com/pulp-platform/transaction-tagger.git + dependencies: + - axi + - common_cells + - common_verification + - register_interface + - tech_cells_generic tech_cells_generic: revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf version: 0.2.13 diff --git a/Bender.yml b/Bender.yml index fc2ce82e..0f14a2a0 100644 --- a/Bender.yml +++ b/Bender.yml @@ -23,13 +23,14 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 } - iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 } + iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.6.2 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "bf5fc00" } # branch: cl/eth_idma export_include_dirs: - hw/include @@ -39,6 +40,7 @@ sources: - hw/regs/cheshire_reg_pkg.sv - hw/regs/cheshire_reg_top.sv - hw/cheshire_pkg.sv + - hw/cva6_wrap.sv - hw/cheshire_soc.sv - target: any(simulation, test) diff --git a/hw/bootrom/cheshire_bootrom.sv b/hw/bootrom/cheshire_bootrom.sv index 072d4ee4..a1b81e7a 100644 --- a/hw/bootrom/cheshire_bootrom.sv +++ b/hw/bootrom/cheshire_bootrom.sv @@ -46,12 +46,12 @@ module cheshire_bootrom #( 014: data_o = 32'h43214f81 /* 0x0038 */; 015: data_o = 32'h30431073 /* 0x003c */; 016: data_o = 32'h23734281 /* 0x0040 */; - 017: data_o = 32'h9663f140 /* 0x0044 */; + 017: data_o = 32'h9e63f140 /* 0x0044 */; 018: data_o = 32'h01170a62 /* 0x0048 */; 019: data_o = 32'h01130e01 /* 0x004c */; 020: data_o = 32'h2197fae1 /* 0x0050 */; 021: data_o = 32'h81930000 /* 0x0054 */; - 022: data_o = 32'h0297ada1 /* 0x0058 */; + 022: data_o = 32'h0297aea1 /* 0x0058 */; 023: data_o = 32'h82930100 /* 0x005c */; 024: data_o = 32'ha283fa62 /* 0x0060 */; 025: data_o = 32'hf2930502 /* 0x0064 */; @@ -73,7 +73,7 @@ module cheshire_bootrom #( 041: data_o = 32'h02971161 /* 0x00a4 */; 042: data_o = 32'h82930100 /* 0x00a8 */; 043: data_o = 32'ha283f5a2 /* 0x00ac */; - 044: data_o = 32'h81630482 /* 0x00b0 */; + 044: data_o = 32'h89630482 /* 0x00b0 */; 045: data_o = 32'h92820a02 /* 0x00b4 */; 046: data_o = 32'h01000297 /* 0x00b8 */; 047: data_o = 32'hf4828293 /* 0x00bc */; @@ -85,1800 +85,1800 @@ module cheshire_bootrom #( 053: data_o = 32'h0397f322 /* 0x00d4 */; 054: data_o = 32'h83930100 /* 0x00d8 */; 055: data_o = 32'ha383f2a3 /* 0x00dc */; - 056: data_o = 32'h038a04c3 /* 0x00e0 */; - 057: data_o = 32'h43059396 /* 0x00e4 */; - 058: data_o = 32'h0062a023 /* 0x00e8 */; - 059: data_o = 32'hcce30291 /* 0x00ec */; - 060: data_o = 32'h0073fe72 /* 0x00f0 */; - 061: data_o = 32'h23731050 /* 0x00f4 */; - 062: data_o = 32'h73133440 /* 0x00f8 */; - 063: data_o = 32'h0ae30083 /* 0x00fc */; - 064: data_o = 32'h0297fe03 /* 0x0100 */; - 065: data_o = 32'h82930004 /* 0x0104 */; - 066: data_o = 32'h2373efe2 /* 0x0108 */; - 067: data_o = 32'h030af140 /* 0x010c */; - 068: data_o = 32'h20239316 /* 0x0110 */; - 069: data_o = 32'h03970003 /* 0x0114 */; - 070: data_o = 32'h83930100 /* 0x0118 */; - 071: data_o = 32'ha383eea3 /* 0x011c */; - 072: data_o = 32'h038a04c3 /* 0x0120 */; - 073: data_o = 32'ha3039396 /* 0x0124 */; - 074: data_o = 32'h1ee30002 /* 0x0128 */; - 075: data_o = 32'h0291fe03 /* 0x012c */; - 076: data_o = 32'hfe72cbe3 /* 0x0130 */; - 077: data_o = 32'h01000297 /* 0x0134 */; - 078: data_o = 32'hecc28293 /* 0x0138 */; - 079: data_o = 32'h0142e303 /* 0x013c */; - 080: data_o = 32'he2831302 /* 0x0140 */; - 081: data_o = 32'he2b30102 /* 0x0144 */; - 082: data_o = 32'h25730062 /* 0x0148 */; - 083: data_o = 32'h80e7f140 /* 0x014c */; - 084: data_o = 32'h80820002 /* 0x0150 */; - 085: data_o = 32'h43014281 /* 0x0154 */; - 086: data_o = 32'h0ff0000f /* 0x0158 */; - 087: data_o = 32'h0000100f /* 0x015c */; - 088: data_o = 32'h3ee010ef /* 0x0160 */; - 089: data_o = 32'h65130506 /* 0x0164 */; - 090: data_o = 32'h02970015 /* 0x0168 */; - 091: data_o = 32'h82930100 /* 0x016c */; - 092: data_o = 32'ha423e962 /* 0x0170 */; - 093: data_o = 32'h007300a2 /* 0x0174 */; - 094: data_o = 32'hbff51050 /* 0x0178 */; - 095: data_o = 32'h0185171b /* 0x017c */; - 096: data_o = 32'h0185579b /* 0x0180 */; - 097: data_o = 32'h8fd966c1 /* 0x0184 */; - 098: data_o = 32'hf0068693 /* 0x0188 */; - 099: data_o = 32'h0085571b /* 0x018c */; - 100: data_o = 32'h8fd98f75 /* 0x0190 */; - 101: data_o = 32'h0085151b /* 0x0194 */; - 102: data_o = 32'h00ff0737 /* 0x0198 */; - 103: data_o = 32'h8d5d8d79 /* 0x019c */; - 104: data_o = 32'h80822501 /* 0x01a0 */; - 105: data_o = 32'hca09832a /* 0x01a4 */; - 106: data_o = 32'h00058383 /* 0x01a8 */; - 107: data_o = 32'h00730023 /* 0x01ac */; - 108: data_o = 32'h0305167d /* 0x01b0 */; - 109: data_o = 32'hfa6d0585 /* 0x01b4 */; - 110: data_o = 32'h66b18082 /* 0x01b8 */; - 111: data_o = 32'h00040797 /* 0x01bc */; - 112: data_o = 32'h00040717 /* 0x01c0 */; - 113: data_o = 32'he4478793 /* 0x01c4 */; - 114: data_o = 32'he4070713 /* 0x01c8 */; - 115: data_o = 32'h973697b6 /* 0x01cc */; - 116: data_o = 32'hffc7a783 /* 0x01d0 */; - 117: data_o = 32'hff872703 /* 0x01d4 */; - 118: data_o = 32'h17021782 /* 0x01d8 */; - 119: data_o = 32'h8fd99301 /* 0x01dc */; - 120: data_o = 32'hfca7eee3 /* 0x01e0 */; - 121: data_o = 32'hc5298082 /* 0x01e4 */; - 122: data_o = 32'h4789ee9d /* 0x01e8 */; - 123: data_o = 32'h04f60963 /* 0x01ec */; - 124: data_o = 32'h0163478d /* 0x01f0 */; - 125: data_o = 32'h167d04f6 /* 0x01f4 */; - 126: data_o = 32'h00c03633 /* 0x01f8 */; - 127: data_o = 32'h47014801 /* 0x01fc */; - 128: data_o = 32'h00c6969b /* 0x0200 */; - 129: data_o = 32'h00d5e7b3 /* 0x0204 */; - 130: data_o = 32'h0086161b /* 0x0208 */; - 131: data_o = 32'h181b8fd1 /* 0x020c */; - 132: data_o = 32'h611400a8 /* 0x0210 */; - 133: data_o = 32'h0107e7b3 /* 0x0214 */; - 134: data_o = 32'h0097171b /* 0x0218 */; - 135: data_o = 32'h27818fd9 /* 0x021c */; - 136: data_o = 32'h4501cedc /* 0x0220 */; - 137: data_o = 32'h079b8082 /* 0x0224 */; - 138: data_o = 32'h4709ffd6 /* 0x0228 */; - 139: data_o = 32'hfaf76fe3 /* 0x022c */; - 140: data_o = 32'h8082450d /* 0x0230 */; - 141: data_o = 32'h4601fef5 /* 0x0234 */; - 142: data_o = 32'h47014805 /* 0x0238 */; - 143: data_o = 32'h4801b7d1 /* 0x023c */; - 144: data_o = 32'h46014705 /* 0x0240 */; - 145: data_o = 32'h7159bf75 /* 0x0244 */; - 146: data_o = 32'he8caf0a2 /* 0x0248 */; - 147: data_o = 32'he0d2e4ce /* 0x024c */; - 148: data_o = 32'hf85afc56 /* 0x0250 */; - 149: data_o = 32'hf062f45e /* 0x0254 */; - 150: data_o = 32'heca6f486 /* 0x0258 */; - 151: data_o = 32'he86aec66 /* 0x025c */; - 152: data_o = 32'h8936e46e /* 0x0260 */; - 153: data_o = 32'h89ae842a /* 0x0264 */; - 154: data_o = 32'h8b3a8ab2 /* 0x0268 */; - 155: data_o = 32'hfff68b93 /* 0x026c */; - 156: data_o = 32'h0c136a31 /* 0x0270 */; - 157: data_o = 32'h0b630200 /* 0x0274 */; - 158: data_o = 32'h60040e04 /* 0x0278 */; - 159: data_o = 32'hf51350dc /* 0x027c */; - 160: data_o = 32'h278107f7 /* 0x0280 */; - 161: data_o = 32'hd71bf96d /* 0x0284 */; - 162: data_o = 32'hd51b0107 /* 0x0288 */; - 163: data_o = 32'h8d590087 /* 0x028c */; - 164: data_o = 32'h0187d79b /* 0x0290 */; - 165: data_o = 32'hf7938fc9 /* 0x0294 */; - 166: data_o = 32'hfff107f7 /* 0x0298 */; - 167: data_o = 32'h00040717 /* 0x029c */; - 168: data_o = 32'h00040797 /* 0x02a0 */; - 169: data_o = 32'hd6470713 /* 0x02a4 */; - 170: data_o = 32'hd6078793 /* 0x02a8 */; - 171: data_o = 32'h97d29752 /* 0x02ac */; - 172: data_o = 32'hffc72683 /* 0x02b0 */; - 173: data_o = 32'hff87a783 /* 0x02b4 */; - 174: data_o = 32'h17821682 /* 0x02b8 */; - 175: data_o = 32'h8edd9381 /* 0x02bc */; - 176: data_o = 32'h07970685 /* 0x02c0 */; - 177: data_o = 32'h05170004 /* 0x02c4 */; - 178: data_o = 32'h87930004 /* 0x02c8 */; - 179: data_o = 32'h0513d3e7 /* 0x02cc */; - 180: data_o = 32'h97d2d3a5 /* 0x02d0 */; - 181: data_o = 32'ha7839552 /* 0x02d4 */; - 182: data_o = 32'h2703ffc7 /* 0x02d8 */; - 183: data_o = 32'h1782ff85 /* 0x02dc */; - 184: data_o = 32'h93011702 /* 0x02e0 */; - 185: data_o = 32'heee38fd9 /* 0x02e4 */; - 186: data_o = 32'h489cfcd7 /* 0x02e8 */; - 187: data_o = 32'h46014685 /* 0x02ec */; - 188: data_o = 32'hc89c9bf9 /* 0x02f0 */; - 189: data_o = 32'h0a000593 /* 0x02f4 */; - 190: data_o = 32'hf0ef8522 /* 0x02f8 */; - 191: data_o = 32'h0c9beedf /* 0x02fc */; - 192: data_o = 32'h96630005 /* 0x0300 */; - 193: data_o = 32'hd593060c /* 0x0304 */; - 194: data_o = 32'h4685008a /* 0x0308 */; - 195: data_o = 32'hf5934605 /* 0x030c */; - 196: data_o = 32'h85220ff5 /* 0x0310 */; - 197: data_o = 32'hed3ff0ef /* 0x0314 */; - 198: data_o = 32'h00050c9b /* 0x0318 */; - 199: data_o = 32'h040c9963 /* 0x031c */; - 200: data_o = 32'h0ffaf593 /* 0x0320 */; - 201: data_o = 32'h060b0563 /* 0x0324 */; - 202: data_o = 32'h46054685 /* 0x0328 */; - 203: data_o = 32'hf0ef8522 /* 0x032c */; - 204: data_o = 32'h079beb9f /* 0x0330 */; - 205: data_o = 32'heb8d0005 /* 0x0334 */; - 206: data_o = 32'h74638d5e /* 0x0338 */; - 207: data_o = 32'h0d13017c /* 0x033c */; - 208: data_o = 32'h4d810200 /* 0x0340 */; - 209: data_o = 32'h000b9563 /* 0x0344 */; - 210: data_o = 32'hf563a075 /* 0x0348 */; - 211: data_o = 32'h87b30bad /* 0x034c */; - 212: data_o = 32'hc58301b9 /* 0x0350 */; - 213: data_o = 32'h46850007 /* 0x0354 */; - 214: data_o = 32'h85224605 /* 0x0358 */; - 215: data_o = 32'he8bff0ef /* 0x035c */; - 216: data_o = 32'h0005079b /* 0x0360 */; - 217: data_o = 32'hd3f50d85 /* 0x0364 */; - 218: data_o = 32'ha0118cbe /* 0x0368 */; - 219: data_o = 32'h70a64c8d /* 0x036c */; - 220: data_o = 32'h64e67406 /* 0x0370 */; - 221: data_o = 32'h69a66946 /* 0x0374 */; - 222: data_o = 32'h7ae26a06 /* 0x0378 */; - 223: data_o = 32'h7ba27b42 /* 0x037c */; - 224: data_o = 32'h6d427c02 /* 0x0380 */; - 225: data_o = 32'h85666da2 /* 0x0384 */; - 226: data_o = 32'h61656ce2 /* 0x0388 */; - 227: data_o = 32'h46858082 /* 0x038c */; - 228: data_o = 32'h85224609 /* 0x0390 */; - 229: data_o = 32'he53ff0ef /* 0x0394 */; - 230: data_o = 32'h0005079b /* 0x0398 */; - 231: data_o = 32'h4685f7f1 /* 0x039c */; - 232: data_o = 32'h05934601 /* 0x03a0 */; - 233: data_o = 32'h85220a10 /* 0x03a4 */; - 234: data_o = 32'he3fff0ef /* 0x03a8 */; - 235: data_o = 32'h0005079b /* 0x03ac */; - 236: data_o = 32'h4681ffc5 /* 0x03b0 */; - 237: data_o = 32'h7593460d /* 0x03b4 */; - 238: data_o = 32'h85220ff9 /* 0x03b8 */; - 239: data_o = 32'he2bff0ef /* 0x03bc */; - 240: data_o = 32'h0005079b /* 0x03c0 */; - 241: data_o = 32'h489cf3d5 /* 0x03c4 */; - 242: data_o = 32'h0017e793 /* 0x03c8 */; - 243: data_o = 32'h50dcc89c /* 0x03cc */; - 244: data_o = 32'h0107d79b /* 0x03d0 */; - 245: data_o = 32'h07f7f793 /* 0x03d4 */; - 246: data_o = 32'hff27ebe3 /* 0x03d8 */; - 247: data_o = 32'h601c994e /* 0x03dc */; - 248: data_o = 32'h27814f9c /* 0x03e0 */; - 249: data_o = 32'h00098463 /* 0x03e4 */; - 250: data_o = 32'h00f98023 /* 0x03e8 */; - 251: data_o = 32'h18e30985 /* 0x03ec */; - 252: data_o = 32'hbfb5ff39 /* 0x03f0 */; - 253: data_o = 32'h017987b3 /* 0x03f4 */; - 254: data_o = 32'h0007c583 /* 0x03f8 */; - 255: data_o = 32'h46054685 /* 0x03fc */; - 256: data_o = 32'hf0ef8522 /* 0x0400 */; - 257: data_o = 32'h079bde5f /* 0x0404 */; - 258: data_o = 32'hffb90005 /* 0x0408 */; - 259: data_o = 32'h1b81489c /* 0x040c */; - 260: data_o = 32'h0017e793 /* 0x0410 */; - 261: data_o = 32'h7ce3c89c /* 0x0414 */; - 262: data_o = 32'h99caf52c /* 0x0418 */; - 263: data_o = 32'h19019aca /* 0x041c */; - 264: data_o = 32'h7139bd99 /* 0x0420 */; - 265: data_o = 32'hf426f822 /* 0x0424 */; - 266: data_o = 32'hec4ef04a /* 0x0428 */; - 267: data_o = 32'hfc06e852 /* 0x042c */; - 268: data_o = 32'h7413e456 /* 0x0430 */; - 269: data_o = 32'h893203f6 /* 0x0434 */; - 270: data_o = 32'h8a2e89aa /* 0x0438 */; - 271: data_o = 32'he42184b6 /* 0x043c */; - 272: data_o = 32'h04000a93 /* 0x0440 */; - 273: data_o = 32'h00946563 /* 0x0444 */; - 274: data_o = 32'h7c63a82d /* 0x0448 */; - 275: data_o = 32'h86b30294 /* 0x044c */; - 276: data_o = 32'h06334084 /* 0x0450 */; - 277: data_o = 32'h05b30089 /* 0x0454 */; - 278: data_o = 32'h4701008a /* 0x0458 */; - 279: data_o = 32'h0413854e /* 0x045c */; - 280: data_o = 32'hf4630404 /* 0x0460 */; - 281: data_o = 32'h069300da /* 0x0464 */; - 282: data_o = 32'hf0ef0400 /* 0x0468 */; - 283: data_o = 32'hdd71dddf /* 0x046c */; - 284: data_o = 32'h744270e2 /* 0x0470 */; - 285: data_o = 32'h790274a2 /* 0x0474 */; - 286: data_o = 32'h6a4269e2 /* 0x0478 */; - 287: data_o = 32'h61216aa2 /* 0x047c */; - 288: data_o = 32'h45018082 /* 0x0480 */; - 289: data_o = 32'h0793b7f5 /* 0x0484 */; - 290: data_o = 32'h84330400 /* 0x0488 */; - 291: data_o = 32'h47014087 /* 0x048c */; - 292: data_o = 32'hf0ef86a2 /* 0x0490 */; - 293: data_o = 32'hd54ddb5f /* 0x0494 */; - 294: data_o = 32'h1141bfe1 /* 0x0498 */; - 295: data_o = 32'he432e02e /* 0x049c */; - 296: data_o = 32'h9581c141 /* 0x04a0 */; - 297: data_o = 32'h4782cdb5 /* 0x04a4 */; - 298: data_o = 32'hd5bbcfa5 /* 0x04a8 */; - 299: data_o = 32'h77c102f5 /* 0x04ac */; - 300: data_o = 32'h269988aa /* 0x04b0 */; - 301: data_o = 32'h0026969b /* 0x04b4 */; - 302: data_o = 32'h0015d59b /* 0x04b8 */; - 303: data_o = 32'h8fed35fd /* 0x04bc */; - 304: data_o = 32'h0007851b /* 0x04c0 */; - 305: data_o = 32'h4783ed31 /* 0x04c4 */; - 306: data_o = 32'h4e0300c1 /* 0x04c8 */; - 307: data_o = 32'h430300b1 /* 0x04cc */; - 308: data_o = 32'h480300d1 /* 0x04d0 */; - 309: data_o = 32'h46030081 /* 0x04d4 */; - 310: data_o = 32'h979b0091 /* 0x04d8 */; - 311: data_o = 32'h1e1b01e7 /* 0x04dc */; - 312: data_o = 32'h470301de /* 0x04e0 */; - 313: data_o = 32'he7b300a1 /* 0x04e4 */; - 314: data_o = 32'h131b01c7 /* 0x04e8 */; - 315: data_o = 32'h781301f3 /* 0x04ec */; - 316: data_o = 32'he7b300f8 /* 0x04f0 */; - 317: data_o = 32'h8fcd0067 /* 0x04f4 */; - 318: data_o = 32'h159b8a3d /* 0x04f8 */; - 319: data_o = 32'h8fcd0108 /* 0x04fc */; - 320: data_o = 32'h0008b803 /* 0x0500 */; - 321: data_o = 32'h0146161b /* 0x0504 */; - 322: data_o = 32'h171b8b3d /* 0x0508 */; - 323: data_o = 32'h8fd10187 /* 0x050c */; - 324: data_o = 32'h8fd91682 /* 0x0510 */; - 325: data_o = 32'h27819281 /* 0x0514 */; - 326: data_o = 32'h00d80733 /* 0x0518 */; - 327: data_o = 32'ha011c31c /* 0x051c */; - 328: data_o = 32'h0141450d /* 0x0520 */; - 329: data_o = 32'h65858082 /* 0x0524 */; - 330: data_o = 32'h9c458593 /* 0x0528 */; - 331: data_o = 32'h02b555b3 /* 0x052c */; - 332: data_o = 32'h00040797 /* 0x0530 */; - 333: data_o = 32'h00040697 /* 0x0534 */; - 334: data_o = 32'h86936731 /* 0x0538 */; - 335: data_o = 32'h8793acc6 /* 0x053c */; - 336: data_o = 32'h97baad07 /* 0x0540 */; - 337: data_o = 32'ha6039736 /* 0x0544 */; - 338: data_o = 32'h2783ffc7 /* 0x0548 */; - 339: data_o = 32'h66b1ff87 /* 0x054c */; - 340: data_o = 32'h17821602 /* 0x0550 */; - 341: data_o = 32'h8e5d9381 /* 0x0554 */; - 342: data_o = 32'hb0002873 /* 0x0558 */; - 343: data_o = 32'h00040717 /* 0x055c */; - 344: data_o = 32'h00040797 /* 0x0560 */; - 345: data_o = 32'haa470713 /* 0x0564 */; - 346: data_o = 32'haa078793 /* 0x0568 */; - 347: data_o = 32'h97b69736 /* 0x056c */; - 348: data_o = 32'hffc72703 /* 0x0570 */; - 349: data_o = 32'hff87a783 /* 0x0574 */; - 350: data_o = 32'h17821702 /* 0x0578 */; - 351: data_o = 32'h8f5d9381 /* 0x057c */; - 352: data_o = 32'hfce60ce3 /* 0x0580 */; - 353: data_o = 32'h663195ba /* 0x0584 */; - 354: data_o = 32'hb00028f3 /* 0x0588 */; - 355: data_o = 32'h00040797 /* 0x058c */; - 356: data_o = 32'h00040697 /* 0x0590 */; - 357: data_o = 32'ha7478793 /* 0x0594 */; - 358: data_o = 32'ha7068693 /* 0x0598 */; - 359: data_o = 32'h96b297b2 /* 0x059c */; - 360: data_o = 32'hffc7a783 /* 0x05a0 */; - 361: data_o = 32'hff86a683 /* 0x05a4 */; - 362: data_o = 32'h16821782 /* 0x05a8 */; - 363: data_o = 32'h8fd59281 /* 0x05ac */; - 364: data_o = 32'hfcb7ece3 /* 0x05b0 */; - 365: data_o = 32'h410888b3 /* 0x05b4 */; - 366: data_o = 32'h85338f99 /* 0x05b8 */; - 367: data_o = 32'h553302a8 /* 0x05bc */; - 368: data_o = 32'h808202f5 /* 0x05c0 */; - 369: data_o = 32'h0733c585 /* 0x05c4 */; - 370: data_o = 32'h279700b5 /* 0x05c8 */; - 371: data_o = 32'h87930100 /* 0x05cc */; - 372: data_o = 32'hc783a367 /* 0x05d0 */; - 373: data_o = 32'h8b850147 /* 0x05d4 */; - 374: data_o = 32'h2797dbed /* 0x05d8 */; - 375: data_o = 32'hc7830100 /* 0x05dc */; - 376: data_o = 32'h0505a267 /* 0x05e0 */; - 377: data_o = 32'hfef50fa3 /* 0x05e4 */; - 378: data_o = 32'hfee511e3 /* 0x05e8 */; - 379: data_o = 32'h71398082 /* 0x05ec */; - 380: data_o = 32'hf822fc06 /* 0x05f0 */; - 381: data_o = 32'hf04af426 /* 0x05f4 */; - 382: data_o = 32'he852ec4e /* 0x05f8 */; - 383: data_o = 32'h01002797 /* 0x05fc */; - 384: data_o = 32'ha0478793 /* 0x0600 */; - 385: data_o = 32'h0147c783 /* 0x0604 */; - 386: data_o = 32'h0207f793 /* 0x0608 */; - 387: data_o = 32'h2797dbe5 /* 0x060c */; - 388: data_o = 32'h47190100 /* 0x0610 */; - 389: data_o = 32'h9ee78923 /* 0x0614 */; - 390: data_o = 32'h44994a49 /* 0x0618 */; - 391: data_o = 32'h49cd4411 /* 0x061c */; - 392: data_o = 32'h000f4945 /* 0x0620 */; - 393: data_o = 32'h27970ff0 /* 0x0624 */; - 394: data_o = 32'h87930100 /* 0x0628 */; - 395: data_o = 32'hc7839da7 /* 0x062c */; - 396: data_o = 32'h8b850147 /* 0x0630 */; - 397: data_o = 32'h2797dbed /* 0x0634 */; - 398: data_o = 32'hc7030100 /* 0x0638 */; - 399: data_o = 32'h77939ca7 /* 0x063c */; - 400: data_o = 32'h0f630ff7 /* 0x0640 */; - 401: data_o = 32'h8d630147 /* 0x0644 */; - 402: data_o = 32'h82630d37 /* 0x0648 */; - 403: data_o = 32'h45050727 /* 0x064c */; - 404: data_o = 32'h744270e2 /* 0x0650 */; - 405: data_o = 32'h790274a2 /* 0x0654 */; - 406: data_o = 32'h6a4269e2 /* 0x0658 */; - 407: data_o = 32'h80826121 /* 0x065c */; - 408: data_o = 32'h850a45a1 /* 0x0660 */; - 409: data_o = 32'hf61ff0ef /* 0x0664 */; - 410: data_o = 32'h002845a1 /* 0x0668 */; - 411: data_o = 32'hf59ff0ef /* 0x066c */; - 412: data_o = 32'h01002797 /* 0x0670 */; - 413: data_o = 32'h99078793 /* 0x0674 */; - 414: data_o = 32'h0147c783 /* 0x0678 */; - 415: data_o = 32'h0207f793 /* 0x067c */; - 416: data_o = 32'h65a2dbe5 /* 0x0680 */; - 417: data_o = 32'h27976502 /* 0x0684 */; - 418: data_o = 32'h8d230100 /* 0x0688 */; - 419: data_o = 32'hf0ef9697 /* 0x068c */; - 420: data_o = 32'h2797f37f /* 0x0690 */; - 421: data_o = 32'h87930100 /* 0x0694 */; - 422: data_o = 32'hc78396e7 /* 0x0698 */; - 423: data_o = 32'hf7930147 /* 0x069c */; - 424: data_o = 32'hdbe50207 /* 0x06a0 */; - 425: data_o = 32'h01002797 /* 0x06a4 */; - 426: data_o = 32'h94878e23 /* 0x06a8 */; - 427: data_o = 32'h45a1bf9d /* 0x06ac */; - 428: data_o = 32'hf0ef850a /* 0x06b0 */; - 429: data_o = 32'h45a1f13f /* 0x06b4 */; - 430: data_o = 32'hf0ef0028 /* 0x06b8 */; - 431: data_o = 32'h2797f0bf /* 0x06bc */; - 432: data_o = 32'h87930100 /* 0x06c0 */; - 433: data_o = 32'hc7839427 /* 0x06c4 */; - 434: data_o = 32'hf7930147 /* 0x06c8 */; - 435: data_o = 32'hdbe50207 /* 0x06cc */; - 436: data_o = 32'h27976622 /* 0x06d0 */; - 437: data_o = 32'h87230100 /* 0x06d4 */; - 438: data_o = 32'h67029297 /* 0x06d8 */; - 439: data_o = 32'h963ac605 /* 0x06dc */; - 440: data_o = 32'h00074683 /* 0x06e0 */; - 441: data_o = 32'h01002797 /* 0x06e4 */; - 442: data_o = 32'h91c78793 /* 0x06e8 */; - 443: data_o = 32'h0147c783 /* 0x06ec */; - 444: data_o = 32'h0207f793 /* 0x06f0 */; - 445: data_o = 32'h2797dbe5 /* 0x06f4 */; - 446: data_o = 32'h85230100 /* 0x06f8 */; - 447: data_o = 32'h070590d7 /* 0x06fc */; - 448: data_o = 32'hfee610e3 /* 0x0700 */; - 449: data_o = 32'h01002797 /* 0x0704 */; - 450: data_o = 32'h8fc78793 /* 0x0708 */; - 451: data_o = 32'h0147c783 /* 0x070c */; - 452: data_o = 32'h0207f793 /* 0x0710 */; - 453: data_o = 32'h2797dbe5 /* 0x0714 */; - 454: data_o = 32'h85230100 /* 0x0718 */; - 455: data_o = 32'hb7118e87 /* 0x071c */; - 456: data_o = 32'h850a45a1 /* 0x0720 */; - 457: data_o = 32'hea1ff0ef /* 0x0724 */; - 458: data_o = 32'h01002797 /* 0x0728 */; - 459: data_o = 32'h8d878793 /* 0x072c */; - 460: data_o = 32'h0147c783 /* 0x0730 */; - 461: data_o = 32'h0207f793 /* 0x0734 */; - 462: data_o = 32'h2797dbe5 /* 0x0738 */; - 463: data_o = 32'h47190100 /* 0x073c */; - 464: data_o = 32'h8ce78323 /* 0x0740 */; - 465: data_o = 32'h0ff0000f /* 0x0744 */; - 466: data_o = 32'h100f6782 /* 0x0748 */; - 467: data_o = 32'h97820000 /* 0x074c */; - 468: data_o = 32'h000fc42a /* 0x0750 */; - 469: data_o = 32'h27970ff0 /* 0x0754 */; - 470: data_o = 32'h87930100 /* 0x0758 */; - 471: data_o = 32'hc7838aa7 /* 0x075c */; - 472: data_o = 32'hf7930147 /* 0x0760 */; - 473: data_o = 32'hdbe50207 /* 0x0764 */; - 474: data_o = 32'h27974751 /* 0x0768 */; - 475: data_o = 32'h8b230100 /* 0x076c */; - 476: data_o = 32'h007088e7 /* 0x0770 */; - 477: data_o = 32'h46830038 /* 0x0774 */; - 478: data_o = 32'h27970007 /* 0x0778 */; - 479: data_o = 32'h87930100 /* 0x077c */; - 480: data_o = 32'hc7838867 /* 0x0780 */; - 481: data_o = 32'hf7930147 /* 0x0784 */; - 482: data_o = 32'hdbe50207 /* 0x0788 */; - 483: data_o = 32'h01002797 /* 0x078c */; - 484: data_o = 32'h86d78a23 /* 0x0790 */; - 485: data_o = 32'h10e30705 /* 0x0794 */; - 486: data_o = 32'h4522fec7 /* 0x0798 */; - 487: data_o = 32'h07b7bd55 /* 0x079c */; - 488: data_o = 32'hc91c4000 /* 0x07a0 */; - 489: data_o = 32'hd79b495c /* 0x07a4 */; - 490: data_o = 32'h8b8501e7 /* 0x07a8 */; - 491: data_o = 32'h495cffe5 /* 0x07ac */; - 492: data_o = 32'h0087d71b /* 0x07b0 */; - 493: data_o = 32'hf7938fd9 /* 0x07b4 */; - 494: data_o = 32'hfbf50ff7 /* 0x07b8 */; - 495: data_o = 32'h00052823 /* 0x07bc */; - 496: data_o = 32'hc93d8082 /* 0x07c0 */; - 497: data_o = 32'h001c27b7 /* 0x07c4 */; - 498: data_o = 32'h02f55533 /* 0x07c8 */; - 499: data_o = 32'h01002797 /* 0x07cc */; - 500: data_o = 32'h83478793 /* 0x07d0 */; - 501: data_o = 32'h00078223 /* 0x07d4 */; - 502: data_o = 32'h01002797 /* 0x07d8 */; - 503: data_o = 32'h82878793 /* 0x07dc */; - 504: data_o = 32'hf8000693 /* 0x07e0 */; - 505: data_o = 32'h00d78623 /* 0x07e4 */; + 056: data_o = 32'hb31704c3 /* 0x00e0 */; + 057: data_o = 32'h03130100 /* 0x00e4 */; + 058: data_o = 32'h2303f1e3 /* 0x00e8 */; + 059: data_o = 32'hd3b32003 /* 0x00ec */; + 060: data_o = 32'h038a0063 /* 0x00f0 */; + 061: data_o = 32'h43059396 /* 0x00f4 */; + 062: data_o = 32'h0062a023 /* 0x00f8 */; + 063: data_o = 32'hcce30291 /* 0x00fc */; + 064: data_o = 32'h0073fe72 /* 0x0100 */; + 065: data_o = 32'h23731050 /* 0x0104 */; + 066: data_o = 32'h73133440 /* 0x0108 */; + 067: data_o = 32'h0ae30083 /* 0x010c */; + 068: data_o = 32'h0297fe03 /* 0x0110 */; + 069: data_o = 32'h82930004 /* 0x0114 */; + 070: data_o = 32'h2373eee2 /* 0x0118 */; + 071: data_o = 32'h030af140 /* 0x011c */; + 072: data_o = 32'h20239316 /* 0x0120 */; + 073: data_o = 32'h03970003 /* 0x0124 */; + 074: data_o = 32'h83930100 /* 0x0128 */; + 075: data_o = 32'ha383eda3 /* 0x012c */; + 076: data_o = 32'h038a04c3 /* 0x0130 */; + 077: data_o = 32'ha3039396 /* 0x0134 */; + 078: data_o = 32'h1ee30002 /* 0x0138 */; + 079: data_o = 32'h0291fe03 /* 0x013c */; + 080: data_o = 32'hfe72cbe3 /* 0x0140 */; + 081: data_o = 32'h01000297 /* 0x0144 */; + 082: data_o = 32'hebc28293 /* 0x0148 */; + 083: data_o = 32'h0142e303 /* 0x014c */; + 084: data_o = 32'he2831302 /* 0x0150 */; + 085: data_o = 32'he2b30102 /* 0x0154 */; + 086: data_o = 32'h25730062 /* 0x0158 */; + 087: data_o = 32'h80e7f140 /* 0x015c */; + 088: data_o = 32'h80820002 /* 0x0160 */; + 089: data_o = 32'h43014281 /* 0x0164 */; + 090: data_o = 32'h0ff0000f /* 0x0168 */; + 091: data_o = 32'h0000100f /* 0x016c */; + 092: data_o = 32'h3f0010ef /* 0x0170 */; + 093: data_o = 32'h65130506 /* 0x0174 */; + 094: data_o = 32'h02970015 /* 0x0178 */; + 095: data_o = 32'h82930100 /* 0x017c */; + 096: data_o = 32'ha423e862 /* 0x0180 */; + 097: data_o = 32'h007300a2 /* 0x0184 */; + 098: data_o = 32'hbff51050 /* 0x0188 */; + 099: data_o = 32'h0185171b /* 0x018c */; + 100: data_o = 32'h0185579b /* 0x0190 */; + 101: data_o = 32'h8fd966c1 /* 0x0194 */; + 102: data_o = 32'hf0068693 /* 0x0198 */; + 103: data_o = 32'h0085571b /* 0x019c */; + 104: data_o = 32'h8fd98f75 /* 0x01a0 */; + 105: data_o = 32'h0085151b /* 0x01a4 */; + 106: data_o = 32'h00ff0737 /* 0x01a8 */; + 107: data_o = 32'h8d5d8d79 /* 0x01ac */; + 108: data_o = 32'h80822501 /* 0x01b0 */; + 109: data_o = 32'hca09832a /* 0x01b4 */; + 110: data_o = 32'h00058383 /* 0x01b8 */; + 111: data_o = 32'h00730023 /* 0x01bc */; + 112: data_o = 32'h0305167d /* 0x01c0 */; + 113: data_o = 32'hfa6d0585 /* 0x01c4 */; + 114: data_o = 32'h66b18082 /* 0x01c8 */; + 115: data_o = 32'h00040797 /* 0x01cc */; + 116: data_o = 32'h00040717 /* 0x01d0 */; + 117: data_o = 32'he3478793 /* 0x01d4 */; + 118: data_o = 32'he3070713 /* 0x01d8 */; + 119: data_o = 32'h973697b6 /* 0x01dc */; + 120: data_o = 32'hffc7a783 /* 0x01e0 */; + 121: data_o = 32'hff872703 /* 0x01e4 */; + 122: data_o = 32'h17021782 /* 0x01e8 */; + 123: data_o = 32'h8fd99301 /* 0x01ec */; + 124: data_o = 32'hfca7eee3 /* 0x01f0 */; + 125: data_o = 32'hc5298082 /* 0x01f4 */; + 126: data_o = 32'h4789ee9d /* 0x01f8 */; + 127: data_o = 32'h04f60963 /* 0x01fc */; + 128: data_o = 32'h0163478d /* 0x0200 */; + 129: data_o = 32'h167d04f6 /* 0x0204 */; + 130: data_o = 32'h00c03633 /* 0x0208 */; + 131: data_o = 32'h47014801 /* 0x020c */; + 132: data_o = 32'h00c6969b /* 0x0210 */; + 133: data_o = 32'h00d5e7b3 /* 0x0214 */; + 134: data_o = 32'h0086161b /* 0x0218 */; + 135: data_o = 32'h181b8fd1 /* 0x021c */; + 136: data_o = 32'h611400a8 /* 0x0220 */; + 137: data_o = 32'h0107e7b3 /* 0x0224 */; + 138: data_o = 32'h0097171b /* 0x0228 */; + 139: data_o = 32'h27818fd9 /* 0x022c */; + 140: data_o = 32'h4501cedc /* 0x0230 */; + 141: data_o = 32'h079b8082 /* 0x0234 */; + 142: data_o = 32'h4709ffd6 /* 0x0238 */; + 143: data_o = 32'hfaf76fe3 /* 0x023c */; + 144: data_o = 32'h8082450d /* 0x0240 */; + 145: data_o = 32'h4601fef5 /* 0x0244 */; + 146: data_o = 32'h47014805 /* 0x0248 */; + 147: data_o = 32'h4801b7d1 /* 0x024c */; + 148: data_o = 32'h46014705 /* 0x0250 */; + 149: data_o = 32'h7159bf75 /* 0x0254 */; + 150: data_o = 32'he8caf0a2 /* 0x0258 */; + 151: data_o = 32'he0d2e4ce /* 0x025c */; + 152: data_o = 32'hf85afc56 /* 0x0260 */; + 153: data_o = 32'hf062f45e /* 0x0264 */; + 154: data_o = 32'heca6f486 /* 0x0268 */; + 155: data_o = 32'he86aec66 /* 0x026c */; + 156: data_o = 32'h8936e46e /* 0x0270 */; + 157: data_o = 32'h89ae842a /* 0x0274 */; + 158: data_o = 32'h8b3a8ab2 /* 0x0278 */; + 159: data_o = 32'hfff68b93 /* 0x027c */; + 160: data_o = 32'h0c136a31 /* 0x0280 */; + 161: data_o = 32'h0b630200 /* 0x0284 */; + 162: data_o = 32'h60040e04 /* 0x0288 */; + 163: data_o = 32'hf51350dc /* 0x028c */; + 164: data_o = 32'h278107f7 /* 0x0290 */; + 165: data_o = 32'hd71bf96d /* 0x0294 */; + 166: data_o = 32'hd51b0107 /* 0x0298 */; + 167: data_o = 32'h8d590087 /* 0x029c */; + 168: data_o = 32'h0187d79b /* 0x02a0 */; + 169: data_o = 32'hf7938fc9 /* 0x02a4 */; + 170: data_o = 32'hfff107f7 /* 0x02a8 */; + 171: data_o = 32'h00040717 /* 0x02ac */; + 172: data_o = 32'h00040797 /* 0x02b0 */; + 173: data_o = 32'hd5470713 /* 0x02b4 */; + 174: data_o = 32'hd5078793 /* 0x02b8 */; + 175: data_o = 32'h97d29752 /* 0x02bc */; + 176: data_o = 32'hffc72683 /* 0x02c0 */; + 177: data_o = 32'hff87a783 /* 0x02c4 */; + 178: data_o = 32'h17821682 /* 0x02c8 */; + 179: data_o = 32'h8edd9381 /* 0x02cc */; + 180: data_o = 32'h07970685 /* 0x02d0 */; + 181: data_o = 32'h05170004 /* 0x02d4 */; + 182: data_o = 32'h87930004 /* 0x02d8 */; + 183: data_o = 32'h0513d2e7 /* 0x02dc */; + 184: data_o = 32'h97d2d2a5 /* 0x02e0 */; + 185: data_o = 32'ha7839552 /* 0x02e4 */; + 186: data_o = 32'h2703ffc7 /* 0x02e8 */; + 187: data_o = 32'h1782ff85 /* 0x02ec */; + 188: data_o = 32'h93011702 /* 0x02f0 */; + 189: data_o = 32'heee38fd9 /* 0x02f4 */; + 190: data_o = 32'h489cfcd7 /* 0x02f8 */; + 191: data_o = 32'h46014685 /* 0x02fc */; + 192: data_o = 32'hc89c9bf9 /* 0x0300 */; + 193: data_o = 32'h0a000593 /* 0x0304 */; + 194: data_o = 32'hf0ef8522 /* 0x0308 */; + 195: data_o = 32'h0c9beedf /* 0x030c */; + 196: data_o = 32'h96630005 /* 0x0310 */; + 197: data_o = 32'hd593060c /* 0x0314 */; + 198: data_o = 32'h4685008a /* 0x0318 */; + 199: data_o = 32'hf5934605 /* 0x031c */; + 200: data_o = 32'h85220ff5 /* 0x0320 */; + 201: data_o = 32'hed3ff0ef /* 0x0324 */; + 202: data_o = 32'h00050c9b /* 0x0328 */; + 203: data_o = 32'h040c9963 /* 0x032c */; + 204: data_o = 32'h0ffaf593 /* 0x0330 */; + 205: data_o = 32'h060b0563 /* 0x0334 */; + 206: data_o = 32'h46054685 /* 0x0338 */; + 207: data_o = 32'hf0ef8522 /* 0x033c */; + 208: data_o = 32'h079beb9f /* 0x0340 */; + 209: data_o = 32'heb8d0005 /* 0x0344 */; + 210: data_o = 32'h74638d5e /* 0x0348 */; + 211: data_o = 32'h0d13017c /* 0x034c */; + 212: data_o = 32'h4d810200 /* 0x0350 */; + 213: data_o = 32'h000b9563 /* 0x0354 */; + 214: data_o = 32'hf563a075 /* 0x0358 */; + 215: data_o = 32'h87b30bad /* 0x035c */; + 216: data_o = 32'hc58301b9 /* 0x0360 */; + 217: data_o = 32'h46850007 /* 0x0364 */; + 218: data_o = 32'h85224605 /* 0x0368 */; + 219: data_o = 32'he8bff0ef /* 0x036c */; + 220: data_o = 32'h0005079b /* 0x0370 */; + 221: data_o = 32'hd3f50d85 /* 0x0374 */; + 222: data_o = 32'ha0118cbe /* 0x0378 */; + 223: data_o = 32'h70a64c8d /* 0x037c */; + 224: data_o = 32'h64e67406 /* 0x0380 */; + 225: data_o = 32'h69a66946 /* 0x0384 */; + 226: data_o = 32'h7ae26a06 /* 0x0388 */; + 227: data_o = 32'h7ba27b42 /* 0x038c */; + 228: data_o = 32'h6d427c02 /* 0x0390 */; + 229: data_o = 32'h85666da2 /* 0x0394 */; + 230: data_o = 32'h61656ce2 /* 0x0398 */; + 231: data_o = 32'h46858082 /* 0x039c */; + 232: data_o = 32'h85224609 /* 0x03a0 */; + 233: data_o = 32'he53ff0ef /* 0x03a4 */; + 234: data_o = 32'h0005079b /* 0x03a8 */; + 235: data_o = 32'h4685f7f1 /* 0x03ac */; + 236: data_o = 32'h05934601 /* 0x03b0 */; + 237: data_o = 32'h85220a10 /* 0x03b4 */; + 238: data_o = 32'he3fff0ef /* 0x03b8 */; + 239: data_o = 32'h0005079b /* 0x03bc */; + 240: data_o = 32'h4681ffc5 /* 0x03c0 */; + 241: data_o = 32'h7593460d /* 0x03c4 */; + 242: data_o = 32'h85220ff9 /* 0x03c8 */; + 243: data_o = 32'he2bff0ef /* 0x03cc */; + 244: data_o = 32'h0005079b /* 0x03d0 */; + 245: data_o = 32'h489cf3d5 /* 0x03d4 */; + 246: data_o = 32'h0017e793 /* 0x03d8 */; + 247: data_o = 32'h50dcc89c /* 0x03dc */; + 248: data_o = 32'h0107d79b /* 0x03e0 */; + 249: data_o = 32'h07f7f793 /* 0x03e4 */; + 250: data_o = 32'hff27ebe3 /* 0x03e8 */; + 251: data_o = 32'h601c994e /* 0x03ec */; + 252: data_o = 32'h27814f9c /* 0x03f0 */; + 253: data_o = 32'h00098463 /* 0x03f4 */; + 254: data_o = 32'h00f98023 /* 0x03f8 */; + 255: data_o = 32'h18e30985 /* 0x03fc */; + 256: data_o = 32'hbfb5ff39 /* 0x0400 */; + 257: data_o = 32'h017987b3 /* 0x0404 */; + 258: data_o = 32'h0007c583 /* 0x0408 */; + 259: data_o = 32'h46054685 /* 0x040c */; + 260: data_o = 32'hf0ef8522 /* 0x0410 */; + 261: data_o = 32'h079bde5f /* 0x0414 */; + 262: data_o = 32'hffb90005 /* 0x0418 */; + 263: data_o = 32'h1b81489c /* 0x041c */; + 264: data_o = 32'h0017e793 /* 0x0420 */; + 265: data_o = 32'h7ce3c89c /* 0x0424 */; + 266: data_o = 32'h99caf52c /* 0x0428 */; + 267: data_o = 32'h19019aca /* 0x042c */; + 268: data_o = 32'h7139bd99 /* 0x0430 */; + 269: data_o = 32'hf426f822 /* 0x0434 */; + 270: data_o = 32'hec4ef04a /* 0x0438 */; + 271: data_o = 32'hfc06e852 /* 0x043c */; + 272: data_o = 32'h7413e456 /* 0x0440 */; + 273: data_o = 32'h893203f6 /* 0x0444 */; + 274: data_o = 32'h8a2e89aa /* 0x0448 */; + 275: data_o = 32'he42184b6 /* 0x044c */; + 276: data_o = 32'h04000a93 /* 0x0450 */; + 277: data_o = 32'h00946563 /* 0x0454 */; + 278: data_o = 32'h7c63a82d /* 0x0458 */; + 279: data_o = 32'h86b30294 /* 0x045c */; + 280: data_o = 32'h06334084 /* 0x0460 */; + 281: data_o = 32'h05b30089 /* 0x0464 */; + 282: data_o = 32'h4701008a /* 0x0468 */; + 283: data_o = 32'h0413854e /* 0x046c */; + 284: data_o = 32'hf4630404 /* 0x0470 */; + 285: data_o = 32'h069300da /* 0x0474 */; + 286: data_o = 32'hf0ef0400 /* 0x0478 */; + 287: data_o = 32'hdd71dddf /* 0x047c */; + 288: data_o = 32'h744270e2 /* 0x0480 */; + 289: data_o = 32'h790274a2 /* 0x0484 */; + 290: data_o = 32'h6a4269e2 /* 0x0488 */; + 291: data_o = 32'h61216aa2 /* 0x048c */; + 292: data_o = 32'h45018082 /* 0x0490 */; + 293: data_o = 32'h0793b7f5 /* 0x0494 */; + 294: data_o = 32'h84330400 /* 0x0498 */; + 295: data_o = 32'h47014087 /* 0x049c */; + 296: data_o = 32'hf0ef86a2 /* 0x04a0 */; + 297: data_o = 32'hd54ddb5f /* 0x04a4 */; + 298: data_o = 32'h1141bfe1 /* 0x04a8 */; + 299: data_o = 32'he432e02e /* 0x04ac */; + 300: data_o = 32'h9581c141 /* 0x04b0 */; + 301: data_o = 32'h4782cdb5 /* 0x04b4 */; + 302: data_o = 32'hd5bbcfa5 /* 0x04b8 */; + 303: data_o = 32'h77c102f5 /* 0x04bc */; + 304: data_o = 32'h269988aa /* 0x04c0 */; + 305: data_o = 32'h0026969b /* 0x04c4 */; + 306: data_o = 32'h0015d59b /* 0x04c8 */; + 307: data_o = 32'h8fed35fd /* 0x04cc */; + 308: data_o = 32'h0007851b /* 0x04d0 */; + 309: data_o = 32'h4783ed31 /* 0x04d4 */; + 310: data_o = 32'h4e0300c1 /* 0x04d8 */; + 311: data_o = 32'h430300b1 /* 0x04dc */; + 312: data_o = 32'h480300d1 /* 0x04e0 */; + 313: data_o = 32'h46030081 /* 0x04e4 */; + 314: data_o = 32'h979b0091 /* 0x04e8 */; + 315: data_o = 32'h1e1b01e7 /* 0x04ec */; + 316: data_o = 32'h470301de /* 0x04f0 */; + 317: data_o = 32'he7b300a1 /* 0x04f4 */; + 318: data_o = 32'h131b01c7 /* 0x04f8 */; + 319: data_o = 32'h781301f3 /* 0x04fc */; + 320: data_o = 32'he7b300f8 /* 0x0500 */; + 321: data_o = 32'h8fcd0067 /* 0x0504 */; + 322: data_o = 32'h159b8a3d /* 0x0508 */; + 323: data_o = 32'h8fcd0108 /* 0x050c */; + 324: data_o = 32'h0008b803 /* 0x0510 */; + 325: data_o = 32'h0146161b /* 0x0514 */; + 326: data_o = 32'h171b8b3d /* 0x0518 */; + 327: data_o = 32'h8fd10187 /* 0x051c */; + 328: data_o = 32'h8fd91682 /* 0x0520 */; + 329: data_o = 32'h27819281 /* 0x0524 */; + 330: data_o = 32'h00d80733 /* 0x0528 */; + 331: data_o = 32'ha011c31c /* 0x052c */; + 332: data_o = 32'h0141450d /* 0x0530 */; + 333: data_o = 32'h65858082 /* 0x0534 */; + 334: data_o = 32'h9c458593 /* 0x0538 */; + 335: data_o = 32'h02b555b3 /* 0x053c */; + 336: data_o = 32'h00040797 /* 0x0540 */; + 337: data_o = 32'h00040697 /* 0x0544 */; + 338: data_o = 32'h86936731 /* 0x0548 */; + 339: data_o = 32'h8793abc6 /* 0x054c */; + 340: data_o = 32'h97baac07 /* 0x0550 */; + 341: data_o = 32'ha6039736 /* 0x0554 */; + 342: data_o = 32'h2783ffc7 /* 0x0558 */; + 343: data_o = 32'h66b1ff87 /* 0x055c */; + 344: data_o = 32'h17821602 /* 0x0560 */; + 345: data_o = 32'h8e5d9381 /* 0x0564 */; + 346: data_o = 32'hb0002873 /* 0x0568 */; + 347: data_o = 32'h00040717 /* 0x056c */; + 348: data_o = 32'h00040797 /* 0x0570 */; + 349: data_o = 32'ha9470713 /* 0x0574 */; + 350: data_o = 32'ha9078793 /* 0x0578 */; + 351: data_o = 32'h97b69736 /* 0x057c */; + 352: data_o = 32'hffc72703 /* 0x0580 */; + 353: data_o = 32'hff87a783 /* 0x0584 */; + 354: data_o = 32'h17821702 /* 0x0588 */; + 355: data_o = 32'h8f5d9381 /* 0x058c */; + 356: data_o = 32'hfce60ce3 /* 0x0590 */; + 357: data_o = 32'h663195ba /* 0x0594 */; + 358: data_o = 32'hb00028f3 /* 0x0598 */; + 359: data_o = 32'h00040797 /* 0x059c */; + 360: data_o = 32'h00040697 /* 0x05a0 */; + 361: data_o = 32'ha6478793 /* 0x05a4 */; + 362: data_o = 32'ha6068693 /* 0x05a8 */; + 363: data_o = 32'h96b297b2 /* 0x05ac */; + 364: data_o = 32'hffc7a783 /* 0x05b0 */; + 365: data_o = 32'hff86a683 /* 0x05b4 */; + 366: data_o = 32'h16821782 /* 0x05b8 */; + 367: data_o = 32'h8fd59281 /* 0x05bc */; + 368: data_o = 32'hfcb7ece3 /* 0x05c0 */; + 369: data_o = 32'h410888b3 /* 0x05c4 */; + 370: data_o = 32'h85338f99 /* 0x05c8 */; + 371: data_o = 32'h553302a8 /* 0x05cc */; + 372: data_o = 32'h808202f5 /* 0x05d0 */; + 373: data_o = 32'h0733c585 /* 0x05d4 */; + 374: data_o = 32'h279700b5 /* 0x05d8 */; + 375: data_o = 32'h87930100 /* 0x05dc */; + 376: data_o = 32'hc783a267 /* 0x05e0 */; + 377: data_o = 32'h8b850147 /* 0x05e4 */; + 378: data_o = 32'h2797dbed /* 0x05e8 */; + 379: data_o = 32'hc7830100 /* 0x05ec */; + 380: data_o = 32'h0505a167 /* 0x05f0 */; + 381: data_o = 32'hfef50fa3 /* 0x05f4 */; + 382: data_o = 32'hfee511e3 /* 0x05f8 */; + 383: data_o = 32'h71398082 /* 0x05fc */; + 384: data_o = 32'hf822fc06 /* 0x0600 */; + 385: data_o = 32'hf04af426 /* 0x0604 */; + 386: data_o = 32'he852ec4e /* 0x0608 */; + 387: data_o = 32'h01002797 /* 0x060c */; + 388: data_o = 32'h9f478793 /* 0x0610 */; + 389: data_o = 32'h0147c783 /* 0x0614 */; + 390: data_o = 32'h0207f793 /* 0x0618 */; + 391: data_o = 32'h2797dbe5 /* 0x061c */; + 392: data_o = 32'h47190100 /* 0x0620 */; + 393: data_o = 32'h9ee78123 /* 0x0624 */; + 394: data_o = 32'h44994a49 /* 0x0628 */; + 395: data_o = 32'h49cd4411 /* 0x062c */; + 396: data_o = 32'h000f4945 /* 0x0630 */; + 397: data_o = 32'h27970ff0 /* 0x0634 */; + 398: data_o = 32'h87930100 /* 0x0638 */; + 399: data_o = 32'hc7839ca7 /* 0x063c */; + 400: data_o = 32'h8b850147 /* 0x0640 */; + 401: data_o = 32'h2797dbed /* 0x0644 */; + 402: data_o = 32'hc7030100 /* 0x0648 */; + 403: data_o = 32'h77939ba7 /* 0x064c */; + 404: data_o = 32'h0f630ff7 /* 0x0650 */; + 405: data_o = 32'h8d630147 /* 0x0654 */; + 406: data_o = 32'h82630d37 /* 0x0658 */; + 407: data_o = 32'h45050727 /* 0x065c */; + 408: data_o = 32'h744270e2 /* 0x0660 */; + 409: data_o = 32'h790274a2 /* 0x0664 */; + 410: data_o = 32'h6a4269e2 /* 0x0668 */; + 411: data_o = 32'h80826121 /* 0x066c */; + 412: data_o = 32'h850a45a1 /* 0x0670 */; + 413: data_o = 32'hf61ff0ef /* 0x0674 */; + 414: data_o = 32'h002845a1 /* 0x0678 */; + 415: data_o = 32'hf59ff0ef /* 0x067c */; + 416: data_o = 32'h01002797 /* 0x0680 */; + 417: data_o = 32'h98078793 /* 0x0684 */; + 418: data_o = 32'h0147c783 /* 0x0688 */; + 419: data_o = 32'h0207f793 /* 0x068c */; + 420: data_o = 32'h65a2dbe5 /* 0x0690 */; + 421: data_o = 32'h27976502 /* 0x0694 */; + 422: data_o = 32'h85230100 /* 0x0698 */; + 423: data_o = 32'hf0ef9697 /* 0x069c */; + 424: data_o = 32'h2797f37f /* 0x06a0 */; + 425: data_o = 32'h87930100 /* 0x06a4 */; + 426: data_o = 32'hc78395e7 /* 0x06a8 */; + 427: data_o = 32'hf7930147 /* 0x06ac */; + 428: data_o = 32'hdbe50207 /* 0x06b0 */; + 429: data_o = 32'h01002797 /* 0x06b4 */; + 430: data_o = 32'h94878623 /* 0x06b8 */; + 431: data_o = 32'h45a1bf9d /* 0x06bc */; + 432: data_o = 32'hf0ef850a /* 0x06c0 */; + 433: data_o = 32'h45a1f13f /* 0x06c4 */; + 434: data_o = 32'hf0ef0028 /* 0x06c8 */; + 435: data_o = 32'h2797f0bf /* 0x06cc */; + 436: data_o = 32'h87930100 /* 0x06d0 */; + 437: data_o = 32'hc7839327 /* 0x06d4 */; + 438: data_o = 32'hf7930147 /* 0x06d8 */; + 439: data_o = 32'hdbe50207 /* 0x06dc */; + 440: data_o = 32'h27976622 /* 0x06e0 */; + 441: data_o = 32'h8f230100 /* 0x06e4 */; + 442: data_o = 32'h67029097 /* 0x06e8 */; + 443: data_o = 32'h963ac605 /* 0x06ec */; + 444: data_o = 32'h00074683 /* 0x06f0 */; + 445: data_o = 32'h01002797 /* 0x06f4 */; + 446: data_o = 32'h90c78793 /* 0x06f8 */; + 447: data_o = 32'h0147c783 /* 0x06fc */; + 448: data_o = 32'h0207f793 /* 0x0700 */; + 449: data_o = 32'h2797dbe5 /* 0x0704 */; + 450: data_o = 32'h8d230100 /* 0x0708 */; + 451: data_o = 32'h07058ed7 /* 0x070c */; + 452: data_o = 32'hfee610e3 /* 0x0710 */; + 453: data_o = 32'h01002797 /* 0x0714 */; + 454: data_o = 32'h8ec78793 /* 0x0718 */; + 455: data_o = 32'h0147c783 /* 0x071c */; + 456: data_o = 32'h0207f793 /* 0x0720 */; + 457: data_o = 32'h2797dbe5 /* 0x0724 */; + 458: data_o = 32'h8d230100 /* 0x0728 */; + 459: data_o = 32'hb7118c87 /* 0x072c */; + 460: data_o = 32'h850a45a1 /* 0x0730 */; + 461: data_o = 32'hea1ff0ef /* 0x0734 */; + 462: data_o = 32'h01002797 /* 0x0738 */; + 463: data_o = 32'h8c878793 /* 0x073c */; + 464: data_o = 32'h0147c783 /* 0x0740 */; + 465: data_o = 32'h0207f793 /* 0x0744 */; + 466: data_o = 32'h2797dbe5 /* 0x0748 */; + 467: data_o = 32'h47190100 /* 0x074c */; + 468: data_o = 32'h8ae78b23 /* 0x0750 */; + 469: data_o = 32'h0ff0000f /* 0x0754 */; + 470: data_o = 32'h100f6782 /* 0x0758 */; + 471: data_o = 32'h97820000 /* 0x075c */; + 472: data_o = 32'h000fc42a /* 0x0760 */; + 473: data_o = 32'h27970ff0 /* 0x0764 */; + 474: data_o = 32'h87930100 /* 0x0768 */; + 475: data_o = 32'hc78389a7 /* 0x076c */; + 476: data_o = 32'hf7930147 /* 0x0770 */; + 477: data_o = 32'hdbe50207 /* 0x0774 */; + 478: data_o = 32'h27974751 /* 0x0778 */; + 479: data_o = 32'h83230100 /* 0x077c */; + 480: data_o = 32'h007088e7 /* 0x0780 */; + 481: data_o = 32'h46830038 /* 0x0784 */; + 482: data_o = 32'h27970007 /* 0x0788 */; + 483: data_o = 32'h87930100 /* 0x078c */; + 484: data_o = 32'hc7838767 /* 0x0790 */; + 485: data_o = 32'hf7930147 /* 0x0794 */; + 486: data_o = 32'hdbe50207 /* 0x0798 */; + 487: data_o = 32'h01002797 /* 0x079c */; + 488: data_o = 32'h86d78223 /* 0x07a0 */; + 489: data_o = 32'h10e30705 /* 0x07a4 */; + 490: data_o = 32'h4522fec7 /* 0x07a8 */; + 491: data_o = 32'h07b7bd55 /* 0x07ac */; + 492: data_o = 32'hc91c4000 /* 0x07b0 */; + 493: data_o = 32'hd79b495c /* 0x07b4 */; + 494: data_o = 32'h8b8501e7 /* 0x07b8 */; + 495: data_o = 32'h495cffe5 /* 0x07bc */; + 496: data_o = 32'h0087d71b /* 0x07c0 */; + 497: data_o = 32'hf7938fd9 /* 0x07c4 */; + 498: data_o = 32'hfbf50ff7 /* 0x07c8 */; + 499: data_o = 32'h00052823 /* 0x07cc */; + 500: data_o = 32'hc93d8082 /* 0x07d0 */; + 501: data_o = 32'h001c27b7 /* 0x07d4 */; + 502: data_o = 32'h02f55533 /* 0x07d8 */; + 503: data_o = 32'h01002797 /* 0x07dc */; + 504: data_o = 32'h82478793 /* 0x07e0 */; + 505: data_o = 32'h00078223 /* 0x07e4 */; 506: data_o = 32'h01002797 /* 0x07e8 */; - 507: data_o = 32'h0ff57713 /* 0x07ec */; - 508: data_o = 32'h80e78c23 /* 0x07f0 */; - 509: data_o = 32'h27978121 /* 0x07f4 */; - 510: data_o = 32'h75130100 /* 0x07f8 */; - 511: data_o = 32'h87930ff5 /* 0x07fc */; - 512: data_o = 32'h822380a7 /* 0x0800 */; - 513: data_o = 32'h179700a7 /* 0x0804 */; - 514: data_o = 32'h87930100 /* 0x0808 */; - 515: data_o = 32'h470d7fa7 /* 0x080c */; - 516: data_o = 32'h00e78623 /* 0x0810 */; - 517: data_o = 32'h01001797 /* 0x0814 */; - 518: data_o = 32'h7ec78793 /* 0x0818 */; - 519: data_o = 32'hfc700713 /* 0x081c */; - 520: data_o = 32'h00e78423 /* 0x0820 */; + 507: data_o = 32'h81878793 /* 0x07ec */; + 508: data_o = 32'hf8000693 /* 0x07f0 */; + 509: data_o = 32'h00d78623 /* 0x07f4 */; + 510: data_o = 32'h01002797 /* 0x07f8 */; + 511: data_o = 32'h0ff57713 /* 0x07fc */; + 512: data_o = 32'h80e78423 /* 0x0800 */; + 513: data_o = 32'h17978121 /* 0x0804 */; + 514: data_o = 32'h75130100 /* 0x0808 */; + 515: data_o = 32'h87930ff5 /* 0x080c */; + 516: data_o = 32'h82237fa7 /* 0x0810 */; + 517: data_o = 32'h179700a7 /* 0x0814 */; + 518: data_o = 32'h87930100 /* 0x0818 */; + 519: data_o = 32'h470d7ea7 /* 0x081c */; + 520: data_o = 32'h00e78623 /* 0x0820 */; 521: data_o = 32'h01001797 /* 0x0824 */; 522: data_o = 32'h7dc78793 /* 0x0828 */; - 523: data_o = 32'h02000713 /* 0x082c */; - 524: data_o = 32'h00e78823 /* 0x0830 */; - 525: data_o = 32'h0ff0000f /* 0x0834 */; - 526: data_o = 32'hf7974719 /* 0x0838 */; - 527: data_o = 32'h879300ff /* 0x083c */; - 528: data_o = 32'h479c7c67 /* 0x0840 */; - 529: data_o = 32'hc78d8b89 /* 0x0844 */; - 530: data_o = 32'h00fff797 /* 0x0848 */; - 531: data_o = 32'h7b878793 /* 0x084c */; - 532: data_o = 32'h0007a423 /* 0x0850 */; - 533: data_o = 32'h00fff797 /* 0x0854 */; - 534: data_o = 32'h7ac78793 /* 0x0858 */; - 535: data_o = 32'hf79743c8 /* 0x085c */; - 536: data_o = 32'ha78300ff /* 0x0860 */; - 537: data_o = 32'h15027a27 /* 0x0864 */; - 538: data_o = 32'h93811782 /* 0x0868 */; - 539: data_o = 32'hb0a98d5d /* 0x086c */; - 540: data_o = 32'h01001797 /* 0x0870 */; - 541: data_o = 32'h79078793 /* 0x0874 */; - 542: data_o = 32'h0147c783 /* 0x0878 */; - 543: data_o = 32'hdfd58b85 /* 0x087c */; - 544: data_o = 32'h01001797 /* 0x0880 */; - 545: data_o = 32'h7807c783 /* 0x0884 */; - 546: data_o = 32'hfae799e3 /* 0x0888 */; - 547: data_o = 32'h1101b38d /* 0x088c */; - 548: data_o = 32'h6100e822 /* 0x0890 */; - 549: data_o = 32'he04ae426 /* 0x0894 */; - 550: data_o = 32'h892eec06 /* 0x0898 */; - 551: data_o = 32'h071384b2 /* 0x089c */; - 552: data_o = 32'h485c0480 /* 0x08a0 */; - 553: data_o = 32'h0ff7f793 /* 0x08a4 */; - 554: data_o = 32'hfee78de3 /* 0x08a8 */; - 555: data_o = 32'h01092503 /* 0x08ac */; - 556: data_o = 32'h8cdff0ef /* 0x08b0 */; - 557: data_o = 32'h00c92703 /* 0x08b4 */; - 558: data_o = 32'h0f634785 /* 0x08b8 */; - 559: data_o = 32'h551b02f7 /* 0x08bc */; - 560: data_o = 32'hd8080085 /* 0x08c0 */; - 561: data_o = 32'h27834689 /* 0x08c4 */; - 562: data_o = 32'hc4930089 /* 0x08c8 */; - 563: data_o = 32'h67050014 /* 0x08cc */; - 564: data_o = 32'h0094949b /* 0x08d0 */; - 565: data_o = 32'hc0070713 /* 0x08d4 */; - 566: data_o = 32'h00a7979b /* 0x08d8 */; - 567: data_o = 32'he7338ff9 /* 0x08dc */; - 568: data_o = 32'h8fd90096 /* 0x08e0 */; - 569: data_o = 32'h8fd96709 /* 0x08e4 */; - 570: data_o = 32'h60e22781 /* 0x08e8 */; - 571: data_o = 32'h6442d41c /* 0x08ec */; - 572: data_o = 32'h690264a2 /* 0x08f0 */; - 573: data_o = 32'h80826105 /* 0x08f4 */; - 574: data_o = 32'h468dd808 /* 0x08f8 */; - 575: data_o = 32'hcd0db7e9 /* 0x08fc */; - 576: data_o = 32'hf793c99d /* 0x0900 */; - 577: data_o = 32'hcb9d0035 /* 0x0904 */; - 578: data_o = 32'h04800693 /* 0x0908 */; - 579: data_o = 32'h6118c21d /* 0x090c */; - 580: data_o = 32'hf7934b5c /* 0x0910 */; - 581: data_o = 32'h8de30ff7 /* 0x0914 */; - 582: data_o = 32'hc783fed7 /* 0x0918 */; - 583: data_o = 32'h367d0005 /* 0x091c */; - 584: data_o = 32'h08230585 /* 0x0920 */; - 585: data_o = 32'h164202f7 /* 0x0924 */; - 586: data_o = 32'h0035f793 /* 0x0928 */; - 587: data_o = 32'hc7999241 /* 0x092c */; - 588: data_o = 32'h4501fe79 /* 0x0930 */; - 589: data_o = 32'hde758082 /* 0x0934 */; - 590: data_o = 32'h8082450d /* 0x0938 */; - 591: data_o = 32'h882e478d /* 0x093c */; - 592: data_o = 32'h02c7f963 /* 0x0940 */; - 593: data_o = 32'hffc6081b /* 0x0944 */; - 594: data_o = 32'h58131842 /* 0x0948 */; - 595: data_o = 32'h61180328 /* 0x094c */; - 596: data_o = 32'h8793080a /* 0x0950 */; - 597: data_o = 32'h983e0045 /* 0x0954 */; - 598: data_o = 32'h04800693 /* 0x0958 */; - 599: data_o = 32'hf7934b5c /* 0x095c */; - 600: data_o = 32'h8de30ff7 /* 0x0960 */; - 601: data_o = 32'h419cfed7 /* 0x0964 */; - 602: data_o = 32'hdb1c0591 /* 0x0968 */; - 603: data_o = 32'hff0598e3 /* 0x096c */; - 604: data_o = 32'h85c28a0d /* 0x0970 */; - 605: data_o = 32'h073bde5d /* 0x0974 */; - 606: data_o = 32'h174200c8 /* 0x0978 */; - 607: data_o = 32'h04800613 /* 0x097c */; - 608: data_o = 32'h61149341 /* 0x0980 */; - 609: data_o = 32'hf7934adc /* 0x0984 */; - 610: data_o = 32'h8de30ff7 /* 0x0988 */; - 611: data_o = 32'hc803fec7 /* 0x098c */; - 612: data_o = 32'h05850005 /* 0x0990 */; - 613: data_o = 32'h03059793 /* 0x0994 */; - 614: data_o = 32'h882393c1 /* 0x0998 */; - 615: data_o = 32'h12e30306 /* 0x099c */; - 616: data_o = 32'h4501fef7 /* 0x09a0 */; - 617: data_o = 32'h41988082 /* 0x09a4 */; - 618: data_o = 32'hf0227179 /* 0x09a8 */; - 619: data_o = 32'hf406e44e /* 0x09ac */; - 620: data_o = 32'he84aec26 /* 0x09b0 */; - 621: data_o = 32'h87ae4691 /* 0x09b4 */; - 622: data_o = 32'h843289aa /* 0x09b8 */; - 623: data_o = 32'h02d70063 /* 0x09bc */; - 624: data_o = 32'h0a634695 /* 0x09c0 */; - 625: data_o = 32'h468d06d7 /* 0x09c4 */; - 626: data_o = 32'h04d70d63 /* 0x09c8 */; - 627: data_o = 32'h740270a2 /* 0x09cc */; - 628: data_o = 32'h694264e2 /* 0x09d0 */; - 629: data_o = 32'h450d69a2 /* 0x09d4 */; - 630: data_o = 32'h80826145 /* 0x09d8 */; - 631: data_o = 32'h0085a903 /* 0x09dc */; - 632: data_o = 32'h0185d483 /* 0x09e0 */; - 633: data_o = 32'h44136785 /* 0x09e4 */; - 634: data_o = 32'h67050014 /* 0x09e8 */; - 635: data_o = 32'h0094141b /* 0x09ec */; - 636: data_o = 32'hc0070713 /* 0x09f0 */; - 637: data_o = 32'h00a9191b /* 0x09f4 */; - 638: data_o = 32'h00e97933 /* 0x09f8 */; - 639: data_o = 32'h34fd8fc1 /* 0x09fc */; - 640: data_o = 32'h0009b703 /* 0x0a00 */; - 641: data_o = 32'h0127e7b3 /* 0x0a04 */; - 642: data_o = 32'h1ff4f493 /* 0x0a08 */; - 643: data_o = 32'h740270a2 /* 0x0a0c */; - 644: data_o = 32'h27818fc5 /* 0x0a10 */; - 645: data_o = 32'h64e2d71c /* 0x0a14 */; - 646: data_o = 32'h69a26942 /* 0x0a18 */; - 647: data_o = 32'h61454501 /* 0x0a1c */; - 648: data_o = 32'hd4838082 /* 0x0a20 */; - 649: data_o = 32'h698c0185 /* 0x0a24 */; - 650: data_o = 32'h0087a903 /* 0x0a28 */; - 651: data_o = 32'hf0ef8626 /* 0x0a2c */; - 652: data_o = 32'h6789ed1f /* 0x0a30 */; - 653: data_o = 32'hd483bf4d /* 0x0a34 */; - 654: data_o = 32'h698c0205 /* 0x0a38 */; - 655: data_o = 32'h0087a903 /* 0x0a3c */; - 656: data_o = 32'hf0ef8626 /* 0x0a40 */; - 657: data_o = 32'h678debdf /* 0x0a44 */; - 658: data_o = 32'h0a63bf79 /* 0x0a48 */; - 659: data_o = 32'h87631605 /* 0x0a4c */; - 660: data_o = 32'h11411405 /* 0x0a50 */; - 661: data_o = 32'he402e002 /* 0x0a54 */; - 662: data_o = 32'h0035f793 /* 0x0a58 */; - 663: data_o = 32'h4701c78d /* 0x0a5c */; - 664: data_o = 32'h5663c641 /* 0x0a60 */; - 665: data_o = 32'h377d08e0 /* 0x0a64 */; - 666: data_o = 32'h00814783 /* 0x0a68 */; - 667: data_o = 32'h367d0585 /* 0x0a6c */; - 668: data_o = 32'hfef58fa3 /* 0x0a70 */; - 669: data_o = 32'h164267a2 /* 0x0a74 */; - 670: data_o = 32'h83a1c03a /* 0x0a78 */; - 671: data_o = 32'hf793e43e /* 0x0a7c */; - 672: data_o = 32'h92410035 /* 0x0a80 */; - 673: data_o = 32'h478dfff1 /* 0x0a84 */; - 674: data_o = 32'h12c7fd63 /* 0x0a88 */; - 675: data_o = 32'hffc6069b /* 0x0a8c */; - 676: data_o = 32'h92c916c2 /* 0x0a90 */; - 677: data_o = 32'h068a4702 /* 0x0a94 */; - 678: data_o = 32'h00458793 /* 0x0a98 */; - 679: data_o = 32'h488d96be /* 0x0a9c */; - 680: data_o = 32'h08e8d863 /* 0x0aa0 */; - 681: data_o = 32'h48223771 /* 0x0aa4 */; - 682: data_o = 32'hc03a47b2 /* 0x0aa8 */; - 683: data_o = 32'h0105a023 /* 0x0aac */; - 684: data_o = 32'h0591c43e /* 0x0ab0 */; - 685: data_o = 32'hfed596e3 /* 0x0ab4 */; - 686: data_o = 32'hc61d8a0d /* 0x0ab8 */; - 687: data_o = 32'h9e398736 /* 0x0abc */; - 688: data_o = 32'h16424682 /* 0x0ac0 */; - 689: data_o = 32'h58639241 /* 0x0ac4 */; - 690: data_o = 32'h36fd0ad0 /* 0x0ac8 */; - 691: data_o = 32'h00814783 /* 0x0acc */; - 692: data_o = 32'hc0360705 /* 0x0ad0 */; - 693: data_o = 32'hfef70fa3 /* 0x0ad4 */; - 694: data_o = 32'h83a167a2 /* 0x0ad8 */; - 695: data_o = 32'h1793e43e /* 0x0adc */; - 696: data_o = 32'h93c10307 /* 0x0ae0 */; - 697: data_o = 32'hfef611e3 /* 0x0ae4 */; - 698: data_o = 32'h01414501 /* 0x0ae8 */; - 699: data_o = 32'h61148082 /* 0x0aec */; - 700: data_o = 32'hd79b4adc /* 0x0af0 */; - 701: data_o = 32'hf7930087 /* 0x0af4 */; - 702: data_o = 32'hdbfd0ff7 /* 0x0af8 */; - 703: data_o = 32'h769356dc /* 0x0afc */; - 704: data_o = 32'h27810037 /* 0x0b00 */; - 705: data_o = 32'h0741ea81 /* 0x0b04 */; - 706: data_o = 32'h2c23970a /* 0x0b08 */; - 707: data_o = 32'h4702fef7 /* 0x0b0c */; - 708: data_o = 32'hbf99270d /* 0x0b10 */; - 709: data_o = 32'h00410813 /* 0x0b14 */; - 710: data_o = 32'h00e106b3 /* 0x0b18 */; - 711: data_o = 32'h8423983a /* 0x0b1c */; - 712: data_o = 32'h068500f6 /* 0x0b20 */; - 713: data_o = 32'h0087d79b /* 0x0b24 */; - 714: data_o = 32'hff069be3 /* 0x0b28 */; - 715: data_o = 32'hbf2d270d /* 0x0b2c */; - 716: data_o = 32'h00053803 /* 0x0b30 */; - 717: data_o = 32'h01482783 /* 0x0b34 */; - 718: data_o = 32'h0087d79b /* 0x0b38 */; - 719: data_o = 32'h0ff7f793 /* 0x0b3c */; - 720: data_o = 32'h2783dbf5 /* 0x0b40 */; - 721: data_o = 32'h781302c8 /* 0x0b44 */; - 722: data_o = 32'h27810037 /* 0x0b48 */; - 723: data_o = 32'h00081863 /* 0x0b4c */; - 724: data_o = 32'h970a0741 /* 0x0b50 */; - 725: data_o = 32'hfef72c23 /* 0x0b54 */; - 726: data_o = 32'hb7b14702 /* 0x0b58 */; - 727: data_o = 32'h00410313 /* 0x0b5c */; - 728: data_o = 32'h00e10833 /* 0x0b60 */; - 729: data_o = 32'h0423933a /* 0x0b64 */; - 730: data_o = 32'h080500f8 /* 0x0b68 */; - 731: data_o = 32'h0087d79b /* 0x0b6c */; - 732: data_o = 32'hfe681be3 /* 0x0b70 */; - 733: data_o = 32'h610cbf0d /* 0x0b74 */; - 734: data_o = 32'hd79b49dc /* 0x0b78 */; - 735: data_o = 32'hf7930087 /* 0x0b7c */; - 736: data_o = 32'hdbfd0ff7 /* 0x0b80 */; - 737: data_o = 32'hf59355dc /* 0x0b84 */; - 738: data_o = 32'h27810036 /* 0x0b88 */; - 739: data_o = 32'h06c1e999 /* 0x0b8c */; - 740: data_o = 32'hac23968a /* 0x0b90 */; - 741: data_o = 32'h4682fef6 /* 0x0b94 */; - 742: data_o = 32'hbf0d268d /* 0x0b98 */; - 743: data_o = 32'h4501e20d /* 0x0b9c */; - 744: data_o = 32'h08138082 /* 0x0ba0 */; - 745: data_o = 32'h05b30041 /* 0x0ba4 */; - 746: data_o = 32'h983600d1 /* 0x0ba8 */; - 747: data_o = 32'h00f58423 /* 0x0bac */; - 748: data_o = 32'hd79b0585 /* 0x0bb0 */; - 749: data_o = 32'h1be30087 /* 0x0bb4 */; - 750: data_o = 32'h268dfeb8 /* 0x0bb8 */; - 751: data_o = 32'h450dbf01 /* 0x0bbc */; - 752: data_o = 32'h86ae8082 /* 0x0bc0 */; - 753: data_o = 32'h6518bddd /* 0x0bc4 */; - 754: data_o = 32'hf7b7712d /* 0x0bc8 */; - 755: data_o = 32'hee0602fa /* 0x0bcc */; - 756: data_o = 32'he626ea22 /* 0x0bd0 */; - 757: data_o = 32'hfdcee24a /* 0x0bd4 */; - 758: data_o = 32'hf5d6f9d2 /* 0x0bd8 */; - 759: data_o = 32'heddef1da /* 0x0bdc */; - 760: data_o = 32'he5e6e9e2 /* 0x0be0 */; - 761: data_o = 32'hfd6ee1ea /* 0x0be4 */; - 762: data_o = 32'h07f78793 /* 0x0be8 */; - 763: data_o = 32'hf432f02e /* 0x0bec */; - 764: data_o = 32'hed63e436 /* 0x0bf0 */; - 765: data_o = 32'h67a21ce7 /* 0x0bf4 */; - 766: data_o = 32'h88634c01 /* 0x0bf8 */; - 767: data_o = 32'h6a851207 /* 0x0bfc */; - 768: data_o = 32'hc00a8793 /* 0x0c00 */; - 769: data_o = 32'h44858d2a /* 0x0c04 */; - 770: data_o = 32'h4985e83e /* 0x0c08 */; - 771: data_o = 32'hf88277a2 /* 0x0c0c */; - 772: data_o = 32'h073be082 /* 0x0c10 */; - 773: data_o = 32'h778200fc /* 0x0c14 */; - 774: data_o = 32'hf482f082 /* 0x0c18 */; - 775: data_o = 32'hed3e97e2 /* 0x0c1c */; - 776: data_o = 32'he50267a2 /* 0x0c20 */; - 777: data_o = 32'hd8ba46cd /* 0x0c24 */; - 778: data_o = 32'hc53a4711 /* 0x0c28 */; - 779: data_o = 32'he482fc02 /* 0x0c2c */; - 780: data_o = 32'hec82e882 /* 0x0c30 */; - 781: data_o = 32'he102fc82 /* 0x0c34 */; - 782: data_o = 32'hf502e902 /* 0x0c38 */; - 783: data_o = 32'h04d10023 /* 0x0c3c */; - 784: data_o = 32'hd6a6d0a6 /* 0x0c40 */; - 785: data_o = 32'h418787b3 /* 0x0c44 */; - 786: data_o = 32'h10000713 /* 0x0c48 */; - 787: data_o = 32'h00f77463 /* 0x0c4c */; - 788: data_o = 32'h10000793 /* 0x0c50 */; - 789: data_o = 32'h010d2703 /* 0x0c54 */; - 790: data_o = 32'h000d3403 /* 0x0c58 */; - 791: data_o = 32'h03810d93 /* 0x0c5c */; - 792: data_o = 32'hd058f13e /* 0x0c60 */; - 793: data_o = 32'h47018a6e /* 0x0c64 */; - 794: data_o = 32'h4b894a81 /* 0x0c68 */; - 795: data_o = 32'h04800c93 /* 0x0c6c */; - 796: data_o = 32'h4b0d6909 /* 0x0c70 */; - 797: data_o = 32'hffea8613 /* 0x0c74 */; - 798: data_o = 32'h00163613 /* 0x0c78 */; - 799: data_o = 32'hd79b485c /* 0x0c7c */; - 800: data_o = 32'hdfed01f7 /* 0x0c80 */; - 801: data_o = 32'h11770d63 /* 0x0c84 */; - 802: data_o = 32'h0eebe063 /* 0x0c88 */; - 803: data_o = 32'h485cc34d /* 0x0c8c */; - 804: data_o = 32'h0ff7f793 /* 0x0c90 */; - 805: data_o = 32'hff978de3 /* 0x0c94 */; - 806: data_o = 32'h010a2503 /* 0x0c98 */; - 807: data_o = 32'hf0efec32 /* 0x0c9c */; - 808: data_o = 32'h2783cdef /* 0x0ca0 */; - 809: data_o = 32'h666200ca /* 0x0ca4 */; - 810: data_o = 32'h10978f63 /* 0x0ca8 */; - 811: data_o = 32'h0085551b /* 0x0cac */; - 812: data_o = 32'h4709d808 /* 0x0cb0 */; - 813: data_o = 32'h008a2783 /* 0x0cb4 */; - 814: data_o = 32'h863b66c2 /* 0x0cb8 */; - 815: data_o = 32'h979b40c9 /* 0x0cbc */; - 816: data_o = 32'h161b00a7 /* 0x0cc0 */; - 817: data_o = 32'h8ff50096 /* 0x0cc4 */; - 818: data_o = 32'h8fd98fd1 /* 0x0cc8 */; - 819: data_o = 32'h0127e7b3 /* 0x0ccc */; - 820: data_o = 32'hd41c2781 /* 0x0cd0 */; - 821: data_o = 32'h0a130a85 /* 0x0cd4 */; - 822: data_o = 32'h9263028a /* 0x0cd8 */; - 823: data_o = 32'h8c93096a /* 0x0cdc */; - 824: data_o = 32'h4911078d /* 0x0ce0 */; - 825: data_o = 32'ha8314415 /* 0x0ce4 */; - 826: data_o = 32'h9863856a /* 0x0ce8 */; - 827: data_o = 32'hd6030087 /* 0x0cec */; - 828: data_o = 32'hb583020d /* 0x0cf0 */; - 829: data_o = 32'hf0ef018d /* 0x0cf4 */; - 830: data_o = 32'h8d93d55f /* 0x0cf8 */; - 831: data_o = 32'h8163028d /* 0x0cfc */; - 832: data_o = 32'ha78303bc /* 0x0d00 */; - 833: data_o = 32'h91e3000d /* 0x0d04 */; - 834: data_o = 32'hd603ff27 /* 0x0d08 */; - 835: data_o = 32'hb583018d /* 0x0d0c */; - 836: data_o = 32'h856a010d /* 0x0d10 */; - 837: data_o = 32'h028d8d93 /* 0x0d14 */; - 838: data_o = 32'hd33ff0ef /* 0x0d18 */; - 839: data_o = 32'hffbc93e3 /* 0x0d1c */; - 840: data_o = 32'h0c1367a2 /* 0x0d20 */; - 841: data_o = 32'h63e3100c /* 0x0d24 */; - 842: data_o = 32'h4501eefc /* 0x0d28 */; - 843: data_o = 32'h485ca891 /* 0x0d2c */; - 844: data_o = 32'h0ff7f793 /* 0x0d30 */; - 845: data_o = 32'hff978de3 /* 0x0d34 */; - 846: data_o = 32'h008a4703 /* 0x0d38 */; - 847: data_o = 32'h40c987bb /* 0x0d3c */; - 848: data_o = 32'h0097979b /* 0x0d40 */; - 849: data_o = 32'h02e40823 /* 0x0d44 */; - 850: data_o = 32'h000d3703 /* 0x0d48 */; - 851: data_o = 32'h0127e7b3 /* 0x0d4c */; - 852: data_o = 32'hd71c2781 /* 0x0d50 */; - 853: data_o = 32'h0a130a85 /* 0x0d54 */; - 854: data_o = 32'h82e3028a /* 0x0d58 */; - 855: data_o = 32'h3403f96a /* 0x0d5c */; - 856: data_o = 32'h2703000d /* 0x0d60 */; - 857: data_o = 32'hb739000a /* 0x0d64 */; - 858: data_o = 32'hea633775 /* 0x0d68 */; - 859: data_o = 32'h85d200eb /* 0x0d6c */; - 860: data_o = 32'hf0ef856a /* 0x0d70 */; - 861: data_o = 32'h2501c35f /* 0x0d74 */; - 862: data_o = 32'h2501dd71 /* 0x0d78 */; - 863: data_o = 32'h450da011 /* 0x0d7c */; - 864: data_o = 32'h645260f2 /* 0x0d80 */; - 865: data_o = 32'h691264b2 /* 0x0d84 */; - 866: data_o = 32'h7a4e79ee /* 0x0d88 */; - 867: data_o = 32'h7b0e7aae /* 0x0d8c */; - 868: data_o = 32'h6c4e6bee /* 0x0d90 */; - 869: data_o = 32'h6d0e6cae /* 0x0d94 */; - 870: data_o = 32'h61157dea /* 0x0d98 */; - 871: data_o = 32'h27838082 /* 0x0d9c */; - 872: data_o = 32'h5703008a /* 0x0da0 */; - 873: data_o = 32'h66c2010a /* 0x0da4 */; - 874: data_o = 32'h40c9863b /* 0x0da8 */; - 875: data_o = 32'h00a7979b /* 0x0dac */; - 876: data_o = 32'h161b8ff5 /* 0x0db0 */; - 877: data_o = 32'h377d0096 /* 0x0db4 */; - 878: data_o = 32'h77138fd1 /* 0x0db8 */; - 879: data_o = 32'h8fd91ff7 /* 0x0dbc */; - 880: data_o = 32'hd41c2781 /* 0x0dc0 */; - 881: data_o = 32'hd808bf41 /* 0x0dc4 */; - 882: data_o = 32'hb5ed470d /* 0x0dc8 */; - 883: data_o = 32'hbf4d4555 /* 0x0dcc */; - 884: data_o = 32'h11016118 /* 0x0dd0 */; - 885: data_o = 32'he426e822 /* 0x0dd4 */; - 886: data_o = 32'h84aaec06 /* 0x0dd8 */; - 887: data_o = 32'hd34c8432 /* 0x0ddc */; - 888: data_o = 32'hd79b4b5c /* 0x0de0 */; - 889: data_o = 32'hdfed01f7 /* 0x0de4 */; - 890: data_o = 32'h4689401c /* 0x0de8 */; - 891: data_o = 32'h08d78a63 /* 0x0dec */; - 892: data_o = 32'h02f6eb63 /* 0x0df0 */; - 893: data_o = 32'h4601c3bd /* 0x0df4 */; - 894: data_o = 32'h852685a2 /* 0x0df8 */; - 895: data_o = 32'ha93ff0ef /* 0x0dfc */; - 896: data_o = 32'h4711401c /* 0x0e00 */; - 897: data_o = 32'h02e78f63 /* 0x0e04 */; - 898: data_o = 32'h92634715 /* 0x0e08 */; - 899: data_o = 32'h560304e7 /* 0x0e0c */; - 900: data_o = 32'h6c0c0204 /* 0x0e10 */; - 901: data_o = 32'hf0ef8526 /* 0x0e14 */; - 902: data_o = 32'h4501c35f /* 0x0e18 */; - 903: data_o = 32'h644260e2 /* 0x0e1c */; - 904: data_o = 32'h610564a2 /* 0x0e20 */; - 905: data_o = 32'h37f58082 /* 0x0e24 */; - 906: data_o = 32'h04f6ea63 /* 0x0e28 */; - 907: data_o = 32'h85a24601 /* 0x0e2c */; - 908: data_o = 32'hf0ef8526 /* 0x0e30 */; - 909: data_o = 32'h2501b75f /* 0x0e34 */; - 910: data_o = 32'h401cf175 /* 0x0e38 */; - 911: data_o = 32'h95e34711 /* 0x0e3c */; - 912: data_o = 32'h5603fce7 /* 0x0e40 */; - 913: data_o = 32'h680c0184 /* 0x0e44 */; - 914: data_o = 32'hf0ef8526 /* 0x0e48 */; - 915: data_o = 32'h60e2c01f /* 0x0e4c */; - 916: data_o = 32'h64a26442 /* 0x0e50 */; - 917: data_o = 32'h61054501 /* 0x0e54 */; - 918: data_o = 32'h06938082 /* 0x0e58 */; - 919: data_o = 32'h4b5c0480 /* 0x0e5c */; - 920: data_o = 32'h0ff7f793 /* 0x0e60 */; - 921: data_o = 32'hfed78de3 /* 0x0e64 */; - 922: data_o = 32'h00844783 /* 0x0e68 */; - 923: data_o = 32'h02f70823 /* 0x0e6c */; - 924: data_o = 32'h67896098 /* 0x0e70 */; - 925: data_o = 32'h20078793 /* 0x0e74 */; - 926: data_o = 32'hb759d71c /* 0x0e78 */; - 927: data_o = 32'hbf79450d /* 0x0e7c */; - 928: data_o = 32'h01045783 /* 0x0e80 */; - 929: data_o = 32'h66054414 /* 0x0e84 */; - 930: data_o = 32'h969b37fd /* 0x0e88 */; - 931: data_o = 32'h061300a6 /* 0x0e8c */; - 932: data_o = 32'hf793c006 /* 0x0e90 */; - 933: data_o = 32'h8ef11ff7 /* 0x0e94 */; - 934: data_o = 32'he7938fd5 /* 0x0e98 */; - 935: data_o = 32'h27812007 /* 0x0e9c */; - 936: data_o = 32'hbfb9d71c /* 0x0ea0 */; - 937: data_o = 32'he42e7175 /* 0x0ea4 */; - 938: data_o = 32'h478dec02 /* 0x0ea8 */; - 939: data_o = 32'hcc3e490c /* 0x0eac */; - 940: data_o = 32'hf0d2003c /* 0x0eb0 */; - 941: data_o = 32'hf43ee8da /* 0x0eb4 */; - 942: data_o = 32'h47998b32 /* 0x0eb8 */; - 943: data_o = 32'h08308a36 /* 0x0ebc */; - 944: data_o = 32'he1224685 /* 0x0ec0 */; - 945: data_o = 32'hf4cef8ca /* 0x0ec4 */; - 946: data_o = 32'hfca6e506 /* 0x0ec8 */; - 947: data_o = 32'he4deecd6 /* 0x0ecc */; - 948: data_o = 32'h893a89aa /* 0x0ed0 */; - 949: data_o = 32'hfc02f002 /* 0x0ed4 */; - 950: data_o = 32'hf0eff83e /* 0x0ed8 */; - 951: data_o = 32'h041bef7f /* 0x0edc */; - 952: data_o = 32'he4210005 /* 0x0ee0 */; - 953: data_o = 32'h00814703 /* 0x0ee4 */; - 954: data_o = 32'h04c00793 /* 0x0ee8 */; - 955: data_o = 32'h0109a583 /* 0x0eec */; - 956: data_o = 32'h0af70663 /* 0x0ef0 */; - 957: data_o = 32'h4b9144a1 /* 0x0ef4 */; - 958: data_o = 32'ha0294a85 /* 0x0ef8 */; - 959: data_o = 32'h000a0783 /* 0x0efc */; - 960: data_o = 32'h0407d163 /* 0x0f00 */; - 961: data_o = 32'h0109a583 /* 0x0f04 */; - 962: data_o = 32'h4685ec02 /* 0x0f08 */; - 963: data_o = 32'h854e0830 /* 0x0f0c */; - 964: data_o = 32'hfc02f002 /* 0x0f10 */; - 965: data_o = 32'hf452cc5e /* 0x0f14 */; - 966: data_o = 32'hf0eff856 /* 0x0f18 */; - 967: data_o = 32'h041beb7f /* 0x0f1c */; - 968: data_o = 32'h34fd0005 /* 0x0f20 */; - 969: data_o = 32'hf8f9e019 /* 0x0f24 */; - 970: data_o = 32'h60aa4449 /* 0x0f28 */; - 971: data_o = 32'h640a8522 /* 0x0f2c */; - 972: data_o = 32'h794674e6 /* 0x0f30 */; - 973: data_o = 32'h7a0679a6 /* 0x0f34 */; - 974: data_o = 32'h6b466ae6 /* 0x0f38 */; - 975: data_o = 32'h61496ba6 /* 0x0f3c */; - 976: data_o = 32'h16938082 /* 0x0f40 */; - 977: data_o = 32'h8793020b /* 0x0f44 */; - 978: data_o = 32'hd7131541 /* 0x0f48 */; - 979: data_o = 32'h97ba01d6 /* 0x0f4c */; - 980: data_o = 32'h0863639c /* 0x0f50 */; - 981: data_o = 32'h17fd075b /* 0x0f54 */; - 982: data_o = 32'h18e3e385 /* 0x0f58 */; - 983: data_o = 32'ha783fc09 /* 0x0f5c */; - 984: data_o = 32'hb7030149 /* 0x0f60 */; - 985: data_o = 32'hd35c0009 /* 0x0f64 */; - 986: data_o = 32'hd79b4b5c /* 0x0f68 */; - 987: data_o = 32'hdfed01f7 /* 0x0f6c */; - 988: data_o = 32'hd71c479d /* 0x0f70 */; - 989: data_o = 32'hbf554401 /* 0x0f74 */; - 990: data_o = 32'h0109a583 /* 0x0f78 */; - 991: data_o = 32'h0a05ec02 /* 0x0f7c */; - 992: data_o = 32'h08304685 /* 0x0f80 */; - 993: data_o = 32'hf002854e /* 0x0f84 */; - 994: data_o = 32'hcc5efc02 /* 0x0f88 */; - 995: data_o = 32'hf83ef452 /* 0x0f8c */; - 996: data_o = 32'he41ff0ef /* 0x0f90 */; - 997: data_o = 32'hd1712501 /* 0x0f94 */; - 998: data_o = 32'hbf41842a /* 0x0f98 */; - 999: data_o = 32'h4791ec02 /* 0x0f9c */; - 1000: data_o = 32'h0793cc3e /* 0x0fa0 */; - 1001: data_o = 32'hf43e0171 /* 0x0fa4 */; - 1002: data_o = 32'h47854685 /* 0x0fa8 */; - 1003: data_o = 32'h854e0830 /* 0x0fac */; - 1004: data_o = 32'hfc02f002 /* 0x0fb0 */; - 1005: data_o = 32'hf0eff83e /* 0x0fb4 */; - 1006: data_o = 32'h041be1bf /* 0x0fb8 */; - 1007: data_o = 32'hd81d0005 /* 0x0fbc */; - 1008: data_o = 32'h6489b7ad /* 0x0fc0 */; - 1009: data_o = 32'h71048493 /* 0x0fc4 */; - 1010: data_o = 32'h0a934b11 /* 0x0fc8 */; - 1011: data_o = 32'h4a050171 /* 0x0fcc */; - 1012: data_o = 32'hc49da029 /* 0x0fd0 */; - 1013: data_o = 32'h01714783 /* 0x0fd4 */; - 1014: data_o = 32'ha583f3c9 /* 0x0fd8 */; - 1015: data_o = 32'hec020109 /* 0x0fdc */; - 1016: data_o = 32'h08304685 /* 0x0fe0 */; - 1017: data_o = 32'hf002854e /* 0x0fe4 */; - 1018: data_o = 32'hcc5afc02 /* 0x0fe8 */; - 1019: data_o = 32'hf852f456 /* 0x0fec */; - 1020: data_o = 32'hde1ff0ef /* 0x0ff0 */; - 1021: data_o = 32'h0005079b /* 0x0ff4 */; - 1022: data_o = 32'hdfe134fd /* 0x0ff8 */; - 1023: data_o = 32'hb735843e /* 0x0ffc */; - 1024: data_o = 32'hb725444d /* 0x1000 */; - 1025: data_o = 32'hec267179 /* 0x1004 */; - 1026: data_o = 32'h84b6e84a /* 0x1008 */; - 1027: data_o = 32'h0034893a /* 0x100c */; - 1028: data_o = 32'hf0224701 /* 0x1010 */; - 1029: data_o = 32'h8432f406 /* 0x1014 */; - 1030: data_o = 32'he8dff0ef /* 0x1018 */; - 1031: data_o = 32'hc485e50d /* 0x101c */; - 1032: data_o = 32'h02041713 /* 0x1020 */; - 1033: data_o = 32'h01d75613 /* 0x1024 */; - 1034: data_o = 32'h15418793 /* 0x1028 */; - 1035: data_o = 32'h639897b2 /* 0x102c */; - 1036: data_o = 32'h478566a2 /* 0x1030 */; - 1037: data_o = 32'h0037171b /* 0x1034 */; - 1038: data_o = 32'h00e797bb /* 0x1038 */; - 1039: data_o = 32'hc73337fd /* 0x103c */; - 1040: data_o = 32'h8f7d0126 /* 0x1040 */; - 1041: data_o = 32'h70a2e719 /* 0x1044 */; - 1042: data_o = 32'h64e27402 /* 0x1048 */; - 1043: data_o = 32'h61456942 /* 0x104c */; - 1044: data_o = 32'h70a28082 /* 0x1050 */; - 1045: data_o = 32'h8ff57402 /* 0x1054 */; - 1046: data_o = 32'h694264e2 /* 0x1058 */; - 1047: data_o = 32'h0007851b /* 0x105c */; + 523: data_o = 32'hfc700713 /* 0x082c */; + 524: data_o = 32'h00e78423 /* 0x0830 */; + 525: data_o = 32'h01001797 /* 0x0834 */; + 526: data_o = 32'h7cc78793 /* 0x0838 */; + 527: data_o = 32'h02000713 /* 0x083c */; + 528: data_o = 32'h00e78823 /* 0x0840 */; + 529: data_o = 32'h0ff0000f /* 0x0844 */; + 530: data_o = 32'hf7974719 /* 0x0848 */; + 531: data_o = 32'h879300ff /* 0x084c */; + 532: data_o = 32'h479c7b67 /* 0x0850 */; + 533: data_o = 32'hc7958b89 /* 0x0854 */; + 534: data_o = 32'h00fff797 /* 0x0858 */; + 535: data_o = 32'h7a878793 /* 0x085c */; + 536: data_o = 32'h0007a423 /* 0x0860 */; + 537: data_o = 32'h00fff797 /* 0x0864 */; + 538: data_o = 32'h79c78793 /* 0x0868 */; + 539: data_o = 32'hf79743c8 /* 0x086c */; + 540: data_o = 32'ha78300ff /* 0x0870 */; + 541: data_o = 32'h15027927 /* 0x0874 */; + 542: data_o = 32'h93811782 /* 0x0878 */; + 543: data_o = 32'hf06f8d5d /* 0x087c */; + 544: data_o = 32'h179783bf /* 0x0880 */; + 545: data_o = 32'h87930100 /* 0x0884 */; + 546: data_o = 32'hc78377e7 /* 0x0888 */; + 547: data_o = 32'h8b850147 /* 0x088c */; + 548: data_o = 32'h1797dfcd /* 0x0890 */; + 549: data_o = 32'hc7830100 /* 0x0894 */; + 550: data_o = 32'h98e376e7 /* 0x0898 */; + 551: data_o = 32'hb385fae7 /* 0x089c */; + 552: data_o = 32'he8221101 /* 0x08a0 */; + 553: data_o = 32'he4266100 /* 0x08a4 */; + 554: data_o = 32'hec06e04a /* 0x08a8 */; + 555: data_o = 32'h84b2892e /* 0x08ac */; + 556: data_o = 32'h04800713 /* 0x08b0 */; + 557: data_o = 32'hf793485c /* 0x08b4 */; + 558: data_o = 32'h8de30ff7 /* 0x08b8 */; + 559: data_o = 32'h2503fee7 /* 0x08bc */; + 560: data_o = 32'hf0ef0109 /* 0x08c0 */; + 561: data_o = 32'h27038cbf /* 0x08c4 */; + 562: data_o = 32'h478500c9 /* 0x08c8 */; + 563: data_o = 32'h02f70f63 /* 0x08cc */; + 564: data_o = 32'h0085551b /* 0x08d0 */; + 565: data_o = 32'h4689d808 /* 0x08d4 */; + 566: data_o = 32'h00892783 /* 0x08d8 */; + 567: data_o = 32'h0014c493 /* 0x08dc */; + 568: data_o = 32'h949b6705 /* 0x08e0 */; + 569: data_o = 32'h07130094 /* 0x08e4 */; + 570: data_o = 32'h979bc007 /* 0x08e8 */; + 571: data_o = 32'h8ff900a7 /* 0x08ec */; + 572: data_o = 32'h0096e733 /* 0x08f0 */; + 573: data_o = 32'h67098fd9 /* 0x08f4 */; + 574: data_o = 32'h27818fd9 /* 0x08f8 */; + 575: data_o = 32'hd41c60e2 /* 0x08fc */; + 576: data_o = 32'h64a26442 /* 0x0900 */; + 577: data_o = 32'h61056902 /* 0x0904 */; + 578: data_o = 32'hd8088082 /* 0x0908 */; + 579: data_o = 32'hb7e9468d /* 0x090c */; + 580: data_o = 32'hc99dcd0d /* 0x0910 */; + 581: data_o = 32'h0035f793 /* 0x0914 */; + 582: data_o = 32'h0693cb9d /* 0x0918 */; + 583: data_o = 32'hc21d0480 /* 0x091c */; + 584: data_o = 32'h4b5c6118 /* 0x0920 */; + 585: data_o = 32'h0ff7f793 /* 0x0924 */; + 586: data_o = 32'hfed78de3 /* 0x0928 */; + 587: data_o = 32'h0005c783 /* 0x092c */; + 588: data_o = 32'h0585367d /* 0x0930 */; + 589: data_o = 32'h02f70823 /* 0x0934 */; + 590: data_o = 32'hf7931642 /* 0x0938 */; + 591: data_o = 32'h92410035 /* 0x093c */; + 592: data_o = 32'hfe79c799 /* 0x0940 */; + 593: data_o = 32'h80824501 /* 0x0944 */; + 594: data_o = 32'h450dde75 /* 0x0948 */; + 595: data_o = 32'h478d8082 /* 0x094c */; + 596: data_o = 32'hf963882e /* 0x0950 */; + 597: data_o = 32'h081b02c7 /* 0x0954 */; + 598: data_o = 32'h1842ffc6 /* 0x0958 */; + 599: data_o = 32'h03285813 /* 0x095c */; + 600: data_o = 32'h080a6118 /* 0x0960 */; + 601: data_o = 32'h00458793 /* 0x0964 */; + 602: data_o = 32'h0693983e /* 0x0968 */; + 603: data_o = 32'h4b5c0480 /* 0x096c */; + 604: data_o = 32'h0ff7f793 /* 0x0970 */; + 605: data_o = 32'hfed78de3 /* 0x0974 */; + 606: data_o = 32'h0591419c /* 0x0978 */; + 607: data_o = 32'h98e3db1c /* 0x097c */; + 608: data_o = 32'h8a0dff05 /* 0x0980 */; + 609: data_o = 32'hde5d85c2 /* 0x0984 */; + 610: data_o = 32'h00c8073b /* 0x0988 */; + 611: data_o = 32'h06131742 /* 0x098c */; + 612: data_o = 32'h93410480 /* 0x0990 */; + 613: data_o = 32'h4adc6114 /* 0x0994 */; + 614: data_o = 32'h0ff7f793 /* 0x0998 */; + 615: data_o = 32'hfec78de3 /* 0x099c */; + 616: data_o = 32'h0005c803 /* 0x09a0 */; + 617: data_o = 32'h97930585 /* 0x09a4 */; + 618: data_o = 32'h93c10305 /* 0x09a8 */; + 619: data_o = 32'h03068823 /* 0x09ac */; + 620: data_o = 32'hfef712e3 /* 0x09b0 */; + 621: data_o = 32'h80824501 /* 0x09b4 */; + 622: data_o = 32'h71794198 /* 0x09b8 */; + 623: data_o = 32'he44ef022 /* 0x09bc */; + 624: data_o = 32'hec26f406 /* 0x09c0 */; + 625: data_o = 32'h4691e84a /* 0x09c4 */; + 626: data_o = 32'h89aa87ae /* 0x09c8 */; + 627: data_o = 32'h00638432 /* 0x09cc */; + 628: data_o = 32'h469502d7 /* 0x09d0 */; + 629: data_o = 32'h06d70a63 /* 0x09d4 */; + 630: data_o = 32'h0d63468d /* 0x09d8 */; + 631: data_o = 32'h70a204d7 /* 0x09dc */; + 632: data_o = 32'h64e27402 /* 0x09e0 */; + 633: data_o = 32'h69a26942 /* 0x09e4 */; + 634: data_o = 32'h6145450d /* 0x09e8 */; + 635: data_o = 32'ha9038082 /* 0x09ec */; + 636: data_o = 32'hd4830085 /* 0x09f0 */; + 637: data_o = 32'h67850185 /* 0x09f4 */; + 638: data_o = 32'h00144413 /* 0x09f8 */; + 639: data_o = 32'h141b6705 /* 0x09fc */; + 640: data_o = 32'h07130094 /* 0x0a00 */; + 641: data_o = 32'h191bc007 /* 0x0a04 */; + 642: data_o = 32'h793300a9 /* 0x0a08 */; + 643: data_o = 32'h8fc100e9 /* 0x0a0c */; + 644: data_o = 32'hb70334fd /* 0x0a10 */; + 645: data_o = 32'he7b30009 /* 0x0a14 */; + 646: data_o = 32'hf4930127 /* 0x0a18 */; + 647: data_o = 32'h70a21ff4 /* 0x0a1c */; + 648: data_o = 32'h8fc57402 /* 0x0a20 */; + 649: data_o = 32'hd71c2781 /* 0x0a24 */; + 650: data_o = 32'h694264e2 /* 0x0a28 */; + 651: data_o = 32'h450169a2 /* 0x0a2c */; + 652: data_o = 32'h80826145 /* 0x0a30 */; + 653: data_o = 32'h0185d483 /* 0x0a34 */; + 654: data_o = 32'ha903698c /* 0x0a38 */; + 655: data_o = 32'h86260087 /* 0x0a3c */; + 656: data_o = 32'hed1ff0ef /* 0x0a40 */; + 657: data_o = 32'hbf4d6789 /* 0x0a44 */; + 658: data_o = 32'h0205d483 /* 0x0a48 */; + 659: data_o = 32'ha903698c /* 0x0a4c */; + 660: data_o = 32'h86260087 /* 0x0a50 */; + 661: data_o = 32'hebdff0ef /* 0x0a54 */; + 662: data_o = 32'hbf79678d /* 0x0a58 */; + 663: data_o = 32'h16050a63 /* 0x0a5c */; + 664: data_o = 32'h14058763 /* 0x0a60 */; + 665: data_o = 32'he0021141 /* 0x0a64 */; + 666: data_o = 32'hf793e402 /* 0x0a68 */; + 667: data_o = 32'hc78d0035 /* 0x0a6c */; + 668: data_o = 32'hc6414701 /* 0x0a70 */; + 669: data_o = 32'h08e05663 /* 0x0a74 */; + 670: data_o = 32'h4783377d /* 0x0a78 */; + 671: data_o = 32'h05850081 /* 0x0a7c */; + 672: data_o = 32'h8fa3367d /* 0x0a80 */; + 673: data_o = 32'h67a2fef5 /* 0x0a84 */; + 674: data_o = 32'hc03a1642 /* 0x0a88 */; + 675: data_o = 32'he43e83a1 /* 0x0a8c */; + 676: data_o = 32'h0035f793 /* 0x0a90 */; + 677: data_o = 32'hfff19241 /* 0x0a94 */; + 678: data_o = 32'hfd63478d /* 0x0a98 */; + 679: data_o = 32'h069b12c7 /* 0x0a9c */; + 680: data_o = 32'h16c2ffc6 /* 0x0aa0 */; + 681: data_o = 32'h470292c9 /* 0x0aa4 */; + 682: data_o = 32'h8793068a /* 0x0aa8 */; + 683: data_o = 32'h96be0045 /* 0x0aac */; + 684: data_o = 32'hd863488d /* 0x0ab0 */; + 685: data_o = 32'h377108e8 /* 0x0ab4 */; + 686: data_o = 32'h47b24822 /* 0x0ab8 */; + 687: data_o = 32'ha023c03a /* 0x0abc */; + 688: data_o = 32'hc43e0105 /* 0x0ac0 */; + 689: data_o = 32'h96e30591 /* 0x0ac4 */; + 690: data_o = 32'h8a0dfed5 /* 0x0ac8 */; + 691: data_o = 32'h8736c61d /* 0x0acc */; + 692: data_o = 32'h46829e39 /* 0x0ad0 */; + 693: data_o = 32'h92411642 /* 0x0ad4 */; + 694: data_o = 32'h0ad05863 /* 0x0ad8 */; + 695: data_o = 32'h478336fd /* 0x0adc */; + 696: data_o = 32'h07050081 /* 0x0ae0 */; + 697: data_o = 32'h0fa3c036 /* 0x0ae4 */; + 698: data_o = 32'h67a2fef7 /* 0x0ae8 */; + 699: data_o = 32'he43e83a1 /* 0x0aec */; + 700: data_o = 32'h03071793 /* 0x0af0 */; + 701: data_o = 32'h11e393c1 /* 0x0af4 */; + 702: data_o = 32'h4501fef6 /* 0x0af8 */; + 703: data_o = 32'h80820141 /* 0x0afc */; + 704: data_o = 32'h4adc6114 /* 0x0b00 */; + 705: data_o = 32'h0087d79b /* 0x0b04 */; + 706: data_o = 32'h0ff7f793 /* 0x0b08 */; + 707: data_o = 32'h56dcdbfd /* 0x0b0c */; + 708: data_o = 32'h00377693 /* 0x0b10 */; + 709: data_o = 32'hea812781 /* 0x0b14 */; + 710: data_o = 32'h970a0741 /* 0x0b18 */; + 711: data_o = 32'hfef72c23 /* 0x0b1c */; + 712: data_o = 32'h270d4702 /* 0x0b20 */; + 713: data_o = 32'h0813bf99 /* 0x0b24 */; + 714: data_o = 32'h06b30041 /* 0x0b28 */; + 715: data_o = 32'h983a00e1 /* 0x0b2c */; + 716: data_o = 32'h00f68423 /* 0x0b30 */; + 717: data_o = 32'hd79b0685 /* 0x0b34 */; + 718: data_o = 32'h9be30087 /* 0x0b38 */; + 719: data_o = 32'h270dff06 /* 0x0b3c */; + 720: data_o = 32'h3803bf2d /* 0x0b40 */; + 721: data_o = 32'h27830005 /* 0x0b44 */; + 722: data_o = 32'hd79b0148 /* 0x0b48 */; + 723: data_o = 32'hf7930087 /* 0x0b4c */; + 724: data_o = 32'hdbf50ff7 /* 0x0b50 */; + 725: data_o = 32'h02c82783 /* 0x0b54 */; + 726: data_o = 32'h00377813 /* 0x0b58 */; + 727: data_o = 32'h18632781 /* 0x0b5c */; + 728: data_o = 32'h07410008 /* 0x0b60 */; + 729: data_o = 32'h2c23970a /* 0x0b64 */; + 730: data_o = 32'h4702fef7 /* 0x0b68 */; + 731: data_o = 32'h0313b7b1 /* 0x0b6c */; + 732: data_o = 32'h08330041 /* 0x0b70 */; + 733: data_o = 32'h933a00e1 /* 0x0b74 */; + 734: data_o = 32'h00f80423 /* 0x0b78 */; + 735: data_o = 32'hd79b0805 /* 0x0b7c */; + 736: data_o = 32'h1be30087 /* 0x0b80 */; + 737: data_o = 32'hbf0dfe68 /* 0x0b84 */; + 738: data_o = 32'h49dc610c /* 0x0b88 */; + 739: data_o = 32'h0087d79b /* 0x0b8c */; + 740: data_o = 32'h0ff7f793 /* 0x0b90 */; + 741: data_o = 32'h55dcdbfd /* 0x0b94 */; + 742: data_o = 32'h0036f593 /* 0x0b98 */; + 743: data_o = 32'he9992781 /* 0x0b9c */; + 744: data_o = 32'h968a06c1 /* 0x0ba0 */; + 745: data_o = 32'hfef6ac23 /* 0x0ba4 */; + 746: data_o = 32'h268d4682 /* 0x0ba8 */; + 747: data_o = 32'he20dbf0d /* 0x0bac */; + 748: data_o = 32'h80824501 /* 0x0bb0 */; + 749: data_o = 32'h00410813 /* 0x0bb4 */; + 750: data_o = 32'h00d105b3 /* 0x0bb8 */; + 751: data_o = 32'h84239836 /* 0x0bbc */; + 752: data_o = 32'h058500f5 /* 0x0bc0 */; + 753: data_o = 32'h0087d79b /* 0x0bc4 */; + 754: data_o = 32'hfeb81be3 /* 0x0bc8 */; + 755: data_o = 32'hbf01268d /* 0x0bcc */; + 756: data_o = 32'h8082450d /* 0x0bd0 */; + 757: data_o = 32'hbddd86ae /* 0x0bd4 */; + 758: data_o = 32'h712d6518 /* 0x0bd8 */; + 759: data_o = 32'h02faf7b7 /* 0x0bdc */; + 760: data_o = 32'hea22ee06 /* 0x0be0 */; + 761: data_o = 32'he24ae626 /* 0x0be4 */; + 762: data_o = 32'hf9d2fdce /* 0x0be8 */; + 763: data_o = 32'hf1daf5d6 /* 0x0bec */; + 764: data_o = 32'he9e2edde /* 0x0bf0 */; + 765: data_o = 32'he1eae5e6 /* 0x0bf4 */; + 766: data_o = 32'h8793fd6e /* 0x0bf8 */; + 767: data_o = 32'hf02e07f7 /* 0x0bfc */; + 768: data_o = 32'he436f432 /* 0x0c00 */; + 769: data_o = 32'h1ce7ed63 /* 0x0c04 */; + 770: data_o = 32'h4c0167a2 /* 0x0c08 */; + 771: data_o = 32'h12078863 /* 0x0c0c */; + 772: data_o = 32'h87936a85 /* 0x0c10 */; + 773: data_o = 32'h8d2ac00a /* 0x0c14 */; + 774: data_o = 32'he83e4485 /* 0x0c18 */; + 775: data_o = 32'h77a24985 /* 0x0c1c */; + 776: data_o = 32'he082f882 /* 0x0c20 */; + 777: data_o = 32'h00fc073b /* 0x0c24 */; + 778: data_o = 32'hf0827782 /* 0x0c28 */; + 779: data_o = 32'h97e2f482 /* 0x0c2c */; + 780: data_o = 32'h67a2ed3e /* 0x0c30 */; + 781: data_o = 32'h46cde502 /* 0x0c34 */; + 782: data_o = 32'h4711d8ba /* 0x0c38 */; + 783: data_o = 32'hfc02c53a /* 0x0c3c */; + 784: data_o = 32'he882e482 /* 0x0c40 */; + 785: data_o = 32'hfc82ec82 /* 0x0c44 */; + 786: data_o = 32'he902e102 /* 0x0c48 */; + 787: data_o = 32'h0023f502 /* 0x0c4c */; + 788: data_o = 32'hd0a604d1 /* 0x0c50 */; + 789: data_o = 32'h87b3d6a6 /* 0x0c54 */; + 790: data_o = 32'h07134187 /* 0x0c58 */; + 791: data_o = 32'h74631000 /* 0x0c5c */; + 792: data_o = 32'h079300f7 /* 0x0c60 */; + 793: data_o = 32'h27031000 /* 0x0c64 */; + 794: data_o = 32'h3403010d /* 0x0c68 */; + 795: data_o = 32'h0d93000d /* 0x0c6c */; + 796: data_o = 32'hf13e0381 /* 0x0c70 */; + 797: data_o = 32'h8a6ed058 /* 0x0c74 */; + 798: data_o = 32'h4a814701 /* 0x0c78 */; + 799: data_o = 32'h0c934b89 /* 0x0c7c */; + 800: data_o = 32'h69090480 /* 0x0c80 */; + 801: data_o = 32'h86134b0d /* 0x0c84 */; + 802: data_o = 32'h3613ffea /* 0x0c88 */; + 803: data_o = 32'h485c0016 /* 0x0c8c */; + 804: data_o = 32'h01f7d79b /* 0x0c90 */; + 805: data_o = 32'h0d63dfed /* 0x0c94 */; + 806: data_o = 32'he0631177 /* 0x0c98 */; + 807: data_o = 32'hc34d0eeb /* 0x0c9c */; + 808: data_o = 32'hf793485c /* 0x0ca0 */; + 809: data_o = 32'h8de30ff7 /* 0x0ca4 */; + 810: data_o = 32'h2503ff97 /* 0x0ca8 */; + 811: data_o = 32'hec32010a /* 0x0cac */; + 812: data_o = 32'hcdcff0ef /* 0x0cb0 */; + 813: data_o = 32'h00ca2783 /* 0x0cb4 */; + 814: data_o = 32'h8f636662 /* 0x0cb8 */; + 815: data_o = 32'h551b1097 /* 0x0cbc */; + 816: data_o = 32'hd8080085 /* 0x0cc0 */; + 817: data_o = 32'h27834709 /* 0x0cc4 */; + 818: data_o = 32'h66c2008a /* 0x0cc8 */; + 819: data_o = 32'h40c9863b /* 0x0ccc */; + 820: data_o = 32'h00a7979b /* 0x0cd0 */; + 821: data_o = 32'h0096161b /* 0x0cd4 */; + 822: data_o = 32'h8fd18ff5 /* 0x0cd8 */; + 823: data_o = 32'he7b38fd9 /* 0x0cdc */; + 824: data_o = 32'h27810127 /* 0x0ce0 */; + 825: data_o = 32'h0a85d41c /* 0x0ce4 */; + 826: data_o = 32'h028a0a13 /* 0x0ce8 */; + 827: data_o = 32'h096a9263 /* 0x0cec */; + 828: data_o = 32'h078d8c93 /* 0x0cf0 */; + 829: data_o = 32'h44154911 /* 0x0cf4 */; + 830: data_o = 32'h856aa831 /* 0x0cf8 */; + 831: data_o = 32'h00879863 /* 0x0cfc */; + 832: data_o = 32'h020dd603 /* 0x0d00 */; + 833: data_o = 32'h018db583 /* 0x0d04 */; + 834: data_o = 32'hd55ff0ef /* 0x0d08 */; + 835: data_o = 32'h028d8d93 /* 0x0d0c */; + 836: data_o = 32'h03bc8163 /* 0x0d10 */; + 837: data_o = 32'h000da783 /* 0x0d14 */; + 838: data_o = 32'hff2791e3 /* 0x0d18 */; + 839: data_o = 32'h018dd603 /* 0x0d1c */; + 840: data_o = 32'h010db583 /* 0x0d20 */; + 841: data_o = 32'h8d93856a /* 0x0d24 */; + 842: data_o = 32'hf0ef028d /* 0x0d28 */; + 843: data_o = 32'h93e3d33f /* 0x0d2c */; + 844: data_o = 32'h67a2ffbc /* 0x0d30 */; + 845: data_o = 32'h100c0c13 /* 0x0d34 */; + 846: data_o = 32'heefc63e3 /* 0x0d38 */; + 847: data_o = 32'ha8914501 /* 0x0d3c */; + 848: data_o = 32'hf793485c /* 0x0d40 */; + 849: data_o = 32'h8de30ff7 /* 0x0d44 */; + 850: data_o = 32'h4703ff97 /* 0x0d48 */; + 851: data_o = 32'h87bb008a /* 0x0d4c */; + 852: data_o = 32'h979b40c9 /* 0x0d50 */; + 853: data_o = 32'h08230097 /* 0x0d54 */; + 854: data_o = 32'h370302e4 /* 0x0d58 */; + 855: data_o = 32'he7b3000d /* 0x0d5c */; + 856: data_o = 32'h27810127 /* 0x0d60 */; + 857: data_o = 32'h0a85d71c /* 0x0d64 */; + 858: data_o = 32'h028a0a13 /* 0x0d68 */; + 859: data_o = 32'hf96a82e3 /* 0x0d6c */; + 860: data_o = 32'h000d3403 /* 0x0d70 */; + 861: data_o = 32'h000a2703 /* 0x0d74 */; + 862: data_o = 32'h3775b739 /* 0x0d78 */; + 863: data_o = 32'h00ebea63 /* 0x0d7c */; + 864: data_o = 32'h856a85d2 /* 0x0d80 */; + 865: data_o = 32'hc35ff0ef /* 0x0d84 */; + 866: data_o = 32'hdd712501 /* 0x0d88 */; + 867: data_o = 32'ha0112501 /* 0x0d8c */; + 868: data_o = 32'h60f2450d /* 0x0d90 */; + 869: data_o = 32'h64b26452 /* 0x0d94 */; + 870: data_o = 32'h79ee6912 /* 0x0d98 */; + 871: data_o = 32'h7aae7a4e /* 0x0d9c */; + 872: data_o = 32'h6bee7b0e /* 0x0da0 */; + 873: data_o = 32'h6cae6c4e /* 0x0da4 */; + 874: data_o = 32'h7dea6d0e /* 0x0da8 */; + 875: data_o = 32'h80826115 /* 0x0dac */; + 876: data_o = 32'h008a2783 /* 0x0db0 */; + 877: data_o = 32'h010a5703 /* 0x0db4 */; + 878: data_o = 32'h863b66c2 /* 0x0db8 */; + 879: data_o = 32'h979b40c9 /* 0x0dbc */; + 880: data_o = 32'h8ff500a7 /* 0x0dc0 */; + 881: data_o = 32'h0096161b /* 0x0dc4 */; + 882: data_o = 32'h8fd1377d /* 0x0dc8 */; + 883: data_o = 32'h1ff77713 /* 0x0dcc */; + 884: data_o = 32'h27818fd9 /* 0x0dd0 */; + 885: data_o = 32'hbf41d41c /* 0x0dd4 */; + 886: data_o = 32'h470dd808 /* 0x0dd8 */; + 887: data_o = 32'h4555b5ed /* 0x0ddc */; + 888: data_o = 32'h6118bf4d /* 0x0de0 */; + 889: data_o = 32'he8221101 /* 0x0de4 */; + 890: data_o = 32'hec06e426 /* 0x0de8 */; + 891: data_o = 32'h843284aa /* 0x0dec */; + 892: data_o = 32'h4b5cd34c /* 0x0df0 */; + 893: data_o = 32'h01f7d79b /* 0x0df4 */; + 894: data_o = 32'h401cdfed /* 0x0df8 */; + 895: data_o = 32'h8a634689 /* 0x0dfc */; + 896: data_o = 32'heb6308d7 /* 0x0e00 */; + 897: data_o = 32'hc3bd02f6 /* 0x0e04 */; + 898: data_o = 32'h85a24601 /* 0x0e08 */; + 899: data_o = 32'hf0ef8526 /* 0x0e0c */; + 900: data_o = 32'h401ca93f /* 0x0e10 */; + 901: data_o = 32'h8f634711 /* 0x0e14 */; + 902: data_o = 32'h471502e7 /* 0x0e18 */; + 903: data_o = 32'h04e79263 /* 0x0e1c */; + 904: data_o = 32'h02045603 /* 0x0e20 */; + 905: data_o = 32'h85266c0c /* 0x0e24 */; + 906: data_o = 32'hc35ff0ef /* 0x0e28 */; + 907: data_o = 32'h60e24501 /* 0x0e2c */; + 908: data_o = 32'h64a26442 /* 0x0e30 */; + 909: data_o = 32'h80826105 /* 0x0e34 */; + 910: data_o = 32'hea6337f5 /* 0x0e38 */; + 911: data_o = 32'h460104f6 /* 0x0e3c */; + 912: data_o = 32'h852685a2 /* 0x0e40 */; + 913: data_o = 32'hb75ff0ef /* 0x0e44 */; + 914: data_o = 32'hf1752501 /* 0x0e48 */; + 915: data_o = 32'h4711401c /* 0x0e4c */; + 916: data_o = 32'hfce795e3 /* 0x0e50 */; + 917: data_o = 32'h01845603 /* 0x0e54 */; + 918: data_o = 32'h8526680c /* 0x0e58 */; + 919: data_o = 32'hc01ff0ef /* 0x0e5c */; + 920: data_o = 32'h644260e2 /* 0x0e60 */; + 921: data_o = 32'h450164a2 /* 0x0e64 */; + 922: data_o = 32'h80826105 /* 0x0e68 */; + 923: data_o = 32'h04800693 /* 0x0e6c */; + 924: data_o = 32'hf7934b5c /* 0x0e70 */; + 925: data_o = 32'h8de30ff7 /* 0x0e74 */; + 926: data_o = 32'h4783fed7 /* 0x0e78 */; + 927: data_o = 32'h08230084 /* 0x0e7c */; + 928: data_o = 32'h609802f7 /* 0x0e80 */; + 929: data_o = 32'h87936789 /* 0x0e84 */; + 930: data_o = 32'hd71c2007 /* 0x0e88 */; + 931: data_o = 32'h450db759 /* 0x0e8c */; + 932: data_o = 32'h5783bf79 /* 0x0e90 */; + 933: data_o = 32'h44140104 /* 0x0e94 */; + 934: data_o = 32'h37fd6605 /* 0x0e98 */; + 935: data_o = 32'h00a6969b /* 0x0e9c */; + 936: data_o = 32'hc0060613 /* 0x0ea0 */; + 937: data_o = 32'h1ff7f793 /* 0x0ea4 */; + 938: data_o = 32'h8fd58ef1 /* 0x0ea8 */; + 939: data_o = 32'h2007e793 /* 0x0eac */; + 940: data_o = 32'hd71c2781 /* 0x0eb0 */; + 941: data_o = 32'h7175bfb9 /* 0x0eb4 */; + 942: data_o = 32'hec02e42e /* 0x0eb8 */; + 943: data_o = 32'h490c478d /* 0x0ebc */; + 944: data_o = 32'h003ccc3e /* 0x0ec0 */; + 945: data_o = 32'he8daf0d2 /* 0x0ec4 */; + 946: data_o = 32'h8b32f43e /* 0x0ec8 */; + 947: data_o = 32'h8a364799 /* 0x0ecc */; + 948: data_o = 32'h46850830 /* 0x0ed0 */; + 949: data_o = 32'hf8cae122 /* 0x0ed4 */; + 950: data_o = 32'he506f4ce /* 0x0ed8 */; + 951: data_o = 32'hecd6fca6 /* 0x0edc */; + 952: data_o = 32'h89aae4de /* 0x0ee0 */; + 953: data_o = 32'hf002893a /* 0x0ee4 */; + 954: data_o = 32'hf83efc02 /* 0x0ee8 */; + 955: data_o = 32'hef7ff0ef /* 0x0eec */; + 956: data_o = 32'h0005041b /* 0x0ef0 */; + 957: data_o = 32'h4703e421 /* 0x0ef4 */; + 958: data_o = 32'h07930081 /* 0x0ef8 */; + 959: data_o = 32'ha58304c0 /* 0x0efc */; + 960: data_o = 32'h06630109 /* 0x0f00 */; + 961: data_o = 32'h44a10af7 /* 0x0f04 */; + 962: data_o = 32'h4a854b91 /* 0x0f08 */; + 963: data_o = 32'h0783a029 /* 0x0f0c */; + 964: data_o = 32'hd163000a /* 0x0f10 */; + 965: data_o = 32'ha5830407 /* 0x0f14 */; + 966: data_o = 32'hec020109 /* 0x0f18 */; + 967: data_o = 32'h08304685 /* 0x0f1c */; + 968: data_o = 32'hf002854e /* 0x0f20 */; + 969: data_o = 32'hcc5efc02 /* 0x0f24 */; + 970: data_o = 32'hf856f452 /* 0x0f28 */; + 971: data_o = 32'heb7ff0ef /* 0x0f2c */; + 972: data_o = 32'h0005041b /* 0x0f30 */; + 973: data_o = 32'he01934fd /* 0x0f34 */; + 974: data_o = 32'h4449f8f9 /* 0x0f38 */; + 975: data_o = 32'h852260aa /* 0x0f3c */; + 976: data_o = 32'h74e6640a /* 0x0f40 */; + 977: data_o = 32'h79a67946 /* 0x0f44 */; + 978: data_o = 32'h6ae67a06 /* 0x0f48 */; + 979: data_o = 32'h6ba66b46 /* 0x0f4c */; + 980: data_o = 32'h80826149 /* 0x0f50 */; + 981: data_o = 32'h020b1693 /* 0x0f54 */; + 982: data_o = 32'h15418793 /* 0x0f58 */; + 983: data_o = 32'h01d6d713 /* 0x0f5c */; + 984: data_o = 32'h639c97ba /* 0x0f60 */; + 985: data_o = 32'h075b0863 /* 0x0f64 */; + 986: data_o = 32'he38517fd /* 0x0f68 */; + 987: data_o = 32'hfc0918e3 /* 0x0f6c */; + 988: data_o = 32'h0149a783 /* 0x0f70 */; + 989: data_o = 32'h0009b703 /* 0x0f74 */; + 990: data_o = 32'h4b5cd35c /* 0x0f78 */; + 991: data_o = 32'h01f7d79b /* 0x0f7c */; + 992: data_o = 32'h479ddfed /* 0x0f80 */; + 993: data_o = 32'h4401d71c /* 0x0f84 */; + 994: data_o = 32'ha583bf55 /* 0x0f88 */; + 995: data_o = 32'hec020109 /* 0x0f8c */; + 996: data_o = 32'h46850a05 /* 0x0f90 */; + 997: data_o = 32'h854e0830 /* 0x0f94 */; + 998: data_o = 32'hfc02f002 /* 0x0f98 */; + 999: data_o = 32'hf452cc5e /* 0x0f9c */; + 1000: data_o = 32'hf0eff83e /* 0x0fa0 */; + 1001: data_o = 32'h2501e41f /* 0x0fa4 */; + 1002: data_o = 32'h842ad171 /* 0x0fa8 */; + 1003: data_o = 32'hec02bf41 /* 0x0fac */; + 1004: data_o = 32'hcc3e4791 /* 0x0fb0 */; + 1005: data_o = 32'h01710793 /* 0x0fb4 */; + 1006: data_o = 32'h4685f43e /* 0x0fb8 */; + 1007: data_o = 32'h08304785 /* 0x0fbc */; + 1008: data_o = 32'hf002854e /* 0x0fc0 */; + 1009: data_o = 32'hf83efc02 /* 0x0fc4 */; + 1010: data_o = 32'he1bff0ef /* 0x0fc8 */; + 1011: data_o = 32'h0005041b /* 0x0fcc */; + 1012: data_o = 32'hb7add81d /* 0x0fd0 */; + 1013: data_o = 32'h84936489 /* 0x0fd4 */; + 1014: data_o = 32'h4b117104 /* 0x0fd8 */; + 1015: data_o = 32'h01710a93 /* 0x0fdc */; + 1016: data_o = 32'ha0294a05 /* 0x0fe0 */; + 1017: data_o = 32'h4783c49d /* 0x0fe4 */; + 1018: data_o = 32'hf3c90171 /* 0x0fe8 */; + 1019: data_o = 32'h0109a583 /* 0x0fec */; + 1020: data_o = 32'h4685ec02 /* 0x0ff0 */; + 1021: data_o = 32'h854e0830 /* 0x0ff4 */; + 1022: data_o = 32'hfc02f002 /* 0x0ff8 */; + 1023: data_o = 32'hf456cc5a /* 0x0ffc */; + 1024: data_o = 32'hf0eff852 /* 0x1000 */; + 1025: data_o = 32'h079bde1f /* 0x1004 */; + 1026: data_o = 32'h34fd0005 /* 0x1008 */; + 1027: data_o = 32'h843edfe1 /* 0x100c */; + 1028: data_o = 32'h444db735 /* 0x1010 */; + 1029: data_o = 32'h7179b725 /* 0x1014 */; + 1030: data_o = 32'he84aec26 /* 0x1018 */; + 1031: data_o = 32'h893a84b6 /* 0x101c */; + 1032: data_o = 32'h47010034 /* 0x1020 */; + 1033: data_o = 32'hf406f022 /* 0x1024 */; + 1034: data_o = 32'hf0ef8432 /* 0x1028 */; + 1035: data_o = 32'he50de8df /* 0x102c */; + 1036: data_o = 32'h1713c485 /* 0x1030 */; + 1037: data_o = 32'h56130204 /* 0x1034 */; + 1038: data_o = 32'h879301d7 /* 0x1038 */; + 1039: data_o = 32'h97b21541 /* 0x103c */; + 1040: data_o = 32'h66a26398 /* 0x1040 */; + 1041: data_o = 32'h171b4785 /* 0x1044 */; + 1042: data_o = 32'h97bb0037 /* 0x1048 */; + 1043: data_o = 32'h37fd00e7 /* 0x104c */; + 1044: data_o = 32'h0126c733 /* 0x1050 */; + 1045: data_o = 32'he7198f7d /* 0x1054 */; + 1046: data_o = 32'h740270a2 /* 0x1058 */; + 1047: data_o = 32'h694264e2 /* 0x105c */; 1048: data_o = 32'h80826145 /* 0x1060 */; - 1049: data_o = 32'hd4010113 /* 0x1064 */; - 1050: data_o = 32'h29613023 /* 0x1068 */; - 1051: data_o = 32'h00d60b33 /* 0x106c */; - 1052: data_o = 32'h29513423 /* 0x1070 */; - 1053: data_o = 32'h27713c23 /* 0x1074 */; - 1054: data_o = 32'h27a13023 /* 0x1078 */; - 1055: data_o = 32'h2a113c23 /* 0x107c */; - 1056: data_o = 32'h2a813823 /* 0x1080 */; - 1057: data_o = 32'h2a913423 /* 0x1084 */; - 1058: data_o = 32'h2b213023 /* 0x1088 */; - 1059: data_o = 32'h29313c23 /* 0x108c */; - 1060: data_o = 32'h29413823 /* 0x1090 */; - 1061: data_o = 32'h27813823 /* 0x1094 */; - 1062: data_o = 32'h27913423 /* 0x1098 */; - 1063: data_o = 32'h25b13c23 /* 0x109c */; - 1064: data_o = 32'h1ffb7b13 /* 0x10a0 */; - 1065: data_o = 32'h8aae8d2a /* 0x10a4 */; - 1066: data_o = 32'h1ff67b93 /* 0x10a8 */; - 1067: data_o = 32'h000b1463 /* 0x10ac */; - 1068: data_o = 32'h20000b13 /* 0x10b0 */; - 1069: data_o = 32'h1ff68413 /* 0x10b4 */; - 1070: data_o = 32'h0793945e /* 0x10b8 */; - 1071: data_o = 32'h8025faa0 /* 0x10bc */; - 1072: data_o = 32'h02f102a3 /* 0x10c0 */; - 1073: data_o = 32'h24040a63 /* 0x10c4 */; - 1074: data_o = 32'h0b634785 /* 0x10c8 */; - 1075: data_o = 32'h059310f4 /* 0x10cc */; - 1076: data_o = 32'h82250520 /* 0x10d0 */; - 1077: data_o = 32'h0186579b /* 0x10d4 */; - 1078: data_o = 32'h0ff67693 /* 0x10d8 */; - 1079: data_o = 32'h07a21682 /* 0x10dc */; - 1080: data_o = 32'h06b78fd5 /* 0x10e0 */; - 1081: data_o = 32'h571b00ff /* 0x10e4 */; - 1082: data_o = 32'h8e750086 /* 0x10e8 */; - 1083: data_o = 32'h57fd8e5d /* 0x10ec */; - 1084: data_o = 32'h93810762 /* 0x10f0 */; - 1085: data_o = 32'h8e5d8ff9 /* 0x10f4 */; - 1086: data_o = 32'he8b28e4d /* 0x10f8 */; - 1087: data_o = 32'h05130894 /* 0x10fc */; - 1088: data_o = 32'h47010551 /* 0x1100 */; - 1089: data_o = 32'h05418593 /* 0x1104 */; - 1090: data_o = 32'h0006c783 /* 0x1108 */; - 1091: data_o = 32'h0017171b /* 0x110c */; - 1092: data_o = 32'h8fb90685 /* 0x1110 */; - 1093: data_o = 32'h0ff7f793 /* 0x1114 */; - 1094: data_o = 32'hc70397ae /* 0x1118 */; - 1095: data_o = 32'h15e30007 /* 0x111c */; - 1096: data_o = 32'h1793fed5 /* 0x1120 */; - 1097: data_o = 32'he7930017 /* 0x1124 */; - 1098: data_o = 32'h17a20017 /* 0x1128 */; - 1099: data_o = 32'he8828fd1 /* 0x112c */; - 1100: data_o = 32'h2583f43e /* 0x1130 */; - 1101: data_o = 32'h478d010d /* 0x1134 */; - 1102: data_o = 32'h103cc8be /* 0x1138 */; - 1103: data_o = 32'h4685f0be /* 0x113c */; - 1104: data_o = 32'h08904799 /* 0x1140 */; - 1105: data_o = 32'hec82856a /* 0x1144 */; - 1106: data_o = 32'hf4bef882 /* 0x1148 */; - 1107: data_o = 32'hc85ff0ef /* 0x114c */; - 1108: data_o = 32'h00050d9b /* 0x1150 */; - 1109: data_o = 32'h040d9863 /* 0x1154 */; - 1110: data_o = 32'h02814703 /* 0x1158 */; - 1111: data_o = 32'h04c00793 /* 0x115c */; - 1112: data_o = 32'h010d2583 /* 0x1160 */; - 1113: data_o = 32'h20f70e63 /* 0x1164 */; - 1114: data_o = 32'h4a1144a1 /* 0x1168 */; - 1115: data_o = 32'h02510993 /* 0x116c */; - 1116: data_o = 32'ha0294905 /* 0x1170 */; - 1117: data_o = 32'h02510783 /* 0x1174 */; - 1118: data_o = 32'h0607d763 /* 0x1178 */; - 1119: data_o = 32'h010d2583 /* 0x117c */; - 1120: data_o = 32'h4685e882 /* 0x1180 */; - 1121: data_o = 32'h856a0890 /* 0x1184 */; - 1122: data_o = 32'hf882ec82 /* 0x1188 */; - 1123: data_o = 32'hf0cec8d2 /* 0x118c */; - 1124: data_o = 32'hf0eff4ca /* 0x1190 */; - 1125: data_o = 32'h0d9bc3ff /* 0x1194 */; - 1126: data_o = 32'h34fd0005 /* 0x1198 */; - 1127: data_o = 32'h000d9463 /* 0x119c */; - 1128: data_o = 32'h4dc9f8f1 /* 0x11a0 */; - 1129: data_o = 32'h2b813083 /* 0x11a4 */; - 1130: data_o = 32'h2b013403 /* 0x11a8 */; - 1131: data_o = 32'h2a813483 /* 0x11ac */; - 1132: data_o = 32'h2a013903 /* 0x11b0 */; - 1133: data_o = 32'h29813983 /* 0x11b4 */; - 1134: data_o = 32'h29013a03 /* 0x11b8 */; - 1135: data_o = 32'h28813a83 /* 0x11bc */; - 1136: data_o = 32'h28013b03 /* 0x11c0 */; - 1137: data_o = 32'h27813b83 /* 0x11c4 */; - 1138: data_o = 32'h27013c03 /* 0x11c8 */; - 1139: data_o = 32'h26813c83 /* 0x11cc */; - 1140: data_o = 32'h26013d03 /* 0x11d0 */; - 1141: data_o = 32'h3d83856e /* 0x11d4 */; - 1142: data_o = 32'h01132581 /* 0x11d8 */; - 1143: data_o = 32'h80822c01 /* 0x11dc */; - 1144: data_o = 32'h05100593 /* 0x11e0 */; - 1145: data_o = 32'h37b3b5fd /* 0x11e4 */; - 1146: data_o = 32'h6c850170 /* 0x11e8 */; - 1147: data_o = 32'h8793ec3e /* 0x11ec */; - 1148: data_o = 32'he43e800c /* 0x11f0 */; - 1149: data_o = 32'h97de089c /* 0x11f4 */; - 1150: data_o = 32'h417a8ab3 /* 0x11f8 */; - 1151: data_o = 32'he83e4c01 /* 0x11fc */; - 1152: data_o = 32'h0c936709 /* 0x1200 */; - 1153: data_o = 32'h49917107 /* 0x1204 */; - 1154: data_o = 32'h02510913 /* 0x1208 */; - 1155: data_o = 32'h0a134485 /* 0x120c */; - 1156: data_o = 32'ha0390ff0 /* 0x1210 */; - 1157: data_o = 32'h160c8463 /* 0x1214 */; - 1158: data_o = 32'h02514683 /* 0x1218 */; - 1159: data_o = 32'h03469563 /* 0x121c */; - 1160: data_o = 32'h010d2583 /* 0x1220 */; - 1161: data_o = 32'h4685f402 /* 0x1224 */; - 1162: data_o = 32'h856a1030 /* 0x1228 */; - 1163: data_o = 32'he482f802 /* 0x122c */; - 1164: data_o = 32'hfc4ad44e /* 0x1230 */; - 1165: data_o = 32'hf0efe0a6 /* 0x1234 */; - 1166: data_o = 32'h0d9bb9bf /* 0x1238 */; - 1167: data_o = 32'h3cfd0005 /* 0x123c */; - 1168: data_o = 32'hfc0d8ae3 /* 0x1240 */; - 1169: data_o = 32'h0713b785 /* 0x1244 */; - 1170: data_o = 32'h91630fe0 /* 0x1248 */; - 1171: data_o = 32'h0e6318e6 /* 0x124c */; - 1172: data_o = 32'h0713100c /* 0x1250 */; - 1173: data_o = 32'h0163fff4 /* 0x1254 */; - 1174: data_o = 32'h88d610ec /* 0x1258 */; - 1175: data_o = 32'h8cc6e002 /* 0x125c */; - 1176: data_o = 32'h20088a13 /* 0x1260 */; - 1177: data_o = 32'h491189c6 /* 0x1264 */; - 1178: data_o = 32'h10000493 /* 0x1268 */; - 1179: data_o = 32'hf802f402 /* 0x126c */; - 1180: data_o = 32'h0a098663 /* 0x1270 */; - 1181: data_o = 32'hd44ae482 /* 0x1274 */; - 1182: data_o = 32'he0a6fc4e /* 0x1278 */; - 1183: data_o = 32'h010d2583 /* 0x127c */; - 1184: data_o = 32'h10304685 /* 0x1280 */; - 1185: data_o = 32'hf0ef856a /* 0x1284 */; - 1186: data_o = 32'h2501b4bf /* 0x1288 */; - 1187: data_o = 32'h10098993 /* 0x128c */; - 1188: data_o = 32'h1de3e171 /* 0x1290 */; - 1189: data_o = 32'hf402fd3a /* 0x1294 */; - 1190: data_o = 32'h25834711 /* 0x1298 */; - 1191: data_o = 32'hd43a010d /* 0x129c */; - 1192: data_o = 32'h02610713 /* 0x12a0 */; - 1193: data_o = 32'h4685fc3a /* 0x12a4 */; - 1194: data_o = 32'h10304709 /* 0x12a8 */; - 1195: data_o = 32'hf802856a /* 0x12ac */; - 1196: data_o = 32'he0bae482 /* 0x12b0 */; - 1197: data_o = 32'hb1dff0ef /* 0x12b4 */; - 1198: data_o = 32'hed492501 /* 0x12b8 */; - 1199: data_o = 32'h85934681 /* 0x12bc */; - 1200: data_o = 32'hc703e541 /* 0x12c0 */; - 1201: data_o = 32'hd61b000c /* 0x12c4 */; - 1202: data_o = 32'h969b0086 /* 0x12c8 */; - 1203: data_o = 32'h8f310086 /* 0x12cc */; - 1204: data_o = 32'h837d1702 /* 0x12d0 */; - 1205: data_o = 32'h5703972e /* 0x12d4 */; - 1206: data_o = 32'h16c20007 /* 0x12d8 */; - 1207: data_o = 32'h0c8592c1 /* 0x12dc */; - 1208: data_o = 32'h10e38eb9 /* 0x12e0 */; - 1209: data_o = 32'h971bff9a /* 0x12e4 */; - 1210: data_o = 32'hd69b0086 /* 0x12e8 */; - 1211: data_o = 32'h8f550086 /* 0x12ec */; - 1212: data_o = 32'h02615603 /* 0x12f0 */; - 1213: data_o = 32'h93411742 /* 0x12f4 */; - 1214: data_o = 32'h0ce61d63 /* 0x12f8 */; - 1215: data_o = 32'hc7956782 /* 0x12fc */; - 1216: data_o = 32'h015b8533 /* 0x1300 */; - 1217: data_o = 32'h0a0d9863 /* 0x1304 */; - 1218: data_o = 32'h061365c2 /* 0x1308 */; - 1219: data_o = 32'h06332000 /* 0x130c */; - 1220: data_o = 32'he0ef4176 /* 0x1310 */; - 1221: data_o = 32'ha821e93f /* 0x1314 */; - 1222: data_o = 32'hb5694d81 /* 0x1318 */; - 1223: data_o = 32'hd43e4789 /* 0x131c */; - 1224: data_o = 32'he08267a2 /* 0x1320 */; - 1225: data_o = 32'hfc3ee482 /* 0x1324 */; - 1226: data_o = 32'h9f63bf91 /* 0x1328 */; - 1227: data_o = 32'h0c05060d /* 0x132c */; - 1228: data_o = 32'h200a8a93 /* 0x1330 */; - 1229: data_o = 32'hed8416e3 /* 0x1334 */; - 1230: data_o = 32'h02634785 /* 0x1338 */; - 1231: data_o = 32'h05930af4 /* 0x133c */; - 1232: data_o = 32'h15a20610 /* 0x1340 */; - 1233: data_o = 32'h10344701 /* 0x1344 */; - 1234: data_o = 32'h85934605 /* 0x1348 */; - 1235: data_o = 32'h856a04c5 /* 0x134c */; - 1236: data_o = 32'hb55ff0ef /* 0x1350 */; - 1237: data_o = 32'hb5b98daa /* 0x1354 */; - 1238: data_o = 32'h20000713 /* 0x1358 */; - 1239: data_o = 32'heeeb0fe3 /* 0x135c */; - 1240: data_o = 32'h0893e06e /* 0x1360 */; - 1241: data_o = 32'h4d850501 /* 0x1364 */; - 1242: data_o = 32'h0b63bddd /* 0x1368 */; - 1243: data_o = 32'h85630494 /* 0x136c */; - 1244: data_o = 32'h4785060b /* 0x1370 */; - 1245: data_o = 32'h0893e03e /* 0x1374 */; - 1246: data_o = 32'hb5d50501 /* 0x1378 */; - 1247: data_o = 32'hb51d4de5 /* 0x137c */; - 1248: data_o = 32'h4791e882 /* 0x1380 */; - 1249: data_o = 32'h0793c8be /* 0x1384 */; - 1250: data_o = 32'hf0be0261 /* 0x1388 */; - 1251: data_o = 32'h47854685 /* 0x138c */; - 1252: data_o = 32'h856a0890 /* 0x1390 */; - 1253: data_o = 32'hf882ec82 /* 0x1394 */; - 1254: data_o = 32'hf0eff4be /* 0x1398 */; - 1255: data_o = 32'h0d9ba37f /* 0x139c */; - 1256: data_o = 32'h83e30005 /* 0x13a0 */; - 1257: data_o = 32'hbbfddc0d /* 0x13a4 */; - 1258: data_o = 32'h088c865a /* 0x13a8 */; - 1259: data_o = 32'he0ef8556 /* 0x13ac */; - 1260: data_o = 32'hbfb5df7f /* 0x13b0 */; - 1261: data_o = 32'h063365c2 /* 0x13b4 */; - 1262: data_o = 32'he0ef417b /* 0x13b8 */; - 1263: data_o = 32'hbf85debf /* 0x13bc */; - 1264: data_o = 32'h20000713 /* 0x13c0 */; - 1265: data_o = 32'hfaeb05e3 /* 0x13c4 */; - 1266: data_o = 32'hbf596de2 /* 0x13c8 */; - 1267: data_o = 32'h02000d93 /* 0x13cc */; - 1268: data_o = 32'h0d93bbd1 /* 0x13d0 */; - 1269: data_o = 32'hb3f90210 /* 0x13d4 */; - 1270: data_o = 32'h88d6e002 /* 0x13d8 */; - 1271: data_o = 32'h2783b549 /* 0x13dc */; - 1272: data_o = 32'h3703014d /* 0x13e0 */; - 1273: data_o = 32'hd35c000d /* 0x13e4 */; - 1274: data_o = 32'hd79b4b5c /* 0x13e8 */; - 1275: data_o = 32'hdfed01f7 /* 0x13ec */; - 1276: data_o = 32'hd71c479d /* 0x13f0 */; - 1277: data_o = 32'hb37d4d81 /* 0x13f4 */; - 1278: data_o = 32'hb1adc291 /* 0x13f8 */; - 1279: data_o = 32'h80824501 /* 0x13fc */; - 1280: data_o = 32'heca67159 /* 0x1400 */; - 1281: data_o = 32'he8ca84ae /* 0x1404 */; - 1282: data_o = 32'hf0a2f486 /* 0x1408 */; - 1283: data_o = 32'he0d2e4ce /* 0x140c */; - 1284: data_o = 32'hf85afc56 /* 0x1410 */; - 1285: data_o = 32'h46a1892a /* 0x1414 */; - 1286: data_o = 32'h20000613 /* 0x1418 */; - 1287: data_o = 32'h8526100c /* 0x141c */; - 1288: data_o = 32'hed519902 /* 0x1420 */; - 1289: data_o = 32'h00001797 /* 0x1424 */; - 1290: data_o = 32'hb7837702 /* 0x1428 */; - 1291: data_o = 32'h18638847 /* 0x142c */; - 1292: data_o = 32'h46c108f7 /* 0x1430 */; - 1293: data_o = 32'h24800613 /* 0x1434 */; - 1294: data_o = 32'h8526858a /* 0x1438 */; - 1295: data_o = 32'h87aa9902 /* 0x143c */; - 1296: data_o = 32'h47a2e14d /* 0x1440 */; - 1297: data_o = 32'h05f00993 /* 0x1444 */; - 1298: data_o = 32'hcfad4a01 /* 0x1448 */; - 1299: data_o = 32'h0a934b01 /* 0x144c */; - 1300: data_o = 32'h678305f0 /* 0x1450 */; - 1301: data_o = 32'h640200c1 /* 0x1454 */; - 1302: data_o = 32'h87b346c1 /* 0x1458 */; - 1303: data_o = 32'h04260367 /* 0x145c */; - 1304: data_o = 32'h8526080c /* 0x1460 */; - 1305: data_o = 32'h0613943e /* 0x1464 */; - 1306: data_o = 32'h99020204 /* 0x1468 */; - 1307: data_o = 32'h46c187aa /* 0x146c */; - 1308: data_o = 32'h100c8622 /* 0x1470 */; - 1309: data_o = 32'he7b58526 /* 0x1474 */; - 1310: data_o = 32'h67e26742 /* 0x1478 */; - 1311: data_o = 32'h000b1863 /* 0x147c */; - 1312: data_o = 32'h05f70993 /* 0x1480 */; - 1313: data_o = 32'h0137f363 /* 0x1484 */; - 1314: data_o = 32'h8a3a89be /* 0x1488 */; - 1315: data_o = 32'hec638f99 /* 0x148c */; - 1316: data_o = 32'h990200fa /* 0x1490 */; - 1317: data_o = 32'he53187aa /* 0x1494 */; - 1318: data_o = 32'h00001797 /* 0x1498 */; - 1319: data_o = 32'h8187b783 /* 0x149c */; - 1320: data_o = 32'h0e637702 /* 0x14a0 */; - 1321: data_o = 32'h678308f7 /* 0x14a4 */; - 1322: data_o = 32'h0b050081 /* 0x14a8 */; - 1323: data_o = 32'hfafb43e3 /* 0x14ac */; - 1324: data_o = 32'h00816783 /* 0x14b0 */; - 1325: data_o = 32'h00fb0863 /* 0x14b4 */; - 1326: data_o = 32'h69e26a42 /* 0x14b8 */; - 1327: data_o = 32'h0993a021 /* 0x14bc */; - 1328: data_o = 32'h4a0105f0 /* 0x14c0 */; - 1329: data_o = 32'h00198693 /* 0x14c4 */; - 1330: data_o = 32'h414686b3 /* 0x14c8 */; - 1331: data_o = 32'h0dfff597 /* 0x14cc */; - 1332: data_o = 32'h161306a6 /* 0x14d0 */; - 1333: data_o = 32'h8593009a /* 0x14d4 */; - 1334: data_o = 32'h8526b345 /* 0x14d8 */; - 1335: data_o = 32'h87aa9902 /* 0x14dc */; - 1336: data_o = 32'h70a6cd01 /* 0x14e0 */; - 1337: data_o = 32'h64e67406 /* 0x14e4 */; - 1338: data_o = 32'h69a66946 /* 0x14e8 */; - 1339: data_o = 32'h7ae26a06 /* 0x14ec */; - 1340: data_o = 32'h853e7b42 /* 0x14f0 */; - 1341: data_o = 32'h80826165 /* 0x14f4 */; - 1342: data_o = 32'h00196913 /* 0x14f8 */; - 1343: data_o = 32'hf7972901 /* 0x14fc */; - 1344: data_o = 32'ha12300ff /* 0x1500 */; - 1345: data_o = 32'hf797b127 /* 0x1504 */; - 1346: data_o = 32'h248100ff /* 0x1508 */; - 1347: data_o = 32'hafa78793 /* 0x150c */; - 1348: data_o = 32'h870ec3c4 /* 0x1510 */; - 1349: data_o = 32'h00fff797 /* 0x1514 */; - 1350: data_o = 32'h70a67406 /* 0x1518 */; - 1351: data_o = 32'h694664e6 /* 0x151c */; - 1352: data_o = 32'h6a0669a6 /* 0x1520 */; - 1353: data_o = 32'h7b427ae2 /* 0x1524 */; - 1354: data_o = 32'h87932701 /* 0x1528 */; - 1355: data_o = 32'hf517aec7 /* 0x152c */; - 1356: data_o = 32'hc7d80dff /* 0x1530 */; - 1357: data_o = 32'had250513 /* 0x1534 */; - 1358: data_o = 32'he06f6165 /* 0x1538 */; - 1359: data_o = 32'h0797b7ff /* 0x153c */; - 1360: data_o = 32'hb7830000 /* 0x1540 */; - 1361: data_o = 32'h772277a7 /* 0x1544 */; - 1362: data_o = 32'hf4f71fe3 /* 0x1548 */; - 1363: data_o = 32'hf797b795 /* 0x154c */; - 1364: data_o = 32'h711900ff /* 0x1550 */; - 1365: data_o = 32'hab278793 /* 0x1554 */; - 1366: data_o = 32'ha903f0ca /* 0x1558 */; - 1367: data_o = 32'hf7970407 /* 0x155c */; - 1368: data_o = 32'h879300ff /* 0x1560 */; - 1369: data_o = 32'hf8a2aa27 /* 0x1564 */; - 1370: data_o = 32'hf4a643e0 /* 0x1568 */; - 1371: data_o = 32'h1402ecce /* 0x156c */; - 1372: data_o = 32'h85229001 /* 0x1570 */; - 1373: data_o = 32'h2901fc86 /* 0x1574 */; - 1374: data_o = 32'hfaffe0ef /* 0x1578 */; - 1375: data_o = 32'h84aa4989 /* 0x157c */; - 1376: data_o = 32'h1d390863 /* 0x1580 */; - 1377: data_o = 32'h0e63478d /* 0x1584 */; - 1378: data_o = 32'h478526f9 /* 0x1588 */; - 1379: data_o = 32'h3cf91f63 /* 0x158c */; - 1380: data_o = 32'h016e37b7 /* 0x1590 */; - 1381: data_o = 32'h60078713 /* 0x1594 */; - 1382: data_o = 32'hec3ad002 /* 0x1598 */; - 1383: data_o = 32'h8793d24e /* 0x159c */; - 1384: data_o = 32'h45615ff7 /* 0x15a0 */; - 1385: data_o = 32'h1897ff63 /* 0x15a4 */; - 1386: data_o = 32'h01003517 /* 0x15a8 */; - 1387: data_o = 32'ha5850513 /* 0x15ac */; - 1388: data_o = 32'hf0efe82a /* 0x15b0 */; - 1389: data_o = 32'h17b79ecf /* 0x15b4 */; - 1390: data_o = 32'h87930003 /* 0x15b8 */; - 1391: data_o = 32'hc03ed407 /* 0x15bc */; - 1392: data_o = 32'h6582c226 /* 0x15c0 */; - 1393: data_o = 32'h46014681 /* 0x15c4 */; - 1394: data_o = 32'he4020808 /* 0x15c8 */; - 1395: data_o = 32'hecffe0ef /* 0x15cc */; - 1396: data_o = 32'h18632501 /* 0x15d0 */; - 1397: data_o = 32'h56921605 /* 0x15d4 */; - 1398: data_o = 32'h66226582 /* 0x15d8 */; - 1399: data_o = 32'he0ef0808 /* 0x15dc */; - 1400: data_o = 32'h2501ebdf /* 0x15e0 */; - 1401: data_o = 32'h14051f63 /* 0x15e4 */; - 1402: data_o = 32'h01003797 /* 0x15e8 */; - 1403: data_o = 32'ha1878793 /* 0x15ec */; - 1404: data_o = 32'h80000737 /* 0x15f0 */; - 1405: data_o = 32'h3797cb98 /* 0x15f4 */; - 1406: data_o = 32'h87930100 /* 0x15f8 */; - 1407: data_o = 32'h4b9ca0a7 /* 0x15fc */; - 1408: data_o = 32'he0000737 /* 0x1600 */; - 1409: data_o = 32'h8ff9177d /* 0x1604 */; - 1410: data_o = 32'h20000737 /* 0x1608 */; - 1411: data_o = 32'h37178fd9 /* 0x160c */; - 1412: data_o = 32'h07130100 /* 0x1610 */; - 1413: data_o = 32'hcb1c9f27 /* 0x1614 */; - 1414: data_o = 32'hf4025582 /* 0x1618 */; - 1415: data_o = 32'h05000793 /* 0x161c */; - 1416: data_o = 32'h10304685 /* 0x1620 */; - 1417: data_o = 32'hf8020808 /* 0x1624 */; - 1418: data_o = 32'he482e082 /* 0x1628 */; - 1419: data_o = 32'hfc3ed44e /* 0x162c */; - 1420: data_o = 32'hfa0ff0ef /* 0x1630 */; - 1421: data_o = 32'h16632501 /* 0x1634 */; - 1422: data_o = 32'h05931005 /* 0x1638 */; - 1423: data_o = 32'h15a20950 /* 0x163c */; - 1424: data_o = 32'h46854705 /* 0x1640 */; - 1425: data_o = 32'h85934601 /* 0x1644 */; - 1426: data_o = 32'h08080405 /* 0x1648 */; - 1427: data_o = 32'h9b9ff0ef /* 0x164c */; - 1428: data_o = 32'h0e051963 /* 0x1650 */; - 1429: data_o = 32'h00000797 /* 0x1654 */; - 1430: data_o = 32'h0aa01737 /* 0x1658 */; - 1431: data_o = 32'h66c7b583 /* 0x165c */; - 1432: data_o = 32'h07050732 /* 0x1660 */; - 1433: data_o = 32'h46114685 /* 0x1664 */; - 1434: data_o = 32'hf0ef0808 /* 0x1668 */; - 1435: data_o = 32'he97199bf /* 0x166c */; - 1436: data_o = 32'h06500493 /* 0x1670 */; - 1437: data_o = 32'h042314a2 /* 0x1674 */; - 1438: data_o = 32'h84930321 /* 0x1678 */; - 1439: data_o = 32'h47010774 /* 0x167c */; - 1440: data_o = 32'h46014681 /* 0x1680 */; - 1441: data_o = 32'h080885a6 /* 0x1684 */; - 1442: data_o = 32'h97dff0ef /* 0x1688 */; - 1443: data_o = 32'h0797e95d /* 0x168c */; - 1444: data_o = 32'hb5830000 /* 0x1690 */; - 1445: data_o = 32'h470163a7 /* 0x1694 */; - 1446: data_o = 32'h46011034 /* 0x1698 */; - 1447: data_o = 32'hf0ef0808 /* 0x169c */; - 1448: data_o = 32'he145807f /* 0x16a0 */; - 1449: data_o = 32'h02814783 /* 0x16a4 */; - 1450: data_o = 32'h0593fbf9 /* 0x16a8 */; - 1451: data_o = 32'h15a20fd0 /* 0x16ac */; - 1452: data_o = 32'h46814701 /* 0x16b0 */; - 1453: data_o = 32'h8593460d /* 0x16b4 */; - 1454: data_o = 32'h080807a5 /* 0x16b8 */; - 1455: data_o = 32'h949ff0ef /* 0x16bc */; - 1456: data_o = 32'h0797e149 /* 0x16c0 */; - 1457: data_o = 32'hb5830000 /* 0x16c4 */; - 1458: data_o = 32'h470160e7 /* 0x16c8 */; - 1459: data_o = 32'h46014685 /* 0x16cc */; - 1460: data_o = 32'hf0ef0808 /* 0x16d0 */; - 1461: data_o = 32'he535933f /* 0x16d4 */; - 1462: data_o = 32'h093764c2 /* 0x16d8 */; - 1463: data_o = 32'h197de000 /* 0x16dc */; - 1464: data_o = 32'h6622489c /* 0x16e0 */; - 1465: data_o = 32'hf7b30808 /* 0x16e4 */; - 1466: data_o = 32'hc89c0127 /* 0x16e8 */; - 1467: data_o = 32'h568267e2 /* 0x16ec */; - 1468: data_o = 32'h6582c03e /* 0x16f0 */; - 1469: data_o = 32'hda7fe0ef /* 0x16f4 */; - 1470: data_o = 32'he5212501 /* 0x16f8 */; - 1471: data_o = 32'h65825692 /* 0x16fc */; - 1472: data_o = 32'h08086622 /* 0x1700 */; - 1473: data_o = 32'hd97fe0ef /* 0x1704 */; - 1474: data_o = 32'hed052501 /* 0x1708 */; - 1475: data_o = 32'h3e800513 /* 0x170c */; - 1476: data_o = 32'h02a40533 /* 0x1710 */; - 1477: data_o = 32'h0737489c /* 0x1714 */; - 1478: data_o = 32'hf7b32000 /* 0x1718 */; - 1479: data_o = 32'h8fd90127 /* 0x171c */; - 1480: data_o = 32'h47b7c89c /* 0x1720 */; - 1481: data_o = 32'h8793000f /* 0x1724 */; - 1482: data_o = 32'h55332407 /* 0x1728 */; - 1483: data_o = 32'h050502f5 /* 0x172c */; - 1484: data_o = 32'ha8bfe0ef /* 0x1730 */; - 1485: data_o = 32'h00000517 /* 0x1734 */; - 1486: data_o = 32'h0513080c /* 0x1738 */; - 1487: data_o = 32'hf0efcc45 /* 0x173c */; - 1488: data_o = 32'h70e6cc3f /* 0x1740 */; - 1489: data_o = 32'h74a67446 /* 0x1744 */; - 1490: data_o = 32'h69e67906 /* 0x1748 */; - 1491: data_o = 32'h80826109 /* 0x174c */; - 1492: data_o = 32'h098967b7 /* 0x1750 */; - 1493: data_o = 32'h8793fc02 /* 0x1754 */; - 1494: data_o = 32'h59137ff7 /* 0x1758 */; - 1495: data_o = 32'hf6630025 /* 0x175c */; - 1496: data_o = 32'h693700a7 /* 0x1760 */; - 1497: data_o = 32'h09130262 /* 0x1764 */; - 1498: data_o = 32'h4785a009 /* 0x1768 */; - 1499: data_o = 32'hdc3ef84a /* 0x176c */; - 1500: data_o = 32'h08e3454d /* 0x1770 */; - 1501: data_o = 32'h4551fc09 /* 0x1774 */; - 1502: data_o = 32'hfd24e5e3 /* 0x1778 */; - 1503: data_o = 32'h01003517 /* 0x177c */; - 1504: data_o = 32'h88450513 /* 0x1780 */; - 1505: data_o = 32'hf0eff42a /* 0x1784 */; - 1506: data_o = 32'h17b7818f /* 0x1788 */; - 1507: data_o = 32'h8793000f /* 0x178c */; - 1508: data_o = 32'hc84af0f7 /* 0x1790 */; - 1509: data_o = 32'hcc3eca26 /* 0x1794 */; - 1510: data_o = 32'h00011e23 /* 0x1798 */; - 1511: data_o = 32'h666265c2 /* 0x179c */; - 1512: data_o = 32'h10284685 /* 0x17a0 */; - 1513: data_o = 32'hcf7fe0ef /* 0x17a4 */; - 1514: data_o = 32'hfd412501 /* 0x17a8 */; - 1515: data_o = 32'h01003797 /* 0x17ac */; - 1516: data_o = 32'h85478793 /* 0x17b0 */; - 1517: data_o = 32'h80000737 /* 0x17b4 */; - 1518: data_o = 32'h3797cb98 /* 0x17b8 */; - 1519: data_o = 32'h87930100 /* 0x17bc */; - 1520: data_o = 32'h4b9c8467 /* 0x17c0 */; - 1521: data_o = 32'he0000737 /* 0x17c4 */; - 1522: data_o = 32'h8ff9177d /* 0x17c8 */; - 1523: data_o = 32'h20000737 /* 0x17cc */; - 1524: data_o = 32'h37178fd9 /* 0x17d0 */; - 1525: data_o = 32'h07130100 /* 0x17d4 */; - 1526: data_o = 32'hcb1c82e7 /* 0x17d8 */; - 1527: data_o = 32'h15e00793 /* 0x17dc */; - 1528: data_o = 32'h02f40533 /* 0x17e0 */; - 1529: data_o = 32'h000f47b7 /* 0x17e4 */; - 1530: data_o = 32'h24078793 /* 0x17e8 */; - 1531: data_o = 32'h02f55533 /* 0x17ec */; - 1532: data_o = 32'he0ef0505 /* 0x17f0 */; - 1533: data_o = 32'hf5179c9f /* 0x17f4 */; - 1534: data_o = 32'h102cffff /* 0x17f8 */; - 1535: data_o = 32'h3d050513 /* 0x17fc */; - 1536: data_o = 32'h4549bf3d /* 0x1800 */; - 1537: data_o = 32'hd5b7dc9d /* 0x1804 */; - 1538: data_o = 32'h85933b9a /* 0x1808 */; - 1539: data_o = 32'hd5b3a005 /* 0x180c */; - 1540: data_o = 32'h17970295 /* 0x1810 */; - 1541: data_o = 32'h87930100 /* 0x1814 */; - 1542: data_o = 32'hf43e7ee7 /* 0x1818 */; - 1543: data_o = 32'h01001797 /* 0x181c */; - 1544: data_o = 32'h7e478793 /* 0x1820 */; - 1545: data_o = 32'h17974b98 /* 0x1824 */; - 1546: data_o = 32'h87930100 /* 0x1828 */; - 1547: data_o = 32'h9b797da7 /* 0x182c */; - 1548: data_o = 32'h1797cb98 /* 0x1830 */; - 1549: data_o = 32'h87930100 /* 0x1834 */; - 1550: data_o = 32'h53987ce7 /* 0x1838 */; - 1551: data_o = 32'h01001797 /* 0x183c */; - 1552: data_o = 32'h7c478793 /* 0x1840 */; - 1553: data_o = 32'h08076713 /* 0x1844 */; - 1554: data_o = 32'h1797d398 /* 0x1848 */; - 1555: data_o = 32'h87930100 /* 0x184c */; - 1556: data_o = 32'h53987b67 /* 0x1850 */; - 1557: data_o = 32'h01001797 /* 0x1854 */; - 1558: data_o = 32'h7ac78793 /* 0x1858 */; - 1559: data_o = 32'h00276713 /* 0x185c */; - 1560: data_o = 32'h1797d398 /* 0x1860 */; - 1561: data_o = 32'h87930100 /* 0x1864 */; - 1562: data_o = 32'h539879e7 /* 0x1868 */; - 1563: data_o = 32'h01001797 /* 0x186c */; - 1564: data_o = 32'h79478793 /* 0x1870 */; - 1565: data_o = 32'h00176713 /* 0x1874 */; - 1566: data_o = 32'h1797d398 /* 0x1878 */; - 1567: data_o = 32'h87930100 /* 0x187c */; - 1568: data_o = 32'h53987867 /* 0x1880 */; - 1569: data_o = 32'h01001797 /* 0x1884 */; - 1570: data_o = 32'h77c78793 /* 0x1888 */; - 1571: data_o = 32'h10076713 /* 0x188c */; - 1572: data_o = 32'h51300513 /* 0x1890 */; - 1573: data_o = 32'h06300613 /* 0x1894 */; - 1574: data_o = 32'h6685d398 /* 0x1898 */; - 1575: data_o = 32'h12b00713 /* 0x189c */; - 1576: data_o = 32'h9c36869b /* 0x18a0 */; - 1577: data_o = 32'h25700793 /* 0x18a4 */; - 1578: data_o = 32'h02b5553b /* 0x18a8 */; - 1579: data_o = 32'h02b6563b /* 0x18ac */; - 1580: data_o = 32'h91411542 /* 0x18b0 */; - 1581: data_o = 32'h0015081b /* 0x18b4 */; - 1582: data_o = 32'h0108181b /* 0x18b8 */; - 1583: data_o = 32'h02b7573b /* 0x18bc */; - 1584: data_o = 32'h16422605 /* 0x18c0 */; - 1585: data_o = 32'hd6bb9241 /* 0x18c4 */; - 1586: data_o = 32'h270502b6 /* 0x18c8 */; - 1587: data_o = 32'h93411742 /* 0x18cc */; - 1588: data_o = 32'h02b7d7bb /* 0x18d0 */; - 1589: data_o = 32'h9e919e89 /* 0x18d4 */; - 1590: data_o = 32'h85b69e99 /* 0x18d8 */; - 1591: data_o = 32'h92c116c2 /* 0x18dc */; - 1592: data_o = 32'h17c22785 /* 0x18e0 */; - 1593: data_o = 32'hf36393c1 /* 0x18e4 */; - 1594: data_o = 32'h85be00f6 /* 0x18e8 */; - 1595: data_o = 32'h0105959b /* 0x18ec */; - 1596: data_o = 32'h0105d59b /* 0x18f0 */; - 1597: data_o = 32'h0105e5b3 /* 0x18f4 */; - 1598: data_o = 32'h01001697 /* 0x18f8 */; - 1599: data_o = 32'h86932581 /* 0x18fc */; - 1600: data_o = 32'h171b7086 /* 0x1900 */; - 1601: data_o = 32'hda8c0107 /* 0x1904 */; - 1602: data_o = 32'h16978f51 /* 0x1908 */; - 1603: data_o = 32'h27010100 /* 0x190c */; + 1049: data_o = 32'h740270a2 /* 0x1064 */; + 1050: data_o = 32'h64e28ff5 /* 0x1068 */; + 1051: data_o = 32'h851b6942 /* 0x106c */; + 1052: data_o = 32'h61450007 /* 0x1070 */; + 1053: data_o = 32'h01138082 /* 0x1074 */; + 1054: data_o = 32'h3023d401 /* 0x1078 */; + 1055: data_o = 32'h0b332961 /* 0x107c */; + 1056: data_o = 32'h342300d6 /* 0x1080 */; + 1057: data_o = 32'h3c232951 /* 0x1084 */; + 1058: data_o = 32'h30232771 /* 0x1088 */; + 1059: data_o = 32'h3c2327a1 /* 0x108c */; + 1060: data_o = 32'h38232a11 /* 0x1090 */; + 1061: data_o = 32'h34232a81 /* 0x1094 */; + 1062: data_o = 32'h30232a91 /* 0x1098 */; + 1063: data_o = 32'h3c232b21 /* 0x109c */; + 1064: data_o = 32'h38232931 /* 0x10a0 */; + 1065: data_o = 32'h38232941 /* 0x10a4 */; + 1066: data_o = 32'h34232781 /* 0x10a8 */; + 1067: data_o = 32'h3c232791 /* 0x10ac */; + 1068: data_o = 32'h7b1325b1 /* 0x10b0 */; + 1069: data_o = 32'h8d2a1ffb /* 0x10b4 */; + 1070: data_o = 32'h7b938aae /* 0x10b8 */; + 1071: data_o = 32'h14631ff6 /* 0x10bc */; + 1072: data_o = 32'h0b13000b /* 0x10c0 */; + 1073: data_o = 32'h84132000 /* 0x10c4 */; + 1074: data_o = 32'h945e1ff6 /* 0x10c8 */; + 1075: data_o = 32'hfaa00793 /* 0x10cc */; + 1076: data_o = 32'h02a38025 /* 0x10d0 */; + 1077: data_o = 32'h0a6302f1 /* 0x10d4 */; + 1078: data_o = 32'h47852404 /* 0x10d8 */; + 1079: data_o = 32'h10f40b63 /* 0x10dc */; + 1080: data_o = 32'h05200593 /* 0x10e0 */; + 1081: data_o = 32'h579b8225 /* 0x10e4 */; + 1082: data_o = 32'h76930186 /* 0x10e8 */; + 1083: data_o = 32'h16820ff6 /* 0x10ec */; + 1084: data_o = 32'h8fd507a2 /* 0x10f0 */; + 1085: data_o = 32'h00ff06b7 /* 0x10f4 */; + 1086: data_o = 32'h0086571b /* 0x10f8 */; + 1087: data_o = 32'h8e5d8e75 /* 0x10fc */; + 1088: data_o = 32'h076257fd /* 0x1100 */; + 1089: data_o = 32'h8ff99381 /* 0x1104 */; + 1090: data_o = 32'h8e4d8e5d /* 0x1108 */; + 1091: data_o = 32'h0894e8b2 /* 0x110c */; + 1092: data_o = 32'h05510513 /* 0x1110 */; + 1093: data_o = 32'h85934701 /* 0x1114 */; + 1094: data_o = 32'hc7830541 /* 0x1118 */; + 1095: data_o = 32'h171b0006 /* 0x111c */; + 1096: data_o = 32'h06850017 /* 0x1120 */; + 1097: data_o = 32'hf7938fb9 /* 0x1124 */; + 1098: data_o = 32'h97ae0ff7 /* 0x1128 */; + 1099: data_o = 32'h0007c703 /* 0x112c */; + 1100: data_o = 32'hfed515e3 /* 0x1130 */; + 1101: data_o = 32'h00171793 /* 0x1134 */; + 1102: data_o = 32'h0017e793 /* 0x1138 */; + 1103: data_o = 32'h8fd117a2 /* 0x113c */; + 1104: data_o = 32'hf43ee882 /* 0x1140 */; + 1105: data_o = 32'h010d2583 /* 0x1144 */; + 1106: data_o = 32'hc8be478d /* 0x1148 */; + 1107: data_o = 32'hf0be103c /* 0x114c */; + 1108: data_o = 32'h47994685 /* 0x1150 */; + 1109: data_o = 32'h856a0890 /* 0x1154 */; + 1110: data_o = 32'hf882ec82 /* 0x1158 */; + 1111: data_o = 32'hf0eff4be /* 0x115c */; + 1112: data_o = 32'h0d9bc85f /* 0x1160 */; + 1113: data_o = 32'h98630005 /* 0x1164 */; + 1114: data_o = 32'h4703040d /* 0x1168 */; + 1115: data_o = 32'h07930281 /* 0x116c */; + 1116: data_o = 32'h258304c0 /* 0x1170 */; + 1117: data_o = 32'h0e63010d /* 0x1174 */; + 1118: data_o = 32'h44a120f7 /* 0x1178 */; + 1119: data_o = 32'h09934a11 /* 0x117c */; + 1120: data_o = 32'h49050251 /* 0x1180 */; + 1121: data_o = 32'h0783a029 /* 0x1184 */; + 1122: data_o = 32'hd7630251 /* 0x1188 */; + 1123: data_o = 32'h25830607 /* 0x118c */; + 1124: data_o = 32'he882010d /* 0x1190 */; + 1125: data_o = 32'h08904685 /* 0x1194 */; + 1126: data_o = 32'hec82856a /* 0x1198 */; + 1127: data_o = 32'hc8d2f882 /* 0x119c */; + 1128: data_o = 32'hf4caf0ce /* 0x11a0 */; + 1129: data_o = 32'hc3fff0ef /* 0x11a4 */; + 1130: data_o = 32'h00050d9b /* 0x11a8 */; + 1131: data_o = 32'h946334fd /* 0x11ac */; + 1132: data_o = 32'hf8f1000d /* 0x11b0 */; + 1133: data_o = 32'h30834dc9 /* 0x11b4 */; + 1134: data_o = 32'h34032b81 /* 0x11b8 */; + 1135: data_o = 32'h34832b01 /* 0x11bc */; + 1136: data_o = 32'h39032a81 /* 0x11c0 */; + 1137: data_o = 32'h39832a01 /* 0x11c4 */; + 1138: data_o = 32'h3a032981 /* 0x11c8 */; + 1139: data_o = 32'h3a832901 /* 0x11cc */; + 1140: data_o = 32'h3b032881 /* 0x11d0 */; + 1141: data_o = 32'h3b832801 /* 0x11d4 */; + 1142: data_o = 32'h3c032781 /* 0x11d8 */; + 1143: data_o = 32'h3c832701 /* 0x11dc */; + 1144: data_o = 32'h3d032681 /* 0x11e0 */; + 1145: data_o = 32'h856e2601 /* 0x11e4 */; + 1146: data_o = 32'h25813d83 /* 0x11e8 */; + 1147: data_o = 32'h2c010113 /* 0x11ec */; + 1148: data_o = 32'h05938082 /* 0x11f0 */; + 1149: data_o = 32'hb5fd0510 /* 0x11f4 */; + 1150: data_o = 32'h017037b3 /* 0x11f8 */; + 1151: data_o = 32'hec3e6c85 /* 0x11fc */; + 1152: data_o = 32'h800c8793 /* 0x1200 */; + 1153: data_o = 32'h089ce43e /* 0x1204 */; + 1154: data_o = 32'h8ab397de /* 0x1208 */; + 1155: data_o = 32'h4c01417a /* 0x120c */; + 1156: data_o = 32'h6709e83e /* 0x1210 */; + 1157: data_o = 32'h71070c93 /* 0x1214 */; + 1158: data_o = 32'h09134991 /* 0x1218 */; + 1159: data_o = 32'h44850251 /* 0x121c */; + 1160: data_o = 32'h0ff00a13 /* 0x1220 */; + 1161: data_o = 32'h8463a039 /* 0x1224 */; + 1162: data_o = 32'h4683160c /* 0x1228 */; + 1163: data_o = 32'h95630251 /* 0x122c */; + 1164: data_o = 32'h25830346 /* 0x1230 */; + 1165: data_o = 32'hf402010d /* 0x1234 */; + 1166: data_o = 32'h10304685 /* 0x1238 */; + 1167: data_o = 32'hf802856a /* 0x123c */; + 1168: data_o = 32'hd44ee482 /* 0x1240 */; + 1169: data_o = 32'he0a6fc4a /* 0x1244 */; + 1170: data_o = 32'hb9bff0ef /* 0x1248 */; + 1171: data_o = 32'h00050d9b /* 0x124c */; + 1172: data_o = 32'h8ae33cfd /* 0x1250 */; + 1173: data_o = 32'hb785fc0d /* 0x1254 */; + 1174: data_o = 32'h0fe00713 /* 0x1258 */; + 1175: data_o = 32'h18e69163 /* 0x125c */; + 1176: data_o = 32'h100c0e63 /* 0x1260 */; + 1177: data_o = 32'hfff40713 /* 0x1264 */; + 1178: data_o = 32'h10ec0163 /* 0x1268 */; + 1179: data_o = 32'he00288d6 /* 0x126c */; + 1180: data_o = 32'h8a138cc6 /* 0x1270 */; + 1181: data_o = 32'h89c62008 /* 0x1274 */; + 1182: data_o = 32'h04934911 /* 0x1278 */; + 1183: data_o = 32'hf4021000 /* 0x127c */; + 1184: data_o = 32'h8663f802 /* 0x1280 */; + 1185: data_o = 32'he4820a09 /* 0x1284 */; + 1186: data_o = 32'hfc4ed44a /* 0x1288 */; + 1187: data_o = 32'h2583e0a6 /* 0x128c */; + 1188: data_o = 32'h4685010d /* 0x1290 */; + 1189: data_o = 32'h856a1030 /* 0x1294 */; + 1190: data_o = 32'hb4bff0ef /* 0x1298 */; + 1191: data_o = 32'h89932501 /* 0x129c */; + 1192: data_o = 32'he1711009 /* 0x12a0 */; + 1193: data_o = 32'hfd3a1de3 /* 0x12a4 */; + 1194: data_o = 32'h4711f402 /* 0x12a8 */; + 1195: data_o = 32'h010d2583 /* 0x12ac */; + 1196: data_o = 32'h0713d43a /* 0x12b0 */; + 1197: data_o = 32'hfc3a0261 /* 0x12b4 */; + 1198: data_o = 32'h47094685 /* 0x12b8 */; + 1199: data_o = 32'h856a1030 /* 0x12bc */; + 1200: data_o = 32'he482f802 /* 0x12c0 */; + 1201: data_o = 32'hf0efe0ba /* 0x12c4 */; + 1202: data_o = 32'h2501b1df /* 0x12c8 */; + 1203: data_o = 32'h4681ed49 /* 0x12cc */; + 1204: data_o = 32'he5418593 /* 0x12d0 */; + 1205: data_o = 32'h000cc703 /* 0x12d4 */; + 1206: data_o = 32'h0086d61b /* 0x12d8 */; + 1207: data_o = 32'h0086969b /* 0x12dc */; + 1208: data_o = 32'h17028f31 /* 0x12e0 */; + 1209: data_o = 32'h972e837d /* 0x12e4 */; + 1210: data_o = 32'h00075703 /* 0x12e8 */; + 1211: data_o = 32'h92c116c2 /* 0x12ec */; + 1212: data_o = 32'h8eb90c85 /* 0x12f0 */; + 1213: data_o = 32'hff9a10e3 /* 0x12f4 */; + 1214: data_o = 32'h0086971b /* 0x12f8 */; + 1215: data_o = 32'h0086d69b /* 0x12fc */; + 1216: data_o = 32'h56038f55 /* 0x1300 */; + 1217: data_o = 32'h17420261 /* 0x1304 */; + 1218: data_o = 32'h1d639341 /* 0x1308 */; + 1219: data_o = 32'h67820ce6 /* 0x130c */; + 1220: data_o = 32'h8533c795 /* 0x1310 */; + 1221: data_o = 32'h9863015b /* 0x1314 */; + 1222: data_o = 32'h65c20a0d /* 0x1318 */; + 1223: data_o = 32'h20000613 /* 0x131c */; + 1224: data_o = 32'h41760633 /* 0x1320 */; + 1225: data_o = 32'he91fe0ef /* 0x1324 */; + 1226: data_o = 32'h4d81a821 /* 0x1328 */; + 1227: data_o = 32'h4789b569 /* 0x132c */; + 1228: data_o = 32'h67a2d43e /* 0x1330 */; + 1229: data_o = 32'he482e082 /* 0x1334 */; + 1230: data_o = 32'hbf91fc3e /* 0x1338 */; + 1231: data_o = 32'h060d9f63 /* 0x133c */; + 1232: data_o = 32'h8a930c05 /* 0x1340 */; + 1233: data_o = 32'h16e3200a /* 0x1344 */; + 1234: data_o = 32'h4785ed84 /* 0x1348 */; + 1235: data_o = 32'h0af40263 /* 0x134c */; + 1236: data_o = 32'h06100593 /* 0x1350 */; + 1237: data_o = 32'h470115a2 /* 0x1354 */; + 1238: data_o = 32'h46051034 /* 0x1358 */; + 1239: data_o = 32'h04c58593 /* 0x135c */; + 1240: data_o = 32'hf0ef856a /* 0x1360 */; + 1241: data_o = 32'h8daab55f /* 0x1364 */; + 1242: data_o = 32'h0713b5b9 /* 0x1368 */; + 1243: data_o = 32'h0fe32000 /* 0x136c */; + 1244: data_o = 32'he06eeeeb /* 0x1370 */; + 1245: data_o = 32'h05010893 /* 0x1374 */; + 1246: data_o = 32'hbddd4d85 /* 0x1378 */; + 1247: data_o = 32'h04940b63 /* 0x137c */; + 1248: data_o = 32'h060b8563 /* 0x1380 */; + 1249: data_o = 32'he03e4785 /* 0x1384 */; + 1250: data_o = 32'h05010893 /* 0x1388 */; + 1251: data_o = 32'h4de5b5d5 /* 0x138c */; + 1252: data_o = 32'he882b51d /* 0x1390 */; + 1253: data_o = 32'hc8be4791 /* 0x1394 */; + 1254: data_o = 32'h02610793 /* 0x1398 */; + 1255: data_o = 32'h4685f0be /* 0x139c */; + 1256: data_o = 32'h08904785 /* 0x13a0 */; + 1257: data_o = 32'hec82856a /* 0x13a4 */; + 1258: data_o = 32'hf4bef882 /* 0x13a8 */; + 1259: data_o = 32'ha37ff0ef /* 0x13ac */; + 1260: data_o = 32'h00050d9b /* 0x13b0 */; + 1261: data_o = 32'hdc0d83e3 /* 0x13b4 */; + 1262: data_o = 32'h865abbfd /* 0x13b8 */; + 1263: data_o = 32'h8556088c /* 0x13bc */; + 1264: data_o = 32'hdf5fe0ef /* 0x13c0 */; + 1265: data_o = 32'h65c2bfb5 /* 0x13c4 */; + 1266: data_o = 32'h417b0633 /* 0x13c8 */; + 1267: data_o = 32'hde9fe0ef /* 0x13cc */; + 1268: data_o = 32'h0713bf85 /* 0x13d0 */; + 1269: data_o = 32'h05e32000 /* 0x13d4 */; + 1270: data_o = 32'h6de2faeb /* 0x13d8 */; + 1271: data_o = 32'h0d93bf59 /* 0x13dc */; + 1272: data_o = 32'hbbd10200 /* 0x13e0 */; + 1273: data_o = 32'h02100d93 /* 0x13e4 */; + 1274: data_o = 32'he002b3f9 /* 0x13e8 */; + 1275: data_o = 32'hb54988d6 /* 0x13ec */; + 1276: data_o = 32'h014d2783 /* 0x13f0 */; + 1277: data_o = 32'h000d3703 /* 0x13f4 */; + 1278: data_o = 32'h4b5cd35c /* 0x13f8 */; + 1279: data_o = 32'h01f7d79b /* 0x13fc */; + 1280: data_o = 32'h479ddfed /* 0x1400 */; + 1281: data_o = 32'h4d81d71c /* 0x1404 */; + 1282: data_o = 32'hc291b37d /* 0x1408 */; + 1283: data_o = 32'h4501b1ad /* 0x140c */; + 1284: data_o = 32'h71598082 /* 0x1410 */; + 1285: data_o = 32'h84aeeca6 /* 0x1414 */; + 1286: data_o = 32'hf486e8ca /* 0x1418 */; + 1287: data_o = 32'he4cef0a2 /* 0x141c */; + 1288: data_o = 32'hfc56e0d2 /* 0x1420 */; + 1289: data_o = 32'h892af85a /* 0x1424 */; + 1290: data_o = 32'h061346a1 /* 0x1428 */; + 1291: data_o = 32'h100c2000 /* 0x142c */; + 1292: data_o = 32'h99028526 /* 0x1430 */; + 1293: data_o = 32'h1797ed51 /* 0x1434 */; + 1294: data_o = 32'h77020000 /* 0x1438 */; + 1295: data_o = 32'h8827b783 /* 0x143c */; + 1296: data_o = 32'h08f71863 /* 0x1440 */; + 1297: data_o = 32'h061346c1 /* 0x1444 */; + 1298: data_o = 32'h858a2480 /* 0x1448 */; + 1299: data_o = 32'h99028526 /* 0x144c */; + 1300: data_o = 32'he14d87aa /* 0x1450 */; + 1301: data_o = 32'h099347a2 /* 0x1454 */; + 1302: data_o = 32'h4a0105f0 /* 0x1458 */; + 1303: data_o = 32'h4b01cfad /* 0x145c */; + 1304: data_o = 32'h05f00a93 /* 0x1460 */; + 1305: data_o = 32'h00c16783 /* 0x1464 */; + 1306: data_o = 32'h46c16402 /* 0x1468 */; + 1307: data_o = 32'h036787b3 /* 0x146c */; + 1308: data_o = 32'h080c0426 /* 0x1470 */; + 1309: data_o = 32'h943e8526 /* 0x1474 */; + 1310: data_o = 32'h02040613 /* 0x1478 */; + 1311: data_o = 32'h87aa9902 /* 0x147c */; + 1312: data_o = 32'h862246c1 /* 0x1480 */; + 1313: data_o = 32'h8526100c /* 0x1484 */; + 1314: data_o = 32'h6742e7b5 /* 0x1488 */; + 1315: data_o = 32'h186367e2 /* 0x148c */; + 1316: data_o = 32'h0993000b /* 0x1490 */; + 1317: data_o = 32'hf36305f7 /* 0x1494 */; + 1318: data_o = 32'h89be0137 /* 0x1498 */; + 1319: data_o = 32'h8f998a3a /* 0x149c */; + 1320: data_o = 32'h00faec63 /* 0x14a0 */; + 1321: data_o = 32'h87aa9902 /* 0x14a4 */; + 1322: data_o = 32'h1797e531 /* 0x14a8 */; + 1323: data_o = 32'hb7830000 /* 0x14ac */; + 1324: data_o = 32'h77028167 /* 0x14b0 */; + 1325: data_o = 32'h08f70e63 /* 0x14b4 */; + 1326: data_o = 32'h00816783 /* 0x14b8 */; + 1327: data_o = 32'h43e30b05 /* 0x14bc */; + 1328: data_o = 32'h6783fafb /* 0x14c0 */; + 1329: data_o = 32'h08630081 /* 0x14c4 */; + 1330: data_o = 32'h6a4200fb /* 0x14c8 */; + 1331: data_o = 32'ha02169e2 /* 0x14cc */; + 1332: data_o = 32'h05f00993 /* 0x14d0 */; + 1333: data_o = 32'h86934a01 /* 0x14d4 */; + 1334: data_o = 32'h86b30019 /* 0x14d8 */; + 1335: data_o = 32'hf5974146 /* 0x14dc */; + 1336: data_o = 32'h06a60dff /* 0x14e0 */; + 1337: data_o = 32'h009a1613 /* 0x14e4 */; + 1338: data_o = 32'hb2258593 /* 0x14e8 */; + 1339: data_o = 32'h99028526 /* 0x14ec */; + 1340: data_o = 32'hcd0187aa /* 0x14f0 */; + 1341: data_o = 32'h740670a6 /* 0x14f4 */; + 1342: data_o = 32'h694664e6 /* 0x14f8 */; + 1343: data_o = 32'h6a0669a6 /* 0x14fc */; + 1344: data_o = 32'h7b427ae2 /* 0x1500 */; + 1345: data_o = 32'h6165853e /* 0x1504 */; + 1346: data_o = 32'h69138082 /* 0x1508 */; + 1347: data_o = 32'h29010019 /* 0x150c */; + 1348: data_o = 32'h00fff797 /* 0x1510 */; + 1349: data_o = 32'haf27a823 /* 0x1514 */; + 1350: data_o = 32'h00fff797 /* 0x1518 */; + 1351: data_o = 32'h87932481 /* 0x151c */; + 1352: data_o = 32'hc3c4ae87 /* 0x1520 */; + 1353: data_o = 32'hf797870e /* 0x1524 */; + 1354: data_o = 32'h740600ff /* 0x1528 */; + 1355: data_o = 32'h64e670a6 /* 0x152c */; + 1356: data_o = 32'h69a66946 /* 0x1530 */; + 1357: data_o = 32'h7ae26a06 /* 0x1534 */; + 1358: data_o = 32'h27017b42 /* 0x1538 */; + 1359: data_o = 32'hada78793 /* 0x153c */; + 1360: data_o = 32'h0dfff517 /* 0x1540 */; + 1361: data_o = 32'h0513c7d8 /* 0x1544 */; + 1362: data_o = 32'h6165ac05 /* 0x1548 */; + 1363: data_o = 32'hb6dfe06f /* 0x154c */; + 1364: data_o = 32'h00000797 /* 0x1550 */; + 1365: data_o = 32'h7787b783 /* 0x1554 */; + 1366: data_o = 32'h1fe37722 /* 0x1558 */; + 1367: data_o = 32'hb795f4f7 /* 0x155c */; + 1368: data_o = 32'h00fff797 /* 0x1560 */; + 1369: data_o = 32'h87937119 /* 0x1564 */; + 1370: data_o = 32'hf0caaa07 /* 0x1568 */; + 1371: data_o = 32'h0407a903 /* 0x156c */; + 1372: data_o = 32'h00fff797 /* 0x1570 */; + 1373: data_o = 32'ha9078793 /* 0x1574 */; + 1374: data_o = 32'h43e0f8a2 /* 0x1578 */; + 1375: data_o = 32'heccef4a6 /* 0x157c */; + 1376: data_o = 32'h90011402 /* 0x1580 */; + 1377: data_o = 32'hfc868522 /* 0x1584 */; + 1378: data_o = 32'he0ef2901 /* 0x1588 */; + 1379: data_o = 32'h4989fadf /* 0x158c */; + 1380: data_o = 32'h086384aa /* 0x1590 */; + 1381: data_o = 32'h478d1d39 /* 0x1594 */; + 1382: data_o = 32'h26f90e63 /* 0x1598 */; + 1383: data_o = 32'h1f634785 /* 0x159c */; + 1384: data_o = 32'h37b73cf9 /* 0x15a0 */; + 1385: data_o = 32'h8713016e /* 0x15a4 */; + 1386: data_o = 32'hd0026007 /* 0x15a8 */; + 1387: data_o = 32'hd24eec3a /* 0x15ac */; + 1388: data_o = 32'h5ff78793 /* 0x15b0 */; + 1389: data_o = 32'hff634561 /* 0x15b4 */; + 1390: data_o = 32'h35171897 /* 0x15b8 */; + 1391: data_o = 32'h05130100 /* 0x15bc */; + 1392: data_o = 32'he82aa465 /* 0x15c0 */; + 1393: data_o = 32'h9eaff0ef /* 0x15c4 */; + 1394: data_o = 32'h000317b7 /* 0x15c8 */; + 1395: data_o = 32'hd4078793 /* 0x15cc */; + 1396: data_o = 32'hc226c03e /* 0x15d0 */; + 1397: data_o = 32'h46816582 /* 0x15d4 */; + 1398: data_o = 32'h08084601 /* 0x15d8 */; + 1399: data_o = 32'he0efe402 /* 0x15dc */; + 1400: data_o = 32'h2501ecdf /* 0x15e0 */; + 1401: data_o = 32'h16051863 /* 0x15e4 */; + 1402: data_o = 32'h65825692 /* 0x15e8 */; + 1403: data_o = 32'h08086622 /* 0x15ec */; + 1404: data_o = 32'hebbfe0ef /* 0x15f0 */; + 1405: data_o = 32'h1f632501 /* 0x15f4 */; + 1406: data_o = 32'h37971405 /* 0x15f8 */; + 1407: data_o = 32'h87930100 /* 0x15fc */; + 1408: data_o = 32'h0737a067 /* 0x1600 */; + 1409: data_o = 32'hcb988000 /* 0x1604 */; + 1410: data_o = 32'h01003797 /* 0x1608 */; + 1411: data_o = 32'h9f878793 /* 0x160c */; + 1412: data_o = 32'h07374b9c /* 0x1610 */; + 1413: data_o = 32'h177de000 /* 0x1614 */; + 1414: data_o = 32'h07378ff9 /* 0x1618 */; + 1415: data_o = 32'h8fd92000 /* 0x161c */; + 1416: data_o = 32'h01003717 /* 0x1620 */; + 1417: data_o = 32'h9e070713 /* 0x1624 */; + 1418: data_o = 32'h5582cb1c /* 0x1628 */; + 1419: data_o = 32'h0793f402 /* 0x162c */; + 1420: data_o = 32'h46850500 /* 0x1630 */; + 1421: data_o = 32'h08081030 /* 0x1634 */; + 1422: data_o = 32'he082f802 /* 0x1638 */; + 1423: data_o = 32'hd44ee482 /* 0x163c */; + 1424: data_o = 32'hf0effc3e /* 0x1640 */; + 1425: data_o = 32'h2501fa0f /* 0x1644 */; + 1426: data_o = 32'h10051663 /* 0x1648 */; + 1427: data_o = 32'h09500593 /* 0x164c */; + 1428: data_o = 32'h470515a2 /* 0x1650 */; + 1429: data_o = 32'h46014685 /* 0x1654 */; + 1430: data_o = 32'h04058593 /* 0x1658 */; + 1431: data_o = 32'hf0ef0808 /* 0x165c */; + 1432: data_o = 32'h19639b9f /* 0x1660 */; + 1433: data_o = 32'h07970e05 /* 0x1664 */; + 1434: data_o = 32'h17370000 /* 0x1668 */; + 1435: data_o = 32'hb5830aa0 /* 0x166c */; + 1436: data_o = 32'h073266a7 /* 0x1670 */; + 1437: data_o = 32'h46850705 /* 0x1674 */; + 1438: data_o = 32'h08084611 /* 0x1678 */; + 1439: data_o = 32'h99bff0ef /* 0x167c */; + 1440: data_o = 32'h0493e971 /* 0x1680 */; + 1441: data_o = 32'h14a20650 /* 0x1684 */; + 1442: data_o = 32'h03210423 /* 0x1688 */; + 1443: data_o = 32'h07748493 /* 0x168c */; + 1444: data_o = 32'h46814701 /* 0x1690 */; + 1445: data_o = 32'h85a64601 /* 0x1694 */; + 1446: data_o = 32'hf0ef0808 /* 0x1698 */; + 1447: data_o = 32'he95d97df /* 0x169c */; + 1448: data_o = 32'h00000797 /* 0x16a0 */; + 1449: data_o = 32'h6387b583 /* 0x16a4 */; + 1450: data_o = 32'h10344701 /* 0x16a8 */; + 1451: data_o = 32'h08084601 /* 0x16ac */; + 1452: data_o = 32'h807ff0ef /* 0x16b0 */; + 1453: data_o = 32'h4783e145 /* 0x16b4 */; + 1454: data_o = 32'hfbf90281 /* 0x16b8 */; + 1455: data_o = 32'h0fd00593 /* 0x16bc */; + 1456: data_o = 32'h470115a2 /* 0x16c0 */; + 1457: data_o = 32'h460d4681 /* 0x16c4 */; + 1458: data_o = 32'h07a58593 /* 0x16c8 */; + 1459: data_o = 32'hf0ef0808 /* 0x16cc */; + 1460: data_o = 32'he149949f /* 0x16d0 */; + 1461: data_o = 32'h00000797 /* 0x16d4 */; + 1462: data_o = 32'h60c7b583 /* 0x16d8 */; + 1463: data_o = 32'h46854701 /* 0x16dc */; + 1464: data_o = 32'h08084601 /* 0x16e0 */; + 1465: data_o = 32'h933ff0ef /* 0x16e4 */; + 1466: data_o = 32'h64c2e535 /* 0x16e8 */; + 1467: data_o = 32'he0000937 /* 0x16ec */; + 1468: data_o = 32'h489c197d /* 0x16f0 */; + 1469: data_o = 32'h08086622 /* 0x16f4 */; + 1470: data_o = 32'h0127f7b3 /* 0x16f8 */; + 1471: data_o = 32'h67e2c89c /* 0x16fc */; + 1472: data_o = 32'hc03e5682 /* 0x1700 */; + 1473: data_o = 32'he0ef6582 /* 0x1704 */; + 1474: data_o = 32'h2501da5f /* 0x1708 */; + 1475: data_o = 32'h5692e521 /* 0x170c */; + 1476: data_o = 32'h66226582 /* 0x1710 */; + 1477: data_o = 32'he0ef0808 /* 0x1714 */; + 1478: data_o = 32'h2501d95f /* 0x1718 */; + 1479: data_o = 32'h0513ed05 /* 0x171c */; + 1480: data_o = 32'h05333e80 /* 0x1720 */; + 1481: data_o = 32'h489c02a4 /* 0x1724 */; + 1482: data_o = 32'h20000737 /* 0x1728 */; + 1483: data_o = 32'h0127f7b3 /* 0x172c */; + 1484: data_o = 32'hc89c8fd9 /* 0x1730 */; + 1485: data_o = 32'h000f47b7 /* 0x1734 */; + 1486: data_o = 32'h24078793 /* 0x1738 */; + 1487: data_o = 32'h02f55533 /* 0x173c */; + 1488: data_o = 32'he0ef0505 /* 0x1740 */; + 1489: data_o = 32'h0517a89f /* 0x1744 */; + 1490: data_o = 32'h080c0000 /* 0x1748 */; + 1491: data_o = 32'hcc450513 /* 0x174c */; + 1492: data_o = 32'hcc3ff0ef /* 0x1750 */; + 1493: data_o = 32'h744670e6 /* 0x1754 */; + 1494: data_o = 32'h790674a6 /* 0x1758 */; + 1495: data_o = 32'h610969e6 /* 0x175c */; + 1496: data_o = 32'h67b78082 /* 0x1760 */; + 1497: data_o = 32'hfc020989 /* 0x1764 */; + 1498: data_o = 32'h7ff78793 /* 0x1768 */; + 1499: data_o = 32'h00255913 /* 0x176c */; + 1500: data_o = 32'h00a7f663 /* 0x1770 */; + 1501: data_o = 32'h02626937 /* 0x1774 */; + 1502: data_o = 32'ha0090913 /* 0x1778 */; + 1503: data_o = 32'hf84a4785 /* 0x177c */; + 1504: data_o = 32'h454ddc3e /* 0x1780 */; + 1505: data_o = 32'hfc0908e3 /* 0x1784 */; + 1506: data_o = 32'he5e34551 /* 0x1788 */; + 1507: data_o = 32'h3517fd24 /* 0x178c */; + 1508: data_o = 32'h05130100 /* 0x1790 */; + 1509: data_o = 32'hf42a8725 /* 0x1794 */; + 1510: data_o = 32'h816ff0ef /* 0x1798 */; + 1511: data_o = 32'h000f17b7 /* 0x179c */; + 1512: data_o = 32'hf0f78793 /* 0x17a0 */; + 1513: data_o = 32'hca26c84a /* 0x17a4 */; + 1514: data_o = 32'h1e23cc3e /* 0x17a8 */; + 1515: data_o = 32'h65c20001 /* 0x17ac */; + 1516: data_o = 32'h46856662 /* 0x17b0 */; + 1517: data_o = 32'he0ef1028 /* 0x17b4 */; + 1518: data_o = 32'h2501cf5f /* 0x17b8 */; + 1519: data_o = 32'h3797fd41 /* 0x17bc */; + 1520: data_o = 32'h87930100 /* 0x17c0 */; + 1521: data_o = 32'h07378427 /* 0x17c4 */; + 1522: data_o = 32'hcb988000 /* 0x17c8 */; + 1523: data_o = 32'h01003797 /* 0x17cc */; + 1524: data_o = 32'h83478793 /* 0x17d0 */; + 1525: data_o = 32'h07374b9c /* 0x17d4 */; + 1526: data_o = 32'h177de000 /* 0x17d8 */; + 1527: data_o = 32'h07378ff9 /* 0x17dc */; + 1528: data_o = 32'h8fd92000 /* 0x17e0 */; + 1529: data_o = 32'h01003717 /* 0x17e4 */; + 1530: data_o = 32'h81c70713 /* 0x17e8 */; + 1531: data_o = 32'h0793cb1c /* 0x17ec */; + 1532: data_o = 32'h053315e0 /* 0x17f0 */; + 1533: data_o = 32'h47b702f4 /* 0x17f4 */; + 1534: data_o = 32'h8793000f /* 0x17f8 */; + 1535: data_o = 32'h55332407 /* 0x17fc */; + 1536: data_o = 32'h050502f5 /* 0x1800 */; + 1537: data_o = 32'h9c7fe0ef /* 0x1804 */; + 1538: data_o = 32'hfffff517 /* 0x1808 */; + 1539: data_o = 32'h0513102c /* 0x180c */; + 1540: data_o = 32'hbf3d3d05 /* 0x1810 */; + 1541: data_o = 32'hdc9d4549 /* 0x1814 */; + 1542: data_o = 32'h3b9ad5b7 /* 0x1818 */; + 1543: data_o = 32'ha0058593 /* 0x181c */; + 1544: data_o = 32'h0295d5b3 /* 0x1820 */; + 1545: data_o = 32'h01001797 /* 0x1824 */; + 1546: data_o = 32'h7dc78793 /* 0x1828 */; + 1547: data_o = 32'h1797f43e /* 0x182c */; + 1548: data_o = 32'h87930100 /* 0x1830 */; + 1549: data_o = 32'h4b987d27 /* 0x1834 */; + 1550: data_o = 32'h01001797 /* 0x1838 */; + 1551: data_o = 32'h7c878793 /* 0x183c */; + 1552: data_o = 32'hcb989b79 /* 0x1840 */; + 1553: data_o = 32'h01001797 /* 0x1844 */; + 1554: data_o = 32'h7bc78793 /* 0x1848 */; + 1555: data_o = 32'h17975398 /* 0x184c */; + 1556: data_o = 32'h87930100 /* 0x1850 */; + 1557: data_o = 32'h67137b27 /* 0x1854 */; + 1558: data_o = 32'hd3980807 /* 0x1858 */; + 1559: data_o = 32'h01001797 /* 0x185c */; + 1560: data_o = 32'h7a478793 /* 0x1860 */; + 1561: data_o = 32'h17975398 /* 0x1864 */; + 1562: data_o = 32'h87930100 /* 0x1868 */; + 1563: data_o = 32'h671379a7 /* 0x186c */; + 1564: data_o = 32'hd3980027 /* 0x1870 */; + 1565: data_o = 32'h01001797 /* 0x1874 */; + 1566: data_o = 32'h78c78793 /* 0x1878 */; + 1567: data_o = 32'h17975398 /* 0x187c */; + 1568: data_o = 32'h87930100 /* 0x1880 */; + 1569: data_o = 32'h67137827 /* 0x1884 */; + 1570: data_o = 32'hd3980017 /* 0x1888 */; + 1571: data_o = 32'h01001797 /* 0x188c */; + 1572: data_o = 32'h77478793 /* 0x1890 */; + 1573: data_o = 32'h17975398 /* 0x1894 */; + 1574: data_o = 32'h87930100 /* 0x1898 */; + 1575: data_o = 32'h671376a7 /* 0x189c */; + 1576: data_o = 32'h05131007 /* 0x18a0 */; + 1577: data_o = 32'h06135130 /* 0x18a4 */; + 1578: data_o = 32'hd3980630 /* 0x18a8 */; + 1579: data_o = 32'h07136685 /* 0x18ac */; + 1580: data_o = 32'h869b12b0 /* 0x18b0 */; + 1581: data_o = 32'h07939c36 /* 0x18b4 */; + 1582: data_o = 32'h553b2570 /* 0x18b8 */; + 1583: data_o = 32'h563b02b5 /* 0x18bc */; + 1584: data_o = 32'h154202b6 /* 0x18c0 */; + 1585: data_o = 32'h081b9141 /* 0x18c4 */; + 1586: data_o = 32'h181b0015 /* 0x18c8 */; + 1587: data_o = 32'h573b0108 /* 0x18cc */; + 1588: data_o = 32'h260502b7 /* 0x18d0 */; + 1589: data_o = 32'h92411642 /* 0x18d4 */; + 1590: data_o = 32'h02b6d6bb /* 0x18d8 */; + 1591: data_o = 32'h17422705 /* 0x18dc */; + 1592: data_o = 32'hd7bb9341 /* 0x18e0 */; + 1593: data_o = 32'h9e8902b7 /* 0x18e4 */; + 1594: data_o = 32'h9e999e91 /* 0x18e8 */; + 1595: data_o = 32'h16c285b6 /* 0x18ec */; + 1596: data_o = 32'h278592c1 /* 0x18f0 */; + 1597: data_o = 32'h93c117c2 /* 0x18f4 */; + 1598: data_o = 32'h00f6f363 /* 0x18f8 */; + 1599: data_o = 32'h959b85be /* 0x18fc */; + 1600: data_o = 32'hd59b0105 /* 0x1900 */; + 1601: data_o = 32'he5b30105 /* 0x1904 */; + 1602: data_o = 32'h16970105 /* 0x1908 */; + 1603: data_o = 32'h25810100 /* 0x190c */; 1604: data_o = 32'h6f668693 /* 0x1910 */; - 1605: data_o = 32'h971bdad8 /* 0x1914 */; - 1606: data_o = 32'h8f5d0107 /* 0x1918 */; + 1605: data_o = 32'h0107171b /* 0x1914 */; + 1606: data_o = 32'h8f51da8c /* 0x1918 */; 1607: data_o = 32'h01001697 /* 0x191c */; 1608: data_o = 32'h86932701 /* 0x1920 */; - 1609: data_o = 32'hde986e46 /* 0x1924 */; - 1610: data_o = 32'h8e596741 /* 0x1928 */; - 1611: data_o = 32'h01001717 /* 0x192c */; - 1612: data_o = 32'h6d470713 /* 0x1930 */; - 1613: data_o = 32'he7b3df50 /* 0x1934 */; - 1614: data_o = 32'h17170107 /* 0x1938 */; - 1615: data_o = 32'h27810100 /* 0x193c */; - 1616: data_o = 32'h6c670713 /* 0x1940 */; - 1617: data_o = 32'h1797c33c /* 0x1944 */; - 1618: data_o = 32'h87930100 /* 0x1948 */; - 1619: data_o = 32'h4b986ba7 /* 0x194c */; - 1620: data_o = 32'h01001797 /* 0x1950 */; - 1621: data_o = 32'h6b078793 /* 0x1954 */; - 1622: data_o = 32'h00176713 /* 0x1958 */; - 1623: data_o = 32'hfffff517 /* 0x195c */; - 1624: data_o = 32'h102ccb98 /* 0x1960 */; - 1625: data_o = 32'hac650513 /* 0x1964 */; - 1626: data_o = 32'h7446bbd9 /* 0x1968 */; - 1627: data_o = 32'h74a670e6 /* 0x196c */; - 1628: data_o = 32'h69e67906 /* 0x1970 */; - 1629: data_o = 32'he06f6109 /* 0x1974 */; - 1630: data_o = 32'h0000e4df /* 0x1978 */; - 1631: data_o = 32'h00000000 /* 0x197c */; - 1632: data_o = 32'h10210000 /* 0x1980 */; - 1633: data_o = 32'h30632042 /* 0x1984 */; - 1634: data_o = 32'h50a54084 /* 0x1988 */; - 1635: data_o = 32'h70e760c6 /* 0x198c */; - 1636: data_o = 32'h91298108 /* 0x1990 */; - 1637: data_o = 32'hb16ba14a /* 0x1994 */; - 1638: data_o = 32'hd1adc18c /* 0x1998 */; - 1639: data_o = 32'hf1efe1ce /* 0x199c */; - 1640: data_o = 32'h02101231 /* 0x19a0 */; - 1641: data_o = 32'h22523273 /* 0x19a4 */; - 1642: data_o = 32'h429452b5 /* 0x19a8 */; - 1643: data_o = 32'h62d672f7 /* 0x19ac */; - 1644: data_o = 32'h83189339 /* 0x19b0 */; - 1645: data_o = 32'ha35ab37b /* 0x19b4 */; - 1646: data_o = 32'hc39cd3bd /* 0x19b8 */; - 1647: data_o = 32'he3def3ff /* 0x19bc */; - 1648: data_o = 32'h34432462 /* 0x19c0 */; - 1649: data_o = 32'h14010420 /* 0x19c4 */; - 1650: data_o = 32'h74c764e6 /* 0x19c8 */; - 1651: data_o = 32'h548544a4 /* 0x19cc */; - 1652: data_o = 32'hb54ba56a /* 0x19d0 */; - 1653: data_o = 32'h95098528 /* 0x19d4 */; - 1654: data_o = 32'hf5cfe5ee /* 0x19d8 */; - 1655: data_o = 32'hd58dc5ac /* 0x19dc */; - 1656: data_o = 32'h26723653 /* 0x19e0 */; - 1657: data_o = 32'h06301611 /* 0x19e4 */; - 1658: data_o = 32'h66f676d7 /* 0x19e8 */; - 1659: data_o = 32'h46b45695 /* 0x19ec */; - 1660: data_o = 32'ha77ab75b /* 0x19f0 */; - 1661: data_o = 32'h87389719 /* 0x19f4 */; - 1662: data_o = 32'he7fef7df /* 0x19f8 */; - 1663: data_o = 32'hc7bcd79d /* 0x19fc */; - 1664: data_o = 32'h58e548c4 /* 0x1a00 */; - 1665: data_o = 32'h78a76886 /* 0x1a04 */; - 1666: data_o = 32'h18610840 /* 0x1a08 */; - 1667: data_o = 32'h38232802 /* 0x1a0c */; - 1668: data_o = 32'hd9edc9cc /* 0x1a10 */; - 1669: data_o = 32'hf9afe98e /* 0x1a14 */; - 1670: data_o = 32'h99698948 /* 0x1a18 */; - 1671: data_o = 32'hb92ba90a /* 0x1a1c */; - 1672: data_o = 32'h4ad45af5 /* 0x1a20 */; - 1673: data_o = 32'h6a967ab7 /* 0x1a24 */; - 1674: data_o = 32'h0a501a71 /* 0x1a28 */; - 1675: data_o = 32'h2a123a33 /* 0x1a2c */; - 1676: data_o = 32'hcbdcdbfd /* 0x1a30 */; - 1677: data_o = 32'heb9efbbf /* 0x1a34 */; - 1678: data_o = 32'h8b589b79 /* 0x1a38 */; - 1679: data_o = 32'hab1abb3b /* 0x1a3c */; - 1680: data_o = 32'h7c876ca6 /* 0x1a40 */; - 1681: data_o = 32'h5cc54ce4 /* 0x1a44 */; - 1682: data_o = 32'h3c032c22 /* 0x1a48 */; - 1683: data_o = 32'h1c410c60 /* 0x1a4c */; - 1684: data_o = 32'hfd8fedae /* 0x1a50 */; - 1685: data_o = 32'hddcdcdec /* 0x1a54 */; - 1686: data_o = 32'hbd0bad2a /* 0x1a58 */; - 1687: data_o = 32'h9d498d68 /* 0x1a5c */; - 1688: data_o = 32'h6eb67e97 /* 0x1a60 */; - 1689: data_o = 32'h4ef45ed5 /* 0x1a64 */; - 1690: data_o = 32'h2e323e13 /* 0x1a68 */; - 1691: data_o = 32'h0e701e51 /* 0x1a6c */; - 1692: data_o = 32'hefbeff9f /* 0x1a70 */; - 1693: data_o = 32'hcffcdfdd /* 0x1a74 */; - 1694: data_o = 32'haf3abf1b /* 0x1a78 */; - 1695: data_o = 32'h8f789f59 /* 0x1a7c */; - 1696: data_o = 32'h81a99188 /* 0x1a80 */; - 1697: data_o = 32'ha1ebb1ca /* 0x1a84 */; - 1698: data_o = 32'hc12dd10c /* 0x1a88 */; - 1699: data_o = 32'he16ff14e /* 0x1a8c */; - 1700: data_o = 32'h00a11080 /* 0x1a90 */; - 1701: data_o = 32'h20e330c2 /* 0x1a94 */; - 1702: data_o = 32'h40255004 /* 0x1a98 */; - 1703: data_o = 32'h60677046 /* 0x1a9c */; - 1704: data_o = 32'h939883b9 /* 0x1aa0 */; - 1705: data_o = 32'hb3daa3fb /* 0x1aa4 */; - 1706: data_o = 32'hd31cc33d /* 0x1aa8 */; - 1707: data_o = 32'hf35ee37f /* 0x1aac */; - 1708: data_o = 32'h129002b1 /* 0x1ab0 */; - 1709: data_o = 32'h32d222f3 /* 0x1ab4 */; - 1710: data_o = 32'h52144235 /* 0x1ab8 */; - 1711: data_o = 32'h72566277 /* 0x1abc */; - 1712: data_o = 32'ha5cbb5ea /* 0x1ac0 */; - 1713: data_o = 32'h858995a8 /* 0x1ac4 */; - 1714: data_o = 32'he54ff56e /* 0x1ac8 */; - 1715: data_o = 32'hc50dd52c /* 0x1acc */; - 1716: data_o = 32'h24c334e2 /* 0x1ad0 */; - 1717: data_o = 32'h048114a0 /* 0x1ad4 */; - 1718: data_o = 32'h64477466 /* 0x1ad8 */; - 1719: data_o = 32'h44055424 /* 0x1adc */; - 1720: data_o = 32'hb7faa7db /* 0x1ae0 */; - 1721: data_o = 32'h97b88799 /* 0x1ae4 */; - 1722: data_o = 32'hf77ee75f /* 0x1ae8 */; - 1723: data_o = 32'hd73cc71d /* 0x1aec */; - 1724: data_o = 32'h36f226d3 /* 0x1af0 */; - 1725: data_o = 32'h16b00691 /* 0x1af4 */; - 1726: data_o = 32'h76766657 /* 0x1af8 */; - 1727: data_o = 32'h56344615 /* 0x1afc */; - 1728: data_o = 32'hc96dd94c /* 0x1b00 */; - 1729: data_o = 32'he92ff90e /* 0x1b04 */; - 1730: data_o = 32'h89e999c8 /* 0x1b08 */; - 1731: data_o = 32'ha9abb98a /* 0x1b0c */; - 1732: data_o = 32'h48655844 /* 0x1b10 */; - 1733: data_o = 32'h68277806 /* 0x1b14 */; - 1734: data_o = 32'h08e118c0 /* 0x1b18 */; - 1735: data_o = 32'h28a33882 /* 0x1b1c */; - 1736: data_o = 32'hdb5ccb7d /* 0x1b20 */; - 1737: data_o = 32'hfb1eeb3f /* 0x1b24 */; - 1738: data_o = 32'h9bd88bf9 /* 0x1b28 */; - 1739: data_o = 32'hbb9aabbb /* 0x1b2c */; - 1740: data_o = 32'h5a544a75 /* 0x1b30 */; - 1741: data_o = 32'h7a166a37 /* 0x1b34 */; - 1742: data_o = 32'h1ad00af1 /* 0x1b38 */; - 1743: data_o = 32'h3a922ab3 /* 0x1b3c */; - 1744: data_o = 32'hed0ffd2e /* 0x1b40 */; - 1745: data_o = 32'hcd4ddd6c /* 0x1b44 */; - 1746: data_o = 32'had8bbdaa /* 0x1b48 */; - 1747: data_o = 32'h8dc99de8 /* 0x1b4c */; - 1748: data_o = 32'h6c077c26 /* 0x1b50 */; - 1749: data_o = 32'h4c455c64 /* 0x1b54 */; - 1750: data_o = 32'h2c833ca2 /* 0x1b58 */; - 1751: data_o = 32'h0cc11ce0 /* 0x1b5c */; - 1752: data_o = 32'hff3eef1f /* 0x1b60 */; - 1753: data_o = 32'hdf7ccf5d /* 0x1b64 */; - 1754: data_o = 32'hbfbaaf9b /* 0x1b68 */; - 1755: data_o = 32'h9ff88fd9 /* 0x1b6c */; - 1756: data_o = 32'h7e366e17 /* 0x1b70 */; - 1757: data_o = 32'h5e744e55 /* 0x1b74 */; - 1758: data_o = 32'h3eb22e93 /* 0x1b78 */; - 1759: data_o = 32'h1ef00ed1 /* 0x1b7c */; - 1760: data_o = 32'h36241200 /* 0x1b80 */; - 1761: data_o = 32'h7e6c5a48 /* 0x1b84 */; - 1762: data_o = 32'ha6b48290 /* 0x1b88 */; - 1763: data_o = 32'heefccad8 /* 0x1b8c */; - 1764: data_o = 32'h04162032 /* 0x1b90 */; - 1765: data_o = 32'h4c5e687a /* 0x1b94 */; - 1766: data_o = 32'h9486b0a2 /* 0x1b98 */; - 1767: data_o = 32'hdccef8ea /* 0x1b9c */; - 1768: data_o = 32'h52407664 /* 0x1ba0 */; - 1769: data_o = 32'h1a083e2c /* 0x1ba4 */; - 1770: data_o = 32'hc2d0e6f4 /* 0x1ba8 */; - 1771: data_o = 32'h8a98aebc /* 0x1bac */; - 1772: data_o = 32'h60724456 /* 0x1bb0 */; - 1773: data_o = 32'h283a0c1e /* 0x1bb4 */; - 1774: data_o = 32'hf0e2d4c6 /* 0x1bb8 */; - 1775: data_o = 32'hb8aa9c8e /* 0x1bbc */; - 1776: data_o = 32'hfeecdac8 /* 0x1bc0 */; - 1777: data_o = 32'hb6a49280 /* 0x1bc4 */; - 1778: data_o = 32'h6e7c4a58 /* 0x1bc8 */; - 1779: data_o = 32'h26340210 /* 0x1bcc */; - 1780: data_o = 32'hccdee8fa /* 0x1bd0 */; - 1781: data_o = 32'h8496a0b2 /* 0x1bd4 */; - 1782: data_o = 32'h5c4e786a /* 0x1bd8 */; - 1783: data_o = 32'h14063022 /* 0x1bdc */; - 1784: data_o = 32'h9a88beac /* 0x1be0 */; - 1785: data_o = 32'hd2c0f6e4 /* 0x1be4 */; - 1786: data_o = 32'h0a182e3c /* 0x1be8 */; - 1787: data_o = 32'h42506674 /* 0x1bec */; - 1788: data_o = 32'ha8ba8c9e /* 0x1bf0 */; - 1789: data_o = 32'he0f2c4d6 /* 0x1bf4 */; - 1790: data_o = 32'h382a1c0e /* 0x1bf8 */; - 1791: data_o = 32'h70625446 /* 0x1bfc */; - 1792: data_o = 32'hb4a69082 /* 0x1c00 */; - 1793: data_o = 32'hfceed8ca /* 0x1c04 */; - 1794: data_o = 32'h24360012 /* 0x1c08 */; - 1795: data_o = 32'h6c7e485a /* 0x1c0c */; - 1796: data_o = 32'h8694a2b0 /* 0x1c10 */; - 1797: data_o = 32'hcedceaf8 /* 0x1c14 */; - 1798: data_o = 32'h16043220 /* 0x1c18 */; - 1799: data_o = 32'h5e4c7a68 /* 0x1c1c */; - 1800: data_o = 32'hd0c2f4e6 /* 0x1c20 */; - 1801: data_o = 32'h988abcae /* 0x1c24 */; - 1802: data_o = 32'h40526476 /* 0x1c28 */; - 1803: data_o = 32'h081a2c3e /* 0x1c2c */; - 1804: data_o = 32'he2f0c6d4 /* 0x1c30 */; - 1805: data_o = 32'haab88e9c /* 0x1c34 */; - 1806: data_o = 32'h72605644 /* 0x1c38 */; - 1807: data_o = 32'h3a281e0c /* 0x1c3c */; - 1808: data_o = 32'h7c6e584a /* 0x1c40 */; - 1809: data_o = 32'h34261002 /* 0x1c44 */; - 1810: data_o = 32'hecfec8da /* 0x1c48 */; - 1811: data_o = 32'ha4b68092 /* 0x1c4c */; - 1812: data_o = 32'h4e5c6a78 /* 0x1c50 */; - 1813: data_o = 32'h06142230 /* 0x1c54 */; - 1814: data_o = 32'hdeccfae8 /* 0x1c58 */; - 1815: data_o = 32'h9684b2a0 /* 0x1c5c */; - 1816: data_o = 32'h180a3c2e /* 0x1c60 */; - 1817: data_o = 32'h50427466 /* 0x1c64 */; - 1818: data_o = 32'h889aacbe /* 0x1c68 */; - 1819: data_o = 32'hc0d2e4f6 /* 0x1c6c */; - 1820: data_o = 32'h2a380e1c /* 0x1c70 */; - 1821: data_o = 32'h62704654 /* 0x1c74 */; - 1822: data_o = 32'hbaa89e8c /* 0x1c78 */; - 1823: data_o = 32'hf2e0d6c4 /* 0x1c7c */; - 1824: data_o = 32'h00000001 /* 0x1c80 */; - 1825: data_o = 32'h00000000 /* 0x1c84 */; - 1826: data_o = 32'h00000001 /* 0x1c88 */; - 1827: data_o = 32'h00000000 /* 0x1c8c */; - 1828: data_o = 32'h00000002 /* 0x1c90 */; + 1609: data_o = 32'hdad86e46 /* 0x1924 */; + 1610: data_o = 32'h0107971b /* 0x1928 */; + 1611: data_o = 32'h16978f5d /* 0x192c */; + 1612: data_o = 32'h27010100 /* 0x1930 */; + 1613: data_o = 32'h6d268693 /* 0x1934 */; + 1614: data_o = 32'h6741de98 /* 0x1938 */; + 1615: data_o = 32'h17178e59 /* 0x193c */; + 1616: data_o = 32'h07130100 /* 0x1940 */; + 1617: data_o = 32'hdf506c27 /* 0x1944 */; + 1618: data_o = 32'h0107e7b3 /* 0x1948 */; + 1619: data_o = 32'h01001717 /* 0x194c */; + 1620: data_o = 32'h07132781 /* 0x1950 */; + 1621: data_o = 32'hc33c6b47 /* 0x1954 */; + 1622: data_o = 32'h01001797 /* 0x1958 */; + 1623: data_o = 32'h6a878793 /* 0x195c */; + 1624: data_o = 32'h17974b98 /* 0x1960 */; + 1625: data_o = 32'h87930100 /* 0x1964 */; + 1626: data_o = 32'h671369e7 /* 0x1968 */; + 1627: data_o = 32'hf5170017 /* 0x196c */; + 1628: data_o = 32'hcb98ffff /* 0x1970 */; + 1629: data_o = 32'h0513102c /* 0x1974 */; + 1630: data_o = 32'hbbd9ac45 /* 0x1978 */; + 1631: data_o = 32'h70e67446 /* 0x197c */; + 1632: data_o = 32'h790674a6 /* 0x1980 */; + 1633: data_o = 32'h610969e6 /* 0x1984 */; + 1634: data_o = 32'he4bfe06f /* 0x1988 */; + 1635: data_o = 32'h00000000 /* 0x198c */; + 1636: data_o = 32'h10210000 /* 0x1990 */; + 1637: data_o = 32'h30632042 /* 0x1994 */; + 1638: data_o = 32'h50a54084 /* 0x1998 */; + 1639: data_o = 32'h70e760c6 /* 0x199c */; + 1640: data_o = 32'h91298108 /* 0x19a0 */; + 1641: data_o = 32'hb16ba14a /* 0x19a4 */; + 1642: data_o = 32'hd1adc18c /* 0x19a8 */; + 1643: data_o = 32'hf1efe1ce /* 0x19ac */; + 1644: data_o = 32'h02101231 /* 0x19b0 */; + 1645: data_o = 32'h22523273 /* 0x19b4 */; + 1646: data_o = 32'h429452b5 /* 0x19b8 */; + 1647: data_o = 32'h62d672f7 /* 0x19bc */; + 1648: data_o = 32'h83189339 /* 0x19c0 */; + 1649: data_o = 32'ha35ab37b /* 0x19c4 */; + 1650: data_o = 32'hc39cd3bd /* 0x19c8 */; + 1651: data_o = 32'he3def3ff /* 0x19cc */; + 1652: data_o = 32'h34432462 /* 0x19d0 */; + 1653: data_o = 32'h14010420 /* 0x19d4 */; + 1654: data_o = 32'h74c764e6 /* 0x19d8 */; + 1655: data_o = 32'h548544a4 /* 0x19dc */; + 1656: data_o = 32'hb54ba56a /* 0x19e0 */; + 1657: data_o = 32'h95098528 /* 0x19e4 */; + 1658: data_o = 32'hf5cfe5ee /* 0x19e8 */; + 1659: data_o = 32'hd58dc5ac /* 0x19ec */; + 1660: data_o = 32'h26723653 /* 0x19f0 */; + 1661: data_o = 32'h06301611 /* 0x19f4 */; + 1662: data_o = 32'h66f676d7 /* 0x19f8 */; + 1663: data_o = 32'h46b45695 /* 0x19fc */; + 1664: data_o = 32'ha77ab75b /* 0x1a00 */; + 1665: data_o = 32'h87389719 /* 0x1a04 */; + 1666: data_o = 32'he7fef7df /* 0x1a08 */; + 1667: data_o = 32'hc7bcd79d /* 0x1a0c */; + 1668: data_o = 32'h58e548c4 /* 0x1a10 */; + 1669: data_o = 32'h78a76886 /* 0x1a14 */; + 1670: data_o = 32'h18610840 /* 0x1a18 */; + 1671: data_o = 32'h38232802 /* 0x1a1c */; + 1672: data_o = 32'hd9edc9cc /* 0x1a20 */; + 1673: data_o = 32'hf9afe98e /* 0x1a24 */; + 1674: data_o = 32'h99698948 /* 0x1a28 */; + 1675: data_o = 32'hb92ba90a /* 0x1a2c */; + 1676: data_o = 32'h4ad45af5 /* 0x1a30 */; + 1677: data_o = 32'h6a967ab7 /* 0x1a34 */; + 1678: data_o = 32'h0a501a71 /* 0x1a38 */; + 1679: data_o = 32'h2a123a33 /* 0x1a3c */; + 1680: data_o = 32'hcbdcdbfd /* 0x1a40 */; + 1681: data_o = 32'heb9efbbf /* 0x1a44 */; + 1682: data_o = 32'h8b589b79 /* 0x1a48 */; + 1683: data_o = 32'hab1abb3b /* 0x1a4c */; + 1684: data_o = 32'h7c876ca6 /* 0x1a50 */; + 1685: data_o = 32'h5cc54ce4 /* 0x1a54 */; + 1686: data_o = 32'h3c032c22 /* 0x1a58 */; + 1687: data_o = 32'h1c410c60 /* 0x1a5c */; + 1688: data_o = 32'hfd8fedae /* 0x1a60 */; + 1689: data_o = 32'hddcdcdec /* 0x1a64 */; + 1690: data_o = 32'hbd0bad2a /* 0x1a68 */; + 1691: data_o = 32'h9d498d68 /* 0x1a6c */; + 1692: data_o = 32'h6eb67e97 /* 0x1a70 */; + 1693: data_o = 32'h4ef45ed5 /* 0x1a74 */; + 1694: data_o = 32'h2e323e13 /* 0x1a78 */; + 1695: data_o = 32'h0e701e51 /* 0x1a7c */; + 1696: data_o = 32'hefbeff9f /* 0x1a80 */; + 1697: data_o = 32'hcffcdfdd /* 0x1a84 */; + 1698: data_o = 32'haf3abf1b /* 0x1a88 */; + 1699: data_o = 32'h8f789f59 /* 0x1a8c */; + 1700: data_o = 32'h81a99188 /* 0x1a90 */; + 1701: data_o = 32'ha1ebb1ca /* 0x1a94 */; + 1702: data_o = 32'hc12dd10c /* 0x1a98 */; + 1703: data_o = 32'he16ff14e /* 0x1a9c */; + 1704: data_o = 32'h00a11080 /* 0x1aa0 */; + 1705: data_o = 32'h20e330c2 /* 0x1aa4 */; + 1706: data_o = 32'h40255004 /* 0x1aa8 */; + 1707: data_o = 32'h60677046 /* 0x1aac */; + 1708: data_o = 32'h939883b9 /* 0x1ab0 */; + 1709: data_o = 32'hb3daa3fb /* 0x1ab4 */; + 1710: data_o = 32'hd31cc33d /* 0x1ab8 */; + 1711: data_o = 32'hf35ee37f /* 0x1abc */; + 1712: data_o = 32'h129002b1 /* 0x1ac0 */; + 1713: data_o = 32'h32d222f3 /* 0x1ac4 */; + 1714: data_o = 32'h52144235 /* 0x1ac8 */; + 1715: data_o = 32'h72566277 /* 0x1acc */; + 1716: data_o = 32'ha5cbb5ea /* 0x1ad0 */; + 1717: data_o = 32'h858995a8 /* 0x1ad4 */; + 1718: data_o = 32'he54ff56e /* 0x1ad8 */; + 1719: data_o = 32'hc50dd52c /* 0x1adc */; + 1720: data_o = 32'h24c334e2 /* 0x1ae0 */; + 1721: data_o = 32'h048114a0 /* 0x1ae4 */; + 1722: data_o = 32'h64477466 /* 0x1ae8 */; + 1723: data_o = 32'h44055424 /* 0x1aec */; + 1724: data_o = 32'hb7faa7db /* 0x1af0 */; + 1725: data_o = 32'h97b88799 /* 0x1af4 */; + 1726: data_o = 32'hf77ee75f /* 0x1af8 */; + 1727: data_o = 32'hd73cc71d /* 0x1afc */; + 1728: data_o = 32'h36f226d3 /* 0x1b00 */; + 1729: data_o = 32'h16b00691 /* 0x1b04 */; + 1730: data_o = 32'h76766657 /* 0x1b08 */; + 1731: data_o = 32'h56344615 /* 0x1b0c */; + 1732: data_o = 32'hc96dd94c /* 0x1b10 */; + 1733: data_o = 32'he92ff90e /* 0x1b14 */; + 1734: data_o = 32'h89e999c8 /* 0x1b18 */; + 1735: data_o = 32'ha9abb98a /* 0x1b1c */; + 1736: data_o = 32'h48655844 /* 0x1b20 */; + 1737: data_o = 32'h68277806 /* 0x1b24 */; + 1738: data_o = 32'h08e118c0 /* 0x1b28 */; + 1739: data_o = 32'h28a33882 /* 0x1b2c */; + 1740: data_o = 32'hdb5ccb7d /* 0x1b30 */; + 1741: data_o = 32'hfb1eeb3f /* 0x1b34 */; + 1742: data_o = 32'h9bd88bf9 /* 0x1b38 */; + 1743: data_o = 32'hbb9aabbb /* 0x1b3c */; + 1744: data_o = 32'h5a544a75 /* 0x1b40 */; + 1745: data_o = 32'h7a166a37 /* 0x1b44 */; + 1746: data_o = 32'h1ad00af1 /* 0x1b48 */; + 1747: data_o = 32'h3a922ab3 /* 0x1b4c */; + 1748: data_o = 32'hed0ffd2e /* 0x1b50 */; + 1749: data_o = 32'hcd4ddd6c /* 0x1b54 */; + 1750: data_o = 32'had8bbdaa /* 0x1b58 */; + 1751: data_o = 32'h8dc99de8 /* 0x1b5c */; + 1752: data_o = 32'h6c077c26 /* 0x1b60 */; + 1753: data_o = 32'h4c455c64 /* 0x1b64 */; + 1754: data_o = 32'h2c833ca2 /* 0x1b68 */; + 1755: data_o = 32'h0cc11ce0 /* 0x1b6c */; + 1756: data_o = 32'hff3eef1f /* 0x1b70 */; + 1757: data_o = 32'hdf7ccf5d /* 0x1b74 */; + 1758: data_o = 32'hbfbaaf9b /* 0x1b78 */; + 1759: data_o = 32'h9ff88fd9 /* 0x1b7c */; + 1760: data_o = 32'h7e366e17 /* 0x1b80 */; + 1761: data_o = 32'h5e744e55 /* 0x1b84 */; + 1762: data_o = 32'h3eb22e93 /* 0x1b88 */; + 1763: data_o = 32'h1ef00ed1 /* 0x1b8c */; + 1764: data_o = 32'h36241200 /* 0x1b90 */; + 1765: data_o = 32'h7e6c5a48 /* 0x1b94 */; + 1766: data_o = 32'ha6b48290 /* 0x1b98 */; + 1767: data_o = 32'heefccad8 /* 0x1b9c */; + 1768: data_o = 32'h04162032 /* 0x1ba0 */; + 1769: data_o = 32'h4c5e687a /* 0x1ba4 */; + 1770: data_o = 32'h9486b0a2 /* 0x1ba8 */; + 1771: data_o = 32'hdccef8ea /* 0x1bac */; + 1772: data_o = 32'h52407664 /* 0x1bb0 */; + 1773: data_o = 32'h1a083e2c /* 0x1bb4 */; + 1774: data_o = 32'hc2d0e6f4 /* 0x1bb8 */; + 1775: data_o = 32'h8a98aebc /* 0x1bbc */; + 1776: data_o = 32'h60724456 /* 0x1bc0 */; + 1777: data_o = 32'h283a0c1e /* 0x1bc4 */; + 1778: data_o = 32'hf0e2d4c6 /* 0x1bc8 */; + 1779: data_o = 32'hb8aa9c8e /* 0x1bcc */; + 1780: data_o = 32'hfeecdac8 /* 0x1bd0 */; + 1781: data_o = 32'hb6a49280 /* 0x1bd4 */; + 1782: data_o = 32'h6e7c4a58 /* 0x1bd8 */; + 1783: data_o = 32'h26340210 /* 0x1bdc */; + 1784: data_o = 32'hccdee8fa /* 0x1be0 */; + 1785: data_o = 32'h8496a0b2 /* 0x1be4 */; + 1786: data_o = 32'h5c4e786a /* 0x1be8 */; + 1787: data_o = 32'h14063022 /* 0x1bec */; + 1788: data_o = 32'h9a88beac /* 0x1bf0 */; + 1789: data_o = 32'hd2c0f6e4 /* 0x1bf4 */; + 1790: data_o = 32'h0a182e3c /* 0x1bf8 */; + 1791: data_o = 32'h42506674 /* 0x1bfc */; + 1792: data_o = 32'ha8ba8c9e /* 0x1c00 */; + 1793: data_o = 32'he0f2c4d6 /* 0x1c04 */; + 1794: data_o = 32'h382a1c0e /* 0x1c08 */; + 1795: data_o = 32'h70625446 /* 0x1c0c */; + 1796: data_o = 32'hb4a69082 /* 0x1c10 */; + 1797: data_o = 32'hfceed8ca /* 0x1c14 */; + 1798: data_o = 32'h24360012 /* 0x1c18 */; + 1799: data_o = 32'h6c7e485a /* 0x1c1c */; + 1800: data_o = 32'h8694a2b0 /* 0x1c20 */; + 1801: data_o = 32'hcedceaf8 /* 0x1c24 */; + 1802: data_o = 32'h16043220 /* 0x1c28 */; + 1803: data_o = 32'h5e4c7a68 /* 0x1c2c */; + 1804: data_o = 32'hd0c2f4e6 /* 0x1c30 */; + 1805: data_o = 32'h988abcae /* 0x1c34 */; + 1806: data_o = 32'h40526476 /* 0x1c38 */; + 1807: data_o = 32'h081a2c3e /* 0x1c3c */; + 1808: data_o = 32'he2f0c6d4 /* 0x1c40 */; + 1809: data_o = 32'haab88e9c /* 0x1c44 */; + 1810: data_o = 32'h72605644 /* 0x1c48 */; + 1811: data_o = 32'h3a281e0c /* 0x1c4c */; + 1812: data_o = 32'h7c6e584a /* 0x1c50 */; + 1813: data_o = 32'h34261002 /* 0x1c54 */; + 1814: data_o = 32'hecfec8da /* 0x1c58 */; + 1815: data_o = 32'ha4b68092 /* 0x1c5c */; + 1816: data_o = 32'h4e5c6a78 /* 0x1c60 */; + 1817: data_o = 32'h06142230 /* 0x1c64 */; + 1818: data_o = 32'hdeccfae8 /* 0x1c68 */; + 1819: data_o = 32'h9684b2a0 /* 0x1c6c */; + 1820: data_o = 32'h180a3c2e /* 0x1c70 */; + 1821: data_o = 32'h50427466 /* 0x1c74 */; + 1822: data_o = 32'h889aacbe /* 0x1c78 */; + 1823: data_o = 32'hc0d2e4f6 /* 0x1c7c */; + 1824: data_o = 32'h2a380e1c /* 0x1c80 */; + 1825: data_o = 32'h62704654 /* 0x1c84 */; + 1826: data_o = 32'hbaa89e8c /* 0x1c88 */; + 1827: data_o = 32'hf2e0d6c4 /* 0x1c8c */; + 1828: data_o = 32'h00000001 /* 0x1c90 */; 1829: data_o = 32'h00000000 /* 0x1c94 */; - 1830: data_o = 32'h00000005 /* 0x1c98 */; + 1830: data_o = 32'h00000001 /* 0x1c98 */; 1831: data_o = 32'h00000000 /* 0x1c9c */; - 1832: data_o = 32'h00000005 /* 0x1ca0 */; + 1832: data_o = 32'h00000002 /* 0x1ca0 */; 1833: data_o = 32'h00000000 /* 0x1ca4 */; - 1834: data_o = 32'h20494645 /* 0x1ca8 */; - 1835: data_o = 32'h54524150 /* 0x1cac */; - 1836: data_o = 32'h0269b26a /* 0x1cb0 */; - 1837: data_o = 32'h4ce4fd95 /* 0x1cb4 */; - 1838: data_o = 32'h1494cf98 /* 0x1cb8 */; - 1839: data_o = 32'h622c4101 /* 0x1cbc */; - 1840: data_o = 32'h01000048 /* 0x1cc0 */; - 1841: data_o = 32'h000087aa /* 0x1cc4 */; - 1842: data_o = 32'h00004069 /* 0x1cc8 */; - 1843: data_o = 32'h00007700 /* 0x1ccc */; - 1844: data_o = 32'h02000050 /* 0x1cd0 */; - 1845: data_o = 32'h00001500 /* 0x1cd4 */; - 1846: data_o = 32'h00000000 /* 0x1cd8 */; - 1847: data_o = 32'h00000000 /* 0x1cdc */; - 1848: data_o = 32'h00000000 /* 0x1ce0 */; - 1849: data_o = 32'h00000000 /* 0x1ce4 */; + 1834: data_o = 32'h00000005 /* 0x1ca8 */; + 1835: data_o = 32'h00000000 /* 0x1cac */; + 1836: data_o = 32'h00000005 /* 0x1cb0 */; + 1837: data_o = 32'h00000000 /* 0x1cb4 */; + 1838: data_o = 32'h20494645 /* 0x1cb8 */; + 1839: data_o = 32'h54524150 /* 0x1cbc */; + 1840: data_o = 32'h0269b26a /* 0x1cc0 */; + 1841: data_o = 32'h4ce4fd95 /* 0x1cc4 */; + 1842: data_o = 32'h1494cf98 /* 0x1cc8 */; + 1843: data_o = 32'h622c4101 /* 0x1ccc */; + 1844: data_o = 32'h01000048 /* 0x1cd0 */; + 1845: data_o = 32'h000087aa /* 0x1cd4 */; + 1846: data_o = 32'h00004069 /* 0x1cd8 */; + 1847: data_o = 32'h00007700 /* 0x1cdc */; + 1848: data_o = 32'h02000050 /* 0x1ce0 */; + 1849: data_o = 32'h00001500 /* 0x1ce4 */; 1850: data_o = 32'h00000000 /* 0x1ce8 */; 1851: data_o = 32'h00000000 /* 0x1cec */; 1852: data_o = 32'h00000000 /* 0x1cf0 */; diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 691952b0..721f8737 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -103,6 +103,7 @@ package cheshire_pkg; // Reg parameters dw_bt RegMaxReadTxns; dw_bt RegMaxWriteTxns; + bit AxiToRegCut; aw_bt RegAmoNumCuts; bit RegAmoPostCut; bit RegAdaptMemCut; @@ -136,6 +137,10 @@ package cheshire_pkg; bit Clic; bit IrqRouter; bit BusErr; + bit HmrUnit; + bit Cva6DMR; + bit Cva6DMRFixed; + bit RapidRecovery; // Parameters for Debug Module jtag_idcode_t DbgIdCode; dw_bt DbgMaxReqs; @@ -148,6 +153,9 @@ package cheshire_pkg; shrt_bt LlcSetAssoc; shrt_bt LlcNumLines; shrt_bt LlcNumBlocks; + bit LlcCachePartition; + shrt_bt LlcMaxPartition; + axi_llc_pkg::algorithm_e LlcRemapHash; dw_bt LlcMaxReadTxns; dw_bt LlcMaxWriteTxns; aw_bt LlcAmoNumCuts; @@ -155,6 +163,8 @@ package cheshire_pkg; bit LlcOutConnect; doub_bt LlcOutRegionStart; doub_bt LlcOutRegionEnd; + dw_bt LlcUserMsb; + dw_bt LlcUserLsb; // Parameters for VGA byte_bt VgaRedWidth; byte_bt VgaGreenWidth; @@ -266,14 +276,18 @@ package cheshire_pkg; endfunction // Static addresses (defined here only if multiply used) - localparam doub_bt AmDbg = 'h0000_0000; // Base of AXI peripherals - localparam doub_bt AmBrom = 'h0200_0000; // Base of reg peripherals - localparam doub_bt AmRegs = 'h0300_0000; - localparam doub_bt AmLlc = 'h0300_1000; - localparam doub_bt AmSlink = 'h0300_6000; - localparam doub_bt AmBusErr = 'h0300_8000; - localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top - localparam doub_bt AmClic = 'h0800_0000; + localparam doub_bt AmDbg = 'h0000_0000; // Base of AXI peripherals + localparam doub_bt AmBrom = 'h0200_0000; // Base of reg peripherals + localparam doub_bt AmRegs = 'h0300_0000; + localparam doub_bt AmLlc = 'h0300_1000; + localparam doub_bt AmSlink = 'h0300_6000; + localparam doub_bt AmBusErr = 'h0300_8000; + // Address 0x0300_A000 is occupied by the tagger in Carfield. + // Removed for the moment to isolate the contribution of this PR. + // Leaving this comment and the free scope to keep track. + localparam doub_bt AmHmrUnit = 'h0300_B000; + localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top + localparam doub_bt AmClic = 'h0800_0000; // Static masks localparam doub_bt AmSpmBaseUncached = 'h1400_0000; @@ -388,6 +402,7 @@ package cheshire_pkg; aw_bt irq_router; aw_bt [2**MaxCoresWidth-1:0] bus_err; aw_bt [2**MaxCoresWidth-1:0] clic; + aw_bt hmr_unit; aw_bt ext_base; aw_bt num_out; aw_bt num_rules; @@ -416,6 +431,9 @@ package cheshire_pkg; if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40, AmBusErr + (j+1)*'h40}; end + if (cfg.HmrUnit) begin + i++; ret.hmr_unit = i; r++; ret.map[r] = '{i, AmHmrUnit, AmHmrUnit+'h400}; + end i++; r++; ret.ext_base = i; ret.num_out = i + cfg.RegExtNumSlv; @@ -580,6 +598,7 @@ package cheshire_pkg; AxiUserDefault : 0, RegMaxReadTxns : 8, RegMaxWriteTxns : 8, + AxiToRegCut : 0, RegAmoNumCuts : 1, RegAmoPostCut : 1, RegAdaptMemCut : 1, @@ -598,6 +617,10 @@ package cheshire_pkg; Clic : 0, IrqRouter : 0, BusErr : 1, + HmrUnit : 1, + Cva6DMR : 1, + Cva6DMRFixed : 0, + RapidRecovery : 0, // Debug DbgIdCode : CheshireIdCode, DbgMaxReqs : 4, @@ -617,6 +640,12 @@ package cheshire_pkg; LlcOutConnect : 1, LlcOutRegionStart : 'h8000_0000, LlcOutRegionEnd : 'h1_0000_0000, + LlcUserMsb : 0, + LlcUserLsb : 0, + // LLC Partitioning + LlcCachePartition : 0, + LlcMaxPartition : 0, + LlcRemapHash : axi_llc_pkg::Modulo, // VGA: RGB332 VgaRedWidth : 3, VgaGreenWidth : 3, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index c8c7f077..e643d1a6 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -503,10 +503,15 @@ module cheshire_soc import cheshire_pkg::*; #( .SetAssociativity ( Cfg.LlcSetAssoc ), .NumLines ( Cfg.LlcNumLines ), .NumBlocks ( Cfg.LlcNumBlocks ), + .CachePartition ( Cfg.LlcCachePartition ), + .MaxPartition ( Cfg.LlcMaxPartition ), + .RemapHash ( Cfg.LlcRemapHash ), .AxiIdWidth ( AxiSlvIdWidth ), .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiUserIdMsb ( Cfg.LlcUserMsb ), + .AxiUserIdLsb ( Cfg.LlcUserLsb ), .slv_req_t ( axi_slv_req_t ), .slv_resp_t ( axi_slv_rsp_t ), .mst_req_t ( axi_ext_llc_req_t ), @@ -578,50 +583,70 @@ module cheshire_soc import cheshire_pkg::*; #( assign intr.intn.bus_err.cores = core_bus_err_intr_comb; - for (genvar i = 0; i < NumIntHarts; i++) begin : gen_cva6_cores - axi_cva6_req_t core_out_req, core_ur_req; - axi_cva6_rsp_t core_out_rsp, core_ur_rsp; - - // CLIC interface - logic clic_irq_valid, clic_irq_ready; - logic clic_irq_kill_req, clic_irq_kill_ack; - logic clic_irq_shv; - logic [$clog2(NumClicIntrs)-1:0] clic_irq_id; - logic [7:0] clic_irq_level; - riscv::priv_lvl_t clic_irq_priv; - - cva6 #( - .CVA6Cfg ( Cva6Cfg ), - .axi_ar_chan_t ( axi_cva6_ar_chan_t ), - .axi_aw_chan_t ( axi_cva6_aw_chan_t ), - .axi_w_chan_t ( axi_cva6_w_chan_t ), - .b_chan_t ( axi_cva6_b_chan_t ), - .r_chan_t ( axi_cva6_r_chan_t ), - .noc_req_t ( axi_cva6_req_t ), - .noc_resp_t ( axi_cva6_rsp_t ) - ) i_core_cva6 ( - .clk_i, - .rst_ni, - .boot_addr_i ( BootAddr ), - .hart_id_i ( 64'(i) ), - .irq_i ( xeip[i] ), - .ipi_i ( msip[i] ), - .time_irq_i ( mtip[i] ), - .debug_req_i ( dbg_int_req[i] ), - .clic_irq_valid_i ( clic_irq_valid ), - .clic_irq_id_i ( clic_irq_id ), - .clic_irq_level_i ( clic_irq_level ), - .clic_irq_priv_i ( clic_irq_priv ), - .clic_irq_shv_i ( clic_irq_shv ), - .clic_irq_ready_o ( clic_irq_ready ), - .clic_kill_req_i ( clic_irq_kill_req ), - .clic_kill_ack_o ( clic_irq_kill_ack ), - .rvfi_probes_o ( ), - .cvxif_req_o ( ), - .cvxif_resp_i ( '0 ), - .noc_req_o ( core_out_req ), - .noc_resp_i ( core_out_rsp ) - ); + axi_cva6_req_t [NumIntHarts-1:0] core_out_req, core_ur_req; + axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp, core_ur_rsp; + + // CLIC interface + logic [NumIntHarts-1:0] clic_irq_valid, clic_irq_ready; + logic [NumIntHarts-1:0] clic_irq_kill_req, clic_irq_kill_ack; + logic [NumIntHarts-1:0] clic_irq_shv; + logic [NumIntHarts-1:0] clic_irq_v; + logic [NumIntHarts-1:0] [$clog2(NumClicIntrs)-1:0] clic_irq_id; + logic [NumIntHarts-1:0] [7:0] clic_irq_level; + logic [NumIntHarts-1:0] [5:0] clic_irq_vsid; + riscv::priv_lvl_t [NumIntHarts-1:0] clic_irq_priv; + + reg_req_t reg_out_core_req; + reg_rsp_t reg_out_core_rsp; + + // Additional register intergace bus for the HMR unit configuration + if (Cfg.HmrUnit == 1) begin : gen_hmr_unit_reg_intf + assign reg_out_core_req = reg_out_req[RegOut.hmr_unit]; + assign reg_out_rsp[RegOut.hmr_unit] = reg_out_core_rsp; + end else begin : gen_no_hmr_unit_reg_intf + assign reg_out_core_req = '0; + end + + cva6_wrap #( + .Cfg ( Cfg ), + .Cva6Cfg ( Cva6Cfg ), + .NumHarts ( NumIntHarts ), + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ), + .axi_ar_chan_t ( axi_cva6_ar_chan_t ), + .axi_aw_chan_t ( axi_cva6_aw_chan_t ), + .axi_w_chan_t ( axi_cva6_w_chan_t ), + .b_chan_t ( axi_cva6_b_chan_t ), + .r_chan_t ( axi_cva6_r_chan_t ), + .axi_req_t ( axi_cva6_req_t ), + .axi_rsp_t ( axi_cva6_rsp_t ) + ) i_core_wrap ( + .clk_i ( clk_i ), + .rstn_i ( rst_ni ), + .bootaddress_i ( BootAddr ), + .hart_id_i ( '0 ), + .harts_sync_req_i ( reg_reg2hw.harts_sync.q ), + .irq_i ( xeip[NumIntHarts-1:0] ), + .ipi_i ( msip[NumIntHarts-1:0] ), + .time_irq_i ( mtip[NumIntHarts-1:0] ), + .debug_req_i ( dbg_int_req ), + .clic_irq_valid_i ( clic_irq_valid ), + .clic_irq_id_i ( clic_irq_id[NumIntHarts-1:0] ), + .clic_irq_level_i ( clic_irq_level[NumIntHarts-1:0] ), + .clic_irq_priv_i ( clic_irq_priv ), + .clic_irq_shv_i ( clic_irq_shv ), + .clic_irq_v_i ( clic_irq_v ), + .clic_irq_vsid_i ( clic_irq_vsid[NumIntHarts-1:0] ), + .clic_irq_ready_o ( clic_irq_ready ), + .clic_kill_req_i ( clic_irq_kill_req ), + .clic_kill_ack_o ( clic_irq_kill_ack ), + .reg_req_i ( reg_out_core_req ), + .reg_rsp_o ( reg_out_core_rsp ), + .axi_req_o ( core_out_req ), + .axi_rsp_i ( core_out_rsp ) + ); + + for (genvar i = 0; i < NumIntHarts; i++) begin : gen_core_surroundings if (Cfg.BusErr) begin : gen_cva6_bus_err axi_err_unit_wrap #( @@ -639,9 +664,9 @@ module cheshire_soc import cheshire_pkg::*; #( ) i_cva6_bus_err ( .clk_i, .rst_ni, - .testmode_i ( test_mode_i ), - .axi_req_i ( core_out_req ), - .axi_rsp_i ( core_out_rsp ), + .testmode_i ( test_mode_i ), + .axi_req_i ( core_out_req[i] ), + .axi_rsp_i ( core_out_rsp[i] ), .err_irq_o ( core_bus_err_intr[i] ), .reg_req_i ( reg_out_req[RegOut.bus_err[RegBusErrCoresBase+i]] ), .reg_rsp_o ( reg_out_rsp[RegOut.bus_err[RegBusErrCoresBase+i]] ) @@ -677,39 +702,43 @@ module cheshire_soc import cheshire_pkg::*; #( .rst_ni, .reg_req_i ( reg_out_req[RegOut.clic[i]] ), .reg_rsp_o ( reg_out_rsp[RegOut.clic[i]] ), - .intr_src_i ( clic_intr ), - .irq_valid_o ( clic_irq_valid ), - .irq_ready_i ( clic_irq_ready ), - .irq_id_o ( clic_irq_id ), - .irq_level_o ( clic_irq_level ), - .irq_shv_o ( clic_irq_shv ), - .irq_priv_o ( clic_irq_priv ), - .irq_kill_req_o ( clic_irq_kill_req ), - .irq_kill_ack_i ( clic_irq_kill_ack ) + .intr_src_i ( clic_intr ), + .irq_valid_o ( clic_irq_valid[i] ), + .irq_ready_i ( clic_irq_ready[i] ), + .irq_id_o ( clic_irq_id[i] ), + .irq_level_o ( clic_irq_level[i] ), + .irq_shv_o ( clic_irq_shv[i] ), + .irq_priv_o ( clic_irq_priv[i] ), + .irq_v_o ( clic_irq_v[i] ), + .irq_vsid_o ( clic_irq_vsid[i] ), + .irq_kill_req_o ( clic_irq_kill_req[i] ), + .irq_kill_ack_i ( clic_irq_kill_ack[i] ) ); end else begin : gen_no_clic - assign clic_irq_valid = '0; - assign clic_irq_id = '0; - assign clic_irq_level = '0; - assign clic_irq_shv = '0; - assign clic_irq_priv = riscv::priv_lvl_t'(0); - assign clic_irq_kill_req = '0; + assign clic_irq_valid[i] = '0; + assign clic_irq_id[i] = '0; + assign clic_irq_level[i] = '0; + assign clic_irq_shv[i] = '0; + assign clic_irq_priv[i] = riscv::priv_lvl_t'(0); + assign clic_irq_v[i] = '0; + assign clic_irq_vsid[i] = '0; + assign clic_irq_kill_req[i] = '0; end // Map user to AMO domain as we are an atomics-capable master. // Within the provided AMO user range, we count up from the provided core AMO offset. always_comb begin - core_ur_req = core_out_req; - core_ur_req.aw.user = Cfg.AxiUserDefault; - core_ur_req.ar.user = Cfg.AxiUserDefault; - core_ur_req.w.user = Cfg.AxiUserDefault; - core_ur_req.aw.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; - core_ur_req.ar.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; - core_ur_req.w.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; - core_out_rsp = core_ur_rsp; + core_ur_req[i] = core_out_req[i]; + core_ur_req[i].aw.user = Cfg.AxiUserDefault; + core_ur_req[i].ar.user = Cfg.AxiUserDefault; + core_ur_req[i].w.user = Cfg.AxiUserDefault; + core_ur_req[i].aw.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; + core_ur_req[i].ar.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; + core_ur_req[i].w.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; + core_out_rsp[i] = core_ur_rsp[i]; end // CVA6's ID encoding is wasteful; remap it statically pack into available bits @@ -733,8 +762,8 @@ module cheshire_soc import cheshire_pkg::*; #( ) i_axi_id_serialize ( .clk_i, .rst_ni, - .slv_req_i ( core_ur_req ), - .slv_resp_o ( core_ur_rsp ), + .slv_req_i ( core_ur_req[i] ), + .slv_resp_o ( core_ur_rsp[i] ), .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] ) ); @@ -976,6 +1005,7 @@ module cheshire_soc import cheshire_pkg::*; #( ///////////////////// cheshire_reg_pkg::cheshire_hw2reg_t reg_hw2reg; + cheshire_reg_pkg::cheshire_reg2hw_t reg_reg2hw; assign reg_hw2reg = '{ boot_mode : boot_mode_i, @@ -1014,6 +1044,7 @@ module cheshire_soc import cheshire_pkg::*; #( .reg_req_i ( reg_out_req[RegOut.regs] ), .reg_rsp_o ( reg_out_rsp[RegOut.regs] ), .hw2reg ( reg_hw2reg ), + .reg2hw ( reg_reg2hw ), .devmode_i ( 1'b1 ) ); diff --git a/hw/cva6_wrap.sv b/hw/cva6_wrap.sv new file mode 100644 index 00000000..fb1affbf --- /dev/null +++ b/hw/cva6_wrap.sv @@ -0,0 +1,225 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +`include "axi/assign.svh" + +module cva6_wrap #( + parameter cheshire_pkg::cheshire_cfg_t Cfg = '0, + parameter config_pkg::cva6_cfg_t Cva6Cfg = cva6_config_pkg::cva6_cfg, + parameter int unsigned NumHarts = 1, + parameter int unsigned ClicNumIrqs = $clog2(Cva6Cfg.CLICNumInterruptSrc), + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter type axi_ar_chan_t = logic, + parameter type axi_aw_chan_t = logic, + parameter type axi_w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type r_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic +)( + input logic clk_i, + input logic rstn_i, + input cheshire_pkg::doub_bt bootaddress_i, + input cheshire_pkg::doub_bt hart_id_i, + input logic [31:0] harts_sync_req_i, + input logic [NumHarts-1:0][1:0] irq_i, + input logic [NumHarts-1:0] ipi_i, + input logic [NumHarts-1:0] time_irq_i, + input logic [NumHarts-1:0] debug_req_i, + input logic [NumHarts-1:0] clic_irq_valid_i, + input logic [NumHarts-1:0][ClicNumIrqs-1:0] clic_irq_id_i, + input logic [NumHarts-1:0][7:0] clic_irq_level_i, + input riscv::priv_lvl_t [NumHarts-1:0] clic_irq_priv_i, + input logic [NumHarts-1:0] clic_irq_v_i, + input logic [NumHarts-1:0][5:0] clic_irq_vsid_i, + input logic [NumHarts-1:0] clic_irq_shv_i, + output logic [NumHarts-1:0] clic_irq_ready_o, + input logic [NumHarts-1:0] clic_kill_req_i, + output logic [NumHarts-1:0] clic_kill_ack_o, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + output axi_req_t [NumHarts-1:0] axi_req_o, + input axi_rsp_t [NumHarts-1:0] axi_rsp_i +); + +typedef struct packed { + // cheshire_pkg::doub_bt bootaddress; + cheshire_pkg::doub_bt hart_id; + logic [1:0] irq; + logic ipi; + logic time_irq; + logic debug_req; + logic clic_irq_valid; + logic [ClicNumIrqs-1:0] clic_irq_id; + logic [7:0] clic_irq_level; + riscv::priv_lvl_t clic_irq_priv; + logic clic_irq_v; + logic [5:0] clic_irq_vsid; + logic clic_irq_shv; + logic clic_kill_req; + axi_rsp_t axi_rsp; +} cva6_inputs_t; + +typedef struct packed { + logic clic_irq_ready; + logic clic_kill_ack; + axi_req_t axi_req; +} cva6_outputs_t; + +logic cores_sync; +logic [NumHarts-1:0] core_setback; +cva6_inputs_t [NumHarts-1:0] sys2hmr, hmr2core; +cva6_outputs_t [NumHarts-1:0] hmr2sys, core2hmr; +cheshire_pkg::doub_bt [NumHarts-1:0] core_bootaddress; + +for (genvar i = 0; i < NumHarts; i++) begin: gen_cva6_cores + // Bind system inputs to HMR. + // assign sys2hmr[i].bootaddress = bootaddress_i; // TODO: differentiate? + assign sys2hmr[i].hart_id = hart_id_i + 64'(i); + assign sys2hmr[i].irq = irq_i[i]; + assign sys2hmr[i].ipi = ipi_i[i]; + assign sys2hmr[i].time_irq = time_irq_i[i]; + assign sys2hmr[i].debug_req = debug_req_i[i]; + assign sys2hmr[i].clic_irq_valid = clic_irq_valid_i[i]; + assign sys2hmr[i].clic_irq_id = clic_irq_id_i[i]; + assign sys2hmr[i].clic_irq_level = clic_irq_level_i[i]; + assign sys2hmr[i].clic_irq_priv = clic_irq_priv_i[i]; + assign sys2hmr[i].clic_irq_v = clic_irq_v_i[i]; + assign sys2hmr[i].clic_irq_vsid = clic_irq_vsid_i[i]; + assign sys2hmr[i].clic_irq_shv = clic_irq_shv_i[i]; + assign sys2hmr[i].clic_kill_req = clic_kill_req_i[i]; + `AXI_ASSIGN_RESP_STRUCT(sys2hmr[i].axi_rsp, axi_rsp_i[i]); + + // Bind HMR outputs to system. + assign clic_irq_ready_o[i] = hmr2sys[i].clic_irq_ready; + assign clic_kill_ack_o[i] = hmr2sys[i].clic_kill_ack; + `AXI_ASSIGN_REQ_STRUCT(axi_req_o[i], hmr2sys[i].axi_req); + + cva6 #( + .CVA6Cfg ( Cva6Cfg ), + .axi_ar_chan_t ( axi_ar_chan_t ), + .axi_aw_chan_t ( axi_aw_chan_t ), + .axi_w_chan_t ( axi_w_chan_t ), + .b_chan_t ( b_chan_t ), + .r_chan_t ( r_chan_t ), + .noc_req_t ( axi_req_t ), + .noc_resp_t ( axi_rsp_t ) + ) i_core_cva6 ( + .clk_i ( clk_i ), + .rst_ni ( rstn_i ), + .clear_i ( core_setback[i] ), + // .boot_addr_i ( hmr2core[i].bootaddress ), + .boot_addr_i ( core_bootaddress[i] ), + .hart_id_i ( hmr2core[i].hart_id ), + .irq_i ( hmr2core[i].irq ), + .ipi_i ( hmr2core[i].ipi ), + .time_irq_i ( hmr2core[i].time_irq ), + .debug_req_i ( hmr2core[i].debug_req ), + .clic_irq_valid_i ( hmr2core[i].clic_irq_valid ), + .clic_irq_id_i ( hmr2core[i].clic_irq_id ), + .clic_irq_level_i ( hmr2core[i].clic_irq_level ), + .clic_irq_priv_i ( hmr2core[i].clic_irq_priv ), + .clic_irq_shv_i ( hmr2core[i].clic_irq_shv ), + // Clic support changed in CVA6, probably not all the features + // have already been merged + // .clic_irq_v_i ( hmr2core[i].clic_irq_v ), + // .clic_irq_vsid_i ( hmr2core[i].clic_irq_vsid ), + .clic_irq_ready_o ( core2hmr[i].clic_irq_ready ), + .clic_kill_req_i ( hmr2core[i].clic_kill_req ), + .clic_kill_ack_o ( core2hmr[i].clic_kill_ack ), + .rvfi_probes_o ( ), + .cvxif_req_o ( ), + .cvxif_resp_i ( '0 ), + .noc_req_o ( core2hmr[i].axi_req ), + .noc_resp_i ( hmr2core[i].axi_rsp ) + ); +end + +assign cores_sync = (harts_sync_req_i[NumHarts-1:0] == '1) ? 1'b1 : 1'b0; + +if (NumHarts > 1) begin: gen_multicore_hmr + hmr_unit #( + .NumCores ( NumHarts ), + .DMRSupported ( Cfg.Cva6DMR ), + .DMRFixed ( Cfg.Cva6DMRFixed ), // TODO: make configurable + .TMRSupported ( 0 ), + // .InterleaveGrps ( 0 ), + .RapidRecovery ( Cfg.RapidRecovery ), + .SeparateData ( 0 ), + .RfAddrWidth ( 5 ), + .SysDataWidth ( 64 ), + .all_inputs_t ( cva6_inputs_t ), // Inputs from the system to the HMR + .nominal_outputs_t ( cva6_outputs_t ), + // .core_backup_t ( '0 ), // TODO + // .bus_outputs_t ( '0 ), // TODO + .reg_req_t ( reg_req_t ), // TODO + .reg_rsp_t ( reg_rsp_t ), // TODO + .rapid_recovery_t ( rapid_recovery_pkg::rapid_recovery_t ) // TODO + ) i_cva6_hmr ( + .clk_i ( clk_i ), + .rst_ni ( rstn_i ), + .reg_request_i ( reg_req_i ), + .reg_response_o ( reg_rsp_o ), + .tmr_failure_o ( /* Not used */), + .tmr_error_o ( /* Not used */), // Should this not be NumTMRCores? or NumCores? + .tmr_resynch_req_o ( /* Not used */), + .tmr_sw_synch_req_o ( /* Not used */), + .tmr_cores_synch_i ( '0 ), // Not used + + // DMR signals + .dmr_failure_o ( /* TODO */ ), + .dmr_error_o ( /* TODO */ ), // Should this not be NumDMRCores? or NumCores? + .dmr_resynch_req_o ( /* TODO */ ), + .dmr_sw_synch_req_o ( /* TODO */ ), + // In PULP cluster we connected this to the event unit + // to receive information about cores' synchronization. + // How should we handle it here? We could use Cheshire's + // registers to write that a synchronization completed + // succesfully (??) + .dmr_cores_synch_i ( cores_sync ), + + // Rapid recovery buses + .rapid_recovery_o ( /* TODO */ ), + .core_backup_i ( '0 ), // TODO + + .sys_bootaddress_i ( bootaddress_i ), + .sys_inputs_i ( sys2hmr ), + .sys_nominal_outputs_o ( hmr2sys ), + .sys_bus_outputs_o ( ), + // CVA6 boot does not rely on fetch enable. + .sys_fetch_en_i ( '1 ), + .enable_bus_vote_i ( '0 ), // TODO? + + .core_bootaddress_o ( core_bootaddress ), + .core_setback_o ( core_setback ), + .core_inputs_o ( hmr2core ), + .core_nominal_outputs_i ( core2hmr ), + .core_bus_outputs_i ( '0 ) // TODO? + ); + + /* We temporarily hardcode this for permanent lockstep.*/ + // assign hmr2sys[NumHarts-1] = '0; +end else begin : gen_single_core_binding + assign core_bootaddress = bootaddress_i; + assign core_setback = '0; + assign hmr2core = sys2hmr ; + assign hmr2sys = core2hmr; + + // reg error slave when HMR not supported + reg_err_slv #( + .DW ( 32 ), + .ERR_VAL ( 32'hBADCAB1E ), + .req_t ( reg_req_t ), + .rsp_t ( reg_rsp_t ) + ) i_cva6_hmr_err_slv ( + .req_i ( reg_req_i ), + .rsp_o ( reg_rsp_o ) + ); + +end + +endmodule: cva6_wrap diff --git a/hw/regs/cheshire_reg_pkg.sv b/hw/regs/cheshire_reg_pkg.sv index e2a44ade..bd43166c 100644 --- a/hw/regs/cheshire_reg_pkg.sv +++ b/hw/regs/cheshire_reg_pkg.sv @@ -13,6 +13,11 @@ package cheshire_reg_pkg; // Typedefs for registers // //////////////////////////// + typedef struct packed { + logic [31:0] q; + logic qe; + } cheshire_reg2hw_harts_sync_reg_t; + typedef struct packed { logic [1:0] d; } cheshire_hw2reg_boot_mode_reg_t; @@ -87,6 +92,11 @@ package cheshire_reg_pkg; } blue_width; } cheshire_hw2reg_vga_params_reg_t; + // Register -> HW type + typedef struct packed { + cheshire_reg2hw_harts_sync_reg_t harts_sync; // [32:0] + } cheshire_reg2hw_t; + // HW -> register type typedef struct packed { cheshire_hw2reg_boot_mode_reg_t boot_mode; // [166:165] @@ -122,6 +132,7 @@ package cheshire_reg_pkg; parameter logic [BlockAw-1:0] CHESHIRE_HW_FEATURES_OFFSET = 7'h 50; parameter logic [BlockAw-1:0] CHESHIRE_LLC_SIZE_OFFSET = 7'h 54; parameter logic [BlockAw-1:0] CHESHIRE_VGA_PARAMS_OFFSET = 7'h 58; + parameter logic [BlockAw-1:0] CHESHIRE_HARTS_SYNC_OFFSET = 7'h 5c; // Reset values for hwext registers and their fields parameter logic [1:0] CHESHIRE_BOOT_MODE_RESVAL = 2'h 0; @@ -156,11 +167,12 @@ package cheshire_reg_pkg; CHESHIRE_NUM_INT_HARTS, CHESHIRE_HW_FEATURES, CHESHIRE_LLC_SIZE, - CHESHIRE_VGA_PARAMS + CHESHIRE_VGA_PARAMS, + CHESHIRE_HARTS_SYNC } cheshire_id_e; // Register width information to check illegal writes - parameter logic [3:0] CHESHIRE_PERMIT [23] = '{ + parameter logic [3:0] CHESHIRE_PERMIT [24] = '{ 4'b 1111, // index[ 0] CHESHIRE_SCRATCH_0 4'b 1111, // index[ 1] CHESHIRE_SCRATCH_1 4'b 1111, // index[ 2] CHESHIRE_SCRATCH_2 @@ -183,7 +195,8 @@ package cheshire_reg_pkg; 4'b 1111, // index[19] CHESHIRE_NUM_INT_HARTS 4'b 0011, // index[20] CHESHIRE_HW_FEATURES 4'b 1111, // index[21] CHESHIRE_LLC_SIZE - 4'b 0111 // index[22] CHESHIRE_VGA_PARAMS + 4'b 0111, // index[22] CHESHIRE_VGA_PARAMS + 4'b 1111 // index[23] CHESHIRE_HARTS_SYNC }; endpackage diff --git a/hw/regs/cheshire_reg_top.sv b/hw/regs/cheshire_reg_top.sv index bd9f2e27..e39fe687 100644 --- a/hw/regs/cheshire_reg_top.sv +++ b/hw/regs/cheshire_reg_top.sv @@ -17,6 +17,7 @@ module cheshire_reg_top #( input reg_req_t reg_req_i, output reg_rsp_t reg_rsp_o, // To HW + output cheshire_reg_pkg::cheshire_reg2hw_t reg2hw, // Write input cheshire_reg_pkg::cheshire_hw2reg_t hw2reg, // Read @@ -157,6 +158,9 @@ module cheshire_reg_top #( logic vga_params_green_width_re; logic [7:0] vga_params_blue_width_qs; logic vga_params_blue_width_re; + logic [31:0] harts_sync_qs; + logic [31:0] harts_sync_wd; + logic harts_sync_we; // Register instances @@ -917,9 +921,36 @@ module cheshire_reg_top #( ); + // R[harts_sync]: V(False) + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_harts_sync ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (harts_sync_we), + .wd (harts_sync_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), - logic [22:0] addr_hit; + // to internal hardware + .qe (reg2hw.harts_sync.qe), + .q (reg2hw.harts_sync.q ), + + // to register interface (read) + .qs (harts_sync_qs) + ); + + + + + logic [23:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CHESHIRE_SCRATCH_0_OFFSET); @@ -945,6 +976,7 @@ module cheshire_reg_top #( addr_hit[20] = (reg_addr == CHESHIRE_HW_FEATURES_OFFSET); addr_hit[21] = (reg_addr == CHESHIRE_LLC_SIZE_OFFSET); addr_hit[22] = (reg_addr == CHESHIRE_VGA_PARAMS_OFFSET); + addr_hit[23] = (reg_addr == CHESHIRE_HARTS_SYNC_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -974,7 +1006,8 @@ module cheshire_reg_top #( (addr_hit[19] & (|(CHESHIRE_PERMIT[19] & ~reg_be))) | (addr_hit[20] & (|(CHESHIRE_PERMIT[20] & ~reg_be))) | (addr_hit[21] & (|(CHESHIRE_PERMIT[21] & ~reg_be))) | - (addr_hit[22] & (|(CHESHIRE_PERMIT[22] & ~reg_be))))); + (addr_hit[22] & (|(CHESHIRE_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(CHESHIRE_PERMIT[23] & ~reg_be))))); end assign scratch_0_we = addr_hit[0] & reg_we & !reg_error; @@ -1067,6 +1100,9 @@ module cheshire_reg_top #( assign vga_params_blue_width_re = addr_hit[22] & reg_re & !reg_error; + assign harts_sync_we = addr_hit[23] & reg_we & !reg_error; + assign harts_sync_wd = reg_wdata[31:0]; + // Read data return always_comb begin reg_rdata_next = '0; @@ -1177,6 +1213,10 @@ module cheshire_reg_top #( reg_rdata_next[23:16] = vga_params_blue_width_qs; end + addr_hit[23]: begin + reg_rdata_next[31:0] = harts_sync_qs; + end + default: begin reg_rdata_next = '1; end @@ -1206,6 +1246,7 @@ module cheshire_reg_top_intf input logic rst_ni, REG_BUS.in regbus_slave, // To HW + output cheshire_reg_pkg::cheshire_reg2hw_t reg2hw, // Write input cheshire_reg_pkg::cheshire_hw2reg_t hw2reg, // Read // Config input devmode_i // If 1, explicit error return for unmapped register access @@ -1239,6 +1280,7 @@ module cheshire_reg_top_intf .rst_ni, .reg_req_i(s_reg_req), .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write .hw2reg, // Read .devmode_i ); diff --git a/hw/regs/cheshire_regs.hjson b/hw/regs/cheshire_regs.hjson index e551a945..364dd45e 100644 --- a/hw/regs/cheshire_regs.hjson +++ b/hw/regs/cheshire_regs.hjson @@ -131,5 +131,14 @@ ] } + { name: "harts_sync" + desc: "Available harts' synchronization request." + swaccess: "rw" + hwaccess: "hro" + hwqe: "true" + fields: [ + { bits: "31:0", name: "hart_sync", desc: "Harts sync request." } + ] + } ] } diff --git a/sw/include/cheshire_io.h b/sw/include/cheshire_io.h new file mode 100644 index 00000000..ab1e8cc6 --- /dev/null +++ b/sw/include/cheshire_io.h @@ -0,0 +1,11 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "dif/uart.h" +#include "util.h" +#include "params.h" + +void cheshire_init_io(); diff --git a/sw/include/dif/uart.h b/sw/include/dif/uart.h index 134ec814..15a4731c 100644 --- a/sw/include/dif/uart.h +++ b/sw/include/dif/uart.h @@ -42,6 +42,8 @@ uint8_t uart_read(void *uart_base); void uart_read_str(void *uart_base, void *dst, uint64_t len); // Default UART provides console -void _putchar(char byte); +void uart_open(); + +void _putchar(char character); char _getchar(); diff --git a/sw/include/init.h b/sw/include/init.h new file mode 100644 index 00000000..fbbc7a60 --- /dev/null +++ b/sw/include/init.h @@ -0,0 +1,7 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "cheshire_io.h" + +void soc_init(); diff --git a/sw/include/params.h b/sw/include/params.h index 5477689e..0af5e9b6 100644 --- a/sw/include/params.h +++ b/sw/include/params.h @@ -23,6 +23,7 @@ extern void *__base_gpio; extern void *__base_slink; extern void *__base_vga; extern void *__base_clint; +extern void *__base_hmr; extern void *__base_plic; extern void *__base_dma; extern void *__base_axirt; diff --git a/sw/include/regs/axi_llc.h b/sw/include/regs/axi_llc.h index 79a2c7c4..a1b6f589 100644 --- a/sw/include/regs/axi_llc.h +++ b/sw/include/regs/axi_llc.h @@ -72,6 +72,74 @@ extern "C" { #define AXI_LLC_BIST_STATUS_REG_OFFSET 0x48 #define AXI_LLC_BIST_STATUS_DONE_BIT 0 +// Index-based Partition Flush Configuration [31:0] (lower 32 bit) +#define AXI_LLC_CFG_FLUSH_PARTITION_LOW_REG_OFFSET 0x4c + +// Index-based Partition Flush Configuration [63:32] (upper 32 bit) +#define AXI_LLC_CFG_FLUSH_PARTITION_HIGH_REG_OFFSET 0x50 + +// Index-based Partition Configuration [31:0] (lower 32 bit) (common +// parameters) +#define AXI_LLC_CFG_SET_PARTITION_LOW_LOW_FIELD_WIDTH 32 +#define AXI_LLC_CFG_SET_PARTITION_LOW_LOW_FIELDS_PER_REG 1 +#define AXI_LLC_CFG_SET_PARTITION_LOW_MULTIREG_COUNT 2 + +// Index-based Partition Configuration [31:0] (lower 32 bit) +#define AXI_LLC_CFG_SET_PARTITION_LOW_0_REG_OFFSET 0x54 + +// Index-based Partition Configuration [31:0] (lower 32 bit) +#define AXI_LLC_CFG_SET_PARTITION_LOW_1_REG_OFFSET 0x58 + +// Index-based Partition Configuration [63:32] (higher 32 bit) (common +// parameters) +#define AXI_LLC_CFG_SET_PARTITION_HIGH_HIGH_FIELD_WIDTH 32 +#define AXI_LLC_CFG_SET_PARTITION_HIGH_HIGH_FIELDS_PER_REG 1 +#define AXI_LLC_CFG_SET_PARTITION_HIGH_MULTIREG_COUNT 2 + +// Index-based Partition Configuration [63:32] (higher 32 bit) +#define AXI_LLC_CFG_SET_PARTITION_HIGH_0_REG_OFFSET 0x5c + +// Index-based Partition Configuration [63:32] (higher 32 bit) +#define AXI_LLC_CFG_SET_PARTITION_HIGH_1_REG_OFFSET 0x60 + +// Commit the set partition configuration +#define AXI_LLC_COMMIT_PARTITION_CFG_REG_OFFSET 0x64 +#define AXI_LLC_COMMIT_PARTITION_CFG_COMMIT_BIT 0 + +// Index-based Flushed Flag (lower 32 bit) (common parameters) +#define AXI_LLC_FLUSHED_SET_LOW_LOW_FIELD_WIDTH 32 +#define AXI_LLC_FLUSHED_SET_LOW_LOW_FIELDS_PER_REG 1 +#define AXI_LLC_FLUSHED_SET_LOW_MULTIREG_COUNT 4 + +// Index-based Flushed Flag (lower 32 bit) +#define AXI_LLC_FLUSHED_SET_LOW_0_REG_OFFSET 0x6c + +// Index-based Flushed Flag (lower 32 bit) +#define AXI_LLC_FLUSHED_SET_LOW_1_REG_OFFSET 0x70 + +// Index-based Flushed Flag (lower 32 bit) +#define AXI_LLC_FLUSHED_SET_LOW_2_REG_OFFSET 0x74 + +// Index-based Flushed Flag (lower 32 bit) +#define AXI_LLC_FLUSHED_SET_LOW_3_REG_OFFSET 0x78 + +// Index-based Flushed Flag (upper 32 bit) (common parameters) +#define AXI_LLC_FLUSHED_SET_HIGH_HIGH_FIELD_WIDTH 32 +#define AXI_LLC_FLUSHED_SET_HIGH_HIGH_FIELDS_PER_REG 1 +#define AXI_LLC_FLUSHED_SET_HIGH_MULTIREG_COUNT 4 + +// Index-based Flushed Flag (upper 32 bit) +#define AXI_LLC_FLUSHED_SET_HIGH_0_REG_OFFSET 0x7c + +// Index-based Flushed Flag (upper 32 bit) +#define AXI_LLC_FLUSHED_SET_HIGH_1_REG_OFFSET 0x80 + +// Index-based Flushed Flag (upper 32 bit) +#define AXI_LLC_FLUSHED_SET_HIGH_2_REG_OFFSET 0x84 + +// Index-based Flushed Flag (upper 32 bit) +#define AXI_LLC_FLUSHED_SET_HIGH_3_REG_OFFSET 0x88 + #ifdef __cplusplus } // extern "C" #endif diff --git a/sw/include/regs/cheshire.h b/sw/include/regs/cheshire.h index 542d621e..0483f2b5 100644 --- a/sw/include/regs/cheshire.h +++ b/sw/include/regs/cheshire.h @@ -123,6 +123,9 @@ extern "C" { #define CHESHIRE_VGA_PARAMS_BLUE_WIDTH_FIELD \ ((bitfield_field32_t) { .mask = CHESHIRE_VGA_PARAMS_BLUE_WIDTH_MASK, .index = CHESHIRE_VGA_PARAMS_BLUE_WIDTH_OFFSET }) +// Available harts' synchronization request. +#define CHESHIRE_HARTS_SYNC_REG_OFFSET 0x5c + #ifdef __cplusplus } // extern "C" #endif diff --git a/sw/include/smp.h b/sw/include/smp.h index d13d8757..b6a26f33 100644 --- a/sw/include/smp.h +++ b/sw/include/smp.h @@ -17,11 +17,27 @@ csrr reg2, mhartid; \ bne reg1, reg2, 2f +// If the two harts are lockestepped at reset or peremanetly locked, we must +// see a single Hart ID at boot. Otherwise we see NUM_INT_HARTS. +// The procedure to set/unset the CLINT MSIP registers for the two harts is +// the following: +// 0. We read the number of physical harts (NUM_INT_HARTS) in reg3. +// 1. We read the DMR enabled register from the HMR unit in reg2. +// 2. We compute the number of virtual harts: +// 2a. If reg2=1, we divide NUM_INT_HARTS by 2 (reg3 >> reg2). +// 2b. If reg2=0, we divide NUM_INT_HARTS by 1 (reg3 >> reg2). +// 3. We multiply the number of virtual harts by 4: +// 3a. If reg2=1, the result is 4 (reg3 << 2). +// 3b. If reg2=0, the result is 8 (reg3 << 2). +// 4. Consequently, we compute the MSIP offset to access the CLINT. #define smp_resume(reg1, reg2, reg3) \ la reg1, __base_clint; \ la reg3, __base_regs; \ lw reg3, 76(reg3); /* regs.NUM_INT_HARTS */ \ - slli reg3, reg3, 2; \ + la reg2, __base_hmr; \ + lw reg2, 512(reg2); /* DMR en/dis */ \ + srl reg3, reg3, reg2; \ + sll reg3, reg3, 2; \ add reg3, reg1, reg3; \ 1:; \ li reg2, 1; \ diff --git a/sw/include/util.h b/sw/include/util.h index 46dcedb2..a1a0c9e5 100644 --- a/sw/include/util.h +++ b/sw/include/util.h @@ -80,3 +80,33 @@ static inline void *gprw(void *gp) { if (!(cond)) return (ret); #define MIN(a, b) (((a) <= (b)) ? (a) : (b)) + +// Read hart ID +static inline unsigned int hart_id() { + int hart_id; + asm volatile("csrr %0, mhartid" : "=r"(hart_id) :); + return hart_id; +} + +// Disable data caches +static inline void disable_dcache() { + asm volatile("csrrwi x0, 0x701, 0x0 \n\t" : : : "memory"); +} + +// Enable data caches +static inline void enable_dcache() { + asm volatile("csrrwi x0, 0x701, 0x1 \n\t" : : : "memory"); +} + +// The following is for future DMR support +// Wake up sleeping hart using CLINT +// static inline void wakeup_hart(unsigned int hart_id) { +// *reg32(&__base_clint, 0x4*hart_id) = 0x1; +// *reg32(&__base_clint, 0x4*hart_id) = 0x0; +// } + +// Write synchronization request in dedicated register +// static inline void sync_req(unsigned int hart_id){ +// uint32_t sync_reg = *reg32(&__base_regs, CHESHIRE_HARTS_SYNC_REG_OFFSET); +// *reg32(&__base_regs, CHESHIRE_HARTS_SYNC_REG_OFFSET) = sync_reg | (0x1 << hart_id); +// } diff --git a/sw/lib/cheshire_io.c b/sw/lib/cheshire_io.c new file mode 100644 index 00000000..1d723032 --- /dev/null +++ b/sw/lib/cheshire_io.c @@ -0,0 +1,19 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Yvan Tortorella +// +// Library containing IO init/close functions. + +#include "cheshire_io.h" + +void cheshire_init_io() { + // Initialize UART first + uart_open(); + + // Initialize other IOs + // . + // . + // . +}; diff --git a/sw/lib/crt0.S b/sw/lib/crt0.S index ebf372ad..073fc181 100644 --- a/sw/lib/crt0.S +++ b/sw/lib/crt0.S @@ -15,8 +15,10 @@ _start: csrrc x0, mstatus, 10 // Park SMP harts - csrr t0, mhartid - beqz t0, 2f + // csrr t0, mhartid + // beqz t0, 2f + // All harts continue. + beq t0, t0, 2f 1: wfi j 1b @@ -110,8 +112,18 @@ _fp_init: // Set FS state to "Clean" csrrc x0, mstatus, t1 + // Non SMP Hart initializes the SoC + // SMP Harts jump to main + csrr t0, mhartid + beqz t0, _soc_init + j _program_start + +_soc_init: + // Init SoC, than jump to main + jal x1, soc_init - // Full fence, then jump to main +_program_start: + // Full fence, then go to main fence call main diff --git a/sw/lib/dif/uart.c b/sw/lib/dif/uart.c index 09cef30a..a190af0c 100644 --- a/sw/lib/dif/uart.c +++ b/sw/lib/dif/uart.c @@ -5,6 +5,8 @@ // Nils Wistoff // Paul Scheffler +#include "regs/cheshire.h" +#include "dif/clint.h" #include "dif/uart.h" #include "util.h" #include "params.h" @@ -64,8 +66,15 @@ void uart_read_str(void *uart_base, void *dst, uint64_t len) { } // Default UART provides console -void _putchar(char byte) { - uart_write(&__base_uart, byte); +void uart_open() { + uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET); + uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500); + uart_init(&__base_uart, reset_freq, 115200); +}; + +void _putchar(char character) { + uart_write(&__base_uart, character); + uart_write_flush(&__base_uart); }; char _getchar() { diff --git a/sw/lib/init.c b/sw/lib/init.c new file mode 100644 index 00000000..a0f5dc02 --- /dev/null +++ b/sw/lib/init.c @@ -0,0 +1,14 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Yvan Tortorella +// +// Library containing general SoC init/close functions. + +#include "init.h" + +void soc_init() { + // IO initialization + cheshire_init_io(); +}; diff --git a/sw/link/common.ldh b/sw/link/common.ldh index b9bdb43c..f3a9a40c 100644 --- a/sw/link/common.ldh +++ b/sw/link/common.ldh @@ -43,6 +43,7 @@ SECTIONS { __base_gpio = 0x03005000; __base_slink = 0x03006000; __base_vga = 0x03007000; + __base_hmr = 0x0300B000; __base_plic = 0x04000000; __base_spm = ORIGIN(spm); __base_dram = ORIGIN(dram); From 995fe63d4c37dd5aed5fbf3b9b2a0307ff140aa1 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 5 Mar 2024 14:41:29 +0100 Subject: [PATCH 02/48] Add clic virtualization and LLC partitioning. --- cheshire.mk | 17 ++++++++++++++ hw/bootrom/cheshire_bootrom.S | 1 + hw/cheshire_pkg.sv | 20 +++++++++++++---- hw/cheshire_soc.sv | 42 +++++++++++++++++++++++++++++++---- 4 files changed, 72 insertions(+), 8 deletions(-) diff --git a/cheshire.mk b/cheshire.mk index e0fc089d..c96c73e7 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -11,11 +11,16 @@ BENDER ?= bender VLOG_ARGS ?= -suppress 2583 -suppress 13314 VSIM ?= vsim +MAXPARTITION ?= 16 +CACHE_PARTITION ?= 1 + + # Define used paths (prefixed to avoid name conflicts) CHS_ROOT ?= $(shell $(BENDER) path cheshire) CHS_REG_DIR := $(shell $(BENDER) path register_interface) CHS_SLINK_DIR := $(shell $(BENDER) path serial_link) CHS_LLC_DIR := $(shell $(BENDER) path axi_llc) +CHS_TAGGER_DIR := $(shell $(BENDER) path tagger) # Define paths used in dependencies OTPROOT := $(shell $(BENDER) path opentitan_peripherals) @@ -103,12 +108,24 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson cp $< $(dir $@)/src/regs/serial_link_single_channel.hjson flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs BENDER="$(BENDER)" && touch $@ +# LLC partitioning configuration +$(CHS_LLC_DIR)/.generated: + $(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXPARTITION=$(MAXPARTITION) CACHE_PARTITION=$(CACHE_PARTITION) regs + @touch $@ + +# Tagger configuration +$(CHS_TAGGER_DIR)/.generated: + $(MAKE) -C $(CHS_TAGGER_DIR) REGWIDTH=32 MAXPARTITION=$(MAXPARTITION) PATID_LEN=5 regs + @touch $@ + CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv CHS_HW_ALL += $(CLINTROOT)/.generated CHS_HW_ALL += $(OTPROOT)/.generated CHS_HW_ALL += $(AXIRTROOT)/.generated CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated +CHS_HW_ALL += $(CHS_LLC_DIR)/.generated +CHS_HW_ALL += $(CHS_TAGGER_DIR)/.generated ##################### # Generate Boot ROM # diff --git a/hw/bootrom/cheshire_bootrom.S b/hw/bootrom/cheshire_bootrom.S index 22bbeb9f..89e388da 100644 --- a/hw/bootrom/cheshire_bootrom.S +++ b/hw/bootrom/cheshire_bootrom.S @@ -62,6 +62,7 @@ _start: andi t0, t0, 2 // regs.HW_FEATURES.llc beqz t0, _prom_check_run la t0, __base_llc + // Only configure half of LLC as SPM _wait_llc_bist: lw t1, 72(t0) // llc.BIST_STATUS_DONE_BIT beqz t1, _wait_llc_bist diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 721f8737..a53c9c7f 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -85,6 +85,11 @@ package cheshire_pkg; byte_bt NumExtOutIntrTgts; shrt_bt NumExtOutIntrs; shrt_bt ClicIntCtlBits; + bit ClicUseSMode; + bit ClicUseUMode; + bit ClicUseVsMode; + bit ClicUseVsModePrio; + byte_bt ClicNumVsCtxts; shrt_bt NumExtIntrSyncs; // AXI parameters aw_bt AddrWidth; @@ -282,9 +287,7 @@ package cheshire_pkg; localparam doub_bt AmLlc = 'h0300_1000; localparam doub_bt AmSlink = 'h0300_6000; localparam doub_bt AmBusErr = 'h0300_8000; - // Address 0x0300_A000 is occupied by the tagger in Carfield. - // Removed for the moment to isolate the contribution of this PR. - // Leaving this comment and the free scope to keep track. + localparam doub_bt AmTagger = 'h0300_A000; localparam doub_bt AmHmrUnit = 'h0300_B000; localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top localparam doub_bt AmClic = 'h0800_0000; @@ -402,6 +405,7 @@ package cheshire_pkg; aw_bt irq_router; aw_bt [2**MaxCoresWidth-1:0] bus_err; aw_bt [2**MaxCoresWidth-1:0] clic; + aw_bt [2**MaxCoresWidth-1:0] tagger; aw_bt hmr_unit; aw_bt ext_base; aw_bt num_out; @@ -431,6 +435,9 @@ package cheshire_pkg; if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40, AmBusErr + (j+1)*'h40}; end + if (cfg.LlcCachePartition) for (int j = 0; j < cfg.NumCores; j++) begin + i++; ret.tagger[j] = i; r++; ret.map[r] = '{i, AmTagger + j*'h100, AmTagger + (j+1)*'h100}; + end if (cfg.HmrUnit) begin i++; ret.hmr_unit = i; r++; ret.map[r] = '{i, AmHmrUnit, AmHmrUnit+'h400}; end @@ -583,11 +590,16 @@ package cheshire_pkg; NumExtOutIntrTgts : 0, NumExtOutIntrs : 0, ClicIntCtlBits : 8, + ClicUseSMode : 0, + ClicUseUMode : 0, + ClicUseVsMode : 0, + ClicUseVsModePrio : 0, + ClicNumVsCtxts : 0, NumExtIntrSyncs : 2, // Interconnect AddrWidth : 48, AxiDataWidth : 64, - AxiUserWidth : 2, // AMO(2) + AxiUserWidth : 2, // Convention: bit 0 for core(s), bit 1 for serial link AxiMstIdWidth : 2, AxiMaxMstTrans : 24, AxiMaxSlvTrans : 24, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index e643d1a6..5e2df83f 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -492,6 +492,7 @@ module cheshire_soc import cheshire_pkg::*; #( // This is necessary for routing in the LLC-internal interconnect. always_comb begin axi_llc_remap_req = axi_llc_cut_req; + if (axi_llc_cut_req.aw.addr & ~AmSpmRegionMask == AmSpmBaseUncached & ~AmSpmRegionMask) axi_llc_remap_req.aw.addr = AmSpm | (AmSpmRegionMask & axi_llc_cut_req.aw.addr); if (axi_llc_cut_req.ar.addr & ~AmSpmRegionMask == AmSpmBaseUncached & ~AmSpmRegionMask) @@ -583,6 +584,9 @@ module cheshire_soc import cheshire_pkg::*; #( assign intr.intn.bus_err.cores = core_bus_err_intr_comb; + axi_mst_req_t [AxiIn.num_in-1:0] tagger_req; + axi_mst_rsp_t [AxiIn.num_in-1:0] tagger_rsp; + axi_cva6_req_t [NumIntHarts-1:0] core_out_req, core_ur_req; axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp, core_ur_rsp; @@ -695,8 +699,11 @@ module cheshire_soc import cheshire_pkg::*; #( .INTCTLBITS ( Cfg.ClicIntCtlBits ), .reg_req_t ( reg_req_t ), .reg_rsp_t ( reg_rsp_t ), - .SSCLIC ( 1 ), - .USCLIC ( 0 ) + .SSCLIC ( Cfg.ClicUseSMode ), + .USCLIC ( Cfg.ClicUseUMode ), + .VSCLIC ( Cfg.ClicUseVsMode ), + .VSPRIO ( Cfg.ClicUseVsModePrio ), + .N_VSCTXTS ( Cfg.ClicNumVsCtxts ) ) i_clic ( .clk_i, .rst_ni, @@ -764,9 +771,36 @@ module cheshire_soc import cheshire_pkg::*; #( .rst_ni, .slv_req_i ( core_ur_req[i] ), .slv_resp_o ( core_ur_rsp[i] ), - .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), - .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] ) + .mst_req_o ( tagger_req[i] ), + .mst_resp_i ( tagger_rsp[i] ) ); + + if (Cfg.LlcCachePartition) begin : gen_tagger + tagger #( + .DATA_WIDTH ( Cfg.AxiDataWidth ), + .ADDR_WIDTH ( Cfg.AddrWidth ), + .MAXPARTITION ( Cfg.LlcMaxPartition ), + .AXI_USER_ID_MSB ( Cfg.LlcUserMsb ), + .AXI_USER_ID_LSB ( Cfg.LlcUserLsb ), + .TAGGER_GRAN ( 3 ), + .axi_req_t ( axi_mst_req_t ), + .axi_rsp_t ( axi_mst_rsp_t ), + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ) + ) i_tagger ( + .clk_i, + .rst_ni, + .slv_req_i ( tagger_req[i] ), + .slv_rsp_o ( tagger_rsp[i] ), + .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), + .mst_rsp_i ( axi_in_rsp[AxiIn.cores[i]] ), + .cfg_req_i ( reg_out_req[RegOut.tagger[i]] ), + .cfg_rsp_o ( reg_out_rsp[RegOut.tagger[i]] ) + ); + end else begin : gen_no_tagger + assign axi_in_req[AxiIn.cores[i]] = tagger_req[i]; + assign tagger_rsp[i] = axi_in_rsp[AxiIn.cores[i]]; + end end ///////////////////////// From a2c83d58975588f0c419e89e94852b8956241ac3 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 2 Mar 2024 18:22:17 +0100 Subject: [PATCH 03/48] Integrate HMR unit for CVA6 redundancy. --- hw/cheshire_pkg.sv | 8 +++----- hw/cheshire_soc.sv | 7 ++----- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index a53c9c7f..2c772b5f 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -287,7 +287,9 @@ package cheshire_pkg; localparam doub_bt AmLlc = 'h0300_1000; localparam doub_bt AmSlink = 'h0300_6000; localparam doub_bt AmBusErr = 'h0300_8000; - localparam doub_bt AmTagger = 'h0300_A000; + // Address 0x0300_A000 is occupied by the tagger in Carfield. + // Removed for the moment to isolate the contribution of this PR. + // Leaving this comment and the free scope to keep track. localparam doub_bt AmHmrUnit = 'h0300_B000; localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top localparam doub_bt AmClic = 'h0800_0000; @@ -405,7 +407,6 @@ package cheshire_pkg; aw_bt irq_router; aw_bt [2**MaxCoresWidth-1:0] bus_err; aw_bt [2**MaxCoresWidth-1:0] clic; - aw_bt [2**MaxCoresWidth-1:0] tagger; aw_bt hmr_unit; aw_bt ext_base; aw_bt num_out; @@ -435,9 +436,6 @@ package cheshire_pkg; if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40, AmBusErr + (j+1)*'h40}; end - if (cfg.LlcCachePartition) for (int j = 0; j < cfg.NumCores; j++) begin - i++; ret.tagger[j] = i; r++; ret.map[r] = '{i, AmTagger + j*'h100, AmTagger + (j+1)*'h100}; - end if (cfg.HmrUnit) begin i++; ret.hmr_unit = i; r++; ret.map[r] = '{i, AmHmrUnit, AmHmrUnit+'h400}; end diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 5e2df83f..7fca9eb5 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -584,9 +584,6 @@ module cheshire_soc import cheshire_pkg::*; #( assign intr.intn.bus_err.cores = core_bus_err_intr_comb; - axi_mst_req_t [AxiIn.num_in-1:0] tagger_req; - axi_mst_rsp_t [AxiIn.num_in-1:0] tagger_rsp; - axi_cva6_req_t [NumIntHarts-1:0] core_out_req, core_ur_req; axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp, core_ur_rsp; @@ -771,8 +768,8 @@ module cheshire_soc import cheshire_pkg::*; #( .rst_ni, .slv_req_i ( core_ur_req[i] ), .slv_resp_o ( core_ur_rsp[i] ), - .mst_req_o ( tagger_req[i] ), - .mst_resp_i ( tagger_rsp[i] ) + .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), + .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] ) ); if (Cfg.LlcCachePartition) begin : gen_tagger From 1b1afe14961f51c57b33bf6c620f0a7de0badf8e Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 5 Mar 2024 14:41:29 +0100 Subject: [PATCH 04/48] Add clic virtualization and LLC partitioning. --- hw/cheshire_pkg.sv | 8 +++++--- hw/cheshire_soc.sv | 7 +++++-- target/sim/src/vip_cheshire_soc.sv | 1 + 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 2c772b5f..a53c9c7f 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -287,9 +287,7 @@ package cheshire_pkg; localparam doub_bt AmLlc = 'h0300_1000; localparam doub_bt AmSlink = 'h0300_6000; localparam doub_bt AmBusErr = 'h0300_8000; - // Address 0x0300_A000 is occupied by the tagger in Carfield. - // Removed for the moment to isolate the contribution of this PR. - // Leaving this comment and the free scope to keep track. + localparam doub_bt AmTagger = 'h0300_A000; localparam doub_bt AmHmrUnit = 'h0300_B000; localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top localparam doub_bt AmClic = 'h0800_0000; @@ -407,6 +405,7 @@ package cheshire_pkg; aw_bt irq_router; aw_bt [2**MaxCoresWidth-1:0] bus_err; aw_bt [2**MaxCoresWidth-1:0] clic; + aw_bt [2**MaxCoresWidth-1:0] tagger; aw_bt hmr_unit; aw_bt ext_base; aw_bt num_out; @@ -436,6 +435,9 @@ package cheshire_pkg; if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40, AmBusErr + (j+1)*'h40}; end + if (cfg.LlcCachePartition) for (int j = 0; j < cfg.NumCores; j++) begin + i++; ret.tagger[j] = i; r++; ret.map[r] = '{i, AmTagger + j*'h100, AmTagger + (j+1)*'h100}; + end if (cfg.HmrUnit) begin i++; ret.hmr_unit = i; r++; ret.map[r] = '{i, AmHmrUnit, AmHmrUnit+'h400}; end diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 7fca9eb5..5e2df83f 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -584,6 +584,9 @@ module cheshire_soc import cheshire_pkg::*; #( assign intr.intn.bus_err.cores = core_bus_err_intr_comb; + axi_mst_req_t [AxiIn.num_in-1:0] tagger_req; + axi_mst_rsp_t [AxiIn.num_in-1:0] tagger_rsp; + axi_cva6_req_t [NumIntHarts-1:0] core_out_req, core_ur_req; axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp, core_ur_rsp; @@ -768,8 +771,8 @@ module cheshire_soc import cheshire_pkg::*; #( .rst_ni, .slv_req_i ( core_ur_req[i] ), .slv_resp_o ( core_ur_rsp[i] ), - .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), - .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] ) + .mst_req_o ( tagger_req[i] ), + .mst_resp_i ( tagger_rsp[i] ) ); if (Cfg.LlcCachePartition) begin : gen_tagger diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index cfdc05f4..c5cfab20 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -261,6 +261,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( input doub_bt addr, output word_bt data, input int unsigned idle_cycles = 20 + ); automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0}; jtag_write(dm::SBCS, sbcs, 0, 1); From 98d843ceaa896b85d03cb254f4afbcd490a4e9b1 Mon Sep 17 00:00:00 2001 From: Alessandro Ottaviano Date: Tue, 5 Mar 2024 14:27:37 +0100 Subject: [PATCH 05/48] target/sim: Add JTAG tasks for reg access and preloading (#103) * target/sim: Add JTAG tasks to read/write 32b registers * target/sim: Add JTAG task to halt and load binary Can be used by platforms to halt CVA6 and preload a shared memory when execution happens on domains different than Cheshire. * target/sim: Clean up added tasks --------- Co-authored-by: Paul Scheffler --- target/sim/src/vip_cheshire_soc.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index c5cfab20..cfdc05f4 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -261,7 +261,6 @@ module vip_cheshire_soc import cheshire_pkg::*; #( input doub_bt addr, output word_bt data, input int unsigned idle_cycles = 20 - ); automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0}; jtag_write(dm::SBCS, sbcs, 0, 1); From 887ae3a35836f3b736c892c0de85b0f356c3f5c5 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 19 Apr 2024 18:07:22 +0200 Subject: [PATCH 06/48] Bump CVA6-SDK tu fetch buildroot through HTTPS. --- sw/deps/cva6-sdk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sw/deps/cva6-sdk b/sw/deps/cva6-sdk index 1d4ef36b..175b88ba 160000 --- a/sw/deps/cva6-sdk +++ b/sw/deps/cva6-sdk @@ -1 +1 @@ -Subproject commit 1d4ef36baba9ecc63528fa2c0f6fa49db8fb0fbb +Subproject commit 175b88bae504757f93e59d02d437bdfdd886dd2c From 56d7ad518ca37a1a9dfdd1d8ba3a306d5787380b Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 19 Apr 2024 18:08:04 +0200 Subject: [PATCH 07/48] Bump nonfree to filter out SPI fake errors. --- cheshire.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cheshire.mk b/cheshire.mk index c96c73e7..7af158a9 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -58,7 +58,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= 99973e8 +CHS_NONFREE_COMMIT ?= a381e921 chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree From 9540cce819b5daa9cc69d88fe4aa84e74643eb6e Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 19 Apr 2024 17:50:29 +0200 Subject: [PATCH 08/48] Add selectable AXI cut between core and ID remap. --- hw/cheshire_pkg.sv | 2 ++ hw/cheshire_soc.sv | 26 ++++++++++++++++++++++---- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index a53c9c7f..a34fd1d8 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -105,6 +105,7 @@ package cheshire_pkg; dw_bt AxiUserErrBits; dw_bt AxiUserErrLsb; doub_bt AxiUserDefault; // Default user assignment, adjusted by user features (AMO) + bit CorePostCut; // Reg parameters dw_bt RegMaxReadTxns; dw_bt RegMaxWriteTxns; @@ -608,6 +609,7 @@ package cheshire_pkg; AxiUserErrBits : 0, AxiUserErrLsb : 0, AxiUserDefault : 0, + CorePostCut : 0, RegMaxReadTxns : 8, RegMaxWriteTxns : 8, AxiToRegCut : 0, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 5e2df83f..14c58e0e 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -587,8 +587,8 @@ module cheshire_soc import cheshire_pkg::*; #( axi_mst_req_t [AxiIn.num_in-1:0] tagger_req; axi_mst_rsp_t [AxiIn.num_in-1:0] tagger_rsp; - axi_cva6_req_t [NumIntHarts-1:0] core_out_req, core_ur_req; - axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp, core_ur_rsp; + axi_cva6_req_t [NumIntHarts-1:0] core_out_req, core_out_cut_req, core_ur_req; + axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp, core_out_cut_rsp, core_ur_rsp; // CLIC interface logic [NumIntHarts-1:0] clic_irq_valid, clic_irq_ready; @@ -735,17 +735,35 @@ module cheshire_soc import cheshire_pkg::*; #( end + axi_cut #( + .Bypass ( ~Cfg.CorePostCut ), + .aw_chan_t ( axi_cva6_aw_chan_t ), + .w_chan_t ( axi_cva6_w_chan_t ), + .b_chan_t ( axi_cva6_b_chan_t ), + .ar_chan_t ( axi_cva6_ar_chan_t ), + .r_chan_t ( axi_cva6_r_chan_t ), + .axi_req_t ( axi_cva6_req_t ), + .axi_resp_t ( axi_cva6_rsp_t ) + ) i_core_axi_cut ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( core_out_req[i] ), + .slv_resp_o ( core_out_rsp[i] ), + .mst_req_o ( core_out_cut_req[i] ), + .mst_resp_i ( core_out_cut_rsp[i] ) + ); + // Map user to AMO domain as we are an atomics-capable master. // Within the provided AMO user range, we count up from the provided core AMO offset. always_comb begin - core_ur_req[i] = core_out_req[i]; + core_ur_req[i] = core_out_cut_req[i]; core_ur_req[i].aw.user = Cfg.AxiUserDefault; core_ur_req[i].ar.user = Cfg.AxiUserDefault; core_ur_req[i].w.user = Cfg.AxiUserDefault; core_ur_req[i].aw.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; core_ur_req[i].ar.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; core_ur_req[i].w.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; - core_out_rsp[i] = core_ur_rsp[i]; + core_out_cut_rsp[i] = core_ur_rsp[i]; end // CVA6's ID encoding is wasteful; remap it statically pack into available bits From 1625e746873d6421d3053de3405ca71c150dca7f Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 19 Apr 2024 22:07:10 +0200 Subject: [PATCH 09/48] Propagate FullBandwidth parameter to atomics. --- Bender.lock | 8 ++++---- hw/cheshire_soc.sv | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 57b2db7e..d4d9a083 100644 --- a/Bender.lock +++ b/Bender.lock @@ -35,8 +35,8 @@ packages: - register_interface - tech_cells_generic axi_riscv_atomics: - revision: 0ac3a78fe342c5a5b9b10bff49d58897f773059e - version: 0.8.2 + revision: 06d8256ccebb13d50e5feb2c17ce87a2b1f65c46 + version: null source: Git: https://github.com/pulp-platform/axi_riscv_atomics.git dependencies: @@ -78,8 +78,8 @@ packages: - common_cells - register_interface common_cells: - revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239 - version: 1.33.0 + revision: bf98ae5e1832fa75565152837f0c3c3bf8d89759 + version: null source: Git: https://github.com/pulp-platform/common_cells.git dependencies: diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 14c58e0e..ab454d4b 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -326,6 +326,7 @@ module cheshire_soc import cheshire_pkg::*; #( .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), .RiscvWordWidth ( 64 ), .NAxiCuts ( Cfg.RegAmoNumCuts ), + .FullBandwidth ( 1 ), .axi_req_t ( axi_slv_req_t ), .axi_rsp_t ( axi_slv_rsp_t ) ) i_reg_atomics ( From 0b0625004de093dd00e0e94d670abaac367b8524 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 20 Apr 2024 08:09:42 +0200 Subject: [PATCH 10/48] Update atomics tu not include ID queue optimization. --- Bender.lock | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.lock b/Bender.lock index d4d9a083..cdd52835 100644 --- a/Bender.lock +++ b/Bender.lock @@ -35,7 +35,7 @@ packages: - register_interface - tech_cells_generic axi_riscv_atomics: - revision: 06d8256ccebb13d50e5feb2c17ce87a2b1f65c46 + revision: 6a85f44fdb1fe93162de7241476bba81e2247cb5 version: null source: Git: https://github.com/pulp-platform/axi_riscv_atomics.git From 2c3cc405a342183dcd34217c4fb73c1901410210 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 23 Apr 2024 18:27:56 +0200 Subject: [PATCH 11/48] Integrate iDMA v0.6. --- Bender.lock | 29 +++- Bender.yml | 1 + cheshire.mk | 8 +- hw/cheshire_pkg.sv | 2 + hw/cheshire_soc.sv | 1 + hw/dma_core_wrap.sv | 333 ++++++++++++++++++++++++++++++++++++++++ requirements.txt | 1 + sw/include/dif/dma.h | 35 ++--- sw/include/regs/idma.h | 303 ++++++++++++++++++++++++++++++++---- sw/sw.mk | 2 +- sw/tests/idma.c | 54 +++++++ target/xilinx/xilinx.mk | 2 +- 12 files changed, 712 insertions(+), 59 deletions(-) create mode 100644 hw/dma_core_wrap.sv create mode 100644 sw/tests/idma.c diff --git a/Bender.lock b/Bender.lock index cdd52835..1dfa5f7e 100644 --- a/Bender.lock +++ b/Bender.lock @@ -52,6 +52,13 @@ packages: - axi - common_cells - register_interface + axi_vga: + revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 + version: 0.1.3 + source: + Git: https://github.com/pulp-platform/axi_stream.git + dependencies: + - common_cells axi_vga: revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 version: 0.1.3 @@ -78,8 +85,8 @@ packages: - common_cells - register_interface common_cells: - revision: bf98ae5e1832fa75565152837f0c3c3bf8d89759 - version: null + revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 + version: 1.35.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -118,14 +125,16 @@ packages: dependencies: - common_cells idma: - revision: ca1b28816a3706be0bf9ce01378246d5346384f0 - version: 0.5.1 + revision: 88fbe67d8350b4de5ceb3673073bc216b8d585b7 + version: null source: Git: https://github.com/pulp-platform/iDMA.git dependencies: - axi + - axi_stream - common_cells - common_verification + - obi - register_interface irq_router: revision: d1d31350b24f3965b3a51e1bc96c71eb34e94db3 @@ -136,6 +145,14 @@ packages: - axi - common_cells - register_interface + obi: + revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636 + version: 0.1.2 + source: + Git: https://github.com/pulp-platform/obi.git + dependencies: + - common_cells + - common_verification opentitan_peripherals: revision: cd3153de2783abd3d03d0595e6c4b32413c62f14 version: 0.4.0 @@ -156,8 +173,8 @@ packages: - register_interface - tech_cells_generic register_interface: - revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19 - version: 0.4.3 + revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d + version: 0.4.4 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index 0f14a2a0..250d021e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -41,6 +41,7 @@ sources: - hw/regs/cheshire_reg_top.sv - hw/cheshire_pkg.sv - hw/cva6_wrap.sv + - hw/dma_core_wrap.sv - hw/cheshire_soc.sv - target: any(simulation, test) diff --git a/cheshire.mk b/cheshire.mk index 7af158a9..3aec44b5 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -58,7 +58,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= a381e921 +CHS_NONFREE_COMMIT ?= d0a0c9a # branch: astral chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree @@ -118,6 +118,10 @@ $(CHS_TAGGER_DIR)/.generated: $(MAKE) -C $(CHS_TAGGER_DIR) REGWIDTH=32 MAXPARTITION=$(MAXPARTITION) PATID_LEN=5 regs @touch $@ +# iDMA +$(IDMA_ROOT)/.generated: $(IDMA_ROOT)/target/rtl/idma_reg64_2d.hjson + flock -x $@ sh -c "cp $< $(dir $@)/target/rtl/; $(MAKE) -j1 otp" && touch $@ + CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv CHS_HW_ALL += $(CLINTROOT)/.generated CHS_HW_ALL += $(OTPROOT)/.generated @@ -150,7 +154,7 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo ############## $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml - $(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOG_ARGS)" > $@ + $(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl -t snitch_cluster --vlog-arg="$(VLOG_ARGS)" > $@ echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@ .PRECIOUS: $(CHS_ROOT)/target/sim/models diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index a34fd1d8..ce59b9cf 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -96,6 +96,7 @@ package cheshire_pkg; dw_bt AxiDataWidth; dw_bt AxiUserWidth; aw_bt AxiMstIdWidth; + aw_bt TFLenWidth; dw_bt AxiMaxMstTrans; dw_bt AxiMaxSlvTrans; // User signals identify atomics masters. @@ -602,6 +603,7 @@ package cheshire_pkg; AxiDataWidth : 64, AxiUserWidth : 2, // Convention: bit 0 for core(s), bit 1 for serial link AxiMstIdWidth : 2, + TFLenWidth : 32, AxiMaxMstTrans : 24, AxiMaxSlvTrans : 24, AxiUserAmoMsb : 1, // Convention: lower AMO bits for cores, MSB for serial link diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index ab454d4b..57f245dc 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1502,6 +1502,7 @@ module cheshire_soc import cheshire_pkg::*; #( .AxiIdWidth ( Cfg.AxiMstIdWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), .AxiSlvIdWidth ( AxiSlvIdWidth ), + .TFLenWidth ( Cfg.TFLenWidth ), .NumAxInFlight ( Cfg.DmaNumAxInFlight ), .MemSysDepth ( Cfg.DmaMemSysDepth ), .JobFifoDepth ( Cfg.DmaJobFifoDepth ), diff --git a/hw/dma_core_wrap.sv b/hw/dma_core_wrap.sv new file mode 100644 index 00000000..97371a95 --- /dev/null +++ b/hw/dma_core_wrap.sv @@ -0,0 +1,333 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Thomas Benz +// Author: Andreas Kuster +// Author: Paul Scheffler +// Author: Chaoqun Liang + +// Description: DMA core wrapper for the CVA6 integration + +`include "axi/assign.svh" +`include "axi/typedef.svh" +`include "idma/typedef.svh" +`include "register_interface/typedef.svh" + +module dma_core_wrap #( + parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, + parameter int unsigned AxiIdWidth = 32'd0, + parameter int unsigned AxiUserWidth = 32'd0, + parameter int unsigned AxiSlvIdWidth = 32'd0, + parameter int unsigned TFLenWidth = 32'd0, + parameter int unsigned NumAxInFlight = 32'd0, + parameter int unsigned MemSysDepth = 32'd0, + parameter int unsigned JobFifoDepth = 32'd0, + parameter bit RAWCouplingAvail = 32'd0, + parameter bit IsTwoD = 32'd0, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_rsp_t = logic, + parameter type axi_slv_req_t = logic, + parameter type axi_slv_rsp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic testmode_i, + output axi_mst_req_t axi_mst_req_o, + input axi_mst_rsp_t axi_mst_rsp_i, + input axi_slv_req_t axi_slv_req_i, + output axi_slv_rsp_t axi_slv_rsp_o +); + // local params + localparam int unsigned IdCounterWidth = 32'd32; + localparam int unsigned NumDim = 32'd2; + localparam int unsigned RepWidth = 32'd32; + + typedef logic [AxiDataWidth-1:0] data_t; + typedef logic [AxiDataWidth/8-1:0] strb_t; + typedef logic [AxiAddrWidth-1:0] addr_t; + typedef logic [AxiIdWidth-1:0] id_t; + typedef logic [AxiSlvIdWidth-1:0] slv_id_t; + typedef logic [AxiUserWidth-1:0] user_t; + typedef logic [TFLenWidth-1:0] tf_len_t; + typedef logic [IdCounterWidth-1:0] tf_id_t; + typedef logic [RepWidth-1:0] reps_t; + typedef logic [RepWidth-1:0] strides_t; + + // AXI4+ATOP typedefs + `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t) + + // iDMA request / response types + `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, id_t, addr_t, tf_len_t) + `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) + `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, tf_len_t, tf_len_t) + + `REG_BUS_TYPEDEF_ALL(dma_regs, addr_t, data_t, strb_t) + + typedef struct packed { + axi_ar_chan_t ar_chan; + } axi_read_meta_channel_t; + + typedef struct packed { + axi_read_meta_channel_t axi; + } read_meta_channel_t; + + typedef struct packed { + axi_aw_chan_t aw_chan; + } axi_write_meta_channel_t; + + typedef struct packed { + axi_write_meta_channel_t axi; + } write_meta_channel_t; + + dma_regs_req_t dma_reg_req; + dma_regs_rsp_t dma_reg_rsp; + // 1d-fe signals + idma_req_t burst_req_d; + logic be_valid_d; + logic be_ready_d; + // nd-fe signals + idma_nd_req_t idma_nd_req_d; + logic idma_nd_req_valid_d; + logic idma_nd_req_ready_d; + // nd-me signals + idma_nd_req_t idma_nd_req; + logic idma_nd_req_valid; + logic idma_nd_req_ready; + logic idma_nd_rsp_valid; + logic idma_nd_rsp_ready; + // be signals + idma_req_t burst_req; + logic be_valid; + logic be_ready; + idma_rsp_t idma_rsp; + logic idma_rsp_valid; + logic idma_rsp_ready; + // id signals + logic issue_id; + logic retire_id; + logic [IdCounterWidth-1:0] done_id, next_id; + // status signals + idma_pkg::idma_busy_t busy; + logic me_busy; + // internal AXI channels + axi_mst_req_t axi_read_req, axi_write_req; + axi_mst_rsp_t axi_read_rsp, axi_write_rsp; + + axi_to_reg #( + .ADDR_WIDTH( AxiAddrWidth ), + .DATA_WIDTH( AxiDataWidth ), + .ID_WIDTH ( AxiSlvIdWidth ), + .USER_WIDTH( AxiUserWidth ), + .axi_req_t ( axi_slv_req_t ), + .axi_rsp_t ( axi_slv_rsp_t ), + .reg_req_t ( dma_regs_req_t ), + .reg_rsp_t ( dma_regs_rsp_t ) + ) i_axi_translate ( + .clk_i, + .rst_ni, + .testmode_i ( 1'b0 ), + .axi_req_i ( axi_slv_req_i ), + .axi_rsp_o ( axi_slv_rsp_o ), + .reg_req_o ( dma_reg_req ), + .reg_rsp_i ( dma_reg_rsp ) + ); + + if (!IsTwoD) begin : gen_one_d + idma_reg64_1d #( + .NumRegs ( 32'd1 ), + .NumStreams ( 32'd1 ), + .IdCounterWidth ( IdCounterWidth ), + .reg_req_t ( dma_regs_req_t ), + .reg_rsp_t ( dma_regs_rsp_t ), + .dma_req_t ( idma_req_t ) + ) i_dma_frontend_1d ( + .clk_i, + .rst_ni, + .dma_ctrl_req_i ( dma_reg_req ), + .dma_ctrl_rsp_o ( dma_reg_rsp ), + .dma_req_o ( burst_req_d ), + .req_valid_o ( be_valid_d ), + .req_ready_i ( be_ready_d ), + .next_id_i ( next_id ), + .stream_idx_o ( ), + .done_id_i ( done_id ), + .busy_i ( idma_busy ), + .midend_busy_i ( 0 ) + ); + + stream_fifo_optimal_wrap #( + .Depth ( JobFifoDepth ), + .type_t ( idma_req_t ), + .PrintInfo ( 1'b0 ) + ) i_stream_fifo_jobs_1d ( + .clk_i, + .rst_ni, + .testmode_i, + .flush_i ( 1'b0 ), + .usage_o ( /* NC */ ), + .data_i ( burst_req_d ), + .valid_i ( be_valid_d ), + .ready_o ( be_ready_d ), + .data_o ( burst_req ), + .valid_o ( be_valid ), + .ready_i ( be_ready ) + ); + + assign retire_id = idma_rsp_valid & idma_rsp_ready; + assign issue_id = be_valid_d & be_ready_d; + assign idma_rsp_ready = 1'b1; + + idma_transfer_id_gen #( + .IdWidth ( IdCounterWidth ) + ) i_transfer_id_gen_1d ( + .clk_i, + .rst_ni, + .issue_i ( issue_id ), + .retire_i ( retire_id ), + .next_o ( next_id ), + .completed_o ( done_id ) + ); + + end else begin : gen_two + idma_reg64_2d #( + .NumRegs ( 32'd1 ), + .NumStreams ( 32'd1 ), + .IdCounterWidth ( IdCounterWidth ), + .reg_req_t ( dma_regs_req_t ), + .reg_rsp_t ( dma_regs_rsp_t ), + .dma_req_t ( idma_nd_req_t ) + ) idma_frontend_2d ( + .clk_i, + .rst_ni, + .dma_ctrl_req_i ( dma_reg_req ), + .dma_ctrl_rsp_o ( dma_reg_rsp ), + .dma_req_o ( idma_nd_req_d ), + .req_valid_o ( idma_nd_req_valid_d ), + .req_ready_i ( idma_nd_req_ready_d ), + .next_id_i ( next_id ), + .stream_idx_o ( ), + .done_id_i ( done_id ), + .busy_i ( busy ), + .midend_busy_i ( me_busy ) + ); + + stream_fifo_optimal_wrap #( + .Depth ( JobFifoDepth ), + .type_t ( idma_nd_req_t ), + .PrintInfo ( 1'b0 ) + ) i_stream_fifo_jobs_2d ( + .clk_i, + .rst_ni, + .testmode_i, + .flush_i ( 1'b0 ), + .usage_o ( /* NC */ ), + .data_i ( idma_nd_req_d ), + .valid_i ( idma_nd_req_valid_d ), + .ready_o ( idma_nd_req_ready_d ), + .data_o ( idma_nd_req ), + .valid_o ( idma_nd_req_valid ), + .ready_i ( idma_nd_req_ready ) + ); + + idma_nd_midend #( + .NumDim ( NumDim ), + .addr_t ( addr_t ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_nd_req_t ( idma_nd_req_t ), + .RepWidths ( RepWidth ) + ) i_idma_midend ( + .clk_i, + .rst_ni, + .nd_req_i ( idma_nd_req ), + .nd_req_valid_i ( idma_nd_req_valid ), + .nd_req_ready_o ( idma_nd_req_ready ), + .nd_rsp_o ( ), + .nd_rsp_valid_o ( idma_nd_rsp_valid ), + .nd_rsp_ready_i ( idma_nd_rsp_ready ), + .burst_req_o ( burst_req ), + .burst_req_valid_o ( be_valid ), + .burst_req_ready_i ( be_ready ), + .burst_rsp_i ( idma_rsp ), + .burst_rsp_valid_i ( idma_rsp_valid ), + .burst_rsp_ready_o ( idma_rsp_ready ), + .busy_o ( me_busy ) + ); + + assign retire_id = idma_nd_rsp_valid & idma_nd_rsp_ready; + assign issue_id = idma_nd_req_valid_d & idma_nd_req_ready_d; + assign idma_nd_rsp_ready = 1'b1; + + idma_transfer_id_gen #( + .IdWidth ( IdCounterWidth ) + ) i_transfer_id_gen_2d ( + .clk_i, + .rst_ni, + .issue_i ( issue_id ), + .retire_i ( retire_id ), + .next_o ( next_id ), + .completed_o ( done_id ) + ); + end + + idma_backend_rw_axi #( + .CombinedShifter ( 1'b0 ), + .DataWidth ( AxiDataWidth ), + .AddrWidth ( AxiAddrWidth ), + .AxiIdWidth ( AxiIdWidth ), + .UserWidth ( AxiUserWidth ), + .TFLenWidth ( TFLenWidth ), + .MaskInvalidData ( 1 ), + .BufferDepth ( 3 ), + .RAWCouplingAvail ( RAWCouplingAvail ), + .HardwareLegalizer ( 1 ), + .RejectZeroTransfers ( 1 ), + .ErrorCap ( idma_pkg::NO_ERROR_HANDLING ), + .PrintFifoInfo ( 1 ), + .NumAxInFlight ( NumAxInFlight ), + .MemSysDepth ( MemSysDepth ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_eh_req_t ( idma_pkg::idma_eh_req_t ), + .idma_busy_t ( idma_pkg::idma_busy_t ), + .axi_req_t ( axi_mst_req_t ), + .axi_rsp_t ( axi_mst_rsp_t ), + .write_meta_channel_t ( write_meta_channel_t ), + .read_meta_channel_t ( read_meta_channel_t ) + ) i_idma_backend ( + .clk_i, + .rst_ni, + .testmode_i ( 1'b0 ), + .idma_req_i ( burst_req ), + .req_valid_i ( be_valid ), + .req_ready_o ( be_ready ), + .idma_rsp_o ( idma_rsp ), + .rsp_valid_o ( idma_rsp_valid ), + .rsp_ready_i ( idma_rsp_ready ), + .idma_eh_req_i ( '0 ), + .eh_req_valid_i ( '0 ), + .eh_req_ready_o ( ), + .axi_read_req_o ( axi_read_req ), + .axi_read_rsp_i ( axi_read_rsp ), + .axi_write_req_o ( axi_write_req ), + .axi_write_rsp_i ( axi_write_rsp ), + .busy_o ( busy ) + ); + + axi_rw_join #( + .axi_req_t ( axi_mst_req_t ), + .axi_resp_t ( axi_mst_rsp_t ) + ) i_axi_rw_join ( + .clk_i, + .rst_ni, + .slv_read_req_i ( axi_read_req ), + .slv_read_resp_o ( axi_read_rsp ), + .slv_write_req_i ( axi_write_req ), + .slv_write_resp_o ( axi_write_rsp ), + .mst_req_o ( axi_mst_req_o ), + .mst_resp_i ( axi_mst_rsp_i ) + ); +endmodule diff --git a/requirements.txt b/requirements.txt index 58ded7d6..dad86bdd 100644 --- a/requirements.txt +++ b/requirements.txt @@ -7,3 +7,4 @@ yapf mkdocs mkdocs-material markdown-grid-tables +flatdict diff --git a/sw/include/dif/dma.h b/sw/include/dif/dma.h index f48b0a9f..e5a31f82 100644 --- a/sw/include/dif/dma.h +++ b/sw/include/dif/dma.h @@ -1,4 +1,4 @@ -// Copyright 2022 ETH Zurich and University of Bologna. +// Copyright 2024 ETH Zurich and University of Bologna. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -9,17 +9,16 @@ #include "regs/idma.h" #include "params.h" -#define DMA_SRC_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_SRC_ADDR_REG_OFFSET) -#define DMA_DST_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_DST_ADDR_REG_OFFSET) -#define DMA_NUMBYTES_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_NUM_BYTES_REG_OFFSET) -#define DMA_CONF_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_CONF_REG_OFFSET) -#define DMA_STATUS_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_STATUS_REG_OFFSET) -#define DMA_NEXTID_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_NEXT_ID_REG_OFFSET) -#define DMA_DONE_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_DONE_REG_OFFSET) -#define DMA_SRC_STRIDE_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_STRIDE_SRC_REG_OFFSET) -#define DMA_DST_STRIDE_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_STRIDE_DST_REG_OFFSET) -#define DMA_NUM_REPS_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_FRONTEND_NUM_REPETITIONS_REG_OFFSET) - +#define DMA_SRC_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_SRC_ADDR_LOW_REG_OFFSET) +#define DMA_DST_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_DST_ADDR_LOW_REG_OFFSET) +#define DMA_NUMBYTES_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_LENGTH_LOW_REG_OFFSET) +#define DMA_CONF_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_CONF_REG_OFFSET) +#define DMA_STATUS_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_STATUS_0_REG_OFFSET) +#define DMA_NEXTID_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_NEXT_ID_0_REG_OFFSET) +#define DMA_DONE_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_DONE_ID_0_REG_OFFSET) +#define DMA_SRC_STRIDE_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_SRC_STRIDE_2_LOW_REG_OFFSET) +#define DMA_DST_STRIDE_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_DST_STRIDE_2_LOW_REG_OFFSET) +#define DMA_NUM_REPS_ADDR(BASE) ((void *)BASE + IDMA_REG64_2D_REPS_2_LOW_REG_OFFSET) #define DMA_CONF_DECOUPLE 0 #define DMA_CONF_DEBURST 0 #define DMA_CONF_SERIALIZE 0 @@ -81,10 +80,8 @@ *(NAME##_dma_dst_ptr()) = (uint64_t)dst; \ *(NAME##_dma_num_bytes_ptr()) = size; \ *(NAME##_dma_num_reps_ptr()) = 0; \ - *(NAME##_dma_conf_ptr()) = \ - (DMA_CONF_DECOUPLE << IDMA_REG64_2D_FRONTEND_CONF_DECOUPLE_BIT) | \ - (DMA_CONF_DEBURST << IDMA_REG64_2D_FRONTEND_CONF_DEBURST_BIT) | \ - (DMA_CONF_SERIALIZE << IDMA_REG64_2D_FRONTEND_CONF_SERIALIZE_BIT); \ + *(NAME##_dma_conf_ptr()) = (DMA_CONF_DECOUPLE << IDMA_REG64_2D_CONF_DECOUPLE_AW_BIT) | \ + (DMA_CONF_DEBURST << 0) | (DMA_CONF_SERIALIZE << 0); \ return *(NAME##_dma_nextid_ptr()); \ } \ \ @@ -101,10 +98,8 @@ *(NAME##_dma_src_ptr()) = (uint64_t)src; \ *(NAME##_dma_dst_ptr()) = (uint64_t)dst; \ *(NAME##_dma_num_bytes_ptr()) = size; \ - *(NAME##_dma_conf_ptr()) = \ - (DMA_CONF_DECOUPLE << IDMA_REG64_2D_FRONTEND_CONF_DECOUPLE_BIT) | \ - (DMA_CONF_DEBURST << IDMA_REG64_2D_FRONTEND_CONF_DEBURST_BIT) | \ - (DMA_CONF_SERIALIZE << IDMA_REG64_2D_FRONTEND_CONF_SERIALIZE_BIT); \ + *(NAME##_dma_conf_ptr()) = (DMA_CONF_DECOUPLE << IDMA_REG64_2D_CONF_DECOUPLE_AW_BIT) | \ + (DMA_CONF_DEBURST << 0) | (DMA_CONF_SERIALIZE << 0); \ *(NAME##_dma_src_stride_ptr()) = src_stride; \ *(NAME##_dma_dst_stride_ptr()) = dst_stride; \ *(NAME##_dma_num_reps_ptr()) = num_reps; \ diff --git a/sw/include/regs/idma.h b/sw/include/regs/idma.h index 7aa43052..b77785b2 100644 --- a/sw/include/regs/idma.h +++ b/sw/include/regs/idma.h @@ -1,57 +1,302 @@ -// Generated register defines for idma_reg64_2d_frontend +// Generated register defines for idma_reg64_2d // Copyright information found in source file: -// Copyright 2022 ETH Zurich and University of Bologna. +// Copyright 2023 ETH Zurich and University of Bologna. // Licensing information found in source file: -// Licensed under Solderpad Hardware License, Version 0.51 +// // SPDX-License-Identifier: SHL-0.51 -#ifndef _IDMA_REG64_2D_FRONTEND_REG_DEFS_ -#define _IDMA_REG64_2D_FRONTEND_REG_DEFS_ +#ifndef _IDMA_REG64_2D_REG_DEFS_ +#define _IDMA_REG64_2D_REG_DEFS_ #ifdef __cplusplus extern "C" { #endif +// Number of dimensions available +#define IDMA_REG64_2D_PARAM_NUM_DIMS 2 + // Register width -#define IDMA_REG64_2D_FRONTEND_PARAM_REG_WIDTH 64 +#define IDMA_REG64_2D_PARAM_REG_WIDTH 32 -// Source Address -#define IDMA_REG64_2D_FRONTEND_SRC_ADDR_REG_OFFSET 0x0 +// Configuration Register for DMA settings +#define IDMA_REG64_2D_CONF_REG_OFFSET 0x0 +#define IDMA_REG64_2D_CONF_DECOUPLE_AW_BIT 0 +#define IDMA_REG64_2D_CONF_DECOUPLE_RW_BIT 1 +#define IDMA_REG64_2D_CONF_SRC_REDUCE_LEN_BIT 2 +#define IDMA_REG64_2D_CONF_DST_REDUCE_LEN_BIT 3 +#define IDMA_REG64_2D_CONF_SRC_MAX_LLEN_MASK 0x7 +#define IDMA_REG64_2D_CONF_SRC_MAX_LLEN_OFFSET 4 +#define IDMA_REG64_2D_CONF_SRC_MAX_LLEN_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_CONF_SRC_MAX_LLEN_MASK, .index = IDMA_REG64_2D_CONF_SRC_MAX_LLEN_OFFSET }) +#define IDMA_REG64_2D_CONF_DST_MAX_LLEN_MASK 0x7 +#define IDMA_REG64_2D_CONF_DST_MAX_LLEN_OFFSET 7 +#define IDMA_REG64_2D_CONF_DST_MAX_LLEN_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_CONF_DST_MAX_LLEN_MASK, .index = IDMA_REG64_2D_CONF_DST_MAX_LLEN_OFFSET }) +#define IDMA_REG64_2D_CONF_ENABLE_ND_BIT 10 -// Destination Address -#define IDMA_REG64_2D_FRONTEND_DST_ADDR_REG_OFFSET 0x8 +// DMA Status (common parameters) +#define IDMA_REG64_2D_STATUS_BUSY_FIELD_WIDTH 10 +#define IDMA_REG64_2D_STATUS_BUSY_FIELDS_PER_REG 3 +#define IDMA_REG64_2D_STATUS_MULTIREG_COUNT 16 -// Number of bytes -#define IDMA_REG64_2D_FRONTEND_NUM_BYTES_REG_OFFSET 0x10 +// DMA Status +#define IDMA_REG64_2D_STATUS_0_REG_OFFSET 0x4 +#define IDMA_REG64_2D_STATUS_0_BUSY_0_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_0_BUSY_0_OFFSET 0 +#define IDMA_REG64_2D_STATUS_0_BUSY_0_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_0_BUSY_0_MASK, .index = IDMA_REG64_2D_STATUS_0_BUSY_0_OFFSET }) -// Configuration Register for DMA settings -#define IDMA_REG64_2D_FRONTEND_CONF_REG_OFFSET 0x18 -#define IDMA_REG64_2D_FRONTEND_CONF_DECOUPLE_BIT 0 -#define IDMA_REG64_2D_FRONTEND_CONF_DEBURST_BIT 1 -#define IDMA_REG64_2D_FRONTEND_CONF_SERIALIZE_BIT 2 +// DMA Status +#define IDMA_REG64_2D_STATUS_1_REG_OFFSET 0x8 +#define IDMA_REG64_2D_STATUS_1_BUSY_1_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_1_BUSY_1_OFFSET 0 +#define IDMA_REG64_2D_STATUS_1_BUSY_1_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_1_BUSY_1_MASK, .index = IDMA_REG64_2D_STATUS_1_BUSY_1_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_2_REG_OFFSET 0xc +#define IDMA_REG64_2D_STATUS_2_BUSY_2_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_2_BUSY_2_OFFSET 0 +#define IDMA_REG64_2D_STATUS_2_BUSY_2_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_2_BUSY_2_MASK, .index = IDMA_REG64_2D_STATUS_2_BUSY_2_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_3_REG_OFFSET 0x10 +#define IDMA_REG64_2D_STATUS_3_BUSY_3_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_3_BUSY_3_OFFSET 0 +#define IDMA_REG64_2D_STATUS_3_BUSY_3_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_3_BUSY_3_MASK, .index = IDMA_REG64_2D_STATUS_3_BUSY_3_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_4_REG_OFFSET 0x14 +#define IDMA_REG64_2D_STATUS_4_BUSY_4_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_4_BUSY_4_OFFSET 0 +#define IDMA_REG64_2D_STATUS_4_BUSY_4_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_4_BUSY_4_MASK, .index = IDMA_REG64_2D_STATUS_4_BUSY_4_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_5_REG_OFFSET 0x18 +#define IDMA_REG64_2D_STATUS_5_BUSY_5_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_5_BUSY_5_OFFSET 0 +#define IDMA_REG64_2D_STATUS_5_BUSY_5_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_5_BUSY_5_MASK, .index = IDMA_REG64_2D_STATUS_5_BUSY_5_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_6_REG_OFFSET 0x1c +#define IDMA_REG64_2D_STATUS_6_BUSY_6_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_6_BUSY_6_OFFSET 0 +#define IDMA_REG64_2D_STATUS_6_BUSY_6_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_6_BUSY_6_MASK, .index = IDMA_REG64_2D_STATUS_6_BUSY_6_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_7_REG_OFFSET 0x20 +#define IDMA_REG64_2D_STATUS_7_BUSY_7_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_7_BUSY_7_OFFSET 0 +#define IDMA_REG64_2D_STATUS_7_BUSY_7_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_7_BUSY_7_MASK, .index = IDMA_REG64_2D_STATUS_7_BUSY_7_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_8_REG_OFFSET 0x24 +#define IDMA_REG64_2D_STATUS_8_BUSY_8_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_8_BUSY_8_OFFSET 0 +#define IDMA_REG64_2D_STATUS_8_BUSY_8_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_8_BUSY_8_MASK, .index = IDMA_REG64_2D_STATUS_8_BUSY_8_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_9_REG_OFFSET 0x28 +#define IDMA_REG64_2D_STATUS_9_BUSY_9_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_9_BUSY_9_OFFSET 0 +#define IDMA_REG64_2D_STATUS_9_BUSY_9_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_9_BUSY_9_MASK, .index = IDMA_REG64_2D_STATUS_9_BUSY_9_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_10_REG_OFFSET 0x2c +#define IDMA_REG64_2D_STATUS_10_BUSY_10_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_10_BUSY_10_OFFSET 0 +#define IDMA_REG64_2D_STATUS_10_BUSY_10_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_10_BUSY_10_MASK, .index = IDMA_REG64_2D_STATUS_10_BUSY_10_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_11_REG_OFFSET 0x30 +#define IDMA_REG64_2D_STATUS_11_BUSY_11_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_11_BUSY_11_OFFSET 0 +#define IDMA_REG64_2D_STATUS_11_BUSY_11_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_11_BUSY_11_MASK, .index = IDMA_REG64_2D_STATUS_11_BUSY_11_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_12_REG_OFFSET 0x34 +#define IDMA_REG64_2D_STATUS_12_BUSY_12_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_12_BUSY_12_OFFSET 0 +#define IDMA_REG64_2D_STATUS_12_BUSY_12_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_12_BUSY_12_MASK, .index = IDMA_REG64_2D_STATUS_12_BUSY_12_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_13_REG_OFFSET 0x38 +#define IDMA_REG64_2D_STATUS_13_BUSY_13_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_13_BUSY_13_OFFSET 0 +#define IDMA_REG64_2D_STATUS_13_BUSY_13_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_13_BUSY_13_MASK, .index = IDMA_REG64_2D_STATUS_13_BUSY_13_OFFSET }) // DMA Status -#define IDMA_REG64_2D_FRONTEND_STATUS_REG_OFFSET 0x20 -#define IDMA_REG64_2D_FRONTEND_STATUS_BUSY_BIT 0 +#define IDMA_REG64_2D_STATUS_14_REG_OFFSET 0x3c +#define IDMA_REG64_2D_STATUS_14_BUSY_14_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_14_BUSY_14_OFFSET 0 +#define IDMA_REG64_2D_STATUS_14_BUSY_14_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_14_BUSY_14_MASK, .index = IDMA_REG64_2D_STATUS_14_BUSY_14_OFFSET }) + +// DMA Status +#define IDMA_REG64_2D_STATUS_15_REG_OFFSET 0x40 +#define IDMA_REG64_2D_STATUS_15_BUSY_15_MASK 0x3ff +#define IDMA_REG64_2D_STATUS_15_BUSY_15_OFFSET 0 +#define IDMA_REG64_2D_STATUS_15_BUSY_15_FIELD \ + ((bitfield_field32_t) { .mask = IDMA_REG64_2D_STATUS_15_BUSY_15_MASK, .index = IDMA_REG64_2D_STATUS_15_BUSY_15_OFFSET }) + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +// (common parameters) +#define IDMA_REG64_2D_NEXT_ID_NEXT_ID_FIELD_WIDTH 32 +#define IDMA_REG64_2D_NEXT_ID_NEXT_ID_FIELDS_PER_REG 1 +#define IDMA_REG64_2D_NEXT_ID_MULTIREG_COUNT 16 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_0_REG_OFFSET 0x44 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_1_REG_OFFSET 0x48 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_2_REG_OFFSET 0x4c // Next ID, launches transfer, returns 0 if transfer not set up properly. -#define IDMA_REG64_2D_FRONTEND_NEXT_ID_REG_OFFSET 0x28 +#define IDMA_REG64_2D_NEXT_ID_3_REG_OFFSET 0x50 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_4_REG_OFFSET 0x54 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_5_REG_OFFSET 0x58 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_6_REG_OFFSET 0x5c + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_7_REG_OFFSET 0x60 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_8_REG_OFFSET 0x64 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_9_REG_OFFSET 0x68 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_10_REG_OFFSET 0x6c + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_11_REG_OFFSET 0x70 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_12_REG_OFFSET 0x74 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_13_REG_OFFSET 0x78 + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_14_REG_OFFSET 0x7c + +// Next ID, launches transfer, returns 0 if transfer not set up properly. +#define IDMA_REG64_2D_NEXT_ID_15_REG_OFFSET 0x80 + +// Get ID of finished transactions. (common parameters) +#define IDMA_REG64_2D_DONE_ID_DONE_ID_FIELD_WIDTH 32 +#define IDMA_REG64_2D_DONE_ID_DONE_ID_FIELDS_PER_REG 1 +#define IDMA_REG64_2D_DONE_ID_MULTIREG_COUNT 16 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_0_REG_OFFSET 0x84 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_1_REG_OFFSET 0x88 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_2_REG_OFFSET 0x8c + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_3_REG_OFFSET 0x90 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_4_REG_OFFSET 0x94 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_5_REG_OFFSET 0x98 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_6_REG_OFFSET 0x9c // Get ID of finished transactions. -#define IDMA_REG64_2D_FRONTEND_DONE_REG_OFFSET 0x30 +#define IDMA_REG64_2D_DONE_ID_7_REG_OFFSET 0xa0 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_8_REG_OFFSET 0xa4 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_9_REG_OFFSET 0xa8 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_10_REG_OFFSET 0xac + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_11_REG_OFFSET 0xb0 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_12_REG_OFFSET 0xb4 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_13_REG_OFFSET 0xb8 + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_14_REG_OFFSET 0xbc + +// Get ID of finished transactions. +#define IDMA_REG64_2D_DONE_ID_15_REG_OFFSET 0xc0 + +// Low destination address +#define IDMA_REG64_2D_DST_ADDR_LOW_REG_OFFSET 0xd0 + +// High destination address +#define IDMA_REG64_2D_DST_ADDR_HIGH_REG_OFFSET 0xd4 + +// Low source address +#define IDMA_REG64_2D_SRC_ADDR_LOW_REG_OFFSET 0xd8 + +// High source address +#define IDMA_REG64_2D_SRC_ADDR_HIGH_REG_OFFSET 0xdc + +// Low transfer length in byte +#define IDMA_REG64_2D_LENGTH_LOW_REG_OFFSET 0xe0 + +// High transfer length in byte +#define IDMA_REG64_2D_LENGTH_HIGH_REG_OFFSET 0xe4 + +// Low destination stride dimension 2 +#define IDMA_REG64_2D_DST_STRIDE_2_LOW_REG_OFFSET 0xe8 + +// High destination stride dimension 2 +#define IDMA_REG64_2D_DST_STRIDE_2_HIGH_REG_OFFSET 0xec + +// Low source stride dimension 2 +#define IDMA_REG64_2D_SRC_STRIDE_2_LOW_REG_OFFSET 0xf0 -// Source Stride -#define IDMA_REG64_2D_FRONTEND_STRIDE_SRC_REG_OFFSET 0x38 +// High source stride dimension 2 +#define IDMA_REG64_2D_SRC_STRIDE_2_HIGH_REG_OFFSET 0xf4 -// Destination Stride -#define IDMA_REG64_2D_FRONTEND_STRIDE_DST_REG_OFFSET 0x40 +// Low number of repetitions dimension 2 +#define IDMA_REG64_2D_REPS_2_LOW_REG_OFFSET 0xf8 -// Number of 2D repetitions -#define IDMA_REG64_2D_FRONTEND_NUM_REPETITIONS_REG_OFFSET 0x48 +// High number of repetitions dimension 2 +#define IDMA_REG64_2D_REPS_2_HIGH_REG_OFFSET 0xfc #ifdef __cplusplus } // extern "C" #endif -#endif // _IDMA_REG64_2D_FRONTEND_REG_DEFS_ -// End generated register defines for idma_reg64_2d_frontend \ No newline at end of file +#endif // _IDMA_REG64_2D_REG_DEFS_ +// End generated register defines for idma_reg64_2d \ No newline at end of file diff --git a/sw/sw.mk b/sw/sw.mk index 89987310..da518442 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -79,7 +79,7 @@ endef $(eval $(call chs_sw_gen_hdr_rule,clint,$(CLINTROOT)/src/clint.hjson $(CLINTROOT)/.generated)) $(eval $(call chs_sw_gen_hdr_rule,serial_link,$(CHS_ROOT)/hw/serial_link.hjson $(CHS_SLINK_DIR)/.generated)) $(eval $(call chs_sw_gen_hdr_rule,axi_vga,$(AXI_VGA_ROOT)/data/axi_vga.hjson $(AXI_VGA_ROOT)/.generated)) -$(eval $(call chs_sw_gen_hdr_rule,idma,$(IDMA_ROOT)/src/frontends/register_64bit_2d/idma_reg64_2d_frontend.hjson)) +$(eval $(call chs_sw_gen_hdr_rule,idma,$(IDMA_ROOT)/target/rtl/idma_reg64_2d.hjson)) $(eval $(call chs_sw_gen_hdr_rule,axi_llc,$(CHS_LLC_DIR)/data/axi_llc_regs.hjson)) $(eval $(call chs_sw_gen_hdr_rule,cheshire,$(CHS_ROOT)/hw/regs/cheshire_regs.hjson)) $(eval $(call chs_sw_gen_hdr_rule,axi_rt,$(AXIRTROOT)/src/regs/axi_rt.hjson $(AXIRTROOT)/.generated)) diff --git a/sw/tests/idma.c b/sw/tests/idma.c new file mode 100644 index 00000000..fb0a92b2 --- /dev/null +++ b/sw/tests/idma.c @@ -0,0 +1,54 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Chaoqun Liang +// +// Simple payload to test iDMA + +#include +#include +#include +#include "util.h" +#include "printf.h" + +#define IDMA_BASE 0x01000000 +#define SRC_ADDR 0x14000000 +#define DST_ADDR 0x14000100 + +#define IDMA_SRC_ADDR_OFFSET 0x000000d8 +#define IDMA_DST_ADDR_OFFSET 0x000000d0 +#define IDMA_LENGTH_OFFSET 0x000000e0 +#define IDMA_NEXT_ID_OFFSET 0x00000044 +#define IDMA_REPS_2 0x000000f8 +#define IDMA_CONF 0x00000000 + +int main(void) { + int err = 0; + volatile uint64_t src_data[8] = {0x1032207098001032, 0x3210E20020709800, 0x1716151413121110, + 0x2726252423222120, 0x3736353433323130, 0x4746454443424140, + 0x5756555453525150, 0x6766656463626160}; + // load data into src address + for (int i = 0; i < 8; ++i) { + volatile uint64_t *src_addr = (volatile uint64_t *)(SRC_ADDR + i * sizeof(uint64_t)); + *src_addr = src_data[i]; + } + *reg32(IDMA_BASE, IDMA_SRC_ADDR_OFFSET) = SRC_ADDR; + *reg32(IDMA_BASE, IDMA_DST_ADDR_OFFSET) = DST_ADDR; + *reg32(IDMA_BASE, IDMA_LENGTH_OFFSET) = 0x00000040; + *reg32(IDMA_BASE, IDMA_CONF) = 0x1 << 10; + *reg32(IDMA_BASE, IDMA_REPS_2) = 0x00000001; + // ID has to be read to make it work + uint32_t id = *reg32(IDMA_BASE, IDMA_NEXT_ID_OFFSET); + for (int i = 0; i < 8; ++i) { + volatile uint64_t *dst_addr = (volatile uint64_t *)(DST_ADDR + i * sizeof(uint64_t)); + uint64_t dst_data = *dst_addr; + if (dst_data != src_data[i]) { + err++; + } + } + if (err != 0) { + printf("idma failed\n"); + } else + return 0; +} diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index be35b5a9..465448e2 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -41,7 +41,7 @@ CHS_XILINX_IPS_genesys2 := clkwiz vio mig7s CHS_XILINX_IPS_vcu128 := clkwiz vio ddr4 $(CHS_XILINX_DIR)/scripts/add_sources.%.tcl: $(CHS_ROOT)/Bender.yml - $(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 -t $* > $@ + $(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 -t rtl -t snitch_cluster -t $* > $@ define chs_xilinx_bit_rule $$(CHS_XILINX_DIR)/out/%.$(1).bit: \ From 261134ac8355eaf90810edf80c46c48b3e613c6e Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 20 Feb 2024 00:59:58 +0100 Subject: [PATCH 12/48] working sim with local fix on dma --- Bender.lock | 45 ++++++ hw/cheshire_pkg.sv | 8 +- hw/cheshire_soc.sv | 69 ++++++++ target/sim/src/fixture_cheshire_soc.sv | 37 +++++ target/sim/src/tb_cheshire_pkg.sv | 2 +- target/sim/src/vip_cheshire_soc.sv | 210 ++++++++++++++++++++++++- target/sim/vsim/start.cheshire_soc.tcl | 2 +- 7 files changed, 369 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 1dfa5f7e..96d502cf 100644 --- a/Bender.lock +++ b/Bender.lock @@ -34,6 +34,13 @@ packages: - common_verification - register_interface - tech_cells_generic + axi_mem_if: + revision: 3567273b4f67bd57a81a2a503394a49641bae53a + version: 0.2.1 + source: + Git: git@github.com:pulp-platform/axi_mem_if.git + dependencies: + - axi axi_riscv_atomics: revision: 6a85f44fdb1fe93162de7241476bba81e2247cb5 version: null @@ -55,6 +62,13 @@ packages: axi_vga: revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 version: 0.1.3 + source: + Git: git@github.com:pulp-platform/axi_stream.git + dependencies: + - common_cells + axi_vga: + revision: 07be187d1e954d8090031b32d236ad76dc62ce45 + version: 0.1.1 source: Git: https://github.com/pulp-platform/axi_stream.git dependencies: @@ -109,6 +123,19 @@ packages: - fpnew - redundancy_cells - tech_cells_generic + ethernet: + revision: ab333c946fbfea18132904f8de0dc6702d67e741 + version: null + source: + Git: git@github.com:pulp-platform/pulp-ethernet.git + dependencies: + - axi + - axi_mem_if + - axi_stream + - common_cells + - common_verification + - idma + - register_interface fpnew: revision: f231041c610f270ffc03cbdac38739ddb6426572 version: null @@ -125,8 +152,13 @@ packages: dependencies: - common_cells idma: +<<<<<<< HEAD revision: 88fbe67d8350b4de5ceb3673073bc216b8d585b7 version: null +======= + revision: a80fcace92b1562e7cd76c8615298b5623ba74d2 + version: 0.6.0-beta +>>>>>>> 96d0e4e (working sim with local fix on dma) source: Git: https://github.com/pulp-platform/iDMA.git dependencies: @@ -134,7 +166,20 @@ packages: - axi_stream - common_cells - common_verification +<<<<<<< HEAD - obi +======= + - idma_gen + - register_interface + idma_gen: + revision: null + version: null + source: + Path: .bender/git/checkouts/idma-77bf7fa56d324e6a/target/rtl + dependencies: + - axi + - common_cells +>>>>>>> 96d0e4e (working sim with local fix on dma) - register_interface irq_router: revision: d1d31350b24f3965b3a51e1bc96c71eb34e94db3 diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index ce59b9cf..488a4592 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -135,6 +135,7 @@ package cheshire_pkg; bit Bootrom; bit Uart; bit I2c; + bit Ethernet; bit SpiHost; bit Gpio; bit Dma; @@ -312,6 +313,7 @@ package cheshire_pkg; aw_bt vga; aw_bt ext_base; aw_bt num_in; + aw_bt eth_idma; } axi_in_t; function automatic axi_in_t gen_axi_in(cheshire_cfg_t cfg); @@ -322,6 +324,7 @@ package cheshire_pkg; if (cfg.Dma) begin i++; ret.dma = i; end if (cfg.SerialLink) begin i++; ret.slink = i; end if (cfg.Vga) begin i++; ret.vga = i; end + if (cfg.Ethernet) begin i++; ret.eth_idma = i; end i++; ret.ext_base = i; ret.num_in = i + cfg.AxiExtNumMst; @@ -399,6 +402,7 @@ package cheshire_pkg; aw_bt llc; aw_bt uart; aw_bt i2c; + aw_bt ethernet; aw_bt spi_host; aw_bt gpio; aw_bt slink; @@ -431,6 +435,7 @@ package cheshire_pkg; if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end + if (cfg.Ethernet) begin i++; ret.ethernet = i; r++; ret.map[r] = '{i, 'h0300_c000, 'h0300_d000}; end if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin i++; ret.clic[j] = i; r++; ret.map[r] = '{i, AmClic + j*'h40000, AmClic + (j+1)*'h40000}; end @@ -624,9 +629,10 @@ package cheshire_pkg; Bootrom : 1, Uart : 1, I2c : 1, + Ethernet : 1, SpiHost : 1, Gpio : 1, - Dma : 1, + Dma : 0, SerialLink : 1, Vga : 1, AxiRt : 0, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 57f245dc..637ce9ae 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -74,6 +74,20 @@ module cheshire_soc import cheshire_pkg::*; #( output logic i2c_scl_o, input logic i2c_scl_i, output logic i2c_scl_en_o, + // ETHERNET interface + input logic eth_rxck_i, + input logic [3:0] eth_rxd_i, + input logic eth_rxctl_i, + output logic eth_txck_o, + output logic [3:0] eth_txd_o, + output logic eth_txctl_o, + output logic eth_rstn_o, + input logic eth_intn_i, + input logic eth_pme_i, + input logic eth_mdio_i, + output logic eth_mdio_o, + output logic eth_mdio_oe, + output logic eth_mdc_o, // SPI host interface output logic spih_sck_o, output logic spih_sck_en_o, @@ -1365,6 +1379,61 @@ module cheshire_soc import cheshire_pkg::*; #( end + + //////////////// + // ETHERNET // + //////////////// + if (Cfg.Ethernet) begin : gen_ethernet + eth_idma_wrap#( + .DataWidth ( Cfg.AxiDataWidth ), + .AddrWidth ( Cfg.AddrWidth ), + .UserWidth ( Cfg.AxiUserWidth ), + .AxiIdWidth ( Cfg.AxiMstIdWidth ), + .axi_req_t ( axi_mst_req_t ), + .axi_rsp_t ( axi_mst_rsp_t ), + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ) + ) i_tx_eth_idma_wrap ( + .clk_i, + .rst_ni, + .phy_rx_clk_i ( eth_rxck_i ), + .phy_rxd_i ( eth_rxd_i ), + .phy_rx_ctl_i ( eth_rxctl_i ), + .phy_tx_clk_o ( eth_txck_o ), + .phy_txd_o ( eth_txd_o ), + .phy_tx_ctl_o ( eth_txctl_o ), + .phy_resetn_o ( eth_rstn_o ), + .phy_intn_i ( 1'b1 ), + .phy_pme_i ( 1'b1 ), + .phy_mdio_i ( 1'b0 ), + .phy_mdio_o ( eth_mdio_o ), + .phy_mdio_oe ( eth_mdio_oe ), + .phy_mdc_o ( eth_mdc_o ), + .testmode_i ( 1'b0 ), + .axi_req_o ( axi_in_req[AxiIn.eth_idma] ), + .axi_rsp_i ( axi_in_rsp[AxiIn.eth_idma] ), + .reg_req_i ( reg_out_req[RegOut.ethernet] ), + .reg_rsp_o ( reg_out_rsp[RegOut.ethernet] ) // req from cheshire def, but inside ethernet, it awaits for the type + ); + + end else begin : gen_no_ethernet + + assign axi_in_rsp[AxiIn.eth_idma].aw_ready = 1'b1; + assign axi_in_rsp[AxiIn.eth_idma].ar_ready = 1'b1; + assign axi_in_rsp[AxiIn.eth_idma].w_ready = 1'b1; + + // assign axi_in_rsp[AxiIn.eth_idma].b_valid = axi_in_req[AxiIn.eth_idma].aw_valid; + // assign axi_in_rsp[AxiIn.eth_idma].b_id = axi_in_req[AxiIn.eth_idma].aw_id; + // assign axi_in_rsp[AxiIn.eth_idma].b_resp = axi_pkg::RESP_SLVERR; + // assign axi_in_rsp[AxiIn.eth_idma].b_user = '0; + + assign axi_in_rsp[AxiIn.eth_idma].r_valid = axi_in_req[AxiIn.eth_idma].ar_valid; + // assign axi_in_rsp[AxiIn.eth_idma].r_resp = axi_pkg::RESP_SLVERR; + // assign axi_in_rsp[AxiIn.eth_idma].r_data = 'hdeadbeef; + // assign axi_in_rsp[AxiIn.eth_idma].r_last = 1'b1; + + end + //////////////// // SPI Host // //////////////// diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 00f0c493..332e024d 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -49,6 +49,20 @@ module fixture_cheshire_soc #( logic i2c_scl_i; logic i2c_scl_en; + logic eth_rxck_i; + logic [3:0] eth_rxd_i; + logic eth_rxctl_i; + logic eth_txck_o; + logic [3:0] eth_txd_o; + logic eth_txctl_o; + logic eth_rstn_o; + logic eth_intn_i; + logic eth_pme_i; + logic eth_mdio_i; + logic eth_mdio_o; + logic eth_mdio_en; + logic eth_mdc_o; + logic spih_sck_o; logic spih_sck_en; logic [SpihNumCs-1:0] spih_csb_o; @@ -115,6 +129,19 @@ module fixture_cheshire_soc #( .i2c_scl_o ( i2c_scl_o ), .i2c_scl_i ( i2c_scl_i ), .i2c_scl_en_o ( i2c_scl_en ), + .eth_rxck_i ( eth_rxck_i ), + .eth_rxd_i ( eth_rxd_i ), + .eth_rxctl_i ( eth_rxctl_i ), + .eth_txck_o ( eth_txck_o ), + .eth_txd_o ( eth_txd_o ), + .eth_txctl_o ( eth_txctl_o ), + .eth_rstn_o ( eth_rstn_o ), + .eth_intn_i ( eth_intn_i ), + .eth_pme_i ( eth_pme_i ), + .eth_mdio_i ( eth_mdio_i ), + .eth_mdio_o ( eth_mdio_o ), + .eth_mdio_oe ( eth_mdio_en ), + .eth_mdc_o ( eth_mdc_o ), .spih_sck_o ( spih_sck_o ), .spih_sck_en_o ( spih_sck_en ), .spih_csb_o ( spih_csb_o ), @@ -147,6 +174,16 @@ module fixture_cheshire_soc #( wire [SpihNumCs-1:0] spih_csb; wire [ 3:0] spih_sd; + wire [ 3:0] eth_txd; + wire [ 3:0] eth_rxd; + wire eth_txck; + wire eth_rxck; + wire eth_txctl; + wire eth_rxctl; + wire eth_rstn; + wire eth_mdio; + wire eth_mdc; + vip_cheshire_soc_tristate vip_tristate (.*); /////////// diff --git a/target/sim/src/tb_cheshire_pkg.sv b/target/sim/src/tb_cheshire_pkg.sv index 77ab78a2..962ee3fc 100644 --- a/target/sim/src/tb_cheshire_pkg.sv +++ b/target/sim/src/tb_cheshire_pkg.sv @@ -12,7 +12,7 @@ package tb_cheshire_pkg; // A dedicated RT config function automatic cheshire_cfg_t gen_cheshire_rt_cfg(); cheshire_cfg_t ret = DefaultCfg; - ret.AxiRt = 1; + ret.AxiRt = 0; return ret; endfunction diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index cfdc05f4..cdaf19ac 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -8,6 +8,7 @@ // Collects all existing verification IP (VIP) in one module for use in testbenches of // Cheshire-based SoCs and Chips. IOs are of inout direction where applicable. +`include "register_interface/assign.svh" module vip_cheshire_soc import cheshire_pkg::*; #( // DUT (must be set) @@ -67,6 +68,16 @@ module vip_cheshire_soc import cheshire_pkg::*; #( inout wire spih_sck, inout wire [SpihNumCs-1:0] spih_csb, inout wire [ 3:0] spih_sd, + // Ethernet interface + inout wire [ 3:0] eth_txd, + inout wire [ 3:0] eth_rxd, + inout wire eth_txck, + inout wire eth_rxck, + inout wire eth_txctl, + inout wire eth_rxctl, + inout wire eth_rstn, + inout wire eth_mdio, + inout wire eth_mdc, // Serial link interface output logic [SlinkNumChan-1:0] slink_rcv_clk_i, input logic [SlinkNumChan-1:0] slink_rcv_clk_o, @@ -592,6 +603,167 @@ module vip_cheshire_soc import cheshire_pkg::*; #( $readmemh(image, i_spi_norflash.Mem); endtask + /////////////////// + // Ethernet // + /////////////////// + import idma_pkg::*; + localparam REG_BUS_AW = 32; + localparam REG_BUS_DW = 32; + + typedef reg_test::reg_driver #( + .AW(REG_BUS_AW), + .DW(REG_BUS_DW), + .TT(ClkPeriodJtag * TTest), + .TA(ClkPeriodJtag * TAppl) + ) reg_bus_drv_t; + + REG_BUS #( + .DATA_WIDTH(REG_BUS_DW), + .ADDR_WIDTH(REG_BUS_AW) + ) reg_bus_rx ( + .clk_i(clk) + ); + + logic reg_error; + logic [REG_BUS_DW-1:0] rx_req_ready, rx_rsp_valid; + + reg_bus_drv_t reg_drv_rx = new(reg_bus_rx); + + reg_req_t reg_bus_rx_req; + reg_rsp_t reg_bus_rx_rsp; + + `REG_BUS_ASSIGN_TO_REQ (reg_bus_rx_req, reg_bus_rx) + `REG_BUS_ASSIGN_FROM_RSP (reg_bus_rx, reg_bus_rx_rsp) + + axi_mst_req_t axi_req_mem; + axi_mst_rsp_t axi_rsp_mem; + idma_pkg::idma_busy_t idma_busy_o; + + eth_idma_wrap#( + .DataWidth ( DutCfg.AxiDataWidth ), + .AddrWidth ( DutCfg.AddrWidth ), + .UserWidth ( DutCfg.AxiUserWidth ), + .AxiIdWidth ( DutCfg.AxiMstIdWidth ), + .axi_req_t ( axi_mst_req_t ), + .axi_rsp_t ( axi_mst_rsp_t ), + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ) + ) i_rx_eth_idma_wrap ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .phy_rx_clk_i ( eth_txck ), + .phy_rxd_i ( eth_txd ), + .phy_rx_ctl_i ( eth_txctl ), + .phy_tx_clk_o ( eth_rxck ), + .phy_txd_o ( eth_rxd ), + .phy_tx_ctl_o ( eth_rxctl ), + .phy_resetn_o ( eth_rstn ), + .phy_intn_i ( 1'b1 ), + .phy_pme_i ( 1'b1 ), + .phy_mdio_i ( 1'b0 ), + .phy_mdio_o ( ), + .phy_mdio_oe ( ), + .phy_mdc_o ( ), + .reg_req_i ( reg_bus_rx_req ), + .reg_rsp_o ( reg_bus_rx_rsp ), + .testmode_i ( 1'b0 ), + .axi_req_o ( axi_req_mem ), + .axi_rsp_i ( axi_rsp_mem ), + .idma_busy_o ( tx_busy ) + ); + + axi_sim_mem #( + .AddrWidth ( DutCfg.AddrWidth ), + .DataWidth ( DutCfg.AxiDataWidth ), + .IdWidth ( DutCfg.AxiMstIdWidth ), + .UserWidth ( DutCfg.AxiUserWidth ), + .axi_req_t ( axi_slv_req_t ), + .axi_rsp_t ( axi_slv_rsp_t ), + .WarnUninitialized ( 1'b0 ), + .ClearErrOnAccess ( 1'b1 ), + .ApplDelay ( ClkPeriodJtag * TAppl ), + .AcqDelay ( ClkPeriodJtag * TTest ) + ) i_rx_axi_sim_mem ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_req_i ( axi_req_mem ), + .axi_rsp_o ( axi_rsp_mem ), + .mon_r_last_o ( /* NOT CONNECTED */ ), + .mon_r_beat_count_o ( /* NOT CONNECTED */ ), + .mon_r_user_o ( /* NOT CONNECTED */ ), + .mon_r_id_o ( /* NOT CONNECTED */ ), + .mon_r_data_o ( /* NOT CONNECTED */ ), + .mon_r_addr_o ( /* NOT CONNECTED */ ), + .mon_r_valid_o ( /* NOT CONNECTED */ ), + .mon_w_last_o ( /* NOT CONNECTED */ ), + .mon_w_beat_count_o ( /* NOT CONNECTED */ ), + .mon_w_user_o ( /* NOT CONNECTED */ ), + .mon_w_id_o ( /* NOT CONNECTED */ ), + .mon_w_data_o ( /* NOT CONNECTED */ ), + .mon_w_addr_o ( /* NOT CONNECTED */ ), + .mon_w_valid_o ( /* NOT CONNECTED */ ) + ); + + initial begin + + @(posedge clk); + + $readmemh("/scratch/chaol/cheshire/target/sim/src/rx_mem_init.vmem", i_rx_axi_sim_mem.mem); + + @(posedge clk); + reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c010, 32'h0, 'hf, reg_error ); // SRC_ADDR + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error); // DST_ADDR + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c018, 32'h40,'hf , reg_error); // Size in bytes + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c01c, 32'h5,'hf , reg_error); // src protocol + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c020, 32'h0,'hf , reg_error); // dst protocol + @(posedge clk); + + // @(posedge data_ready); + + //#9000ns; + + // while(1) begin + // reg_drv_rx.send_read( 'h3000003c, rx_req_ready, reg_error); + // if(rx_req_ready) begin + reg_drv_rx.send_write( 'h0300c038, 'h1, 'hf , reg_error); // req valid + @(posedge clk); +// break; +// end +// @(posedge clk_i); +// end + +@(posedge clk); + + +reg_drv_rx.send_write( 'h0300c040, 'h1, 'hf, reg_error); //rsp ready +//repeat(25)@(posedge clk_i); +//reg_drv_rx.send_write( 'h30000038, 'h0, 'hf , reg_error); // req valid + +while(1) begin +reg_drv_rx.send_read( 'h0300c044, rx_rsp_valid, reg_error); + if(rx_rsp_valid) begin +reg_drv_rx.send_write( 'h0300c040, 32'h0, 'hf , reg_error); +@(posedge clk); +break; +end +@(posedge clk); +end + end + /////////////////// // Serial Link // /////////////////// @@ -930,13 +1102,36 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( output logic [ 3:0] spih_sd_i, input logic [ 3:0] spih_sd_o, input logic [ 3:0] spih_sd_en, + // Ethernet pad IO + output logic [3:0] eth_rxd_i, + input logic [3:0] eth_txd_o, + output logic eth_rxck_i, + input logic eth_txck_o, + output logic eth_rxctl_i, + input logic eth_txctl_o, + input logic eth_rstn_o, + input logic eth_mdio_o, + output logic eth_mdio_i, + input logic eth_mdio_en, + input logic eth_mdc_o, + // I2C wires inout wire i2c_sda, inout wire i2c_scl, // SPI host wires inout wire spih_sck, inout wire [SpihNumCs-1:0] spih_csb, - inout wire [ 3:0] spih_sd + inout wire [ 3:0] spih_sd, + // Ethernet wires + inout wire [ 3:0] eth_txd, + inout wire [ 3:0] eth_rxd, + inout wire eth_txck, + inout wire eth_rxck, + inout wire eth_txctl, + inout wire eth_rxctl, + inout wire eth_rstn, + inout wire eth_mdio, + inout wire eth_mdc ); // I2C @@ -962,4 +1157,17 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( pullup (spih_csb[i]); end + // Ethernet + assign eth_txd = eth_txd_o; + assign eth_txck = eth_txck_o; + assign eth_txctl = eth_txctl_o; + assign eth_mdc = eth_mdc_o; + assign eth_rxd_i = eth_rxd; + assign eth_rxck_i = eth_rxck; + assign eth_rxctl_i = eth_rxctl; + + + bufif1 (eth_mdio_i, eth_mdio, ~eth_mdio_en); + bufif1 (eth_mdio, eth_mdio_o, eth_mdio_en); + endmodule diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index f9d6cad2..4b5ab7b8 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -12,7 +12,7 @@ set TESTBENCH tb_cheshire_soc # Set voptargs only if not already set to make overridable. # Default on fast simulation flags. if {![info exists VOPTARGS]} { - set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" + set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +acc=p+cheshire_soc. +acc=r+stream_xbar" } set flags "-permissive -suppress 3009 -suppress 8386 -error 7 " From d7b2622f4306eb98e1bd60cf635f1b0062bf2333 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Mon, 6 May 2024 23:58:11 +0200 Subject: [PATCH 13/48] rebase --- Bender.lock | 8 ---- sw/include/dif/dma.h | 2 +- sw/tests/axirt_budget.c | 2 +- sw/tests/ethernet.c | 72 ++++++++++++++++++++++++++++++ target/sim/src/vip_cheshire_soc.sv | 2 +- 5 files changed, 75 insertions(+), 11 deletions(-) create mode 100644 sw/tests/ethernet.c diff --git a/Bender.lock b/Bender.lock index 96d502cf..18b19499 100644 --- a/Bender.lock +++ b/Bender.lock @@ -152,13 +152,8 @@ packages: dependencies: - common_cells idma: -<<<<<<< HEAD revision: 88fbe67d8350b4de5ceb3673073bc216b8d585b7 version: null -======= - revision: a80fcace92b1562e7cd76c8615298b5623ba74d2 - version: 0.6.0-beta ->>>>>>> 96d0e4e (working sim with local fix on dma) source: Git: https://github.com/pulp-platform/iDMA.git dependencies: @@ -166,9 +161,7 @@ packages: - axi_stream - common_cells - common_verification -<<<<<<< HEAD - obi -======= - idma_gen - register_interface idma_gen: @@ -179,7 +172,6 @@ packages: dependencies: - axi - common_cells ->>>>>>> 96d0e4e (working sim with local fix on dma) - register_interface irq_router: revision: d1d31350b24f3965b3a51e1bc96c71eb34e94db3 diff --git a/sw/include/dif/dma.h b/sw/include/dif/dma.h index e5a31f82..2d37ab09 100644 --- a/sw/include/dif/dma.h +++ b/sw/include/dif/dma.h @@ -122,4 +122,4 @@ X(sys, &__base_dma); -#undef X +#undef X \ No newline at end of file diff --git a/sw/tests/axirt_budget.c b/sw/tests/axirt_budget.c index 72ec0281..f36e6b06 100644 --- a/sw/tests/axirt_budget.c +++ b/sw/tests/axirt_budget.c @@ -59,4 +59,4 @@ int main(void) { volatile uint8_t mismatch = read_budget != write_budget; return mismatch | (difference << 1); -} +} \ No newline at end of file diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c new file mode 100644 index 00000000..6850eb10 --- /dev/null +++ b/sw/tests/ethernet.c @@ -0,0 +1,72 @@ +#include +#include +#include +#include "util.h" + +#define ETH_BASE 0x0300c000 + +#define MACLO_OFFSET 0x0 +#define MACHI_OFFSET 0x4 + +#define IDMA_SRC_ADDR_OFFSET 0x10 +#define IDMA_DST_ADDR_OFFSET 0x14 +#define IDMA_LENGTH_OFFSET 0x18 +#define IDMA_SRC_PROTO_OFFSET 0x1c +#define IDMA_DST_PROTO_OFFSET 0x20 +#define IDMA_REQ_VALID_OFFSET 0x38 +#define IDMA_REQ_READY_OFFSET 0x3c +#define IDMA_RSP_READY_OFFSET 0x40 +#define IDMA_RSP_VALID_OFFSET 0x44 + +int main(void) { + + volatile uint64_t data_to_write[8] = { + 0x1032207098001032, + 0x3210E20020709800, + 0x1716151413121110, + 0x2726252423222120, + 0x3736353433323130, + 0x4746454443424140, + 0x5756555453525150, + 0x6766656463626160 + }; + + // load data into mem + for (int i = 0; i < 8; ++i) { + + volatile uint64_t *tx_addr = (volatile uint64_t*)(0x14000000 + i * sizeof(uint64_t)); + *tx_addr = data_to_write[i]; + } + + + *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; + + *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET)= 0x14000000; + *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET)= 0x0; + *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = 0x40; + *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x0; + *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x5; + + + *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; + *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; + *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1; + + // pulp_write32( ETH_BASE + IDMA_REQ_VALID_OFFSET , 0x1); + + // pulp_write32( ETH_BASE + IDMA_REQ_VALID_OFFSET , 0x0); + + + // // data + // pulp_write32( ETH_BASE + IDMA_RSP_READY_OFFSET , 0x1); + + // to-do deassert rsp_ready when rx transaction is complete + + + + while(1); + + //return 0; + +} diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index cdaf19ac..317a224e 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -1165,7 +1165,7 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( assign eth_rxd_i = eth_rxd; assign eth_rxck_i = eth_rxck; assign eth_rxctl_i = eth_rxctl; - + bufif1 (eth_mdio_i, eth_mdio, ~eth_mdio_en); bufif1 (eth_mdio, eth_mdio_o, eth_mdio_en); From b22adae591a62a11686ded2f252ed5f1c82801b3 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 10 Apr 2024 00:34:43 +0200 Subject: [PATCH 14/48] cleanup --- Bender.lock | 6 +- Makefile | 2 +- cheshire.mk | 8 +- hw/cheshire_soc.sv | 12 +- sw/tests/ethernet.c | 18 +-- target/sim/src/fixture_cheshire_soc.sv | 48 ++++---- target/sim/src/vip_cheshire_soc.sv | 143 ++++++++++------------- target/xilinx/scripts/impl_ip.tcl | 12 +- target/xilinx/src/cheshire_top_xilinx.sv | 66 +++++++++-- target/xilinx/src/phy_definitions.svh | 1 + 10 files changed, 169 insertions(+), 147 deletions(-) diff --git a/Bender.lock b/Bender.lock index 18b19499..d43c85d4 100644 --- a/Bender.lock +++ b/Bender.lock @@ -67,8 +67,8 @@ packages: dependencies: - common_cells axi_vga: - revision: 07be187d1e954d8090031b32d236ad76dc62ce45 - version: 0.1.1 + revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 + version: 0.1.3 source: Git: https://github.com/pulp-platform/axi_stream.git dependencies: @@ -124,7 +124,7 @@ packages: - redundancy_cells - tech_cells_generic ethernet: - revision: ab333c946fbfea18132904f8de0dc6702d67e741 + revision: d7d14161b8f129bccfcf9717f33760cb0a027856 version: null source: Git: git@github.com:pulp-platform/pulp-ethernet.git diff --git a/Makefile b/Makefile index 963d40c3..149dc05c 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ include cheshire.mk # Inside the repo, forward (prefixed) all, nonfree, and clean targets all: - @$(MAKE) chs-all + @$(MAKE) chs-all %-all: @$(MAKE) chs-$*-all diff --git a/cheshire.mk b/cheshire.mk index 3aec44b5..24b057f1 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -28,6 +28,7 @@ CLINTROOT := $(shell $(BENDER) path clint) AXIRTROOT := $(shell $(BENDER) path axi_rt) AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga) IDMA_ROOT := $(shell $(BENDER) path idma) +ETH_ROOT := $(shell $(BENDER) path ethernet) REGTOOL ?= $(CHS_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py @@ -48,6 +49,11 @@ ifeq ($(shell test -f $(BENDER_ROOT)/.chs_deps && echo 1),) -include $(BENDER_ROOT)/.chs_deps endif +idma-gen: + make -C $(IDMA_ROOT) idma_hw_all + make -C $(IDMA_ROOT) target/rtl/idma_reg64_2d.hjson + make -C $(ETH_ROOT) eth-gen + # Running this target will reset dependencies (without updating the checked-in Bender.lock) chs-clean-deps: rm -rf .bender @@ -190,7 +196,7 @@ include $(CHS_ROOT)/target/xilinx/xilinx.mk CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) -chs-all: $(CHS_ALL) +chs-all: $(CHS_ALL) idma-gen chs-sw-all: $(CHS_SW_ALL) chs-hw-all: $(CHS_HW_ALL) chs-bootrom-all: $(CHS_BOOTROM_ALL) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 637ce9ae..7f6e93e1 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -28,6 +28,8 @@ module cheshire_soc import cheshire_pkg::*; #( input logic test_mode_i, input logic [1:0] boot_mode_i, input logic rtc_i, + input logic eth_clk_125, + input logic eth_clk_90, // External AXI LLC (DRAM) port output axi_ext_llc_req_t axi_llc_mst_req_o, input axi_ext_llc_rsp_t axi_llc_mst_rsp_i, @@ -81,9 +83,7 @@ module cheshire_soc import cheshire_pkg::*; #( output logic eth_txck_o, output logic [3:0] eth_txd_o, output logic eth_txctl_o, - output logic eth_rstn_o, - input logic eth_intn_i, - input logic eth_pme_i, + output logic eth_rstn_o, input logic eth_mdio_i, output logic eth_mdio_o, output logic eth_mdio_oe, @@ -1395,7 +1395,9 @@ module cheshire_soc import cheshire_pkg::*; #( .reg_rsp_t ( reg_rsp_t ) ) i_tx_eth_idma_wrap ( .clk_i, - .rst_ni, + .rst_ni, + .eth_clk_i ( eth_clk_125 ), + .eth_clk90_i ( eth_clk_90 ), .phy_rx_clk_i ( eth_rxck_i ), .phy_rxd_i ( eth_rxd_i ), .phy_rx_ctl_i ( eth_rxctl_i ), @@ -1405,7 +1407,7 @@ module cheshire_soc import cheshire_pkg::*; #( .phy_resetn_o ( eth_rstn_o ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), - .phy_mdio_i ( 1'b0 ), + .phy_mdio_i ( eth_mdio_i ), .phy_mdio_o ( eth_mdio_o ), .phy_mdio_oe ( eth_mdio_oe ), .phy_mdc_o ( eth_mdc_o ), diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 6850eb10..dd8a1cd3 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -38,7 +38,6 @@ int main(void) { *tx_addr = data_to_write[i]; } - *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; @@ -52,21 +51,8 @@ int main(void) { *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1; - - // pulp_write32( ETH_BASE + IDMA_REQ_VALID_OFFSET , 0x1); - - // pulp_write32( ETH_BASE + IDMA_REQ_VALID_OFFSET , 0x0); - - - // // data - // pulp_write32( ETH_BASE + IDMA_RSP_READY_OFFSET , 0x1); - // to-do deassert rsp_ready when rx transaction is complete - - - - while(1); - - //return 0; + // can leave rsp_ready high + return 0; } diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 332e024d..cc6b1854 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -49,19 +49,19 @@ module fixture_cheshire_soc #( logic i2c_scl_i; logic i2c_scl_en; - logic eth_rxck_i; - logic [3:0] eth_rxd_i; - logic eth_rxctl_i; - logic eth_txck_o; - logic [3:0] eth_txd_o; - logic eth_txctl_o; - logic eth_rstn_o; - logic eth_intn_i; - logic eth_pme_i; + logic eth_clk_125; + logic eth_clk_90; + logic eth_rxck; + logic [3:0] eth_rxd; + logic eth_rxctl; + logic eth_txck; + logic [3:0] eth_txd; + logic eth_txctl; + logic eth_rstn; logic eth_mdio_i; logic eth_mdio_o; logic eth_mdio_en; - logic eth_mdc_o; + logic eth_mdc; logic spih_sck_o; logic spih_sck_en; @@ -129,19 +129,19 @@ module fixture_cheshire_soc #( .i2c_scl_o ( i2c_scl_o ), .i2c_scl_i ( i2c_scl_i ), .i2c_scl_en_o ( i2c_scl_en ), - .eth_rxck_i ( eth_rxck_i ), - .eth_rxd_i ( eth_rxd_i ), - .eth_rxctl_i ( eth_rxctl_i ), - .eth_txck_o ( eth_txck_o ), - .eth_txd_o ( eth_txd_o ), - .eth_txctl_o ( eth_txctl_o ), - .eth_rstn_o ( eth_rstn_o ), - .eth_intn_i ( eth_intn_i ), - .eth_pme_i ( eth_pme_i ), + .eth_clk_125 ( eth_clk_125 ), + .eth_clk_90 ( eth_clk_90 ), + .eth_rxck_i ( eth_rxck ), + .eth_rxd_i ( eth_rxd ), + .eth_rxctl_i ( eth_rxctl ), + .eth_txck_o ( eth_txck ), + .eth_txd_o ( eth_txd ), + .eth_txctl_o ( eth_txctl ), + .eth_rstn_o ( eth_rstn ), .eth_mdio_i ( eth_mdio_i ), .eth_mdio_o ( eth_mdio_o ), .eth_mdio_oe ( eth_mdio_en ), - .eth_mdc_o ( eth_mdc_o ), + .eth_mdc_o ( eth_mdc ), .spih_sck_o ( spih_sck_o ), .spih_sck_en_o ( spih_sck_en ), .spih_csb_o ( spih_csb_o ), @@ -174,15 +174,7 @@ module fixture_cheshire_soc #( wire [SpihNumCs-1:0] spih_csb; wire [ 3:0] spih_sd; - wire [ 3:0] eth_txd; - wire [ 3:0] eth_rxd; - wire eth_txck; - wire eth_rxck; - wire eth_txctl; - wire eth_rxctl; - wire eth_rstn; wire eth_mdio; - wire eth_mdc; vip_cheshire_soc_tristate vip_tristate (.*); diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 317a224e..d7d8efab 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -21,6 +21,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( parameter time ClkPeriodSys = 5ns, parameter time ClkPeriodJtag = 20ns, parameter time ClkPeriodRtc = 30518ns, + parameter time ClkPeriodEth125 = 8ns, parameter int unsigned RstCycles = 5, parameter real TAppl = 0.1, parameter real TTest = 0.9, @@ -69,15 +70,17 @@ module vip_cheshire_soc import cheshire_pkg::*; #( inout wire [SpihNumCs-1:0] spih_csb, inout wire [ 3:0] spih_sd, // Ethernet interface - inout wire [ 3:0] eth_txd, - inout wire [ 3:0] eth_rxd, - inout wire eth_txck, - inout wire eth_rxck, - inout wire eth_txctl, - inout wire eth_rxctl, - inout wire eth_rstn, - inout wire eth_mdio, - inout wire eth_mdc, + output logic eth_clk_125, + output logic eth_clk_90, + input logic [ 3:0] eth_txd, + output logic [ 3:0] eth_rxd, + input logic eth_txck, + output logic eth_rxck, + input logic eth_txctl, + output logic eth_rxctl, + input logic eth_rstn, + inout logic eth_mdio, + input logic eth_mdc, // Serial link interface output logic [SlinkNumChan-1:0] slink_rcv_clk_i, input logic [SlinkNumChan-1:0] slink_rcv_clk_o, @@ -649,21 +652,23 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .reg_req_t ( reg_req_t ), .reg_rsp_t ( reg_rsp_t ) ) i_rx_eth_idma_wrap ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .phy_rx_clk_i ( eth_txck ), - .phy_rxd_i ( eth_txd ), - .phy_rx_ctl_i ( eth_txctl ), - .phy_tx_clk_o ( eth_rxck ), - .phy_txd_o ( eth_rxd ), - .phy_tx_ctl_o ( eth_rxctl ), - .phy_resetn_o ( eth_rstn ), + .clk_i ( clk ), + .rst_ni ( rst_n ), + .eth_clk_i ( eth_clk_125 ), + .eth_clk90_i ( eth_clk_90 ), + .phy_rx_clk_i ( eth_txck ), + .phy_rxd_i ( eth_txd ), + .phy_rx_ctl_i ( eth_txctl ), + .phy_tx_clk_o ( eth_rxck ), + .phy_txd_o ( eth_rxd ), + .phy_tx_ctl_o ( eth_rxctl ), + .phy_resetn_o ( eth_rstn ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), - .phy_mdio_i ( 1'b0 ), - .phy_mdio_o ( ), - .phy_mdio_oe ( ), - .phy_mdc_o ( ), + .phy_mdio_i ( eth_mdio_i ), + .phy_mdio_o ( eth_mdio_o ), + .phy_mdio_oe ( eth_mdio_oe ), + .phy_mdc_o ( eth_mdc ), .reg_req_i ( reg_bus_rx_req ), .reg_rsp_o ( reg_bus_rx_rsp ), .testmode_i ( 1'b0 ), @@ -703,12 +708,30 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .mon_w_addr_o ( /* NOT CONNECTED */ ), .mon_w_valid_o ( /* NOT CONNECTED */ ) ); - + initial begin + forever begin + eth_clk_125 <= 0; + #(ClkPeriodEth125/2); + eth_clk_125 <= 1; + #(ClkPeriodEth125/2); + end + end - @(posedge clk); + initial begin + forever begin + eth_clk_90 <= 0; + #(ClkPeriodEth125/4); + eth_clk_90 <= 1; + #(ClkPeriodEth125/2); + eth_clk_90 <= 0; + #(ClkPeriodEth125/4); + end + end - $readmemh("/scratch/chaol/cheshire/target/sim/src/rx_mem_init.vmem", i_rx_axi_sim_mem.mem); + initial begin + @(posedge clk); + $readmemh("rx_mem_init.vmem", i_rx_axi_sim_mem.mem); @(posedge clk); reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address @@ -732,37 +755,21 @@ module vip_cheshire_soc import cheshire_pkg::*; #( reg_drv_rx.send_write( 'h0300c020, 32'h0,'hf , reg_error); // dst protocol @(posedge clk); - // @(posedge data_ready); + reg_drv_rx.send_write( 'h0300c038, 'h1, 'hf , reg_error); // req valid + @(posedge clk); - //#9000ns; + reg_drv_rx.send_write( 'h0300c040, 'h1, 'hf, reg_error); - // while(1) begin - // reg_drv_rx.send_read( 'h3000003c, rx_req_ready, reg_error); - // if(rx_req_ready) begin - reg_drv_rx.send_write( 'h0300c038, 'h1, 'hf , reg_error); // req valid + while(1) begin + reg_drv_rx.send_read( 'h0300c044, rx_rsp_valid, reg_error); + if(rx_rsp_valid) begin + reg_drv_rx.send_write( 'h0300c040, 32'h0, 'hf , reg_error); + @(posedge clk); + break; + end @(posedge clk); -// break; -// end -// @(posedge clk_i); -// end - -@(posedge clk); - - -reg_drv_rx.send_write( 'h0300c040, 'h1, 'hf, reg_error); //rsp ready -//repeat(25)@(posedge clk_i); -//reg_drv_rx.send_write( 'h30000038, 'h0, 'hf , reg_error); // req valid - -while(1) begin -reg_drv_rx.send_read( 'h0300c044, rx_rsp_valid, reg_error); - if(rx_rsp_valid) begin -reg_drv_rx.send_write( 'h0300c040, 32'h0, 'hf , reg_error); -@(posedge clk); -break; -end -@(posedge clk); -end - end + end +end /////////////////// // Serial Link // @@ -1103,18 +1110,9 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( input logic [ 3:0] spih_sd_o, input logic [ 3:0] spih_sd_en, // Ethernet pad IO - output logic [3:0] eth_rxd_i, - input logic [3:0] eth_txd_o, - output logic eth_rxck_i, - input logic eth_txck_o, - output logic eth_rxctl_i, - input logic eth_txctl_o, - input logic eth_rstn_o, input logic eth_mdio_o, output logic eth_mdio_i, - input logic eth_mdio_en, - input logic eth_mdc_o, - + input logic eth_mdio_en, // I2C wires inout wire i2c_sda, inout wire i2c_scl, @@ -1123,15 +1121,7 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( inout wire [SpihNumCs-1:0] spih_csb, inout wire [ 3:0] spih_sd, // Ethernet wires - inout wire [ 3:0] eth_txd, - inout wire [ 3:0] eth_rxd, - inout wire eth_txck, - inout wire eth_rxck, - inout wire eth_txctl, - inout wire eth_rxctl, - inout wire eth_rstn, - inout wire eth_mdio, - inout wire eth_mdc + input wire eth_mdio ); // I2C @@ -1158,15 +1148,6 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( end // Ethernet - assign eth_txd = eth_txd_o; - assign eth_txck = eth_txck_o; - assign eth_txctl = eth_txctl_o; - assign eth_mdc = eth_mdc_o; - assign eth_rxd_i = eth_rxd; - assign eth_rxck_i = eth_rxck; - assign eth_rxctl_i = eth_rxctl; - - bufif1 (eth_mdio_i, eth_mdio, ~eth_mdio_en); bufif1 (eth_mdio, eth_mdio_o, eth_mdio_en); diff --git a/target/xilinx/scripts/impl_ip.tcl b/target/xilinx/scripts/impl_ip.tcl index 474787fe..1dc82bec 100644 --- a/target/xilinx/scripts/impl_ip.tcl +++ b/target/xilinx/scripts/impl_ip.tcl @@ -24,13 +24,15 @@ switch $proj { CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ - CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT1_PORT {clk_200} \ CONFIG.CLK_OUT2_PORT {clk_50} \ - CONFIG.CLK_OUT3_PORT {clk_20} \ - CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLK_OUT3_PORT {clk_125} \ + CONFIG.CLK_OUT4_PORT {clk_125_90} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ - CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {125.000} \ + CONFIG.CLKOUT4_REQUESTED_PHASE {90.000} \ CONFIG.CLKIN1_JITTER_PS {50.0} \ CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 4e93b2bc..3fc87696 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -48,6 +48,18 @@ module cheshire_top_xilinx ( inout wire i2c_sda_io, `endif +`ifdef USE_ETHERNET + input wire eth_rxck, + input wire [3:0] eth_rxd, + input wire eth_rxctl, + output wire eth_txck, + output wire [3:0] eth_txd, + output wire eth_txctl, + output wire eth_rst_n, + output wire eth_mdc, + inout wire eth_mdio, +`endif + `ifdef USE_SD input logic sd_cd_i, output logic sd_cmd_o, @@ -101,6 +113,7 @@ module cheshire_top_xilinx ( endfunction // Configure cheshire for FPGA mapping + localparam cheshire_cfg_t FPGACfg = gen_cheshire_xilinx_cfg(); `CHESHIRE_TYPEDEF_ALL(, FPGACfg) @@ -110,6 +123,8 @@ module cheshire_top_xilinx ( wire sys_clk; wire soc_clk; + logic eth_clk_125; + logic eth_clk_90; IBUFDS #( .IBUF_LOW_PWR ("FALSE") @@ -120,13 +135,13 @@ module cheshire_top_xilinx ( ); clkwiz i_clkwiz ( - .clk_in1 ( sys_clk ), - .reset ( '0 ), - .locked ( ), - .clk_100 ( ), - .clk_50 ( soc_clk ), - .clk_20 ( ), - .clk_10 ( ) + .clk_in1 ( sys_clk ), + .reset ( '0 ), + .locked ( ), + .clk_200 ( ), + .clk_50 ( soc_clk ), + .clk_125 ( eth_clk_125 ), + .clk_125_90 ( eth_clk_90 ) ); ///////////////////// @@ -236,8 +251,32 @@ module cheshire_top_xilinx ( .I ( i2c_sda_soc_out ), .T ( ~i2c_sda_en ) ); + `endif + + /////////////////////// + // Ethernet Adaption // + ////////////////////// +`ifdef USE_ETHERNET + + logic eth_mdio_i; + logic eth_mdio_o; + logic eth_mdio_oe; + + IOBUF #( + .DRIVE ( 12 ), // Specify the output drive strength + .IBUF_LOW_PWR ( "FALSE" ), // Low Power - "TRUE", High Performance = "FALSE" + .IOSTANDARD ( "DEFAULT" ), // Specify the I/O standard + .SLEW ( "FAST" ) // Specify the output slew rate + ) i_md_iobuf ( + .O ( eth_mdio_i ), // Buffer output + .IO ( eth_mdio ), // Buffer inout port (connect directly to top-level port) + .I ( eth_mdio_o ), // Buffer input + .T ( ~eth_mdio_oe ) // 3-state enable input, high=input, low=output + ); + `endif + /////////////// // SPI to SD // /////////////// @@ -446,6 +485,19 @@ module cheshire_top_xilinx ( .i2c_scl_o ( i2c_scl_soc_out ), .i2c_scl_i ( i2c_scl_soc_in ), .i2c_scl_en_o ( i2c_scl_en ), + .eth_clk_125 ( eth_clk_125 ), + .eth_clk_90 ( eth_clk_90 ), + .eth_rxck_i ( eth_rxck ), + .eth_rxd_i ( eth_rxd ), + .eth_rxctl_i ( eth_rxctl ), + .eth_txck_o ( eth_txck ), + .eth_txd_o ( eth_txd ), + .eth_txctl_o ( eth_txctl ), + .eth_rstn_o ( eth_rstn ), + .eth_mdio_i ( eth_mdio_i ), + .eth_mdio_o ( eth_mdio_o ), + .eth_mdio_oe ( eth_mdio_en ), + .eth_mdc_o ( eth_mdc ), .spih_sck_o ( spi_sck_soc ), .spih_sck_en_o ( spi_sck_en ), .spih_csb_o ( spi_cs_soc ), diff --git a/target/xilinx/src/phy_definitions.svh b/target/xilinx/src/phy_definitions.svh index a4d7798d..bd14caf3 100644 --- a/target/xilinx/src/phy_definitions.svh +++ b/target/xilinx/src/phy_definitions.svh @@ -25,6 +25,7 @@ `define USE_VIO `define USE_I2C `define USE_VGA + `define USE_ETHERNET `endif `ifdef TARGET_ZCU102 From 425304e4698c762a5b456779da1976f616e2ad60 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sun, 14 Apr 2024 12:01:56 +0200 Subject: [PATCH 15/48] update ethernet with idma v0.6.0 --- Bender.lock | 4 ++-- cheshire.mk | 10 +++++----- hw/cheshire_pkg.sv | 1 + hw/cheshire_soc.sv | 26 +++++++------------------ hw/rv_plic.cfg.hjson | 2 +- sw/boot/cheshire.dtsi | 8 ++++++++ sw/tests/ethernet.c | 31 ++++++++++++++++++++---------- target/sim/src/vip_cheshire_soc.sv | 22 ++++++++++----------- 8 files changed, 56 insertions(+), 48 deletions(-) diff --git a/Bender.lock b/Bender.lock index d43c85d4..4ed4cff7 100644 --- a/Bender.lock +++ b/Bender.lock @@ -63,7 +63,7 @@ packages: revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 version: 0.1.3 source: - Git: git@github.com:pulp-platform/axi_stream.git + Git: https://github.com/pulp-platform/axi_stream.git dependencies: - common_cells axi_vga: @@ -124,7 +124,7 @@ packages: - redundancy_cells - tech_cells_generic ethernet: - revision: d7d14161b8f129bccfcf9717f33760cb0a027856 + revision: e3cf735a8df0ecb8e446631386d2d814899a41af version: null source: Git: git@github.com:pulp-platform/pulp-ethernet.git diff --git a/cheshire.mk b/cheshire.mk index 24b057f1..aa7763a7 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -49,10 +49,10 @@ ifeq ($(shell test -f $(BENDER_ROOT)/.chs_deps && echo 1),) -include $(BENDER_ROOT)/.chs_deps endif -idma-gen: - make -C $(IDMA_ROOT) idma_hw_all - make -C $(IDMA_ROOT) target/rtl/idma_reg64_2d.hjson - make -C $(ETH_ROOT) eth-gen +#idma-gen: +# make -C $(IDMA_ROOT) idma_hw_all +# make -C $(IDMA_ROOT) target/rtl/idma_reg64_2d.hjson +# make -C $(ETH_ROOT) eth-gen # Running this target will reset dependencies (without updating the checked-in Bender.lock) chs-clean-deps: @@ -196,7 +196,7 @@ include $(CHS_ROOT)/target/xilinx/xilinx.mk CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) -chs-all: $(CHS_ALL) idma-gen +chs-all: $(CHS_ALL) #idma-gen chs-sw-all: $(CHS_SW_ALL) chs-hw-all: $(CHS_HW_ALL) chs-bootrom-all: $(CHS_BOOTROM_ALL) diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 488a4592..aa41661a 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -230,6 +230,7 @@ package cheshire_pkg; typedef struct packed { cheshire_bus_err_intr_t bus_err; logic [31:0] gpio; + logic ethernet; logic spih_spi_event; logic spih_error; logic i2c_host_timeout; diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 7f6e93e1..adda02c3 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1396,8 +1396,8 @@ module cheshire_soc import cheshire_pkg::*; #( ) i_tx_eth_idma_wrap ( .clk_i, .rst_ni, - .eth_clk_i ( eth_clk_125 ), - .eth_clk90_i ( eth_clk_90 ), + .eth_clk125_i ( eth_clk_125 ), + .eth_clk125q_i ( eth_clk_90 ), .phy_rx_clk_i ( eth_rxck_i ), .phy_rxd_i ( eth_rxd_i ), .phy_rx_ctl_i ( eth_rxctl_i ), @@ -1415,26 +1415,14 @@ module cheshire_soc import cheshire_pkg::*; #( .axi_req_o ( axi_in_req[AxiIn.eth_idma] ), .axi_rsp_i ( axi_in_rsp[AxiIn.eth_idma] ), .reg_req_i ( reg_out_req[RegOut.ethernet] ), - .reg_rsp_o ( reg_out_rsp[RegOut.ethernet] ) // req from cheshire def, but inside ethernet, it awaits for the type + .reg_rsp_o ( reg_out_rsp[RegOut.ethernet] ), + .eth_irq_o ( intr.intn.ethernet ) ); end else begin : gen_no_ethernet - - assign axi_in_rsp[AxiIn.eth_idma].aw_ready = 1'b1; - assign axi_in_rsp[AxiIn.eth_idma].ar_ready = 1'b1; - assign axi_in_rsp[AxiIn.eth_idma].w_ready = 1'b1; - - // assign axi_in_rsp[AxiIn.eth_idma].b_valid = axi_in_req[AxiIn.eth_idma].aw_valid; - // assign axi_in_rsp[AxiIn.eth_idma].b_id = axi_in_req[AxiIn.eth_idma].aw_id; - // assign axi_in_rsp[AxiIn.eth_idma].b_resp = axi_pkg::RESP_SLVERR; - // assign axi_in_rsp[AxiIn.eth_idma].b_user = '0; - - assign axi_in_rsp[AxiIn.eth_idma].r_valid = axi_in_req[AxiIn.eth_idma].ar_valid; - // assign axi_in_rsp[AxiIn.eth_idma].r_resp = axi_pkg::RESP_SLVERR; - // assign axi_in_rsp[AxiIn.eth_idma].r_data = 'hdeadbeef; - // assign axi_in_rsp[AxiIn.eth_idma].r_last = 1'b1; - - end + assign intr.intn.ethernet = 1'b0; + assign eth_txck_o = 1'b0; + end //////////////// // SPI Host // diff --git a/hw/rv_plic.cfg.hjson b/hw/rv_plic.cfg.hjson index 6d16a80c..865be3a9 100644 --- a/hw/rv_plic.cfg.hjson +++ b/hw/rv_plic.cfg.hjson @@ -7,7 +7,7 @@ { instance_name: "rv_plic", param_values: { - src: 57, + src: 58, target: 2, // We need *two targets* per hart: M and S modes prio: 7, nonstd_regs: 0 // Do *not* include these: MSIPs are not used and we use a 64 MiB address space diff --git a/sw/boot/cheshire.dtsi b/sw/boot/cheshire.dtsi index 76decc85..eb27a3d2 100644 --- a/sw/boot/cheshire.dtsi +++ b/sw/boot/cheshire.dtsi @@ -107,5 +107,13 @@ riscv,ndev = <51>; reg = <0x0 0x4000000 0x0 0x4000000>; }; + eth: idma-eth@300c000 { + compatible = "idma-eth"; + device_type = "network"; + interrupt-parent = <&PLIC0>; + interrupts = <19>; + local-mac-address = [00 18 3e 02 e3 7f]; // This needs to change if more than one GenesysII on a VLAN + reg = <0x0 0x300c000 0x0 0x1000>; + }; }; }; diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index dd8a1cd3..79c8ba80 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -7,19 +7,25 @@ #define MACLO_OFFSET 0x0 #define MACHI_OFFSET 0x4 +#define IRQ_OFFSET 0x10 +#define IDMA_SRC_ADDR_OFFSET 0x14 +#define IDMA_DST_ADDR_OFFSET 0x18 +#define IDMA_LENGTH_OFFSET 0x1c +#define IDMA_SRC_PROTO_OFFSET 0x20 +#define IDMA_DST_PROTO_OFFSET 0x24 +#define IDMA_REQ_VALID_OFFSET 0x3c +#define IDMA_REQ_READY_OFFSET 0x40 +#define IDMA_RSP_READY_OFFSET 0x44 +#define IDMA_RSP_VALID_OFFSET 0x48 +#define PRINTF_ON -#define IDMA_SRC_ADDR_OFFSET 0x10 -#define IDMA_DST_ADDR_OFFSET 0x14 -#define IDMA_LENGTH_OFFSET 0x18 -#define IDMA_SRC_PROTO_OFFSET 0x1c -#define IDMA_DST_PROTO_OFFSET 0x20 -#define IDMA_REQ_VALID_OFFSET 0x38 -#define IDMA_REQ_READY_OFFSET 0x3c -#define IDMA_RSP_READY_OFFSET 0x40 -#define IDMA_RSP_VALID_OFFSET 0x44 int main(void) { - + + #ifdef PRINTF_ON + printf ("Start test Ethernet...\n\r"); + #endif + volatile uint64_t data_to_write[8] = { 0x1032207098001032, 0x3210E20020709800, @@ -51,6 +57,11 @@ int main(void) { *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1; + + + while (!(*reg32(ETH_BASE, IRQ_OFFSET))); + + printf ("Ethernet test pass..\n\r"); // can leave rsp_ready high return 0; diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index d7d8efab..f94f5ebf 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -654,8 +654,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( ) i_rx_eth_idma_wrap ( .clk_i ( clk ), .rst_ni ( rst_n ), - .eth_clk_i ( eth_clk_125 ), - .eth_clk90_i ( eth_clk_90 ), + .eth_clk125_i ( eth_clk_125 ), + .eth_clk125q_i ( eth_clk_90 ), .phy_rx_clk_i ( eth_txck ), .phy_rxd_i ( eth_txd ), .phy_rx_ctl_i ( eth_txctl ), @@ -740,30 +740,30 @@ module vip_cheshire_soc import cheshire_pkg::*; #( reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); - reg_drv_rx.send_write( 'h0300c010, 32'h0, 'hf, reg_error ); // SRC_ADDR + reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); - reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error); // DST_ADDR + reg_drv_rx.send_write( 'h0300c018, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge clk); - reg_drv_rx.send_write( 'h0300c018, 32'h40,'hf , reg_error); // Size in bytes + reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes @(posedge clk); - reg_drv_rx.send_write( 'h0300c01c, 32'h5,'hf , reg_error); // src protocol + reg_drv_rx.send_write( 'h0300c020, 32'h5,'hf , reg_error); // src protocol @(posedge clk); - reg_drv_rx.send_write( 'h0300c020, 32'h0,'hf , reg_error); // dst protocol + reg_drv_rx.send_write( 'h0300c024, 32'h0,'hf , reg_error); // dst protocol @(posedge clk); - reg_drv_rx.send_write( 'h0300c038, 'h1, 'hf , reg_error); // req valid + reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid @(posedge clk); - reg_drv_rx.send_write( 'h0300c040, 'h1, 'hf, reg_error); + reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf, reg_error); while(1) begin - reg_drv_rx.send_read( 'h0300c044, rx_rsp_valid, reg_error); + reg_drv_rx.send_read( 'h0300c048, rx_rsp_valid, reg_error); if(rx_rsp_valid) begin - reg_drv_rx.send_write( 'h0300c040, 32'h0, 'hf , reg_error); + reg_drv_rx.send_write( 'h0300c044, 32'h0, 'hf , reg_error); @(posedge clk); break; end From 3bbc33a9ee86e96d8f1579f7b8da32f8f5f6bb75 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sun, 14 Apr 2024 12:29:43 +0200 Subject: [PATCH 16/48] fix --- sw/boot/cheshire.dtsi | 16 ++++++++-------- sw/tests/ethernet.c | 10 +++++----- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/sw/boot/cheshire.dtsi b/sw/boot/cheshire.dtsi index eb27a3d2..39426437 100644 --- a/sw/boot/cheshire.dtsi +++ b/sw/boot/cheshire.dtsi @@ -107,13 +107,13 @@ riscv,ndev = <51>; reg = <0x0 0x4000000 0x0 0x4000000>; }; - eth: idma-eth@300c000 { - compatible = "idma-eth"; - device_type = "network"; - interrupt-parent = <&PLIC0>; - interrupts = <19>; - local-mac-address = [00 18 3e 02 e3 7f]; // This needs to change if more than one GenesysII on a VLAN - reg = <0x0 0x300c000 0x0 0x1000>; - }; + #eth: idma-eth@300c000 { + #compatible = "idma-eth"; + #device_type = "network"; + #interrupt-parent = <&PLIC0>; + #interrupts = <19>; + #local-mac-address = [00 18 3e 02 e3 7f]; // This needs to change if more than one GenesysII on a VLAN + #reg = <0x0 0x300c000 0x0 0x1000>; + #}; }; }; diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 79c8ba80..f7dee4ee 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -17,14 +17,14 @@ #define IDMA_REQ_READY_OFFSET 0x40 #define IDMA_RSP_READY_OFFSET 0x44 #define IDMA_RSP_VALID_OFFSET 0x48 -#define PRINTF_ON +//#define PRINTF_ON int main(void) { - #ifdef PRINTF_ON - printf ("Start test Ethernet...\n\r"); - #endif + // #ifdef PRINTF_ON + // printf ("Start test Ethernet...\n\r"); + // #endif volatile uint64_t data_to_write[8] = { 0x1032207098001032, @@ -59,7 +59,7 @@ int main(void) { *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1; - while (!(*reg32(ETH_BASE, IRQ_OFFSET))); + //while (!(*reg32(ETH_BASE, IRQ_OFFSET))); printf ("Ethernet test pass..\n\r"); From b9c51e4df898a3f0d233713551432d48f13b82eb Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sun, 14 Apr 2024 23:04:46 +0200 Subject: [PATCH 17/48] multiple fixes --- Bender.lock | 10 +--------- hw/cheshire_pkg.sv | 6 +++--- hw/cheshire_soc.sv | 4 ++-- target/sim/src/tb_cheshire_pkg.sv | 2 +- target/sim/vsim/start.cheshire_soc.tcl | 2 +- 5 files changed, 8 insertions(+), 16 deletions(-) diff --git a/Bender.lock b/Bender.lock index 4ed4cff7..c41222cd 100644 --- a/Bender.lock +++ b/Bender.lock @@ -34,13 +34,6 @@ packages: - common_verification - register_interface - tech_cells_generic - axi_mem_if: - revision: 3567273b4f67bd57a81a2a503394a49641bae53a - version: 0.2.1 - source: - Git: git@github.com:pulp-platform/axi_mem_if.git - dependencies: - - axi axi_riscv_atomics: revision: 6a85f44fdb1fe93162de7241476bba81e2247cb5 version: null @@ -124,13 +117,12 @@ packages: - redundancy_cells - tech_cells_generic ethernet: - revision: e3cf735a8df0ecb8e446631386d2d814899a41af + revision: ca7feb6e5722aaec7bdb6d71d4cfddfe58f18afd version: null source: Git: git@github.com:pulp-platform/pulp-ethernet.git dependencies: - axi - - axi_mem_if - axi_stream - common_cells - common_verification diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index aa41661a..97f6eb04 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -314,7 +314,7 @@ package cheshire_pkg; aw_bt vga; aw_bt ext_base; aw_bt num_in; - aw_bt eth_idma; + aw_bt eth; } axi_in_t; function automatic axi_in_t gen_axi_in(cheshire_cfg_t cfg); @@ -325,7 +325,7 @@ package cheshire_pkg; if (cfg.Dma) begin i++; ret.dma = i; end if (cfg.SerialLink) begin i++; ret.slink = i; end if (cfg.Vga) begin i++; ret.vga = i; end - if (cfg.Ethernet) begin i++; ret.eth_idma = i; end + if (cfg.Ethernet) begin i++; ret.eth = i; end i++; ret.ext_base = i; ret.num_in = i + cfg.AxiExtNumMst; @@ -636,7 +636,7 @@ package cheshire_pkg; Dma : 0, SerialLink : 1, Vga : 1, - AxiRt : 0, + AxiRt : 1, Clic : 0, IrqRouter : 0, BusErr : 1, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index adda02c3..beb18e54 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1412,8 +1412,8 @@ module cheshire_soc import cheshire_pkg::*; #( .phy_mdio_oe ( eth_mdio_oe ), .phy_mdc_o ( eth_mdc_o ), .testmode_i ( 1'b0 ), - .axi_req_o ( axi_in_req[AxiIn.eth_idma] ), - .axi_rsp_i ( axi_in_rsp[AxiIn.eth_idma] ), + .axi_req_o ( axi_in_req[AxiIn.eth] ), + .axi_rsp_i ( axi_in_rsp[AxiIn.eth] ), .reg_req_i ( reg_out_req[RegOut.ethernet] ), .reg_rsp_o ( reg_out_rsp[RegOut.ethernet] ), .eth_irq_o ( intr.intn.ethernet ) diff --git a/target/sim/src/tb_cheshire_pkg.sv b/target/sim/src/tb_cheshire_pkg.sv index 962ee3fc..77ab78a2 100644 --- a/target/sim/src/tb_cheshire_pkg.sv +++ b/target/sim/src/tb_cheshire_pkg.sv @@ -12,7 +12,7 @@ package tb_cheshire_pkg; // A dedicated RT config function automatic cheshire_cfg_t gen_cheshire_rt_cfg(); cheshire_cfg_t ret = DefaultCfg; - ret.AxiRt = 0; + ret.AxiRt = 1; return ret; endfunction diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index 4b5ab7b8..f9d6cad2 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -12,7 +12,7 @@ set TESTBENCH tb_cheshire_soc # Set voptargs only if not already set to make overridable. # Default on fast simulation flags. if {![info exists VOPTARGS]} { - set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +acc=p+cheshire_soc. +acc=r+stream_xbar" + set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" } set flags "-permissive -suppress 3009 -suppress 8386 -error 7 " From 111cb7d95188166e64f510fdb11b288d35b1c178 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 16 Apr 2024 17:54:10 +0200 Subject: [PATCH 18/48] plic added --- Bender.lock | 2 +- Makefile | 2 +- sw/tests/ethernet.c | 49 +++++++++++++++----------- target/sim/src/vip_cheshire_soc.sv | 2 +- target/sim/vsim/start.cheshire_soc.tcl | 2 +- 5 files changed, 33 insertions(+), 24 deletions(-) diff --git a/Bender.lock b/Bender.lock index c41222cd..71b7e36b 100644 --- a/Bender.lock +++ b/Bender.lock @@ -120,7 +120,7 @@ packages: revision: ca7feb6e5722aaec7bdb6d71d4cfddfe58f18afd version: null source: - Git: git@github.com:pulp-platform/pulp-ethernet.git + Git: https://github.com/pulp-platform/pulp-ethernet.git dependencies: - axi - axi_stream diff --git a/Makefile b/Makefile index 149dc05c..963d40c3 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ include cheshire.mk # Inside the repo, forward (prefixed) all, nonfree, and clean targets all: - @$(MAKE) chs-all + @$(MAKE) chs-all %-all: @$(MAKE) chs-$*-all diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index f7dee4ee..80b9b709 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -1,6 +1,7 @@ #include #include #include +#include "printf.h" #include "util.h" #define ETH_BASE 0x0300c000 @@ -17,14 +18,27 @@ #define IDMA_REQ_READY_OFFSET 0x40 #define IDMA_RSP_READY_OFFSET 0x44 #define IDMA_RSP_VALID_OFFSET 0x48 -//#define PRINTF_ON +#define PLIC_BASE 0x04000000 +#define RV_PLIC_PRIO19_REG_OFFSET 0x4c +#define RV_PLIC_IE0_0_REG_OFFSET 0x2000 +#define RV_PLIC_CC0_REG_OFFSET 0x200004 +#define RV_PLIC_IE0_0_E_19_BIT 19 +#define PLIC_ENABLE_REG_BASE PLIC_BASE + RV_PLIC_IE0_0_REG_OFFSET +#define PLIC_CLAIM_COMPLETE_BASE PLIC_BASE + RV_PLIC_CC0_REG_OFFSET -int main(void) { +#define RV_PLIC_IP_0_OFFSET 0x1000 + +#define PRINTF_ON + +int main(void) { - // #ifdef PRINTF_ON - // printf ("Start test Ethernet...\n\r"); - // #endif + #ifdef PRINTF_ON + printf ("Start test Ethernet...\n\r"); + #endif + + *reg32(PLIC_BASE, RV_PLIC_PRIO19_REG_OFFSET) = 1; + *reg32(PLIC_BASE, RV_PLIC_IE0_0_REG_OFFSET) |= (1 << (RV_PLIC_IE0_0_E_19_BIT)); // Enable interrupt number ; volatile uint64_t data_to_write[8] = { 0x1032207098001032, @@ -35,35 +49,30 @@ int main(void) { 0x4746454443424140, 0x5756555453525150, 0x6766656463626160 - }; + }; // load data into mem for (int i = 0; i < 8; ++i) { - volatile uint64_t *tx_addr = (volatile uint64_t*)(0x14000000 + i * sizeof(uint64_t)); *tx_addr = data_to_write[i]; } + + *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; - *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; - - *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET)= 0x14000000; - *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET)= 0x0; - *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = 0x40; + *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x14000000; + *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = 0x0; + *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = 0x40; *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x5; - *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1; + while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); - //while (!(*reg32(ETH_BASE, IRQ_OFFSET))); - - printf ("Ethernet test pass..\n\r"); - - // can leave rsp_ready high + printf ("Ethernet test pass...\n\r"); return 0; - } + diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index f94f5ebf..7827b07a 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -665,7 +665,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .phy_resetn_o ( eth_rstn ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), - .phy_mdio_i ( eth_mdio_i ), + .phy_mdio_i ( 1'b0 ), .phy_mdio_o ( eth_mdio_o ), .phy_mdio_oe ( eth_mdio_oe ), .phy_mdc_o ( eth_mdc ), diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index f9d6cad2..e1fb5789 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -12,7 +12,7 @@ set TESTBENCH tb_cheshire_soc # Set voptargs only if not already set to make overridable. # Default on fast simulation flags. if {![info exists VOPTARGS]} { - set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" + set VOPTARGS "+acc" } set flags "-permissive -suppress 3009 -suppress 8386 -error 7 " From 145549289451cc847b4a3c191af38f143415795a Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 16 Apr 2024 19:31:50 +0200 Subject: [PATCH 19/48] undo a crime --- target/sim/vsim/start.cheshire_soc.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index e1fb5789..f9d6cad2 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -12,7 +12,7 @@ set TESTBENCH tb_cheshire_soc # Set voptargs only if not already set to make overridable. # Default on fast simulation flags. if {![info exists VOPTARGS]} { - set VOPTARGS "+acc" + set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" } set flags "-permissive -suppress 3009 -suppress 8386 -error 7 " From 2f0d7d6b97d9e2f108c4ab798472b99e712eb712 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 17 Apr 2024 09:15:41 +0200 Subject: [PATCH 20/48] idma wrapper --- hw/idma_core_wrap.sv | 229 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 hw/idma_core_wrap.sv diff --git a/hw/idma_core_wrap.sv b/hw/idma_core_wrap.sv new file mode 100644 index 00000000..3e21d3c0 --- /dev/null +++ b/hw/idma_core_wrap.sv @@ -0,0 +1,229 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +`include "idma/typedef.svh" +`include "axi/typedef.svh" + +module idma_wrap import idma_pkg::*; #( + parameter int unsigned BufferDepth = 3, + parameter int unsigned NumAxInFlight = 3, + parameter int unsigned TFLenWidth = 32, + parameter int unsigned MemSysDepth = 0, + parameter int unsigned AXI_MemNumReqOutst = 1, + parameter int unsigned AXI_MemLatency = 0, + parameter int unsigned WatchDogNumCycles = 100, + parameter int unsigned NumDim = 3, + parameter bit CombinedShifter = 1'b0, + parameter bit MaskInvalidData = 1, + parameter bit RAWCouplingAvail = 1, + parameter bit HardwareLegalizer = 1, + parameter bit RejectZeroTransfers = 1, + parameter bit ErrorHandling = 0, + parameter bit DmaTracing = 1, + parameter bit PrintFifoInfo = 1'b0, + parameter int unsigned RegAddrWidth = 32, + parameter int unsigned RegDataWidth = 32, + parameter int unsigned AxiAddrWidth = 64, + parameter int unsigned AxiDataWidth = 32, + parameter int unsigned AxiIdWidth = 7, + parameter int unsigned AxiUserWidth = 1, + parameter int unsigned StrideWidth = 32, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic, + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + output axi_req_t axi_read_req_o, + input axi_rsp_t axi_read_rsp_i, + output axi_req_t axi_write_req_o, + input axi_rsp_t axi_write_rsp_i +); + + // dependent parameters + localparam logic [2:0][31:0] RepWidth = '{default: 32'd32}; + localparam int unsigned IdCounterWidth = 16; + localparam int unsigned AxiStrbWidth = AxiDataWidth / 8; + localparam int unsigned RegStrbWidth = RegDataWidth / 8; + localparam idma_pkg::error_cap_e ErrorCap = ErrorHandling ? idma_pkg::ERROR_HANDLING : + idma_pkg::NO_ERROR_HANDLING; + + localparam int unsigned MstIdWidth = AxiIdWidth; + localparam int unsigned SlvIdWidth = AxiIdWidth - $clog2(2); + + typedef logic [AxiDataWidth/8-1:0] axi_strb_t; + typedef logic [AxiDataWidth-1:0] axi_data_t; + typedef logic [AxiAddrWidth-1:0] axi_addr_t; + typedef logic [AxiUserWidth-1:0] axi_user_t; + typedef logic [MstIdWidth-1:0] axi_id_t; + typedef logic [SlvIdWidth-1:0] slv_id_t; + + typedef logic [31:0] reps_t; + typedef logic [StrideWidth-1:0] strides_t; + + // AXI4+ATOP channels typedefs + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) + + `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, axi_addr_t, axi_id_t, axi_user_t) + `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, axi_addr_t, axi_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, axi_data_t, axi_id_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, axi_id_t, axi_user_t) + + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_rsp_t, slv_b_chan_t, slv_r_chan_t) + + //iDMA defines + `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, axi_id_t, axi_addr_t, axi_addr_t) + `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, axi_addr_t) + `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, reps_t, strides_t) + + typedef struct packed { + slv_ar_chan_t ar_chan; + } axi_read_meta_channel_t; + + typedef struct packed { + axi_read_meta_channel_t axi; + } read_meta_channel_t; + + typedef struct packed { + slv_aw_chan_t aw_chan; + } axi_write_meta_channel_t; + + typedef struct packed { + axi_write_meta_channel_t axi; + } write_meta_channel_t; + + idma_req_t be_idma_req; + idma_rsp_t be_idma_rsp; + idma_nd_req_t fe_idma_req; + + logic idma_nd_rsp_valid; + logic idma_nd_rsp_ready; + logic issue_id; + logic retire_id; + + idma_pkg::idma_busy_t busy; + logic me_busy; + + logic fe_req_valid, fe_req_ready; + logic be_req_valid, be_req_ready; + + logic [IdCounterWidth-1:0] done_id, next_id; + + idma_reg64_2d #( + .NumRegs ( 32'd1 ), + .NumStreams ( 32'd1 ), + .IdCounterWidth ( IdCounterWidth ), + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ), + .dma_req_t ( idma_nd_req_t ) + ) idma_frontend ( + .clk_i, + .rst_ni, + .dma_ctrl_req_i ( reg_req_i ), + .dma_ctrl_rsp_o ( reg_rsp_o ), + .dma_req_o ( fe_idma_req ), + .req_valid_o ( fe_req_valid ), + .req_ready_i ( fe_req_ready ), + .next_id_i ( next_id ), + .stream_idx_o ( ), + .done_id_i ( done_id ), + .busy_i ( busy ), + .midend_busy_i ( me_busy ) + ); + + idma_nd_midend #( + .NumDim ( NumDim ), + .addr_t ( axi_addr_t ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_nd_req_t ( idma_nd_req_t ), + .RepWidths ( RepWidth ) + ) idma_midend_i ( + .clk_i, + .rst_ni, + .nd_req_i ( fe_idma_req ), + .nd_req_valid_i ( fe_req_valid ), + .nd_req_ready_o ( fe_req_ready ), + .nd_rsp_o ( ), + .nd_rsp_valid_o ( idma_nd_rsp_valid ), + .nd_rsp_ready_i ( idma_nd_rsp_ready ), + .burst_req_o ( be_idma_req ), + .burst_req_valid_o ( be_req_valid ), + .burst_req_ready_i ( be_req_ready ), + .burst_rsp_i ( be_idma_rsp ), + .burst_rsp_valid_i ( be_rsp_valid ), + .burst_rsp_ready_o ( be_rsp_ready ), + .busy_o ( me_busy ) + ); + + idma_backend_rw_axi #( + .CombinedShifter ( CombinedShifter ), + .DataWidth ( AxiDataWidth ), + .AddrWidth ( AxiAddrWidth ), + .AxiIdWidth ( SlvIdWidth ), + .UserWidth ( AxiUserWidth ), + .TFLenWidth ( TFLenWidth ), + .MaskInvalidData ( MaskInvalidData ), + .BufferDepth ( BufferDepth ), + .RAWCouplingAvail ( RAWCouplingAvail ), + .HardwareLegalizer ( HardwareLegalizer ), + .RejectZeroTransfers ( RejectZeroTransfers ), + .ErrorCap ( ErrorCap ), + .PrintFifoInfo ( PrintFifoInfo ), + .NumAxInFlight ( NumAxInFlight ), + .MemSysDepth ( MemSysDepth ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_eh_req_t ( idma_eh_req_t ), + .idma_busy_t ( idma_busy_t ), + .axi_req_t ( slv_req_t ), + .axi_rsp_t ( slv_rsp_t ), + .write_meta_channel_t ( write_meta_channel_t ), + .read_meta_channel_t ( read_meta_channel_t ) + ) i_idma_backend ( + .clk_i, + .rst_ni, + .testmode_i ( 1'b0 ), + .idma_req_i ( be_idma_req ), + .req_valid_i ( be_req_valid ), + .req_ready_o ( be_req_ready ), + .idma_rsp_o ( be_idma_rsp ), + .rsp_valid_o ( be_rsp_valid ), + .rsp_ready_i ( be_rsp_ready ), + .idma_eh_req_i ( '0 ), + .eh_req_valid_i ( '0 ), + .eh_req_ready_o ( ), + .axi_read_req_o ( axi_read_req_o ), + .axi_read_rsp_i ( axi_read_rsp_i ), + + .axi_write_req_o ( axi_write_req_o ), + .axi_write_rsp_i ( axi_write_rsp_i ), + .busy_o ( busy ) + ); + + assign retire_id = idma_nd_rsp_valid & idma_nd_rsp_ready; + assign issue_id = fe_req_valid & fe_req_ready; + assign idma_nd_rsp_ready = 1'b1; + + idma_transfer_id_gen #( + .IdWidth ( IdCounterWidth ) + ) i_transfer_id_gen ( + .clk_i, + .rst_ni, + .issue_i ( issue_id ), + .retire_i ( retire_id ), + .next_o ( next_id ), + .completed_o ( done_id ) + ); + +endmodule \ No newline at end of file From 1d16b419d8ff24d61c6d847e1ea310b9bef1e680 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sat, 18 May 2024 20:14:52 +0200 Subject: [PATCH 21/48] fix --- hw/cheshire_soc.sv | 37 ++-- hw/dma_core_wrap.sv | 72 +++++--- hw/idma_core_wrap.sv | 229 ------------------------- target/sim/src/fixture_cheshire_soc.sv | 4 +- target/sim/src/vip_cheshire_soc.sv | 17 +- 5 files changed, 69 insertions(+), 290 deletions(-) delete mode 100644 hw/idma_core_wrap.sv diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index beb18e54..daf8bbeb 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -28,8 +28,8 @@ module cheshire_soc import cheshire_pkg::*; #( input logic test_mode_i, input logic [1:0] boot_mode_i, input logic rtc_i, - input logic eth_clk_125, - input logic eth_clk_90, + input logic eth_clk125_i, + input logic eth_clk200_i, // External AXI LLC (DRAM) port output axi_ext_llc_req_t axi_llc_mst_req_o, input axi_ext_llc_rsp_t axi_llc_mst_rsp_i, @@ -1379,7 +1379,6 @@ module cheshire_soc import cheshire_pkg::*; #( end - //////////////// // ETHERNET // //////////////// @@ -1396,22 +1395,22 @@ module cheshire_soc import cheshire_pkg::*; #( ) i_tx_eth_idma_wrap ( .clk_i, .rst_ni, - .eth_clk125_i ( eth_clk_125 ), - .eth_clk125q_i ( eth_clk_90 ), - .phy_rx_clk_i ( eth_rxck_i ), - .phy_rxd_i ( eth_rxd_i ), - .phy_rx_ctl_i ( eth_rxctl_i ), - .phy_tx_clk_o ( eth_txck_o ), - .phy_txd_o ( eth_txd_o ), - .phy_tx_ctl_o ( eth_txctl_o ), - .phy_resetn_o ( eth_rstn_o ), - .phy_intn_i ( 1'b1 ), - .phy_pme_i ( 1'b1 ), - .phy_mdio_i ( eth_mdio_i ), - .phy_mdio_o ( eth_mdio_o ), - .phy_mdio_oe ( eth_mdio_oe ), - .phy_mdc_o ( eth_mdc_o ), - .testmode_i ( 1'b0 ), + .eth_clk_i ( eth_clk125_i ), + .eth_clk200_i ( eth_clk200_i ), + .phy_rx_clk_i ( eth_rxck_i ), + .phy_rxd_i ( eth_rxd_i ), + .phy_rx_ctl_i ( eth_rxctl_i ), + .phy_tx_clk_o ( eth_txck_o ), + .phy_txd_o ( eth_txd_o ), + .phy_tx_ctl_o ( eth_txctl_o ), + .phy_resetn_o ( eth_rstn_o ), + .phy_intn_i ( 1'b1 ), + .phy_pme_i ( 1'b1 ), + .phy_mdio_i ( eth_mdio_i ), + .phy_mdio_o ( eth_mdio_o ), + .phy_mdio_oe ( eth_mdio_oe ), + .phy_mdc_o ( eth_mdc_o ), + .testmode_i ( testmode_i ), .axi_req_o ( axi_in_req[AxiIn.eth] ), .axi_rsp_i ( axi_in_rsp[AxiIn.eth] ), .reg_req_i ( reg_out_req[RegOut.ethernet] ), diff --git a/hw/dma_core_wrap.sv b/hw/dma_core_wrap.sv index 97371a95..07960ac8 100644 --- a/hw/dma_core_wrap.sv +++ b/hw/dma_core_wrap.sv @@ -15,21 +15,27 @@ `include "register_interface/typedef.svh" module dma_core_wrap #( - parameter int unsigned AxiAddrWidth = 32'd0, - parameter int unsigned AxiDataWidth = 32'd0, - parameter int unsigned AxiIdWidth = 32'd0, - parameter int unsigned AxiUserWidth = 32'd0, - parameter int unsigned AxiSlvIdWidth = 32'd0, - parameter int unsigned TFLenWidth = 32'd0, - parameter int unsigned NumAxInFlight = 32'd0, - parameter int unsigned MemSysDepth = 32'd0, - parameter int unsigned JobFifoDepth = 32'd0, - parameter bit RAWCouplingAvail = 32'd0, - parameter bit IsTwoD = 32'd0, - parameter type axi_mst_req_t = logic, - parameter type axi_mst_rsp_t = logic, - parameter type axi_slv_req_t = logic, - parameter type axi_slv_rsp_t = logic + parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, + parameter int unsigned AxiIdWidth = 32'd0, + parameter int unsigned AxiUserWidth = 32'd0, + parameter int unsigned AxiSlvIdWidth = 32'd0, + parameter int unsigned TFLenWidth = 32'd0, + parameter int unsigned NumAxInFlight = 32'd0, + parameter int unsigned MemSysDepth = 32'd0, + parameter int unsigned JobFifoDepth = 32'd0, + parameter bit EnableAxiCut = 1'b1, + parameter bit RAWCouplingAvail = 32'd0, + parameter bit IsTwoD = 32'd0, + parameter type axi_mst_aw_chan_t = logic, + parameter type axi_mst_ar_chan_t = logic, + parameter type axi_mst_w_chan_t = logic, + parameter type axi_mst_r_chan_t = logic, + parameter type axi_mst_b_chan_t = logic, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_rsp_t = logic, + parameter type axi_slv_req_t = logic, + parameter type axi_slv_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -113,8 +119,8 @@ module dma_core_wrap #( idma_pkg::idma_busy_t busy; logic me_busy; // internal AXI channels - axi_mst_req_t axi_read_req, axi_write_req; - axi_mst_rsp_t axi_read_rsp, axi_write_rsp; + axi_mst_req_t axi_read_req, axi_write_req, axi_cut_req; + axi_mst_rsp_t axi_read_rsp, axi_write_rsp, axi_cut_rsp; axi_to_reg #( .ADDR_WIDTH( AxiAddrWidth ), @@ -323,11 +329,29 @@ module dma_core_wrap #( ) i_axi_rw_join ( .clk_i, .rst_ni, - .slv_read_req_i ( axi_read_req ), - .slv_read_resp_o ( axi_read_rsp ), - .slv_write_req_i ( axi_write_req ), - .slv_write_resp_o ( axi_write_rsp ), - .mst_req_o ( axi_mst_req_o ), - .mst_resp_i ( axi_mst_rsp_i ) + .slv_read_req_i ( axi_read_req ), + .slv_read_resp_o ( axi_read_rsp ), + .slv_write_req_i ( axi_write_req ), + .slv_write_resp_o ( axi_write_rsp ), + .mst_req_o ( axi_cut_req ), + .mst_resp_i ( axi_cut_rsp ) ); -endmodule + + axi_cut #( + .Bypass ( ~EnableAxiCut ), + .aw_chan_t ( axi_mst_aw_chan_t ), + .w_chan_t ( axi_mst_w_chan_t ), + .b_chan_t ( axi_mst_b_chan_t ), + .ar_chan_t ( axi_mst_ar_chan_t ), + .r_chan_t ( axi_mst_r_chan_t ), + .axi_req_t ( axi_mst_req_t ), + .axi_resp_t ( axi_mst_rsp_t ) + ) i_axi_cut ( + .clk_i, + .rst_ni, + .slv_req_i ( axi_cut_req ), + .slv_resp_o ( axi_cut_rsp ), + .mst_req_o ( axi_mst_req_o ), + .mst_resp_i ( axi_mst_rsp_i ) + ); +endmodule \ No newline at end of file diff --git a/hw/idma_core_wrap.sv b/hw/idma_core_wrap.sv deleted file mode 100644 index 3e21d3c0..00000000 --- a/hw/idma_core_wrap.sv +++ /dev/null @@ -1,229 +0,0 @@ -// Copyright 2024 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -`include "idma/typedef.svh" -`include "axi/typedef.svh" - -module idma_wrap import idma_pkg::*; #( - parameter int unsigned BufferDepth = 3, - parameter int unsigned NumAxInFlight = 3, - parameter int unsigned TFLenWidth = 32, - parameter int unsigned MemSysDepth = 0, - parameter int unsigned AXI_MemNumReqOutst = 1, - parameter int unsigned AXI_MemLatency = 0, - parameter int unsigned WatchDogNumCycles = 100, - parameter int unsigned NumDim = 3, - parameter bit CombinedShifter = 1'b0, - parameter bit MaskInvalidData = 1, - parameter bit RAWCouplingAvail = 1, - parameter bit HardwareLegalizer = 1, - parameter bit RejectZeroTransfers = 1, - parameter bit ErrorHandling = 0, - parameter bit DmaTracing = 1, - parameter bit PrintFifoInfo = 1'b0, - parameter int unsigned RegAddrWidth = 32, - parameter int unsigned RegDataWidth = 32, - parameter int unsigned AxiAddrWidth = 64, - parameter int unsigned AxiDataWidth = 32, - parameter int unsigned AxiIdWidth = 7, - parameter int unsigned AxiUserWidth = 1, - parameter int unsigned StrideWidth = 32, - parameter type axi_req_t = logic, - parameter type axi_rsp_t = logic, - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic -) ( - input logic clk_i, - input logic rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - output axi_req_t axi_read_req_o, - input axi_rsp_t axi_read_rsp_i, - output axi_req_t axi_write_req_o, - input axi_rsp_t axi_write_rsp_i -); - - // dependent parameters - localparam logic [2:0][31:0] RepWidth = '{default: 32'd32}; - localparam int unsigned IdCounterWidth = 16; - localparam int unsigned AxiStrbWidth = AxiDataWidth / 8; - localparam int unsigned RegStrbWidth = RegDataWidth / 8; - localparam idma_pkg::error_cap_e ErrorCap = ErrorHandling ? idma_pkg::ERROR_HANDLING : - idma_pkg::NO_ERROR_HANDLING; - - localparam int unsigned MstIdWidth = AxiIdWidth; - localparam int unsigned SlvIdWidth = AxiIdWidth - $clog2(2); - - typedef logic [AxiDataWidth/8-1:0] axi_strb_t; - typedef logic [AxiDataWidth-1:0] axi_data_t; - typedef logic [AxiAddrWidth-1:0] axi_addr_t; - typedef logic [AxiUserWidth-1:0] axi_user_t; - typedef logic [MstIdWidth-1:0] axi_id_t; - typedef logic [SlvIdWidth-1:0] slv_id_t; - - typedef logic [31:0] reps_t; - typedef logic [StrideWidth-1:0] strides_t; - - // AXI4+ATOP channels typedefs - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) - - `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, axi_addr_t, axi_id_t, axi_user_t) - `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, axi_addr_t, axi_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, axi_data_t, axi_id_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, axi_id_t, axi_user_t) - - `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RESP_T(slv_rsp_t, slv_b_chan_t, slv_r_chan_t) - - //iDMA defines - `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, axi_id_t, axi_addr_t, axi_addr_t) - `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, axi_addr_t) - `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, reps_t, strides_t) - - typedef struct packed { - slv_ar_chan_t ar_chan; - } axi_read_meta_channel_t; - - typedef struct packed { - axi_read_meta_channel_t axi; - } read_meta_channel_t; - - typedef struct packed { - slv_aw_chan_t aw_chan; - } axi_write_meta_channel_t; - - typedef struct packed { - axi_write_meta_channel_t axi; - } write_meta_channel_t; - - idma_req_t be_idma_req; - idma_rsp_t be_idma_rsp; - idma_nd_req_t fe_idma_req; - - logic idma_nd_rsp_valid; - logic idma_nd_rsp_ready; - logic issue_id; - logic retire_id; - - idma_pkg::idma_busy_t busy; - logic me_busy; - - logic fe_req_valid, fe_req_ready; - logic be_req_valid, be_req_ready; - - logic [IdCounterWidth-1:0] done_id, next_id; - - idma_reg64_2d #( - .NumRegs ( 32'd1 ), - .NumStreams ( 32'd1 ), - .IdCounterWidth ( IdCounterWidth ), - .reg_req_t ( reg_req_t ), - .reg_rsp_t ( reg_rsp_t ), - .dma_req_t ( idma_nd_req_t ) - ) idma_frontend ( - .clk_i, - .rst_ni, - .dma_ctrl_req_i ( reg_req_i ), - .dma_ctrl_rsp_o ( reg_rsp_o ), - .dma_req_o ( fe_idma_req ), - .req_valid_o ( fe_req_valid ), - .req_ready_i ( fe_req_ready ), - .next_id_i ( next_id ), - .stream_idx_o ( ), - .done_id_i ( done_id ), - .busy_i ( busy ), - .midend_busy_i ( me_busy ) - ); - - idma_nd_midend #( - .NumDim ( NumDim ), - .addr_t ( axi_addr_t ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_nd_req_t ( idma_nd_req_t ), - .RepWidths ( RepWidth ) - ) idma_midend_i ( - .clk_i, - .rst_ni, - .nd_req_i ( fe_idma_req ), - .nd_req_valid_i ( fe_req_valid ), - .nd_req_ready_o ( fe_req_ready ), - .nd_rsp_o ( ), - .nd_rsp_valid_o ( idma_nd_rsp_valid ), - .nd_rsp_ready_i ( idma_nd_rsp_ready ), - .burst_req_o ( be_idma_req ), - .burst_req_valid_o ( be_req_valid ), - .burst_req_ready_i ( be_req_ready ), - .burst_rsp_i ( be_idma_rsp ), - .burst_rsp_valid_i ( be_rsp_valid ), - .burst_rsp_ready_o ( be_rsp_ready ), - .busy_o ( me_busy ) - ); - - idma_backend_rw_axi #( - .CombinedShifter ( CombinedShifter ), - .DataWidth ( AxiDataWidth ), - .AddrWidth ( AxiAddrWidth ), - .AxiIdWidth ( SlvIdWidth ), - .UserWidth ( AxiUserWidth ), - .TFLenWidth ( TFLenWidth ), - .MaskInvalidData ( MaskInvalidData ), - .BufferDepth ( BufferDepth ), - .RAWCouplingAvail ( RAWCouplingAvail ), - .HardwareLegalizer ( HardwareLegalizer ), - .RejectZeroTransfers ( RejectZeroTransfers ), - .ErrorCap ( ErrorCap ), - .PrintFifoInfo ( PrintFifoInfo ), - .NumAxInFlight ( NumAxInFlight ), - .MemSysDepth ( MemSysDepth ), - .idma_req_t ( idma_req_t ), - .idma_rsp_t ( idma_rsp_t ), - .idma_eh_req_t ( idma_eh_req_t ), - .idma_busy_t ( idma_busy_t ), - .axi_req_t ( slv_req_t ), - .axi_rsp_t ( slv_rsp_t ), - .write_meta_channel_t ( write_meta_channel_t ), - .read_meta_channel_t ( read_meta_channel_t ) - ) i_idma_backend ( - .clk_i, - .rst_ni, - .testmode_i ( 1'b0 ), - .idma_req_i ( be_idma_req ), - .req_valid_i ( be_req_valid ), - .req_ready_o ( be_req_ready ), - .idma_rsp_o ( be_idma_rsp ), - .rsp_valid_o ( be_rsp_valid ), - .rsp_ready_i ( be_rsp_ready ), - .idma_eh_req_i ( '0 ), - .eh_req_valid_i ( '0 ), - .eh_req_ready_o ( ), - .axi_read_req_o ( axi_read_req_o ), - .axi_read_rsp_i ( axi_read_rsp_i ), - - .axi_write_req_o ( axi_write_req_o ), - .axi_write_rsp_i ( axi_write_rsp_i ), - .busy_o ( busy ) - ); - - assign retire_id = idma_nd_rsp_valid & idma_nd_rsp_ready; - assign issue_id = fe_req_valid & fe_req_ready; - assign idma_nd_rsp_ready = 1'b1; - - idma_transfer_id_gen #( - .IdWidth ( IdCounterWidth ) - ) i_transfer_id_gen ( - .clk_i, - .rst_ni, - .issue_i ( issue_id ), - .retire_i ( retire_id ), - .next_o ( next_id ), - .completed_o ( done_id ) - ); - -endmodule \ No newline at end of file diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index cc6b1854..c8aada3d 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -50,7 +50,6 @@ module fixture_cheshire_soc #( logic i2c_scl_en; logic eth_clk_125; - logic eth_clk_90; logic eth_rxck; logic [3:0] eth_rxd; logic eth_rxctl; @@ -129,8 +128,7 @@ module fixture_cheshire_soc #( .i2c_scl_o ( i2c_scl_o ), .i2c_scl_i ( i2c_scl_i ), .i2c_scl_en_o ( i2c_scl_en ), - .eth_clk_125 ( eth_clk_125 ), - .eth_clk_90 ( eth_clk_90 ), + .eth_clk_i ( eth_clk_125 ), .eth_rxck_i ( eth_rxck ), .eth_rxd_i ( eth_rxd ), .eth_rxctl_i ( eth_rxctl ), diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 7827b07a..823e5bee 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -71,7 +71,6 @@ module vip_cheshire_soc import cheshire_pkg::*; #( inout wire [ 3:0] spih_sd, // Ethernet interface output logic eth_clk_125, - output logic eth_clk_90, input logic [ 3:0] eth_txd, output logic [ 3:0] eth_rxd, input logic eth_txck, @@ -654,8 +653,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( ) i_rx_eth_idma_wrap ( .clk_i ( clk ), .rst_ni ( rst_n ), - .eth_clk125_i ( eth_clk_125 ), - .eth_clk125q_i ( eth_clk_90 ), + .eth_clk_i ( eth_clk_125 ), .phy_rx_clk_i ( eth_txck ), .phy_rxd_i ( eth_txd ), .phy_rx_ctl_i ( eth_txctl ), @@ -718,17 +716,6 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end end - initial begin - forever begin - eth_clk_90 <= 0; - #(ClkPeriodEth125/4); - eth_clk_90 <= 1; - #(ClkPeriodEth125/2); - eth_clk_90 <= 0; - #(ClkPeriodEth125/4); - end - end - initial begin @(posedge clk); $readmemh("rx_mem_init.vmem", i_rx_axi_sim_mem.mem); @@ -1121,7 +1108,7 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( inout wire [SpihNumCs-1:0] spih_csb, inout wire [ 3:0] spih_sd, // Ethernet wires - input wire eth_mdio + inout wire eth_mdio ); // I2C From 3b60f7a16ff8cfa8814bdb9c20cb24877eeec7ef Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sat, 18 May 2024 22:39:03 +0200 Subject: [PATCH 22/48] sim new idma --- Bender.lock | 83 +- Bender.yml | 1 - cheshire.mk | 26 +- hw/bootrom/cheshire_bootrom.sv | 3576 ++++++++++++------------ hw/cheshire_pkg.sv | 55 +- hw/cheshire_soc.sv | 235 +- hw/regs/cheshire_reg_pkg.sv | 19 +- hw/regs/cheshire_reg_top.sv | 46 +- hw/regs/cheshire_regs.hjson | 11 +- sw/include/cheshire_io.h | 11 - sw/include/init.h | 7 - sw/include/params.h | 1 - sw/include/regs/axi_llc.h | 68 - sw/include/regs/cheshire.h | 3 - sw/lib/cheshire_io.c | 19 - sw/lib/crt0.S | 20 +- sw/lib/init.c | 14 - target/sim/src/fixture_cheshire_soc.sv | 2 +- 18 files changed, 1907 insertions(+), 2290 deletions(-) delete mode 100644 sw/include/cheshire_io.h delete mode 100644 sw/include/init.h delete mode 100644 sw/lib/cheshire_io.c delete mode 100644 sw/lib/init.c diff --git a/Bender.lock b/Bender.lock index 71b7e36b..3da77531 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,19 +15,19 @@ packages: - apb - register_interface axi: - revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2 - version: 0.39.2 + revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 + version: 0.39.3 source: - Git: https://github.com/pulp-platform/axi + Git: https://github.com/pulp-platform/axi.git dependencies: - common_cells - common_verification - tech_cells_generic axi_llc: - revision: d79a00b8673b814efacbbe9bf106103407fc401b - version: null + revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39 + version: 0.2.1 source: - Git: https://github.com/pulp-platform/axi_llc + Git: https://github.com/pulp-platform/axi_llc.git dependencies: - axi - common_cells @@ -35,8 +35,8 @@ packages: - register_interface - tech_cells_generic axi_riscv_atomics: - revision: 6a85f44fdb1fe93162de7241476bba81e2247cb5 - version: null + revision: 0ac3a78fe342c5a5b9b10bff49d58897f773059e + version: 0.8.2 source: Git: https://github.com/pulp-platform/axi_riscv_atomics.git dependencies: @@ -52,16 +52,9 @@ packages: - axi - common_cells - register_interface - axi_vga: - revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 - version: 0.1.3 - source: - Git: https://github.com/pulp-platform/axi_stream.git - dependencies: - - common_cells - axi_vga: - revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 - version: 0.1.3 + axi_stream: + revision: 54891ff40455ca94a37641b9da4604647878cc07 + version: 0.1.1 source: Git: https://github.com/pulp-platform/axi_stream.git dependencies: @@ -76,8 +69,8 @@ packages: - common_cells - register_interface clic: - revision: bf6032e1ea30f3a502aa85906520dece53626eb9 - version: 3.0.0-rc4 + revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf + version: 2.0.0 source: Git: https://github.com/pulp-platform/clic.git dependencies: @@ -106,7 +99,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: - revision: dbaecc59b99e3bb4d89fed546d75080f39bfe4f1 + revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5 version: null source: Git: https://github.com/pulp-platform/cva6.git @@ -114,20 +107,7 @@ packages: - axi - common_cells - fpnew - - redundancy_cells - tech_cells_generic - ethernet: - revision: ca7feb6e5722aaec7bdb6d71d4cfddfe58f18afd - version: null - source: - Git: https://github.com/pulp-platform/pulp-ethernet.git - dependencies: - - axi - - axi_stream - - common_cells - - common_verification - - idma - - register_interface fpnew: revision: f231041c610f270ffc03cbdac38739ddb6426572 version: null @@ -144,8 +124,8 @@ packages: dependencies: - common_cells idma: - revision: 88fbe67d8350b4de5ceb3673073bc216b8d585b7 - version: null + revision: 95f366e56f7e772c283fb3c8b343afc4a3978375 + version: 0.6.2 source: Git: https://github.com/pulp-platform/iDMA.git dependencies: @@ -154,16 +134,6 @@ packages: - common_cells - common_verification - obi - - idma_gen - - register_interface - idma_gen: - revision: null - version: null - source: - Path: .bender/git/checkouts/idma-77bf7fa56d324e6a/target/rtl - dependencies: - - axi - - common_cells - register_interface irq_router: revision: d1d31350b24f3965b3a51e1bc96c71eb34e94db3 @@ -191,16 +161,18 @@ packages: - common_cells - register_interface - tech_cells_generic - redundancy_cells: - revision: c37bdb47339bf70e8323de8df14ea8bbeafb6583 + pulp-ethernet: + revision: bf5fc0055a4d3258361e38ee977566fa312570f0 version: null source: - Git: https://github.com/pulp-platform/redundancy_cells.git + Git: https://github.com/pulp-platform/pulp-ethernet.git dependencies: + - axi + - axi_stream - common_cells - common_verification + - idma - register_interface - - tech_cells_generic register_interface: revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d version: 0.4.4 @@ -228,17 +200,6 @@ packages: - axi - common_cells - register_interface - tagger: - revision: b288376b65b6bbd5feea196bb3c220f783d96e29 - version: null - source: - Git: https://github.com/pulp-platform/transaction-tagger.git - dependencies: - - axi - - common_cells - - common_verification - - register_interface - - tech_cells_generic tech_cells_generic: revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf version: 0.2.13 diff --git a/Bender.yml b/Bender.yml index 250d021e..32c29e56 100644 --- a/Bender.yml +++ b/Bender.yml @@ -40,7 +40,6 @@ sources: - hw/regs/cheshire_reg_pkg.sv - hw/regs/cheshire_reg_top.sv - hw/cheshire_pkg.sv - - hw/cva6_wrap.sv - hw/dma_core_wrap.sv - hw/cheshire_soc.sv diff --git a/cheshire.mk b/cheshire.mk index aa7763a7..d32046b0 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -11,16 +11,11 @@ BENDER ?= bender VLOG_ARGS ?= -suppress 2583 -suppress 13314 VSIM ?= vsim -MAXPARTITION ?= 16 -CACHE_PARTITION ?= 1 - - # Define used paths (prefixed to avoid name conflicts) CHS_ROOT ?= $(shell $(BENDER) path cheshire) CHS_REG_DIR := $(shell $(BENDER) path register_interface) CHS_SLINK_DIR := $(shell $(BENDER) path serial_link) CHS_LLC_DIR := $(shell $(BENDER) path axi_llc) -CHS_TAGGER_DIR := $(shell $(BENDER) path tagger) # Define paths used in dependencies OTPROOT := $(shell $(BENDER) path opentitan_peripherals) @@ -28,7 +23,7 @@ CLINTROOT := $(shell $(BENDER) path clint) AXIRTROOT := $(shell $(BENDER) path axi_rt) AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga) IDMA_ROOT := $(shell $(BENDER) path idma) -ETH_ROOT := $(shell $(BENDER) path ethernet) +ETH_ROOT := $(shell $(BENDER) path pulp-ethernet) REGTOOL ?= $(CHS_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py @@ -49,11 +44,6 @@ ifeq ($(shell test -f $(BENDER_ROOT)/.chs_deps && echo 1),) -include $(BENDER_ROOT)/.chs_deps endif -#idma-gen: -# make -C $(IDMA_ROOT) idma_hw_all -# make -C $(IDMA_ROOT) target/rtl/idma_reg64_2d.hjson -# make -C $(ETH_ROOT) eth-gen - # Running this target will reset dependencies (without updating the checked-in Bender.lock) chs-clean-deps: rm -rf .bender @@ -64,7 +54,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= d0a0c9a # branch: astral +CHS_NONFREE_COMMIT ?= 99973e8 chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree @@ -114,16 +104,6 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson cp $< $(dir $@)/src/regs/serial_link_single_channel.hjson flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs BENDER="$(BENDER)" && touch $@ -# LLC partitioning configuration -$(CHS_LLC_DIR)/.generated: - $(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXPARTITION=$(MAXPARTITION) CACHE_PARTITION=$(CACHE_PARTITION) regs - @touch $@ - -# Tagger configuration -$(CHS_TAGGER_DIR)/.generated: - $(MAKE) -C $(CHS_TAGGER_DIR) REGWIDTH=32 MAXPARTITION=$(MAXPARTITION) PATID_LEN=5 regs - @touch $@ - # iDMA $(IDMA_ROOT)/.generated: $(IDMA_ROOT)/target/rtl/idma_reg64_2d.hjson flock -x $@ sh -c "cp $< $(dir $@)/target/rtl/; $(MAKE) -j1 otp" && touch $@ @@ -134,8 +114,6 @@ CHS_HW_ALL += $(OTPROOT)/.generated CHS_HW_ALL += $(AXIRTROOT)/.generated CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated -CHS_HW_ALL += $(CHS_LLC_DIR)/.generated -CHS_HW_ALL += $(CHS_TAGGER_DIR)/.generated ##################### # Generate Boot ROM # diff --git a/hw/bootrom/cheshire_bootrom.sv b/hw/bootrom/cheshire_bootrom.sv index a1b81e7a..9c42aeb2 100644 --- a/hw/bootrom/cheshire_bootrom.sv +++ b/hw/bootrom/cheshire_bootrom.sv @@ -46,12 +46,12 @@ module cheshire_bootrom #( 014: data_o = 32'h43214f81 /* 0x0038 */; 015: data_o = 32'h30431073 /* 0x003c */; 016: data_o = 32'h23734281 /* 0x0040 */; - 017: data_o = 32'h9e63f140 /* 0x0044 */; + 017: data_o = 32'h9663f140 /* 0x0044 */; 018: data_o = 32'h01170a62 /* 0x0048 */; 019: data_o = 32'h01130e01 /* 0x004c */; 020: data_o = 32'h2197fae1 /* 0x0050 */; 021: data_o = 32'h81930000 /* 0x0054 */; - 022: data_o = 32'h0297aea1 /* 0x0058 */; + 022: data_o = 32'h0297ada1 /* 0x0058 */; 023: data_o = 32'h82930100 /* 0x005c */; 024: data_o = 32'ha283fa62 /* 0x0060 */; 025: data_o = 32'hf2930502 /* 0x0064 */; @@ -73,7 +73,7 @@ module cheshire_bootrom #( 041: data_o = 32'h02971161 /* 0x00a4 */; 042: data_o = 32'h82930100 /* 0x00a8 */; 043: data_o = 32'ha283f5a2 /* 0x00ac */; - 044: data_o = 32'h89630482 /* 0x00b0 */; + 044: data_o = 32'h81630482 /* 0x00b0 */; 045: data_o = 32'h92820a02 /* 0x00b4 */; 046: data_o = 32'h01000297 /* 0x00b8 */; 047: data_o = 32'hf4828293 /* 0x00bc */; @@ -85,1800 +85,1800 @@ module cheshire_bootrom #( 053: data_o = 32'h0397f322 /* 0x00d4 */; 054: data_o = 32'h83930100 /* 0x00d8 */; 055: data_o = 32'ha383f2a3 /* 0x00dc */; - 056: data_o = 32'hb31704c3 /* 0x00e0 */; - 057: data_o = 32'h03130100 /* 0x00e4 */; - 058: data_o = 32'h2303f1e3 /* 0x00e8 */; - 059: data_o = 32'hd3b32003 /* 0x00ec */; - 060: data_o = 32'h038a0063 /* 0x00f0 */; - 061: data_o = 32'h43059396 /* 0x00f4 */; - 062: data_o = 32'h0062a023 /* 0x00f8 */; - 063: data_o = 32'hcce30291 /* 0x00fc */; - 064: data_o = 32'h0073fe72 /* 0x0100 */; - 065: data_o = 32'h23731050 /* 0x0104 */; - 066: data_o = 32'h73133440 /* 0x0108 */; - 067: data_o = 32'h0ae30083 /* 0x010c */; - 068: data_o = 32'h0297fe03 /* 0x0110 */; - 069: data_o = 32'h82930004 /* 0x0114 */; - 070: data_o = 32'h2373eee2 /* 0x0118 */; - 071: data_o = 32'h030af140 /* 0x011c */; - 072: data_o = 32'h20239316 /* 0x0120 */; - 073: data_o = 32'h03970003 /* 0x0124 */; - 074: data_o = 32'h83930100 /* 0x0128 */; - 075: data_o = 32'ha383eda3 /* 0x012c */; - 076: data_o = 32'h038a04c3 /* 0x0130 */; - 077: data_o = 32'ha3039396 /* 0x0134 */; - 078: data_o = 32'h1ee30002 /* 0x0138 */; - 079: data_o = 32'h0291fe03 /* 0x013c */; - 080: data_o = 32'hfe72cbe3 /* 0x0140 */; - 081: data_o = 32'h01000297 /* 0x0144 */; - 082: data_o = 32'hebc28293 /* 0x0148 */; - 083: data_o = 32'h0142e303 /* 0x014c */; - 084: data_o = 32'he2831302 /* 0x0150 */; - 085: data_o = 32'he2b30102 /* 0x0154 */; - 086: data_o = 32'h25730062 /* 0x0158 */; - 087: data_o = 32'h80e7f140 /* 0x015c */; - 088: data_o = 32'h80820002 /* 0x0160 */; - 089: data_o = 32'h43014281 /* 0x0164 */; - 090: data_o = 32'h0ff0000f /* 0x0168 */; - 091: data_o = 32'h0000100f /* 0x016c */; - 092: data_o = 32'h3f0010ef /* 0x0170 */; - 093: data_o = 32'h65130506 /* 0x0174 */; - 094: data_o = 32'h02970015 /* 0x0178 */; - 095: data_o = 32'h82930100 /* 0x017c */; - 096: data_o = 32'ha423e862 /* 0x0180 */; - 097: data_o = 32'h007300a2 /* 0x0184 */; - 098: data_o = 32'hbff51050 /* 0x0188 */; - 099: data_o = 32'h0185171b /* 0x018c */; - 100: data_o = 32'h0185579b /* 0x0190 */; - 101: data_o = 32'h8fd966c1 /* 0x0194 */; - 102: data_o = 32'hf0068693 /* 0x0198 */; - 103: data_o = 32'h0085571b /* 0x019c */; - 104: data_o = 32'h8fd98f75 /* 0x01a0 */; - 105: data_o = 32'h0085151b /* 0x01a4 */; - 106: data_o = 32'h00ff0737 /* 0x01a8 */; - 107: data_o = 32'h8d5d8d79 /* 0x01ac */; - 108: data_o = 32'h80822501 /* 0x01b0 */; - 109: data_o = 32'hca09832a /* 0x01b4 */; - 110: data_o = 32'h00058383 /* 0x01b8 */; - 111: data_o = 32'h00730023 /* 0x01bc */; - 112: data_o = 32'h0305167d /* 0x01c0 */; - 113: data_o = 32'hfa6d0585 /* 0x01c4 */; - 114: data_o = 32'h66b18082 /* 0x01c8 */; - 115: data_o = 32'h00040797 /* 0x01cc */; - 116: data_o = 32'h00040717 /* 0x01d0 */; - 117: data_o = 32'he3478793 /* 0x01d4 */; - 118: data_o = 32'he3070713 /* 0x01d8 */; - 119: data_o = 32'h973697b6 /* 0x01dc */; - 120: data_o = 32'hffc7a783 /* 0x01e0 */; - 121: data_o = 32'hff872703 /* 0x01e4 */; - 122: data_o = 32'h17021782 /* 0x01e8 */; - 123: data_o = 32'h8fd99301 /* 0x01ec */; - 124: data_o = 32'hfca7eee3 /* 0x01f0 */; - 125: data_o = 32'hc5298082 /* 0x01f4 */; - 126: data_o = 32'h4789ee9d /* 0x01f8 */; - 127: data_o = 32'h04f60963 /* 0x01fc */; - 128: data_o = 32'h0163478d /* 0x0200 */; - 129: data_o = 32'h167d04f6 /* 0x0204 */; - 130: data_o = 32'h00c03633 /* 0x0208 */; - 131: data_o = 32'h47014801 /* 0x020c */; - 132: data_o = 32'h00c6969b /* 0x0210 */; - 133: data_o = 32'h00d5e7b3 /* 0x0214 */; - 134: data_o = 32'h0086161b /* 0x0218 */; - 135: data_o = 32'h181b8fd1 /* 0x021c */; - 136: data_o = 32'h611400a8 /* 0x0220 */; - 137: data_o = 32'h0107e7b3 /* 0x0224 */; - 138: data_o = 32'h0097171b /* 0x0228 */; - 139: data_o = 32'h27818fd9 /* 0x022c */; - 140: data_o = 32'h4501cedc /* 0x0230 */; - 141: data_o = 32'h079b8082 /* 0x0234 */; - 142: data_o = 32'h4709ffd6 /* 0x0238 */; - 143: data_o = 32'hfaf76fe3 /* 0x023c */; - 144: data_o = 32'h8082450d /* 0x0240 */; - 145: data_o = 32'h4601fef5 /* 0x0244 */; - 146: data_o = 32'h47014805 /* 0x0248 */; - 147: data_o = 32'h4801b7d1 /* 0x024c */; - 148: data_o = 32'h46014705 /* 0x0250 */; - 149: data_o = 32'h7159bf75 /* 0x0254 */; - 150: data_o = 32'he8caf0a2 /* 0x0258 */; - 151: data_o = 32'he0d2e4ce /* 0x025c */; - 152: data_o = 32'hf85afc56 /* 0x0260 */; - 153: data_o = 32'hf062f45e /* 0x0264 */; - 154: data_o = 32'heca6f486 /* 0x0268 */; - 155: data_o = 32'he86aec66 /* 0x026c */; - 156: data_o = 32'h8936e46e /* 0x0270 */; - 157: data_o = 32'h89ae842a /* 0x0274 */; - 158: data_o = 32'h8b3a8ab2 /* 0x0278 */; - 159: data_o = 32'hfff68b93 /* 0x027c */; - 160: data_o = 32'h0c136a31 /* 0x0280 */; - 161: data_o = 32'h0b630200 /* 0x0284 */; - 162: data_o = 32'h60040e04 /* 0x0288 */; - 163: data_o = 32'hf51350dc /* 0x028c */; - 164: data_o = 32'h278107f7 /* 0x0290 */; - 165: data_o = 32'hd71bf96d /* 0x0294 */; - 166: data_o = 32'hd51b0107 /* 0x0298 */; - 167: data_o = 32'h8d590087 /* 0x029c */; - 168: data_o = 32'h0187d79b /* 0x02a0 */; - 169: data_o = 32'hf7938fc9 /* 0x02a4 */; - 170: data_o = 32'hfff107f7 /* 0x02a8 */; - 171: data_o = 32'h00040717 /* 0x02ac */; - 172: data_o = 32'h00040797 /* 0x02b0 */; - 173: data_o = 32'hd5470713 /* 0x02b4 */; - 174: data_o = 32'hd5078793 /* 0x02b8 */; - 175: data_o = 32'h97d29752 /* 0x02bc */; - 176: data_o = 32'hffc72683 /* 0x02c0 */; - 177: data_o = 32'hff87a783 /* 0x02c4 */; - 178: data_o = 32'h17821682 /* 0x02c8 */; - 179: data_o = 32'h8edd9381 /* 0x02cc */; - 180: data_o = 32'h07970685 /* 0x02d0 */; - 181: data_o = 32'h05170004 /* 0x02d4 */; - 182: data_o = 32'h87930004 /* 0x02d8 */; - 183: data_o = 32'h0513d2e7 /* 0x02dc */; - 184: data_o = 32'h97d2d2a5 /* 0x02e0 */; - 185: data_o = 32'ha7839552 /* 0x02e4 */; - 186: data_o = 32'h2703ffc7 /* 0x02e8 */; - 187: data_o = 32'h1782ff85 /* 0x02ec */; - 188: data_o = 32'h93011702 /* 0x02f0 */; - 189: data_o = 32'heee38fd9 /* 0x02f4 */; - 190: data_o = 32'h489cfcd7 /* 0x02f8 */; - 191: data_o = 32'h46014685 /* 0x02fc */; - 192: data_o = 32'hc89c9bf9 /* 0x0300 */; - 193: data_o = 32'h0a000593 /* 0x0304 */; - 194: data_o = 32'hf0ef8522 /* 0x0308 */; - 195: data_o = 32'h0c9beedf /* 0x030c */; - 196: data_o = 32'h96630005 /* 0x0310 */; - 197: data_o = 32'hd593060c /* 0x0314 */; - 198: data_o = 32'h4685008a /* 0x0318 */; - 199: data_o = 32'hf5934605 /* 0x031c */; - 200: data_o = 32'h85220ff5 /* 0x0320 */; - 201: data_o = 32'hed3ff0ef /* 0x0324 */; - 202: data_o = 32'h00050c9b /* 0x0328 */; - 203: data_o = 32'h040c9963 /* 0x032c */; - 204: data_o = 32'h0ffaf593 /* 0x0330 */; - 205: data_o = 32'h060b0563 /* 0x0334 */; - 206: data_o = 32'h46054685 /* 0x0338 */; - 207: data_o = 32'hf0ef8522 /* 0x033c */; - 208: data_o = 32'h079beb9f /* 0x0340 */; - 209: data_o = 32'heb8d0005 /* 0x0344 */; - 210: data_o = 32'h74638d5e /* 0x0348 */; - 211: data_o = 32'h0d13017c /* 0x034c */; - 212: data_o = 32'h4d810200 /* 0x0350 */; - 213: data_o = 32'h000b9563 /* 0x0354 */; - 214: data_o = 32'hf563a075 /* 0x0358 */; - 215: data_o = 32'h87b30bad /* 0x035c */; - 216: data_o = 32'hc58301b9 /* 0x0360 */; - 217: data_o = 32'h46850007 /* 0x0364 */; - 218: data_o = 32'h85224605 /* 0x0368 */; - 219: data_o = 32'he8bff0ef /* 0x036c */; - 220: data_o = 32'h0005079b /* 0x0370 */; - 221: data_o = 32'hd3f50d85 /* 0x0374 */; - 222: data_o = 32'ha0118cbe /* 0x0378 */; - 223: data_o = 32'h70a64c8d /* 0x037c */; - 224: data_o = 32'h64e67406 /* 0x0380 */; - 225: data_o = 32'h69a66946 /* 0x0384 */; - 226: data_o = 32'h7ae26a06 /* 0x0388 */; - 227: data_o = 32'h7ba27b42 /* 0x038c */; - 228: data_o = 32'h6d427c02 /* 0x0390 */; - 229: data_o = 32'h85666da2 /* 0x0394 */; - 230: data_o = 32'h61656ce2 /* 0x0398 */; - 231: data_o = 32'h46858082 /* 0x039c */; - 232: data_o = 32'h85224609 /* 0x03a0 */; - 233: data_o = 32'he53ff0ef /* 0x03a4 */; - 234: data_o = 32'h0005079b /* 0x03a8 */; - 235: data_o = 32'h4685f7f1 /* 0x03ac */; - 236: data_o = 32'h05934601 /* 0x03b0 */; - 237: data_o = 32'h85220a10 /* 0x03b4 */; - 238: data_o = 32'he3fff0ef /* 0x03b8 */; - 239: data_o = 32'h0005079b /* 0x03bc */; - 240: data_o = 32'h4681ffc5 /* 0x03c0 */; - 241: data_o = 32'h7593460d /* 0x03c4 */; - 242: data_o = 32'h85220ff9 /* 0x03c8 */; - 243: data_o = 32'he2bff0ef /* 0x03cc */; - 244: data_o = 32'h0005079b /* 0x03d0 */; - 245: data_o = 32'h489cf3d5 /* 0x03d4 */; - 246: data_o = 32'h0017e793 /* 0x03d8 */; - 247: data_o = 32'h50dcc89c /* 0x03dc */; - 248: data_o = 32'h0107d79b /* 0x03e0 */; - 249: data_o = 32'h07f7f793 /* 0x03e4 */; - 250: data_o = 32'hff27ebe3 /* 0x03e8 */; - 251: data_o = 32'h601c994e /* 0x03ec */; - 252: data_o = 32'h27814f9c /* 0x03f0 */; - 253: data_o = 32'h00098463 /* 0x03f4 */; - 254: data_o = 32'h00f98023 /* 0x03f8 */; - 255: data_o = 32'h18e30985 /* 0x03fc */; - 256: data_o = 32'hbfb5ff39 /* 0x0400 */; - 257: data_o = 32'h017987b3 /* 0x0404 */; - 258: data_o = 32'h0007c583 /* 0x0408 */; - 259: data_o = 32'h46054685 /* 0x040c */; - 260: data_o = 32'hf0ef8522 /* 0x0410 */; - 261: data_o = 32'h079bde5f /* 0x0414 */; - 262: data_o = 32'hffb90005 /* 0x0418 */; - 263: data_o = 32'h1b81489c /* 0x041c */; - 264: data_o = 32'h0017e793 /* 0x0420 */; - 265: data_o = 32'h7ce3c89c /* 0x0424 */; - 266: data_o = 32'h99caf52c /* 0x0428 */; - 267: data_o = 32'h19019aca /* 0x042c */; - 268: data_o = 32'h7139bd99 /* 0x0430 */; - 269: data_o = 32'hf426f822 /* 0x0434 */; - 270: data_o = 32'hec4ef04a /* 0x0438 */; - 271: data_o = 32'hfc06e852 /* 0x043c */; - 272: data_o = 32'h7413e456 /* 0x0440 */; - 273: data_o = 32'h893203f6 /* 0x0444 */; - 274: data_o = 32'h8a2e89aa /* 0x0448 */; - 275: data_o = 32'he42184b6 /* 0x044c */; - 276: data_o = 32'h04000a93 /* 0x0450 */; - 277: data_o = 32'h00946563 /* 0x0454 */; - 278: data_o = 32'h7c63a82d /* 0x0458 */; - 279: data_o = 32'h86b30294 /* 0x045c */; - 280: data_o = 32'h06334084 /* 0x0460 */; - 281: data_o = 32'h05b30089 /* 0x0464 */; - 282: data_o = 32'h4701008a /* 0x0468 */; - 283: data_o = 32'h0413854e /* 0x046c */; - 284: data_o = 32'hf4630404 /* 0x0470 */; - 285: data_o = 32'h069300da /* 0x0474 */; - 286: data_o = 32'hf0ef0400 /* 0x0478 */; - 287: data_o = 32'hdd71dddf /* 0x047c */; - 288: data_o = 32'h744270e2 /* 0x0480 */; - 289: data_o = 32'h790274a2 /* 0x0484 */; - 290: data_o = 32'h6a4269e2 /* 0x0488 */; - 291: data_o = 32'h61216aa2 /* 0x048c */; - 292: data_o = 32'h45018082 /* 0x0490 */; - 293: data_o = 32'h0793b7f5 /* 0x0494 */; - 294: data_o = 32'h84330400 /* 0x0498 */; - 295: data_o = 32'h47014087 /* 0x049c */; - 296: data_o = 32'hf0ef86a2 /* 0x04a0 */; - 297: data_o = 32'hd54ddb5f /* 0x04a4 */; - 298: data_o = 32'h1141bfe1 /* 0x04a8 */; - 299: data_o = 32'he432e02e /* 0x04ac */; - 300: data_o = 32'h9581c141 /* 0x04b0 */; - 301: data_o = 32'h4782cdb5 /* 0x04b4 */; - 302: data_o = 32'hd5bbcfa5 /* 0x04b8 */; - 303: data_o = 32'h77c102f5 /* 0x04bc */; - 304: data_o = 32'h269988aa /* 0x04c0 */; - 305: data_o = 32'h0026969b /* 0x04c4 */; - 306: data_o = 32'h0015d59b /* 0x04c8 */; - 307: data_o = 32'h8fed35fd /* 0x04cc */; - 308: data_o = 32'h0007851b /* 0x04d0 */; - 309: data_o = 32'h4783ed31 /* 0x04d4 */; - 310: data_o = 32'h4e0300c1 /* 0x04d8 */; - 311: data_o = 32'h430300b1 /* 0x04dc */; - 312: data_o = 32'h480300d1 /* 0x04e0 */; - 313: data_o = 32'h46030081 /* 0x04e4 */; - 314: data_o = 32'h979b0091 /* 0x04e8 */; - 315: data_o = 32'h1e1b01e7 /* 0x04ec */; - 316: data_o = 32'h470301de /* 0x04f0 */; - 317: data_o = 32'he7b300a1 /* 0x04f4 */; - 318: data_o = 32'h131b01c7 /* 0x04f8 */; - 319: data_o = 32'h781301f3 /* 0x04fc */; - 320: data_o = 32'he7b300f8 /* 0x0500 */; - 321: data_o = 32'h8fcd0067 /* 0x0504 */; - 322: data_o = 32'h159b8a3d /* 0x0508 */; - 323: data_o = 32'h8fcd0108 /* 0x050c */; - 324: data_o = 32'h0008b803 /* 0x0510 */; - 325: data_o = 32'h0146161b /* 0x0514 */; - 326: data_o = 32'h171b8b3d /* 0x0518 */; - 327: data_o = 32'h8fd10187 /* 0x051c */; - 328: data_o = 32'h8fd91682 /* 0x0520 */; - 329: data_o = 32'h27819281 /* 0x0524 */; - 330: data_o = 32'h00d80733 /* 0x0528 */; - 331: data_o = 32'ha011c31c /* 0x052c */; - 332: data_o = 32'h0141450d /* 0x0530 */; - 333: data_o = 32'h65858082 /* 0x0534 */; - 334: data_o = 32'h9c458593 /* 0x0538 */; - 335: data_o = 32'h02b555b3 /* 0x053c */; - 336: data_o = 32'h00040797 /* 0x0540 */; - 337: data_o = 32'h00040697 /* 0x0544 */; - 338: data_o = 32'h86936731 /* 0x0548 */; - 339: data_o = 32'h8793abc6 /* 0x054c */; - 340: data_o = 32'h97baac07 /* 0x0550 */; - 341: data_o = 32'ha6039736 /* 0x0554 */; - 342: data_o = 32'h2783ffc7 /* 0x0558 */; - 343: data_o = 32'h66b1ff87 /* 0x055c */; - 344: data_o = 32'h17821602 /* 0x0560 */; - 345: data_o = 32'h8e5d9381 /* 0x0564 */; - 346: data_o = 32'hb0002873 /* 0x0568 */; - 347: data_o = 32'h00040717 /* 0x056c */; - 348: data_o = 32'h00040797 /* 0x0570 */; - 349: data_o = 32'ha9470713 /* 0x0574 */; - 350: data_o = 32'ha9078793 /* 0x0578 */; - 351: data_o = 32'h97b69736 /* 0x057c */; - 352: data_o = 32'hffc72703 /* 0x0580 */; - 353: data_o = 32'hff87a783 /* 0x0584 */; - 354: data_o = 32'h17821702 /* 0x0588 */; - 355: data_o = 32'h8f5d9381 /* 0x058c */; - 356: data_o = 32'hfce60ce3 /* 0x0590 */; - 357: data_o = 32'h663195ba /* 0x0594 */; - 358: data_o = 32'hb00028f3 /* 0x0598 */; - 359: data_o = 32'h00040797 /* 0x059c */; - 360: data_o = 32'h00040697 /* 0x05a0 */; - 361: data_o = 32'ha6478793 /* 0x05a4 */; - 362: data_o = 32'ha6068693 /* 0x05a8 */; - 363: data_o = 32'h96b297b2 /* 0x05ac */; - 364: data_o = 32'hffc7a783 /* 0x05b0 */; - 365: data_o = 32'hff86a683 /* 0x05b4 */; - 366: data_o = 32'h16821782 /* 0x05b8 */; - 367: data_o = 32'h8fd59281 /* 0x05bc */; - 368: data_o = 32'hfcb7ece3 /* 0x05c0 */; - 369: data_o = 32'h410888b3 /* 0x05c4 */; - 370: data_o = 32'h85338f99 /* 0x05c8 */; - 371: data_o = 32'h553302a8 /* 0x05cc */; - 372: data_o = 32'h808202f5 /* 0x05d0 */; - 373: data_o = 32'h0733c585 /* 0x05d4 */; - 374: data_o = 32'h279700b5 /* 0x05d8 */; - 375: data_o = 32'h87930100 /* 0x05dc */; - 376: data_o = 32'hc783a267 /* 0x05e0 */; - 377: data_o = 32'h8b850147 /* 0x05e4 */; - 378: data_o = 32'h2797dbed /* 0x05e8 */; - 379: data_o = 32'hc7830100 /* 0x05ec */; - 380: data_o = 32'h0505a167 /* 0x05f0 */; - 381: data_o = 32'hfef50fa3 /* 0x05f4 */; - 382: data_o = 32'hfee511e3 /* 0x05f8 */; - 383: data_o = 32'h71398082 /* 0x05fc */; - 384: data_o = 32'hf822fc06 /* 0x0600 */; - 385: data_o = 32'hf04af426 /* 0x0604 */; - 386: data_o = 32'he852ec4e /* 0x0608 */; - 387: data_o = 32'h01002797 /* 0x060c */; - 388: data_o = 32'h9f478793 /* 0x0610 */; - 389: data_o = 32'h0147c783 /* 0x0614 */; - 390: data_o = 32'h0207f793 /* 0x0618 */; - 391: data_o = 32'h2797dbe5 /* 0x061c */; - 392: data_o = 32'h47190100 /* 0x0620 */; - 393: data_o = 32'h9ee78123 /* 0x0624 */; - 394: data_o = 32'h44994a49 /* 0x0628 */; - 395: data_o = 32'h49cd4411 /* 0x062c */; - 396: data_o = 32'h000f4945 /* 0x0630 */; - 397: data_o = 32'h27970ff0 /* 0x0634 */; - 398: data_o = 32'h87930100 /* 0x0638 */; - 399: data_o = 32'hc7839ca7 /* 0x063c */; - 400: data_o = 32'h8b850147 /* 0x0640 */; - 401: data_o = 32'h2797dbed /* 0x0644 */; - 402: data_o = 32'hc7030100 /* 0x0648 */; - 403: data_o = 32'h77939ba7 /* 0x064c */; - 404: data_o = 32'h0f630ff7 /* 0x0650 */; - 405: data_o = 32'h8d630147 /* 0x0654 */; - 406: data_o = 32'h82630d37 /* 0x0658 */; - 407: data_o = 32'h45050727 /* 0x065c */; - 408: data_o = 32'h744270e2 /* 0x0660 */; - 409: data_o = 32'h790274a2 /* 0x0664 */; - 410: data_o = 32'h6a4269e2 /* 0x0668 */; - 411: data_o = 32'h80826121 /* 0x066c */; - 412: data_o = 32'h850a45a1 /* 0x0670 */; - 413: data_o = 32'hf61ff0ef /* 0x0674 */; - 414: data_o = 32'h002845a1 /* 0x0678 */; - 415: data_o = 32'hf59ff0ef /* 0x067c */; - 416: data_o = 32'h01002797 /* 0x0680 */; - 417: data_o = 32'h98078793 /* 0x0684 */; - 418: data_o = 32'h0147c783 /* 0x0688 */; - 419: data_o = 32'h0207f793 /* 0x068c */; - 420: data_o = 32'h65a2dbe5 /* 0x0690 */; - 421: data_o = 32'h27976502 /* 0x0694 */; - 422: data_o = 32'h85230100 /* 0x0698 */; - 423: data_o = 32'hf0ef9697 /* 0x069c */; - 424: data_o = 32'h2797f37f /* 0x06a0 */; - 425: data_o = 32'h87930100 /* 0x06a4 */; - 426: data_o = 32'hc78395e7 /* 0x06a8 */; - 427: data_o = 32'hf7930147 /* 0x06ac */; - 428: data_o = 32'hdbe50207 /* 0x06b0 */; - 429: data_o = 32'h01002797 /* 0x06b4 */; - 430: data_o = 32'h94878623 /* 0x06b8 */; - 431: data_o = 32'h45a1bf9d /* 0x06bc */; - 432: data_o = 32'hf0ef850a /* 0x06c0 */; - 433: data_o = 32'h45a1f13f /* 0x06c4 */; - 434: data_o = 32'hf0ef0028 /* 0x06c8 */; - 435: data_o = 32'h2797f0bf /* 0x06cc */; - 436: data_o = 32'h87930100 /* 0x06d0 */; - 437: data_o = 32'hc7839327 /* 0x06d4 */; - 438: data_o = 32'hf7930147 /* 0x06d8 */; - 439: data_o = 32'hdbe50207 /* 0x06dc */; - 440: data_o = 32'h27976622 /* 0x06e0 */; - 441: data_o = 32'h8f230100 /* 0x06e4 */; - 442: data_o = 32'h67029097 /* 0x06e8 */; - 443: data_o = 32'h963ac605 /* 0x06ec */; - 444: data_o = 32'h00074683 /* 0x06f0 */; - 445: data_o = 32'h01002797 /* 0x06f4 */; - 446: data_o = 32'h90c78793 /* 0x06f8 */; - 447: data_o = 32'h0147c783 /* 0x06fc */; - 448: data_o = 32'h0207f793 /* 0x0700 */; - 449: data_o = 32'h2797dbe5 /* 0x0704 */; - 450: data_o = 32'h8d230100 /* 0x0708 */; - 451: data_o = 32'h07058ed7 /* 0x070c */; - 452: data_o = 32'hfee610e3 /* 0x0710 */; - 453: data_o = 32'h01002797 /* 0x0714 */; - 454: data_o = 32'h8ec78793 /* 0x0718 */; - 455: data_o = 32'h0147c783 /* 0x071c */; - 456: data_o = 32'h0207f793 /* 0x0720 */; - 457: data_o = 32'h2797dbe5 /* 0x0724 */; - 458: data_o = 32'h8d230100 /* 0x0728 */; - 459: data_o = 32'hb7118c87 /* 0x072c */; - 460: data_o = 32'h850a45a1 /* 0x0730 */; - 461: data_o = 32'hea1ff0ef /* 0x0734 */; - 462: data_o = 32'h01002797 /* 0x0738 */; - 463: data_o = 32'h8c878793 /* 0x073c */; - 464: data_o = 32'h0147c783 /* 0x0740 */; - 465: data_o = 32'h0207f793 /* 0x0744 */; - 466: data_o = 32'h2797dbe5 /* 0x0748 */; - 467: data_o = 32'h47190100 /* 0x074c */; - 468: data_o = 32'h8ae78b23 /* 0x0750 */; - 469: data_o = 32'h0ff0000f /* 0x0754 */; - 470: data_o = 32'h100f6782 /* 0x0758 */; - 471: data_o = 32'h97820000 /* 0x075c */; - 472: data_o = 32'h000fc42a /* 0x0760 */; - 473: data_o = 32'h27970ff0 /* 0x0764 */; - 474: data_o = 32'h87930100 /* 0x0768 */; - 475: data_o = 32'hc78389a7 /* 0x076c */; - 476: data_o = 32'hf7930147 /* 0x0770 */; - 477: data_o = 32'hdbe50207 /* 0x0774 */; - 478: data_o = 32'h27974751 /* 0x0778 */; - 479: data_o = 32'h83230100 /* 0x077c */; - 480: data_o = 32'h007088e7 /* 0x0780 */; - 481: data_o = 32'h46830038 /* 0x0784 */; - 482: data_o = 32'h27970007 /* 0x0788 */; - 483: data_o = 32'h87930100 /* 0x078c */; - 484: data_o = 32'hc7838767 /* 0x0790 */; - 485: data_o = 32'hf7930147 /* 0x0794 */; - 486: data_o = 32'hdbe50207 /* 0x0798 */; - 487: data_o = 32'h01002797 /* 0x079c */; - 488: data_o = 32'h86d78223 /* 0x07a0 */; - 489: data_o = 32'h10e30705 /* 0x07a4 */; - 490: data_o = 32'h4522fec7 /* 0x07a8 */; - 491: data_o = 32'h07b7bd55 /* 0x07ac */; - 492: data_o = 32'hc91c4000 /* 0x07b0 */; - 493: data_o = 32'hd79b495c /* 0x07b4 */; - 494: data_o = 32'h8b8501e7 /* 0x07b8 */; - 495: data_o = 32'h495cffe5 /* 0x07bc */; - 496: data_o = 32'h0087d71b /* 0x07c0 */; - 497: data_o = 32'hf7938fd9 /* 0x07c4 */; - 498: data_o = 32'hfbf50ff7 /* 0x07c8 */; - 499: data_o = 32'h00052823 /* 0x07cc */; - 500: data_o = 32'hc93d8082 /* 0x07d0 */; - 501: data_o = 32'h001c27b7 /* 0x07d4 */; - 502: data_o = 32'h02f55533 /* 0x07d8 */; - 503: data_o = 32'h01002797 /* 0x07dc */; - 504: data_o = 32'h82478793 /* 0x07e0 */; - 505: data_o = 32'h00078223 /* 0x07e4 */; + 056: data_o = 32'h038a04c3 /* 0x00e0 */; + 057: data_o = 32'h43059396 /* 0x00e4 */; + 058: data_o = 32'h0062a023 /* 0x00e8 */; + 059: data_o = 32'hcce30291 /* 0x00ec */; + 060: data_o = 32'h0073fe72 /* 0x00f0 */; + 061: data_o = 32'h23731050 /* 0x00f4 */; + 062: data_o = 32'h73133440 /* 0x00f8 */; + 063: data_o = 32'h0ae30083 /* 0x00fc */; + 064: data_o = 32'h0297fe03 /* 0x0100 */; + 065: data_o = 32'h82930004 /* 0x0104 */; + 066: data_o = 32'h2373efe2 /* 0x0108 */; + 067: data_o = 32'h030af140 /* 0x010c */; + 068: data_o = 32'h20239316 /* 0x0110 */; + 069: data_o = 32'h03970003 /* 0x0114 */; + 070: data_o = 32'h83930100 /* 0x0118 */; + 071: data_o = 32'ha383eea3 /* 0x011c */; + 072: data_o = 32'h038a04c3 /* 0x0120 */; + 073: data_o = 32'ha3039396 /* 0x0124 */; + 074: data_o = 32'h1ee30002 /* 0x0128 */; + 075: data_o = 32'h0291fe03 /* 0x012c */; + 076: data_o = 32'hfe72cbe3 /* 0x0130 */; + 077: data_o = 32'h01000297 /* 0x0134 */; + 078: data_o = 32'hecc28293 /* 0x0138 */; + 079: data_o = 32'h0142e303 /* 0x013c */; + 080: data_o = 32'he2831302 /* 0x0140 */; + 081: data_o = 32'he2b30102 /* 0x0144 */; + 082: data_o = 32'h25730062 /* 0x0148 */; + 083: data_o = 32'h80e7f140 /* 0x014c */; + 084: data_o = 32'h80820002 /* 0x0150 */; + 085: data_o = 32'h43014281 /* 0x0154 */; + 086: data_o = 32'h0ff0000f /* 0x0158 */; + 087: data_o = 32'h0000100f /* 0x015c */; + 088: data_o = 32'h3ee010ef /* 0x0160 */; + 089: data_o = 32'h65130506 /* 0x0164 */; + 090: data_o = 32'h02970015 /* 0x0168 */; + 091: data_o = 32'h82930100 /* 0x016c */; + 092: data_o = 32'ha423e962 /* 0x0170 */; + 093: data_o = 32'h007300a2 /* 0x0174 */; + 094: data_o = 32'hbff51050 /* 0x0178 */; + 095: data_o = 32'h0185171b /* 0x017c */; + 096: data_o = 32'h0185579b /* 0x0180 */; + 097: data_o = 32'h8fd966c1 /* 0x0184 */; + 098: data_o = 32'hf0068693 /* 0x0188 */; + 099: data_o = 32'h0085571b /* 0x018c */; + 100: data_o = 32'h8fd98f75 /* 0x0190 */; + 101: data_o = 32'h0085151b /* 0x0194 */; + 102: data_o = 32'h00ff0737 /* 0x0198 */; + 103: data_o = 32'h8d5d8d79 /* 0x019c */; + 104: data_o = 32'h80822501 /* 0x01a0 */; + 105: data_o = 32'hca09832a /* 0x01a4 */; + 106: data_o = 32'h00058383 /* 0x01a8 */; + 107: data_o = 32'h00730023 /* 0x01ac */; + 108: data_o = 32'h0305167d /* 0x01b0 */; + 109: data_o = 32'hfa6d0585 /* 0x01b4 */; + 110: data_o = 32'h66b18082 /* 0x01b8 */; + 111: data_o = 32'h00040797 /* 0x01bc */; + 112: data_o = 32'h00040717 /* 0x01c0 */; + 113: data_o = 32'he4478793 /* 0x01c4 */; + 114: data_o = 32'he4070713 /* 0x01c8 */; + 115: data_o = 32'h973697b6 /* 0x01cc */; + 116: data_o = 32'hffc7a783 /* 0x01d0 */; + 117: data_o = 32'hff872703 /* 0x01d4 */; + 118: data_o = 32'h17021782 /* 0x01d8 */; + 119: data_o = 32'h8fd99301 /* 0x01dc */; + 120: data_o = 32'hfca7eee3 /* 0x01e0 */; + 121: data_o = 32'hc5298082 /* 0x01e4 */; + 122: data_o = 32'h4789ee9d /* 0x01e8 */; + 123: data_o = 32'h04f60963 /* 0x01ec */; + 124: data_o = 32'h0163478d /* 0x01f0 */; + 125: data_o = 32'h167d04f6 /* 0x01f4 */; + 126: data_o = 32'h00c03633 /* 0x01f8 */; + 127: data_o = 32'h47014801 /* 0x01fc */; + 128: data_o = 32'h00c6969b /* 0x0200 */; + 129: data_o = 32'h00d5e7b3 /* 0x0204 */; + 130: data_o = 32'h0086161b /* 0x0208 */; + 131: data_o = 32'h181b8fd1 /* 0x020c */; + 132: data_o = 32'h611400a8 /* 0x0210 */; + 133: data_o = 32'h0107e7b3 /* 0x0214 */; + 134: data_o = 32'h0097171b /* 0x0218 */; + 135: data_o = 32'h27818fd9 /* 0x021c */; + 136: data_o = 32'h4501cedc /* 0x0220 */; + 137: data_o = 32'h079b8082 /* 0x0224 */; + 138: data_o = 32'h4709ffd6 /* 0x0228 */; + 139: data_o = 32'hfaf76fe3 /* 0x022c */; + 140: data_o = 32'h8082450d /* 0x0230 */; + 141: data_o = 32'h4601fef5 /* 0x0234 */; + 142: data_o = 32'h47014805 /* 0x0238 */; + 143: data_o = 32'h4801b7d1 /* 0x023c */; + 144: data_o = 32'h46014705 /* 0x0240 */; + 145: data_o = 32'h7159bf75 /* 0x0244 */; + 146: data_o = 32'he8caf0a2 /* 0x0248 */; + 147: data_o = 32'he0d2e4ce /* 0x024c */; + 148: data_o = 32'hf85afc56 /* 0x0250 */; + 149: data_o = 32'hf062f45e /* 0x0254 */; + 150: data_o = 32'heca6f486 /* 0x0258 */; + 151: data_o = 32'he86aec66 /* 0x025c */; + 152: data_o = 32'h8936e46e /* 0x0260 */; + 153: data_o = 32'h89ae842a /* 0x0264 */; + 154: data_o = 32'h8b3a8ab2 /* 0x0268 */; + 155: data_o = 32'hfff68b93 /* 0x026c */; + 156: data_o = 32'h0c136a31 /* 0x0270 */; + 157: data_o = 32'h0b630200 /* 0x0274 */; + 158: data_o = 32'h60040e04 /* 0x0278 */; + 159: data_o = 32'hf51350dc /* 0x027c */; + 160: data_o = 32'h278107f7 /* 0x0280 */; + 161: data_o = 32'hd71bf96d /* 0x0284 */; + 162: data_o = 32'hd51b0107 /* 0x0288 */; + 163: data_o = 32'h8d590087 /* 0x028c */; + 164: data_o = 32'h0187d79b /* 0x0290 */; + 165: data_o = 32'hf7938fc9 /* 0x0294 */; + 166: data_o = 32'hfff107f7 /* 0x0298 */; + 167: data_o = 32'h00040717 /* 0x029c */; + 168: data_o = 32'h00040797 /* 0x02a0 */; + 169: data_o = 32'hd6470713 /* 0x02a4 */; + 170: data_o = 32'hd6078793 /* 0x02a8 */; + 171: data_o = 32'h97d29752 /* 0x02ac */; + 172: data_o = 32'hffc72683 /* 0x02b0 */; + 173: data_o = 32'hff87a783 /* 0x02b4 */; + 174: data_o = 32'h17821682 /* 0x02b8 */; + 175: data_o = 32'h8edd9381 /* 0x02bc */; + 176: data_o = 32'h07970685 /* 0x02c0 */; + 177: data_o = 32'h05170004 /* 0x02c4 */; + 178: data_o = 32'h87930004 /* 0x02c8 */; + 179: data_o = 32'h0513d3e7 /* 0x02cc */; + 180: data_o = 32'h97d2d3a5 /* 0x02d0 */; + 181: data_o = 32'ha7839552 /* 0x02d4 */; + 182: data_o = 32'h2703ffc7 /* 0x02d8 */; + 183: data_o = 32'h1782ff85 /* 0x02dc */; + 184: data_o = 32'h93011702 /* 0x02e0 */; + 185: data_o = 32'heee38fd9 /* 0x02e4 */; + 186: data_o = 32'h489cfcd7 /* 0x02e8 */; + 187: data_o = 32'h46014685 /* 0x02ec */; + 188: data_o = 32'hc89c9bf9 /* 0x02f0 */; + 189: data_o = 32'h0a000593 /* 0x02f4 */; + 190: data_o = 32'hf0ef8522 /* 0x02f8 */; + 191: data_o = 32'h0c9beedf /* 0x02fc */; + 192: data_o = 32'h96630005 /* 0x0300 */; + 193: data_o = 32'hd593060c /* 0x0304 */; + 194: data_o = 32'h4685008a /* 0x0308 */; + 195: data_o = 32'hf5934605 /* 0x030c */; + 196: data_o = 32'h85220ff5 /* 0x0310 */; + 197: data_o = 32'hed3ff0ef /* 0x0314 */; + 198: data_o = 32'h00050c9b /* 0x0318 */; + 199: data_o = 32'h040c9963 /* 0x031c */; + 200: data_o = 32'h0ffaf593 /* 0x0320 */; + 201: data_o = 32'h060b0563 /* 0x0324 */; + 202: data_o = 32'h46054685 /* 0x0328 */; + 203: data_o = 32'hf0ef8522 /* 0x032c */; + 204: data_o = 32'h079beb9f /* 0x0330 */; + 205: data_o = 32'heb8d0005 /* 0x0334 */; + 206: data_o = 32'h74638d5e /* 0x0338 */; + 207: data_o = 32'h0d13017c /* 0x033c */; + 208: data_o = 32'h4d810200 /* 0x0340 */; + 209: data_o = 32'h000b9563 /* 0x0344 */; + 210: data_o = 32'hf563a075 /* 0x0348 */; + 211: data_o = 32'h87b30bad /* 0x034c */; + 212: data_o = 32'hc58301b9 /* 0x0350 */; + 213: data_o = 32'h46850007 /* 0x0354 */; + 214: data_o = 32'h85224605 /* 0x0358 */; + 215: data_o = 32'he8bff0ef /* 0x035c */; + 216: data_o = 32'h0005079b /* 0x0360 */; + 217: data_o = 32'hd3f50d85 /* 0x0364 */; + 218: data_o = 32'ha0118cbe /* 0x0368 */; + 219: data_o = 32'h70a64c8d /* 0x036c */; + 220: data_o = 32'h64e67406 /* 0x0370 */; + 221: data_o = 32'h69a66946 /* 0x0374 */; + 222: data_o = 32'h7ae26a06 /* 0x0378 */; + 223: data_o = 32'h7ba27b42 /* 0x037c */; + 224: data_o = 32'h6d427c02 /* 0x0380 */; + 225: data_o = 32'h85666da2 /* 0x0384 */; + 226: data_o = 32'h61656ce2 /* 0x0388 */; + 227: data_o = 32'h46858082 /* 0x038c */; + 228: data_o = 32'h85224609 /* 0x0390 */; + 229: data_o = 32'he53ff0ef /* 0x0394 */; + 230: data_o = 32'h0005079b /* 0x0398 */; + 231: data_o = 32'h4685f7f1 /* 0x039c */; + 232: data_o = 32'h05934601 /* 0x03a0 */; + 233: data_o = 32'h85220a10 /* 0x03a4 */; + 234: data_o = 32'he3fff0ef /* 0x03a8 */; + 235: data_o = 32'h0005079b /* 0x03ac */; + 236: data_o = 32'h4681ffc5 /* 0x03b0 */; + 237: data_o = 32'h7593460d /* 0x03b4 */; + 238: data_o = 32'h85220ff9 /* 0x03b8 */; + 239: data_o = 32'he2bff0ef /* 0x03bc */; + 240: data_o = 32'h0005079b /* 0x03c0 */; + 241: data_o = 32'h489cf3d5 /* 0x03c4 */; + 242: data_o = 32'h0017e793 /* 0x03c8 */; + 243: data_o = 32'h50dcc89c /* 0x03cc */; + 244: data_o = 32'h0107d79b /* 0x03d0 */; + 245: data_o = 32'h07f7f793 /* 0x03d4 */; + 246: data_o = 32'hff27ebe3 /* 0x03d8 */; + 247: data_o = 32'h601c994e /* 0x03dc */; + 248: data_o = 32'h27814f9c /* 0x03e0 */; + 249: data_o = 32'h00098463 /* 0x03e4 */; + 250: data_o = 32'h00f98023 /* 0x03e8 */; + 251: data_o = 32'h18e30985 /* 0x03ec */; + 252: data_o = 32'hbfb5ff39 /* 0x03f0 */; + 253: data_o = 32'h017987b3 /* 0x03f4 */; + 254: data_o = 32'h0007c583 /* 0x03f8 */; + 255: data_o = 32'h46054685 /* 0x03fc */; + 256: data_o = 32'hf0ef8522 /* 0x0400 */; + 257: data_o = 32'h079bde5f /* 0x0404 */; + 258: data_o = 32'hffb90005 /* 0x0408 */; + 259: data_o = 32'h1b81489c /* 0x040c */; + 260: data_o = 32'h0017e793 /* 0x0410 */; + 261: data_o = 32'h7ce3c89c /* 0x0414 */; + 262: data_o = 32'h99caf52c /* 0x0418 */; + 263: data_o = 32'h19019aca /* 0x041c */; + 264: data_o = 32'h7139bd99 /* 0x0420 */; + 265: data_o = 32'hf426f822 /* 0x0424 */; + 266: data_o = 32'hec4ef04a /* 0x0428 */; + 267: data_o = 32'hfc06e852 /* 0x042c */; + 268: data_o = 32'h7413e456 /* 0x0430 */; + 269: data_o = 32'h893203f6 /* 0x0434 */; + 270: data_o = 32'h8a2e89aa /* 0x0438 */; + 271: data_o = 32'he42184b6 /* 0x043c */; + 272: data_o = 32'h04000a93 /* 0x0440 */; + 273: data_o = 32'h00946563 /* 0x0444 */; + 274: data_o = 32'h7c63a82d /* 0x0448 */; + 275: data_o = 32'h86b30294 /* 0x044c */; + 276: data_o = 32'h06334084 /* 0x0450 */; + 277: data_o = 32'h05b30089 /* 0x0454 */; + 278: data_o = 32'h4701008a /* 0x0458 */; + 279: data_o = 32'h0413854e /* 0x045c */; + 280: data_o = 32'hf4630404 /* 0x0460 */; + 281: data_o = 32'h069300da /* 0x0464 */; + 282: data_o = 32'hf0ef0400 /* 0x0468 */; + 283: data_o = 32'hdd71dddf /* 0x046c */; + 284: data_o = 32'h744270e2 /* 0x0470 */; + 285: data_o = 32'h790274a2 /* 0x0474 */; + 286: data_o = 32'h6a4269e2 /* 0x0478 */; + 287: data_o = 32'h61216aa2 /* 0x047c */; + 288: data_o = 32'h45018082 /* 0x0480 */; + 289: data_o = 32'h0793b7f5 /* 0x0484 */; + 290: data_o = 32'h84330400 /* 0x0488 */; + 291: data_o = 32'h47014087 /* 0x048c */; + 292: data_o = 32'hf0ef86a2 /* 0x0490 */; + 293: data_o = 32'hd54ddb5f /* 0x0494 */; + 294: data_o = 32'h1141bfe1 /* 0x0498 */; + 295: data_o = 32'he432e02e /* 0x049c */; + 296: data_o = 32'h9581c141 /* 0x04a0 */; + 297: data_o = 32'h4782cdb5 /* 0x04a4 */; + 298: data_o = 32'hd5bbcfa5 /* 0x04a8 */; + 299: data_o = 32'h77c102f5 /* 0x04ac */; + 300: data_o = 32'h269988aa /* 0x04b0 */; + 301: data_o = 32'h0026969b /* 0x04b4 */; + 302: data_o = 32'h0015d59b /* 0x04b8 */; + 303: data_o = 32'h8fed35fd /* 0x04bc */; + 304: data_o = 32'h0007851b /* 0x04c0 */; + 305: data_o = 32'h4783ed31 /* 0x04c4 */; + 306: data_o = 32'h4e0300c1 /* 0x04c8 */; + 307: data_o = 32'h430300b1 /* 0x04cc */; + 308: data_o = 32'h480300d1 /* 0x04d0 */; + 309: data_o = 32'h46030081 /* 0x04d4 */; + 310: data_o = 32'h979b0091 /* 0x04d8 */; + 311: data_o = 32'h1e1b01e7 /* 0x04dc */; + 312: data_o = 32'h470301de /* 0x04e0 */; + 313: data_o = 32'he7b300a1 /* 0x04e4 */; + 314: data_o = 32'h131b01c7 /* 0x04e8 */; + 315: data_o = 32'h781301f3 /* 0x04ec */; + 316: data_o = 32'he7b300f8 /* 0x04f0 */; + 317: data_o = 32'h8fcd0067 /* 0x04f4 */; + 318: data_o = 32'h159b8a3d /* 0x04f8 */; + 319: data_o = 32'h8fcd0108 /* 0x04fc */; + 320: data_o = 32'h0008b803 /* 0x0500 */; + 321: data_o = 32'h0146161b /* 0x0504 */; + 322: data_o = 32'h171b8b3d /* 0x0508 */; + 323: data_o = 32'h8fd10187 /* 0x050c */; + 324: data_o = 32'h8fd91682 /* 0x0510 */; + 325: data_o = 32'h27819281 /* 0x0514 */; + 326: data_o = 32'h00d80733 /* 0x0518 */; + 327: data_o = 32'ha011c31c /* 0x051c */; + 328: data_o = 32'h0141450d /* 0x0520 */; + 329: data_o = 32'h65858082 /* 0x0524 */; + 330: data_o = 32'h9c458593 /* 0x0528 */; + 331: data_o = 32'h02b555b3 /* 0x052c */; + 332: data_o = 32'h00040797 /* 0x0530 */; + 333: data_o = 32'h00040697 /* 0x0534 */; + 334: data_o = 32'h86936731 /* 0x0538 */; + 335: data_o = 32'h8793acc6 /* 0x053c */; + 336: data_o = 32'h97baad07 /* 0x0540 */; + 337: data_o = 32'ha6039736 /* 0x0544 */; + 338: data_o = 32'h2783ffc7 /* 0x0548 */; + 339: data_o = 32'h66b1ff87 /* 0x054c */; + 340: data_o = 32'h17821602 /* 0x0550 */; + 341: data_o = 32'h8e5d9381 /* 0x0554 */; + 342: data_o = 32'hb0002873 /* 0x0558 */; + 343: data_o = 32'h00040717 /* 0x055c */; + 344: data_o = 32'h00040797 /* 0x0560 */; + 345: data_o = 32'haa470713 /* 0x0564 */; + 346: data_o = 32'haa078793 /* 0x0568 */; + 347: data_o = 32'h97b69736 /* 0x056c */; + 348: data_o = 32'hffc72703 /* 0x0570 */; + 349: data_o = 32'hff87a783 /* 0x0574 */; + 350: data_o = 32'h17821702 /* 0x0578 */; + 351: data_o = 32'h8f5d9381 /* 0x057c */; + 352: data_o = 32'hfce60ce3 /* 0x0580 */; + 353: data_o = 32'h663195ba /* 0x0584 */; + 354: data_o = 32'hb00028f3 /* 0x0588 */; + 355: data_o = 32'h00040797 /* 0x058c */; + 356: data_o = 32'h00040697 /* 0x0590 */; + 357: data_o = 32'ha7478793 /* 0x0594 */; + 358: data_o = 32'ha7068693 /* 0x0598 */; + 359: data_o = 32'h96b297b2 /* 0x059c */; + 360: data_o = 32'hffc7a783 /* 0x05a0 */; + 361: data_o = 32'hff86a683 /* 0x05a4 */; + 362: data_o = 32'h16821782 /* 0x05a8 */; + 363: data_o = 32'h8fd59281 /* 0x05ac */; + 364: data_o = 32'hfcb7ece3 /* 0x05b0 */; + 365: data_o = 32'h410888b3 /* 0x05b4 */; + 366: data_o = 32'h85338f99 /* 0x05b8 */; + 367: data_o = 32'h553302a8 /* 0x05bc */; + 368: data_o = 32'h808202f5 /* 0x05c0 */; + 369: data_o = 32'h0733c585 /* 0x05c4 */; + 370: data_o = 32'h279700b5 /* 0x05c8 */; + 371: data_o = 32'h87930100 /* 0x05cc */; + 372: data_o = 32'hc783a367 /* 0x05d0 */; + 373: data_o = 32'h8b850147 /* 0x05d4 */; + 374: data_o = 32'h2797dbed /* 0x05d8 */; + 375: data_o = 32'hc7830100 /* 0x05dc */; + 376: data_o = 32'h0505a267 /* 0x05e0 */; + 377: data_o = 32'hfef50fa3 /* 0x05e4 */; + 378: data_o = 32'hfee511e3 /* 0x05e8 */; + 379: data_o = 32'h71398082 /* 0x05ec */; + 380: data_o = 32'hf822fc06 /* 0x05f0 */; + 381: data_o = 32'hf04af426 /* 0x05f4 */; + 382: data_o = 32'he852ec4e /* 0x05f8 */; + 383: data_o = 32'h01002797 /* 0x05fc */; + 384: data_o = 32'ha0478793 /* 0x0600 */; + 385: data_o = 32'h0147c783 /* 0x0604 */; + 386: data_o = 32'h0207f793 /* 0x0608 */; + 387: data_o = 32'h2797dbe5 /* 0x060c */; + 388: data_o = 32'h47190100 /* 0x0610 */; + 389: data_o = 32'h9ee78923 /* 0x0614 */; + 390: data_o = 32'h44994a49 /* 0x0618 */; + 391: data_o = 32'h49cd4411 /* 0x061c */; + 392: data_o = 32'h000f4945 /* 0x0620 */; + 393: data_o = 32'h27970ff0 /* 0x0624 */; + 394: data_o = 32'h87930100 /* 0x0628 */; + 395: data_o = 32'hc7839da7 /* 0x062c */; + 396: data_o = 32'h8b850147 /* 0x0630 */; + 397: data_o = 32'h2797dbed /* 0x0634 */; + 398: data_o = 32'hc7030100 /* 0x0638 */; + 399: data_o = 32'h77939ca7 /* 0x063c */; + 400: data_o = 32'h0f630ff7 /* 0x0640 */; + 401: data_o = 32'h8d630147 /* 0x0644 */; + 402: data_o = 32'h82630d37 /* 0x0648 */; + 403: data_o = 32'h45050727 /* 0x064c */; + 404: data_o = 32'h744270e2 /* 0x0650 */; + 405: data_o = 32'h790274a2 /* 0x0654 */; + 406: data_o = 32'h6a4269e2 /* 0x0658 */; + 407: data_o = 32'h80826121 /* 0x065c */; + 408: data_o = 32'h850a45a1 /* 0x0660 */; + 409: data_o = 32'hf61ff0ef /* 0x0664 */; + 410: data_o = 32'h002845a1 /* 0x0668 */; + 411: data_o = 32'hf59ff0ef /* 0x066c */; + 412: data_o = 32'h01002797 /* 0x0670 */; + 413: data_o = 32'h99078793 /* 0x0674 */; + 414: data_o = 32'h0147c783 /* 0x0678 */; + 415: data_o = 32'h0207f793 /* 0x067c */; + 416: data_o = 32'h65a2dbe5 /* 0x0680 */; + 417: data_o = 32'h27976502 /* 0x0684 */; + 418: data_o = 32'h8d230100 /* 0x0688 */; + 419: data_o = 32'hf0ef9697 /* 0x068c */; + 420: data_o = 32'h2797f37f /* 0x0690 */; + 421: data_o = 32'h87930100 /* 0x0694 */; + 422: data_o = 32'hc78396e7 /* 0x0698 */; + 423: data_o = 32'hf7930147 /* 0x069c */; + 424: data_o = 32'hdbe50207 /* 0x06a0 */; + 425: data_o = 32'h01002797 /* 0x06a4 */; + 426: data_o = 32'h94878e23 /* 0x06a8 */; + 427: data_o = 32'h45a1bf9d /* 0x06ac */; + 428: data_o = 32'hf0ef850a /* 0x06b0 */; + 429: data_o = 32'h45a1f13f /* 0x06b4 */; + 430: data_o = 32'hf0ef0028 /* 0x06b8 */; + 431: data_o = 32'h2797f0bf /* 0x06bc */; + 432: data_o = 32'h87930100 /* 0x06c0 */; + 433: data_o = 32'hc7839427 /* 0x06c4 */; + 434: data_o = 32'hf7930147 /* 0x06c8 */; + 435: data_o = 32'hdbe50207 /* 0x06cc */; + 436: data_o = 32'h27976622 /* 0x06d0 */; + 437: data_o = 32'h87230100 /* 0x06d4 */; + 438: data_o = 32'h67029297 /* 0x06d8 */; + 439: data_o = 32'h963ac605 /* 0x06dc */; + 440: data_o = 32'h00074683 /* 0x06e0 */; + 441: data_o = 32'h01002797 /* 0x06e4 */; + 442: data_o = 32'h91c78793 /* 0x06e8 */; + 443: data_o = 32'h0147c783 /* 0x06ec */; + 444: data_o = 32'h0207f793 /* 0x06f0 */; + 445: data_o = 32'h2797dbe5 /* 0x06f4 */; + 446: data_o = 32'h85230100 /* 0x06f8 */; + 447: data_o = 32'h070590d7 /* 0x06fc */; + 448: data_o = 32'hfee610e3 /* 0x0700 */; + 449: data_o = 32'h01002797 /* 0x0704 */; + 450: data_o = 32'h8fc78793 /* 0x0708 */; + 451: data_o = 32'h0147c783 /* 0x070c */; + 452: data_o = 32'h0207f793 /* 0x0710 */; + 453: data_o = 32'h2797dbe5 /* 0x0714 */; + 454: data_o = 32'h85230100 /* 0x0718 */; + 455: data_o = 32'hb7118e87 /* 0x071c */; + 456: data_o = 32'h850a45a1 /* 0x0720 */; + 457: data_o = 32'hea1ff0ef /* 0x0724 */; + 458: data_o = 32'h01002797 /* 0x0728 */; + 459: data_o = 32'h8d878793 /* 0x072c */; + 460: data_o = 32'h0147c783 /* 0x0730 */; + 461: data_o = 32'h0207f793 /* 0x0734 */; + 462: data_o = 32'h2797dbe5 /* 0x0738 */; + 463: data_o = 32'h47190100 /* 0x073c */; + 464: data_o = 32'h8ce78323 /* 0x0740 */; + 465: data_o = 32'h0ff0000f /* 0x0744 */; + 466: data_o = 32'h100f6782 /* 0x0748 */; + 467: data_o = 32'h97820000 /* 0x074c */; + 468: data_o = 32'h000fc42a /* 0x0750 */; + 469: data_o = 32'h27970ff0 /* 0x0754 */; + 470: data_o = 32'h87930100 /* 0x0758 */; + 471: data_o = 32'hc7838aa7 /* 0x075c */; + 472: data_o = 32'hf7930147 /* 0x0760 */; + 473: data_o = 32'hdbe50207 /* 0x0764 */; + 474: data_o = 32'h27974751 /* 0x0768 */; + 475: data_o = 32'h8b230100 /* 0x076c */; + 476: data_o = 32'h007088e7 /* 0x0770 */; + 477: data_o = 32'h46830038 /* 0x0774 */; + 478: data_o = 32'h27970007 /* 0x0778 */; + 479: data_o = 32'h87930100 /* 0x077c */; + 480: data_o = 32'hc7838867 /* 0x0780 */; + 481: data_o = 32'hf7930147 /* 0x0784 */; + 482: data_o = 32'hdbe50207 /* 0x0788 */; + 483: data_o = 32'h01002797 /* 0x078c */; + 484: data_o = 32'h86d78a23 /* 0x0790 */; + 485: data_o = 32'h10e30705 /* 0x0794 */; + 486: data_o = 32'h4522fec7 /* 0x0798 */; + 487: data_o = 32'h07b7bd55 /* 0x079c */; + 488: data_o = 32'hc91c4000 /* 0x07a0 */; + 489: data_o = 32'hd79b495c /* 0x07a4 */; + 490: data_o = 32'h8b8501e7 /* 0x07a8 */; + 491: data_o = 32'h495cffe5 /* 0x07ac */; + 492: data_o = 32'h0087d71b /* 0x07b0 */; + 493: data_o = 32'hf7938fd9 /* 0x07b4 */; + 494: data_o = 32'hfbf50ff7 /* 0x07b8 */; + 495: data_o = 32'h00052823 /* 0x07bc */; + 496: data_o = 32'hc93d8082 /* 0x07c0 */; + 497: data_o = 32'h001c27b7 /* 0x07c4 */; + 498: data_o = 32'h02f55533 /* 0x07c8 */; + 499: data_o = 32'h01002797 /* 0x07cc */; + 500: data_o = 32'h83478793 /* 0x07d0 */; + 501: data_o = 32'h00078223 /* 0x07d4 */; + 502: data_o = 32'h01002797 /* 0x07d8 */; + 503: data_o = 32'h82878793 /* 0x07dc */; + 504: data_o = 32'hf8000693 /* 0x07e0 */; + 505: data_o = 32'h00d78623 /* 0x07e4 */; 506: data_o = 32'h01002797 /* 0x07e8 */; - 507: data_o = 32'h81878793 /* 0x07ec */; - 508: data_o = 32'hf8000693 /* 0x07f0 */; - 509: data_o = 32'h00d78623 /* 0x07f4 */; - 510: data_o = 32'h01002797 /* 0x07f8 */; - 511: data_o = 32'h0ff57713 /* 0x07fc */; - 512: data_o = 32'h80e78423 /* 0x0800 */; - 513: data_o = 32'h17978121 /* 0x0804 */; - 514: data_o = 32'h75130100 /* 0x0808 */; - 515: data_o = 32'h87930ff5 /* 0x080c */; - 516: data_o = 32'h82237fa7 /* 0x0810 */; - 517: data_o = 32'h179700a7 /* 0x0814 */; - 518: data_o = 32'h87930100 /* 0x0818 */; - 519: data_o = 32'h470d7ea7 /* 0x081c */; - 520: data_o = 32'h00e78623 /* 0x0820 */; + 507: data_o = 32'h0ff57713 /* 0x07ec */; + 508: data_o = 32'h80e78c23 /* 0x07f0 */; + 509: data_o = 32'h27978121 /* 0x07f4 */; + 510: data_o = 32'h75130100 /* 0x07f8 */; + 511: data_o = 32'h87930ff5 /* 0x07fc */; + 512: data_o = 32'h822380a7 /* 0x0800 */; + 513: data_o = 32'h179700a7 /* 0x0804 */; + 514: data_o = 32'h87930100 /* 0x0808 */; + 515: data_o = 32'h470d7fa7 /* 0x080c */; + 516: data_o = 32'h00e78623 /* 0x0810 */; + 517: data_o = 32'h01001797 /* 0x0814 */; + 518: data_o = 32'h7ec78793 /* 0x0818 */; + 519: data_o = 32'hfc700713 /* 0x081c */; + 520: data_o = 32'h00e78423 /* 0x0820 */; 521: data_o = 32'h01001797 /* 0x0824 */; 522: data_o = 32'h7dc78793 /* 0x0828 */; - 523: data_o = 32'hfc700713 /* 0x082c */; - 524: data_o = 32'h00e78423 /* 0x0830 */; - 525: data_o = 32'h01001797 /* 0x0834 */; - 526: data_o = 32'h7cc78793 /* 0x0838 */; - 527: data_o = 32'h02000713 /* 0x083c */; - 528: data_o = 32'h00e78823 /* 0x0840 */; - 529: data_o = 32'h0ff0000f /* 0x0844 */; - 530: data_o = 32'hf7974719 /* 0x0848 */; - 531: data_o = 32'h879300ff /* 0x084c */; - 532: data_o = 32'h479c7b67 /* 0x0850 */; - 533: data_o = 32'hc7958b89 /* 0x0854 */; - 534: data_o = 32'h00fff797 /* 0x0858 */; - 535: data_o = 32'h7a878793 /* 0x085c */; - 536: data_o = 32'h0007a423 /* 0x0860 */; - 537: data_o = 32'h00fff797 /* 0x0864 */; - 538: data_o = 32'h79c78793 /* 0x0868 */; - 539: data_o = 32'hf79743c8 /* 0x086c */; - 540: data_o = 32'ha78300ff /* 0x0870 */; - 541: data_o = 32'h15027927 /* 0x0874 */; - 542: data_o = 32'h93811782 /* 0x0878 */; - 543: data_o = 32'hf06f8d5d /* 0x087c */; - 544: data_o = 32'h179783bf /* 0x0880 */; - 545: data_o = 32'h87930100 /* 0x0884 */; - 546: data_o = 32'hc78377e7 /* 0x0888 */; - 547: data_o = 32'h8b850147 /* 0x088c */; - 548: data_o = 32'h1797dfcd /* 0x0890 */; - 549: data_o = 32'hc7830100 /* 0x0894 */; - 550: data_o = 32'h98e376e7 /* 0x0898 */; - 551: data_o = 32'hb385fae7 /* 0x089c */; - 552: data_o = 32'he8221101 /* 0x08a0 */; - 553: data_o = 32'he4266100 /* 0x08a4 */; - 554: data_o = 32'hec06e04a /* 0x08a8 */; - 555: data_o = 32'h84b2892e /* 0x08ac */; - 556: data_o = 32'h04800713 /* 0x08b0 */; - 557: data_o = 32'hf793485c /* 0x08b4 */; - 558: data_o = 32'h8de30ff7 /* 0x08b8 */; - 559: data_o = 32'h2503fee7 /* 0x08bc */; - 560: data_o = 32'hf0ef0109 /* 0x08c0 */; - 561: data_o = 32'h27038cbf /* 0x08c4 */; - 562: data_o = 32'h478500c9 /* 0x08c8 */; - 563: data_o = 32'h02f70f63 /* 0x08cc */; - 564: data_o = 32'h0085551b /* 0x08d0 */; - 565: data_o = 32'h4689d808 /* 0x08d4 */; - 566: data_o = 32'h00892783 /* 0x08d8 */; - 567: data_o = 32'h0014c493 /* 0x08dc */; - 568: data_o = 32'h949b6705 /* 0x08e0 */; - 569: data_o = 32'h07130094 /* 0x08e4 */; - 570: data_o = 32'h979bc007 /* 0x08e8 */; - 571: data_o = 32'h8ff900a7 /* 0x08ec */; - 572: data_o = 32'h0096e733 /* 0x08f0 */; - 573: data_o = 32'h67098fd9 /* 0x08f4 */; - 574: data_o = 32'h27818fd9 /* 0x08f8 */; - 575: data_o = 32'hd41c60e2 /* 0x08fc */; - 576: data_o = 32'h64a26442 /* 0x0900 */; - 577: data_o = 32'h61056902 /* 0x0904 */; - 578: data_o = 32'hd8088082 /* 0x0908 */; - 579: data_o = 32'hb7e9468d /* 0x090c */; - 580: data_o = 32'hc99dcd0d /* 0x0910 */; - 581: data_o = 32'h0035f793 /* 0x0914 */; - 582: data_o = 32'h0693cb9d /* 0x0918 */; - 583: data_o = 32'hc21d0480 /* 0x091c */; - 584: data_o = 32'h4b5c6118 /* 0x0920 */; - 585: data_o = 32'h0ff7f793 /* 0x0924 */; - 586: data_o = 32'hfed78de3 /* 0x0928 */; - 587: data_o = 32'h0005c783 /* 0x092c */; - 588: data_o = 32'h0585367d /* 0x0930 */; - 589: data_o = 32'h02f70823 /* 0x0934 */; - 590: data_o = 32'hf7931642 /* 0x0938 */; - 591: data_o = 32'h92410035 /* 0x093c */; - 592: data_o = 32'hfe79c799 /* 0x0940 */; - 593: data_o = 32'h80824501 /* 0x0944 */; - 594: data_o = 32'h450dde75 /* 0x0948 */; - 595: data_o = 32'h478d8082 /* 0x094c */; - 596: data_o = 32'hf963882e /* 0x0950 */; - 597: data_o = 32'h081b02c7 /* 0x0954 */; - 598: data_o = 32'h1842ffc6 /* 0x0958 */; - 599: data_o = 32'h03285813 /* 0x095c */; - 600: data_o = 32'h080a6118 /* 0x0960 */; - 601: data_o = 32'h00458793 /* 0x0964 */; - 602: data_o = 32'h0693983e /* 0x0968 */; - 603: data_o = 32'h4b5c0480 /* 0x096c */; - 604: data_o = 32'h0ff7f793 /* 0x0970 */; - 605: data_o = 32'hfed78de3 /* 0x0974 */; - 606: data_o = 32'h0591419c /* 0x0978 */; - 607: data_o = 32'h98e3db1c /* 0x097c */; - 608: data_o = 32'h8a0dff05 /* 0x0980 */; - 609: data_o = 32'hde5d85c2 /* 0x0984 */; - 610: data_o = 32'h00c8073b /* 0x0988 */; - 611: data_o = 32'h06131742 /* 0x098c */; - 612: data_o = 32'h93410480 /* 0x0990 */; - 613: data_o = 32'h4adc6114 /* 0x0994 */; - 614: data_o = 32'h0ff7f793 /* 0x0998 */; - 615: data_o = 32'hfec78de3 /* 0x099c */; - 616: data_o = 32'h0005c803 /* 0x09a0 */; - 617: data_o = 32'h97930585 /* 0x09a4 */; - 618: data_o = 32'h93c10305 /* 0x09a8 */; - 619: data_o = 32'h03068823 /* 0x09ac */; - 620: data_o = 32'hfef712e3 /* 0x09b0 */; - 621: data_o = 32'h80824501 /* 0x09b4 */; - 622: data_o = 32'h71794198 /* 0x09b8 */; - 623: data_o = 32'he44ef022 /* 0x09bc */; - 624: data_o = 32'hec26f406 /* 0x09c0 */; - 625: data_o = 32'h4691e84a /* 0x09c4 */; - 626: data_o = 32'h89aa87ae /* 0x09c8 */; - 627: data_o = 32'h00638432 /* 0x09cc */; - 628: data_o = 32'h469502d7 /* 0x09d0 */; - 629: data_o = 32'h06d70a63 /* 0x09d4 */; - 630: data_o = 32'h0d63468d /* 0x09d8 */; - 631: data_o = 32'h70a204d7 /* 0x09dc */; - 632: data_o = 32'h64e27402 /* 0x09e0 */; - 633: data_o = 32'h69a26942 /* 0x09e4 */; - 634: data_o = 32'h6145450d /* 0x09e8 */; - 635: data_o = 32'ha9038082 /* 0x09ec */; - 636: data_o = 32'hd4830085 /* 0x09f0 */; - 637: data_o = 32'h67850185 /* 0x09f4 */; - 638: data_o = 32'h00144413 /* 0x09f8 */; - 639: data_o = 32'h141b6705 /* 0x09fc */; - 640: data_o = 32'h07130094 /* 0x0a00 */; - 641: data_o = 32'h191bc007 /* 0x0a04 */; - 642: data_o = 32'h793300a9 /* 0x0a08 */; - 643: data_o = 32'h8fc100e9 /* 0x0a0c */; - 644: data_o = 32'hb70334fd /* 0x0a10 */; - 645: data_o = 32'he7b30009 /* 0x0a14 */; - 646: data_o = 32'hf4930127 /* 0x0a18 */; - 647: data_o = 32'h70a21ff4 /* 0x0a1c */; - 648: data_o = 32'h8fc57402 /* 0x0a20 */; - 649: data_o = 32'hd71c2781 /* 0x0a24 */; - 650: data_o = 32'h694264e2 /* 0x0a28 */; - 651: data_o = 32'h450169a2 /* 0x0a2c */; - 652: data_o = 32'h80826145 /* 0x0a30 */; - 653: data_o = 32'h0185d483 /* 0x0a34 */; - 654: data_o = 32'ha903698c /* 0x0a38 */; - 655: data_o = 32'h86260087 /* 0x0a3c */; - 656: data_o = 32'hed1ff0ef /* 0x0a40 */; - 657: data_o = 32'hbf4d6789 /* 0x0a44 */; - 658: data_o = 32'h0205d483 /* 0x0a48 */; - 659: data_o = 32'ha903698c /* 0x0a4c */; - 660: data_o = 32'h86260087 /* 0x0a50 */; - 661: data_o = 32'hebdff0ef /* 0x0a54 */; - 662: data_o = 32'hbf79678d /* 0x0a58 */; - 663: data_o = 32'h16050a63 /* 0x0a5c */; - 664: data_o = 32'h14058763 /* 0x0a60 */; - 665: data_o = 32'he0021141 /* 0x0a64 */; - 666: data_o = 32'hf793e402 /* 0x0a68 */; - 667: data_o = 32'hc78d0035 /* 0x0a6c */; - 668: data_o = 32'hc6414701 /* 0x0a70 */; - 669: data_o = 32'h08e05663 /* 0x0a74 */; - 670: data_o = 32'h4783377d /* 0x0a78 */; - 671: data_o = 32'h05850081 /* 0x0a7c */; - 672: data_o = 32'h8fa3367d /* 0x0a80 */; - 673: data_o = 32'h67a2fef5 /* 0x0a84 */; - 674: data_o = 32'hc03a1642 /* 0x0a88 */; - 675: data_o = 32'he43e83a1 /* 0x0a8c */; - 676: data_o = 32'h0035f793 /* 0x0a90 */; - 677: data_o = 32'hfff19241 /* 0x0a94 */; - 678: data_o = 32'hfd63478d /* 0x0a98 */; - 679: data_o = 32'h069b12c7 /* 0x0a9c */; - 680: data_o = 32'h16c2ffc6 /* 0x0aa0 */; - 681: data_o = 32'h470292c9 /* 0x0aa4 */; - 682: data_o = 32'h8793068a /* 0x0aa8 */; - 683: data_o = 32'h96be0045 /* 0x0aac */; - 684: data_o = 32'hd863488d /* 0x0ab0 */; - 685: data_o = 32'h377108e8 /* 0x0ab4 */; - 686: data_o = 32'h47b24822 /* 0x0ab8 */; - 687: data_o = 32'ha023c03a /* 0x0abc */; - 688: data_o = 32'hc43e0105 /* 0x0ac0 */; - 689: data_o = 32'h96e30591 /* 0x0ac4 */; - 690: data_o = 32'h8a0dfed5 /* 0x0ac8 */; - 691: data_o = 32'h8736c61d /* 0x0acc */; - 692: data_o = 32'h46829e39 /* 0x0ad0 */; - 693: data_o = 32'h92411642 /* 0x0ad4 */; - 694: data_o = 32'h0ad05863 /* 0x0ad8 */; - 695: data_o = 32'h478336fd /* 0x0adc */; - 696: data_o = 32'h07050081 /* 0x0ae0 */; - 697: data_o = 32'h0fa3c036 /* 0x0ae4 */; - 698: data_o = 32'h67a2fef7 /* 0x0ae8 */; - 699: data_o = 32'he43e83a1 /* 0x0aec */; - 700: data_o = 32'h03071793 /* 0x0af0 */; - 701: data_o = 32'h11e393c1 /* 0x0af4 */; - 702: data_o = 32'h4501fef6 /* 0x0af8 */; - 703: data_o = 32'h80820141 /* 0x0afc */; - 704: data_o = 32'h4adc6114 /* 0x0b00 */; - 705: data_o = 32'h0087d79b /* 0x0b04 */; - 706: data_o = 32'h0ff7f793 /* 0x0b08 */; - 707: data_o = 32'h56dcdbfd /* 0x0b0c */; - 708: data_o = 32'h00377693 /* 0x0b10 */; - 709: data_o = 32'hea812781 /* 0x0b14 */; - 710: data_o = 32'h970a0741 /* 0x0b18 */; - 711: data_o = 32'hfef72c23 /* 0x0b1c */; - 712: data_o = 32'h270d4702 /* 0x0b20 */; - 713: data_o = 32'h0813bf99 /* 0x0b24 */; - 714: data_o = 32'h06b30041 /* 0x0b28 */; - 715: data_o = 32'h983a00e1 /* 0x0b2c */; - 716: data_o = 32'h00f68423 /* 0x0b30 */; - 717: data_o = 32'hd79b0685 /* 0x0b34 */; - 718: data_o = 32'h9be30087 /* 0x0b38 */; - 719: data_o = 32'h270dff06 /* 0x0b3c */; - 720: data_o = 32'h3803bf2d /* 0x0b40 */; - 721: data_o = 32'h27830005 /* 0x0b44 */; - 722: data_o = 32'hd79b0148 /* 0x0b48 */; - 723: data_o = 32'hf7930087 /* 0x0b4c */; - 724: data_o = 32'hdbf50ff7 /* 0x0b50 */; - 725: data_o = 32'h02c82783 /* 0x0b54 */; - 726: data_o = 32'h00377813 /* 0x0b58 */; - 727: data_o = 32'h18632781 /* 0x0b5c */; - 728: data_o = 32'h07410008 /* 0x0b60 */; - 729: data_o = 32'h2c23970a /* 0x0b64 */; - 730: data_o = 32'h4702fef7 /* 0x0b68 */; - 731: data_o = 32'h0313b7b1 /* 0x0b6c */; - 732: data_o = 32'h08330041 /* 0x0b70 */; - 733: data_o = 32'h933a00e1 /* 0x0b74 */; - 734: data_o = 32'h00f80423 /* 0x0b78 */; - 735: data_o = 32'hd79b0805 /* 0x0b7c */; - 736: data_o = 32'h1be30087 /* 0x0b80 */; - 737: data_o = 32'hbf0dfe68 /* 0x0b84 */; - 738: data_o = 32'h49dc610c /* 0x0b88 */; - 739: data_o = 32'h0087d79b /* 0x0b8c */; - 740: data_o = 32'h0ff7f793 /* 0x0b90 */; - 741: data_o = 32'h55dcdbfd /* 0x0b94 */; - 742: data_o = 32'h0036f593 /* 0x0b98 */; - 743: data_o = 32'he9992781 /* 0x0b9c */; - 744: data_o = 32'h968a06c1 /* 0x0ba0 */; - 745: data_o = 32'hfef6ac23 /* 0x0ba4 */; - 746: data_o = 32'h268d4682 /* 0x0ba8 */; - 747: data_o = 32'he20dbf0d /* 0x0bac */; - 748: data_o = 32'h80824501 /* 0x0bb0 */; - 749: data_o = 32'h00410813 /* 0x0bb4 */; - 750: data_o = 32'h00d105b3 /* 0x0bb8 */; - 751: data_o = 32'h84239836 /* 0x0bbc */; - 752: data_o = 32'h058500f5 /* 0x0bc0 */; - 753: data_o = 32'h0087d79b /* 0x0bc4 */; - 754: data_o = 32'hfeb81be3 /* 0x0bc8 */; - 755: data_o = 32'hbf01268d /* 0x0bcc */; - 756: data_o = 32'h8082450d /* 0x0bd0 */; - 757: data_o = 32'hbddd86ae /* 0x0bd4 */; - 758: data_o = 32'h712d6518 /* 0x0bd8 */; - 759: data_o = 32'h02faf7b7 /* 0x0bdc */; - 760: data_o = 32'hea22ee06 /* 0x0be0 */; - 761: data_o = 32'he24ae626 /* 0x0be4 */; - 762: data_o = 32'hf9d2fdce /* 0x0be8 */; - 763: data_o = 32'hf1daf5d6 /* 0x0bec */; - 764: data_o = 32'he9e2edde /* 0x0bf0 */; - 765: data_o = 32'he1eae5e6 /* 0x0bf4 */; - 766: data_o = 32'h8793fd6e /* 0x0bf8 */; - 767: data_o = 32'hf02e07f7 /* 0x0bfc */; - 768: data_o = 32'he436f432 /* 0x0c00 */; - 769: data_o = 32'h1ce7ed63 /* 0x0c04 */; - 770: data_o = 32'h4c0167a2 /* 0x0c08 */; - 771: data_o = 32'h12078863 /* 0x0c0c */; - 772: data_o = 32'h87936a85 /* 0x0c10 */; - 773: data_o = 32'h8d2ac00a /* 0x0c14 */; - 774: data_o = 32'he83e4485 /* 0x0c18 */; - 775: data_o = 32'h77a24985 /* 0x0c1c */; - 776: data_o = 32'he082f882 /* 0x0c20 */; - 777: data_o = 32'h00fc073b /* 0x0c24 */; - 778: data_o = 32'hf0827782 /* 0x0c28 */; - 779: data_o = 32'h97e2f482 /* 0x0c2c */; - 780: data_o = 32'h67a2ed3e /* 0x0c30 */; - 781: data_o = 32'h46cde502 /* 0x0c34 */; - 782: data_o = 32'h4711d8ba /* 0x0c38 */; - 783: data_o = 32'hfc02c53a /* 0x0c3c */; - 784: data_o = 32'he882e482 /* 0x0c40 */; - 785: data_o = 32'hfc82ec82 /* 0x0c44 */; - 786: data_o = 32'he902e102 /* 0x0c48 */; - 787: data_o = 32'h0023f502 /* 0x0c4c */; - 788: data_o = 32'hd0a604d1 /* 0x0c50 */; - 789: data_o = 32'h87b3d6a6 /* 0x0c54 */; - 790: data_o = 32'h07134187 /* 0x0c58 */; - 791: data_o = 32'h74631000 /* 0x0c5c */; - 792: data_o = 32'h079300f7 /* 0x0c60 */; - 793: data_o = 32'h27031000 /* 0x0c64 */; - 794: data_o = 32'h3403010d /* 0x0c68 */; - 795: data_o = 32'h0d93000d /* 0x0c6c */; - 796: data_o = 32'hf13e0381 /* 0x0c70 */; - 797: data_o = 32'h8a6ed058 /* 0x0c74 */; - 798: data_o = 32'h4a814701 /* 0x0c78 */; - 799: data_o = 32'h0c934b89 /* 0x0c7c */; - 800: data_o = 32'h69090480 /* 0x0c80 */; - 801: data_o = 32'h86134b0d /* 0x0c84 */; - 802: data_o = 32'h3613ffea /* 0x0c88 */; - 803: data_o = 32'h485c0016 /* 0x0c8c */; - 804: data_o = 32'h01f7d79b /* 0x0c90 */; - 805: data_o = 32'h0d63dfed /* 0x0c94 */; - 806: data_o = 32'he0631177 /* 0x0c98 */; - 807: data_o = 32'hc34d0eeb /* 0x0c9c */; - 808: data_o = 32'hf793485c /* 0x0ca0 */; - 809: data_o = 32'h8de30ff7 /* 0x0ca4 */; - 810: data_o = 32'h2503ff97 /* 0x0ca8 */; - 811: data_o = 32'hec32010a /* 0x0cac */; - 812: data_o = 32'hcdcff0ef /* 0x0cb0 */; - 813: data_o = 32'h00ca2783 /* 0x0cb4 */; - 814: data_o = 32'h8f636662 /* 0x0cb8 */; - 815: data_o = 32'h551b1097 /* 0x0cbc */; - 816: data_o = 32'hd8080085 /* 0x0cc0 */; - 817: data_o = 32'h27834709 /* 0x0cc4 */; - 818: data_o = 32'h66c2008a /* 0x0cc8 */; - 819: data_o = 32'h40c9863b /* 0x0ccc */; - 820: data_o = 32'h00a7979b /* 0x0cd0 */; - 821: data_o = 32'h0096161b /* 0x0cd4 */; - 822: data_o = 32'h8fd18ff5 /* 0x0cd8 */; - 823: data_o = 32'he7b38fd9 /* 0x0cdc */; - 824: data_o = 32'h27810127 /* 0x0ce0 */; - 825: data_o = 32'h0a85d41c /* 0x0ce4 */; - 826: data_o = 32'h028a0a13 /* 0x0ce8 */; - 827: data_o = 32'h096a9263 /* 0x0cec */; - 828: data_o = 32'h078d8c93 /* 0x0cf0 */; - 829: data_o = 32'h44154911 /* 0x0cf4 */; - 830: data_o = 32'h856aa831 /* 0x0cf8 */; - 831: data_o = 32'h00879863 /* 0x0cfc */; - 832: data_o = 32'h020dd603 /* 0x0d00 */; - 833: data_o = 32'h018db583 /* 0x0d04 */; - 834: data_o = 32'hd55ff0ef /* 0x0d08 */; - 835: data_o = 32'h028d8d93 /* 0x0d0c */; - 836: data_o = 32'h03bc8163 /* 0x0d10 */; - 837: data_o = 32'h000da783 /* 0x0d14 */; - 838: data_o = 32'hff2791e3 /* 0x0d18 */; - 839: data_o = 32'h018dd603 /* 0x0d1c */; - 840: data_o = 32'h010db583 /* 0x0d20 */; - 841: data_o = 32'h8d93856a /* 0x0d24 */; - 842: data_o = 32'hf0ef028d /* 0x0d28 */; - 843: data_o = 32'h93e3d33f /* 0x0d2c */; - 844: data_o = 32'h67a2ffbc /* 0x0d30 */; - 845: data_o = 32'h100c0c13 /* 0x0d34 */; - 846: data_o = 32'heefc63e3 /* 0x0d38 */; - 847: data_o = 32'ha8914501 /* 0x0d3c */; - 848: data_o = 32'hf793485c /* 0x0d40 */; - 849: data_o = 32'h8de30ff7 /* 0x0d44 */; - 850: data_o = 32'h4703ff97 /* 0x0d48 */; - 851: data_o = 32'h87bb008a /* 0x0d4c */; - 852: data_o = 32'h979b40c9 /* 0x0d50 */; - 853: data_o = 32'h08230097 /* 0x0d54 */; - 854: data_o = 32'h370302e4 /* 0x0d58 */; - 855: data_o = 32'he7b3000d /* 0x0d5c */; - 856: data_o = 32'h27810127 /* 0x0d60 */; - 857: data_o = 32'h0a85d71c /* 0x0d64 */; - 858: data_o = 32'h028a0a13 /* 0x0d68 */; - 859: data_o = 32'hf96a82e3 /* 0x0d6c */; - 860: data_o = 32'h000d3403 /* 0x0d70 */; - 861: data_o = 32'h000a2703 /* 0x0d74 */; - 862: data_o = 32'h3775b739 /* 0x0d78 */; - 863: data_o = 32'h00ebea63 /* 0x0d7c */; - 864: data_o = 32'h856a85d2 /* 0x0d80 */; - 865: data_o = 32'hc35ff0ef /* 0x0d84 */; - 866: data_o = 32'hdd712501 /* 0x0d88 */; - 867: data_o = 32'ha0112501 /* 0x0d8c */; - 868: data_o = 32'h60f2450d /* 0x0d90 */; - 869: data_o = 32'h64b26452 /* 0x0d94 */; - 870: data_o = 32'h79ee6912 /* 0x0d98 */; - 871: data_o = 32'h7aae7a4e /* 0x0d9c */; - 872: data_o = 32'h6bee7b0e /* 0x0da0 */; - 873: data_o = 32'h6cae6c4e /* 0x0da4 */; - 874: data_o = 32'h7dea6d0e /* 0x0da8 */; - 875: data_o = 32'h80826115 /* 0x0dac */; - 876: data_o = 32'h008a2783 /* 0x0db0 */; - 877: data_o = 32'h010a5703 /* 0x0db4 */; - 878: data_o = 32'h863b66c2 /* 0x0db8 */; - 879: data_o = 32'h979b40c9 /* 0x0dbc */; - 880: data_o = 32'h8ff500a7 /* 0x0dc0 */; - 881: data_o = 32'h0096161b /* 0x0dc4 */; - 882: data_o = 32'h8fd1377d /* 0x0dc8 */; - 883: data_o = 32'h1ff77713 /* 0x0dcc */; - 884: data_o = 32'h27818fd9 /* 0x0dd0 */; - 885: data_o = 32'hbf41d41c /* 0x0dd4 */; - 886: data_o = 32'h470dd808 /* 0x0dd8 */; - 887: data_o = 32'h4555b5ed /* 0x0ddc */; - 888: data_o = 32'h6118bf4d /* 0x0de0 */; - 889: data_o = 32'he8221101 /* 0x0de4 */; - 890: data_o = 32'hec06e426 /* 0x0de8 */; - 891: data_o = 32'h843284aa /* 0x0dec */; - 892: data_o = 32'h4b5cd34c /* 0x0df0 */; - 893: data_o = 32'h01f7d79b /* 0x0df4 */; - 894: data_o = 32'h401cdfed /* 0x0df8 */; - 895: data_o = 32'h8a634689 /* 0x0dfc */; - 896: data_o = 32'heb6308d7 /* 0x0e00 */; - 897: data_o = 32'hc3bd02f6 /* 0x0e04 */; - 898: data_o = 32'h85a24601 /* 0x0e08 */; - 899: data_o = 32'hf0ef8526 /* 0x0e0c */; - 900: data_o = 32'h401ca93f /* 0x0e10 */; - 901: data_o = 32'h8f634711 /* 0x0e14 */; - 902: data_o = 32'h471502e7 /* 0x0e18 */; - 903: data_o = 32'h04e79263 /* 0x0e1c */; - 904: data_o = 32'h02045603 /* 0x0e20 */; - 905: data_o = 32'h85266c0c /* 0x0e24 */; - 906: data_o = 32'hc35ff0ef /* 0x0e28 */; - 907: data_o = 32'h60e24501 /* 0x0e2c */; - 908: data_o = 32'h64a26442 /* 0x0e30 */; - 909: data_o = 32'h80826105 /* 0x0e34 */; - 910: data_o = 32'hea6337f5 /* 0x0e38 */; - 911: data_o = 32'h460104f6 /* 0x0e3c */; - 912: data_o = 32'h852685a2 /* 0x0e40 */; - 913: data_o = 32'hb75ff0ef /* 0x0e44 */; - 914: data_o = 32'hf1752501 /* 0x0e48 */; - 915: data_o = 32'h4711401c /* 0x0e4c */; - 916: data_o = 32'hfce795e3 /* 0x0e50 */; - 917: data_o = 32'h01845603 /* 0x0e54 */; - 918: data_o = 32'h8526680c /* 0x0e58 */; - 919: data_o = 32'hc01ff0ef /* 0x0e5c */; - 920: data_o = 32'h644260e2 /* 0x0e60 */; - 921: data_o = 32'h450164a2 /* 0x0e64 */; - 922: data_o = 32'h80826105 /* 0x0e68 */; - 923: data_o = 32'h04800693 /* 0x0e6c */; - 924: data_o = 32'hf7934b5c /* 0x0e70 */; - 925: data_o = 32'h8de30ff7 /* 0x0e74 */; - 926: data_o = 32'h4783fed7 /* 0x0e78 */; - 927: data_o = 32'h08230084 /* 0x0e7c */; - 928: data_o = 32'h609802f7 /* 0x0e80 */; - 929: data_o = 32'h87936789 /* 0x0e84 */; - 930: data_o = 32'hd71c2007 /* 0x0e88 */; - 931: data_o = 32'h450db759 /* 0x0e8c */; - 932: data_o = 32'h5783bf79 /* 0x0e90 */; - 933: data_o = 32'h44140104 /* 0x0e94 */; - 934: data_o = 32'h37fd6605 /* 0x0e98 */; - 935: data_o = 32'h00a6969b /* 0x0e9c */; - 936: data_o = 32'hc0060613 /* 0x0ea0 */; - 937: data_o = 32'h1ff7f793 /* 0x0ea4 */; - 938: data_o = 32'h8fd58ef1 /* 0x0ea8 */; - 939: data_o = 32'h2007e793 /* 0x0eac */; - 940: data_o = 32'hd71c2781 /* 0x0eb0 */; - 941: data_o = 32'h7175bfb9 /* 0x0eb4 */; - 942: data_o = 32'hec02e42e /* 0x0eb8 */; - 943: data_o = 32'h490c478d /* 0x0ebc */; - 944: data_o = 32'h003ccc3e /* 0x0ec0 */; - 945: data_o = 32'he8daf0d2 /* 0x0ec4 */; - 946: data_o = 32'h8b32f43e /* 0x0ec8 */; - 947: data_o = 32'h8a364799 /* 0x0ecc */; - 948: data_o = 32'h46850830 /* 0x0ed0 */; - 949: data_o = 32'hf8cae122 /* 0x0ed4 */; - 950: data_o = 32'he506f4ce /* 0x0ed8 */; - 951: data_o = 32'hecd6fca6 /* 0x0edc */; - 952: data_o = 32'h89aae4de /* 0x0ee0 */; - 953: data_o = 32'hf002893a /* 0x0ee4 */; - 954: data_o = 32'hf83efc02 /* 0x0ee8 */; - 955: data_o = 32'hef7ff0ef /* 0x0eec */; - 956: data_o = 32'h0005041b /* 0x0ef0 */; - 957: data_o = 32'h4703e421 /* 0x0ef4 */; - 958: data_o = 32'h07930081 /* 0x0ef8 */; - 959: data_o = 32'ha58304c0 /* 0x0efc */; - 960: data_o = 32'h06630109 /* 0x0f00 */; - 961: data_o = 32'h44a10af7 /* 0x0f04 */; - 962: data_o = 32'h4a854b91 /* 0x0f08 */; - 963: data_o = 32'h0783a029 /* 0x0f0c */; - 964: data_o = 32'hd163000a /* 0x0f10 */; - 965: data_o = 32'ha5830407 /* 0x0f14 */; - 966: data_o = 32'hec020109 /* 0x0f18 */; - 967: data_o = 32'h08304685 /* 0x0f1c */; - 968: data_o = 32'hf002854e /* 0x0f20 */; - 969: data_o = 32'hcc5efc02 /* 0x0f24 */; - 970: data_o = 32'hf856f452 /* 0x0f28 */; - 971: data_o = 32'heb7ff0ef /* 0x0f2c */; - 972: data_o = 32'h0005041b /* 0x0f30 */; - 973: data_o = 32'he01934fd /* 0x0f34 */; - 974: data_o = 32'h4449f8f9 /* 0x0f38 */; - 975: data_o = 32'h852260aa /* 0x0f3c */; - 976: data_o = 32'h74e6640a /* 0x0f40 */; - 977: data_o = 32'h79a67946 /* 0x0f44 */; - 978: data_o = 32'h6ae67a06 /* 0x0f48 */; - 979: data_o = 32'h6ba66b46 /* 0x0f4c */; - 980: data_o = 32'h80826149 /* 0x0f50 */; - 981: data_o = 32'h020b1693 /* 0x0f54 */; - 982: data_o = 32'h15418793 /* 0x0f58 */; - 983: data_o = 32'h01d6d713 /* 0x0f5c */; - 984: data_o = 32'h639c97ba /* 0x0f60 */; - 985: data_o = 32'h075b0863 /* 0x0f64 */; - 986: data_o = 32'he38517fd /* 0x0f68 */; - 987: data_o = 32'hfc0918e3 /* 0x0f6c */; - 988: data_o = 32'h0149a783 /* 0x0f70 */; - 989: data_o = 32'h0009b703 /* 0x0f74 */; - 990: data_o = 32'h4b5cd35c /* 0x0f78 */; - 991: data_o = 32'h01f7d79b /* 0x0f7c */; - 992: data_o = 32'h479ddfed /* 0x0f80 */; - 993: data_o = 32'h4401d71c /* 0x0f84 */; - 994: data_o = 32'ha583bf55 /* 0x0f88 */; - 995: data_o = 32'hec020109 /* 0x0f8c */; - 996: data_o = 32'h46850a05 /* 0x0f90 */; - 997: data_o = 32'h854e0830 /* 0x0f94 */; - 998: data_o = 32'hfc02f002 /* 0x0f98 */; - 999: data_o = 32'hf452cc5e /* 0x0f9c */; - 1000: data_o = 32'hf0eff83e /* 0x0fa0 */; - 1001: data_o = 32'h2501e41f /* 0x0fa4 */; - 1002: data_o = 32'h842ad171 /* 0x0fa8 */; - 1003: data_o = 32'hec02bf41 /* 0x0fac */; - 1004: data_o = 32'hcc3e4791 /* 0x0fb0 */; - 1005: data_o = 32'h01710793 /* 0x0fb4 */; - 1006: data_o = 32'h4685f43e /* 0x0fb8 */; - 1007: data_o = 32'h08304785 /* 0x0fbc */; - 1008: data_o = 32'hf002854e /* 0x0fc0 */; - 1009: data_o = 32'hf83efc02 /* 0x0fc4 */; - 1010: data_o = 32'he1bff0ef /* 0x0fc8 */; - 1011: data_o = 32'h0005041b /* 0x0fcc */; - 1012: data_o = 32'hb7add81d /* 0x0fd0 */; - 1013: data_o = 32'h84936489 /* 0x0fd4 */; - 1014: data_o = 32'h4b117104 /* 0x0fd8 */; - 1015: data_o = 32'h01710a93 /* 0x0fdc */; - 1016: data_o = 32'ha0294a05 /* 0x0fe0 */; - 1017: data_o = 32'h4783c49d /* 0x0fe4 */; - 1018: data_o = 32'hf3c90171 /* 0x0fe8 */; - 1019: data_o = 32'h0109a583 /* 0x0fec */; - 1020: data_o = 32'h4685ec02 /* 0x0ff0 */; - 1021: data_o = 32'h854e0830 /* 0x0ff4 */; - 1022: data_o = 32'hfc02f002 /* 0x0ff8 */; - 1023: data_o = 32'hf456cc5a /* 0x0ffc */; - 1024: data_o = 32'hf0eff852 /* 0x1000 */; - 1025: data_o = 32'h079bde1f /* 0x1004 */; - 1026: data_o = 32'h34fd0005 /* 0x1008 */; - 1027: data_o = 32'h843edfe1 /* 0x100c */; - 1028: data_o = 32'h444db735 /* 0x1010 */; - 1029: data_o = 32'h7179b725 /* 0x1014 */; - 1030: data_o = 32'he84aec26 /* 0x1018 */; - 1031: data_o = 32'h893a84b6 /* 0x101c */; - 1032: data_o = 32'h47010034 /* 0x1020 */; - 1033: data_o = 32'hf406f022 /* 0x1024 */; - 1034: data_o = 32'hf0ef8432 /* 0x1028 */; - 1035: data_o = 32'he50de8df /* 0x102c */; - 1036: data_o = 32'h1713c485 /* 0x1030 */; - 1037: data_o = 32'h56130204 /* 0x1034 */; - 1038: data_o = 32'h879301d7 /* 0x1038 */; - 1039: data_o = 32'h97b21541 /* 0x103c */; - 1040: data_o = 32'h66a26398 /* 0x1040 */; - 1041: data_o = 32'h171b4785 /* 0x1044 */; - 1042: data_o = 32'h97bb0037 /* 0x1048 */; - 1043: data_o = 32'h37fd00e7 /* 0x104c */; - 1044: data_o = 32'h0126c733 /* 0x1050 */; - 1045: data_o = 32'he7198f7d /* 0x1054 */; - 1046: data_o = 32'h740270a2 /* 0x1058 */; - 1047: data_o = 32'h694264e2 /* 0x105c */; + 523: data_o = 32'h02000713 /* 0x082c */; + 524: data_o = 32'h00e78823 /* 0x0830 */; + 525: data_o = 32'h0ff0000f /* 0x0834 */; + 526: data_o = 32'hf7974719 /* 0x0838 */; + 527: data_o = 32'h879300ff /* 0x083c */; + 528: data_o = 32'h479c7c67 /* 0x0840 */; + 529: data_o = 32'hc78d8b89 /* 0x0844 */; + 530: data_o = 32'h00fff797 /* 0x0848 */; + 531: data_o = 32'h7b878793 /* 0x084c */; + 532: data_o = 32'h0007a423 /* 0x0850 */; + 533: data_o = 32'h00fff797 /* 0x0854 */; + 534: data_o = 32'h7ac78793 /* 0x0858 */; + 535: data_o = 32'hf79743c8 /* 0x085c */; + 536: data_o = 32'ha78300ff /* 0x0860 */; + 537: data_o = 32'h15027a27 /* 0x0864 */; + 538: data_o = 32'h93811782 /* 0x0868 */; + 539: data_o = 32'hb0a98d5d /* 0x086c */; + 540: data_o = 32'h01001797 /* 0x0870 */; + 541: data_o = 32'h79078793 /* 0x0874 */; + 542: data_o = 32'h0147c783 /* 0x0878 */; + 543: data_o = 32'hdfd58b85 /* 0x087c */; + 544: data_o = 32'h01001797 /* 0x0880 */; + 545: data_o = 32'h7807c783 /* 0x0884 */; + 546: data_o = 32'hfae799e3 /* 0x0888 */; + 547: data_o = 32'h1101b38d /* 0x088c */; + 548: data_o = 32'h6100e822 /* 0x0890 */; + 549: data_o = 32'he04ae426 /* 0x0894 */; + 550: data_o = 32'h892eec06 /* 0x0898 */; + 551: data_o = 32'h071384b2 /* 0x089c */; + 552: data_o = 32'h485c0480 /* 0x08a0 */; + 553: data_o = 32'h0ff7f793 /* 0x08a4 */; + 554: data_o = 32'hfee78de3 /* 0x08a8 */; + 555: data_o = 32'h01092503 /* 0x08ac */; + 556: data_o = 32'h8cdff0ef /* 0x08b0 */; + 557: data_o = 32'h00c92703 /* 0x08b4 */; + 558: data_o = 32'h0f634785 /* 0x08b8 */; + 559: data_o = 32'h551b02f7 /* 0x08bc */; + 560: data_o = 32'hd8080085 /* 0x08c0 */; + 561: data_o = 32'h27834689 /* 0x08c4 */; + 562: data_o = 32'hc4930089 /* 0x08c8 */; + 563: data_o = 32'h67050014 /* 0x08cc */; + 564: data_o = 32'h0094949b /* 0x08d0 */; + 565: data_o = 32'hc0070713 /* 0x08d4 */; + 566: data_o = 32'h00a7979b /* 0x08d8 */; + 567: data_o = 32'he7338ff9 /* 0x08dc */; + 568: data_o = 32'h8fd90096 /* 0x08e0 */; + 569: data_o = 32'h8fd96709 /* 0x08e4 */; + 570: data_o = 32'h60e22781 /* 0x08e8 */; + 571: data_o = 32'h6442d41c /* 0x08ec */; + 572: data_o = 32'h690264a2 /* 0x08f0 */; + 573: data_o = 32'h80826105 /* 0x08f4 */; + 574: data_o = 32'h468dd808 /* 0x08f8 */; + 575: data_o = 32'hcd0db7e9 /* 0x08fc */; + 576: data_o = 32'hf793c99d /* 0x0900 */; + 577: data_o = 32'hcb9d0035 /* 0x0904 */; + 578: data_o = 32'h04800693 /* 0x0908 */; + 579: data_o = 32'h6118c21d /* 0x090c */; + 580: data_o = 32'hf7934b5c /* 0x0910 */; + 581: data_o = 32'h8de30ff7 /* 0x0914 */; + 582: data_o = 32'hc783fed7 /* 0x0918 */; + 583: data_o = 32'h367d0005 /* 0x091c */; + 584: data_o = 32'h08230585 /* 0x0920 */; + 585: data_o = 32'h164202f7 /* 0x0924 */; + 586: data_o = 32'h0035f793 /* 0x0928 */; + 587: data_o = 32'hc7999241 /* 0x092c */; + 588: data_o = 32'h4501fe79 /* 0x0930 */; + 589: data_o = 32'hde758082 /* 0x0934 */; + 590: data_o = 32'h8082450d /* 0x0938 */; + 591: data_o = 32'h882e478d /* 0x093c */; + 592: data_o = 32'h02c7f963 /* 0x0940 */; + 593: data_o = 32'hffc6081b /* 0x0944 */; + 594: data_o = 32'h58131842 /* 0x0948 */; + 595: data_o = 32'h61180328 /* 0x094c */; + 596: data_o = 32'h8793080a /* 0x0950 */; + 597: data_o = 32'h983e0045 /* 0x0954 */; + 598: data_o = 32'h04800693 /* 0x0958 */; + 599: data_o = 32'hf7934b5c /* 0x095c */; + 600: data_o = 32'h8de30ff7 /* 0x0960 */; + 601: data_o = 32'h419cfed7 /* 0x0964 */; + 602: data_o = 32'hdb1c0591 /* 0x0968 */; + 603: data_o = 32'hff0598e3 /* 0x096c */; + 604: data_o = 32'h85c28a0d /* 0x0970 */; + 605: data_o = 32'h073bde5d /* 0x0974 */; + 606: data_o = 32'h174200c8 /* 0x0978 */; + 607: data_o = 32'h04800613 /* 0x097c */; + 608: data_o = 32'h61149341 /* 0x0980 */; + 609: data_o = 32'hf7934adc /* 0x0984 */; + 610: data_o = 32'h8de30ff7 /* 0x0988 */; + 611: data_o = 32'hc803fec7 /* 0x098c */; + 612: data_o = 32'h05850005 /* 0x0990 */; + 613: data_o = 32'h03059793 /* 0x0994 */; + 614: data_o = 32'h882393c1 /* 0x0998 */; + 615: data_o = 32'h12e30306 /* 0x099c */; + 616: data_o = 32'h4501fef7 /* 0x09a0 */; + 617: data_o = 32'h41988082 /* 0x09a4 */; + 618: data_o = 32'hf0227179 /* 0x09a8 */; + 619: data_o = 32'hf406e44e /* 0x09ac */; + 620: data_o = 32'he84aec26 /* 0x09b0 */; + 621: data_o = 32'h87ae4691 /* 0x09b4 */; + 622: data_o = 32'h843289aa /* 0x09b8 */; + 623: data_o = 32'h02d70063 /* 0x09bc */; + 624: data_o = 32'h0a634695 /* 0x09c0 */; + 625: data_o = 32'h468d06d7 /* 0x09c4 */; + 626: data_o = 32'h04d70d63 /* 0x09c8 */; + 627: data_o = 32'h740270a2 /* 0x09cc */; + 628: data_o = 32'h694264e2 /* 0x09d0 */; + 629: data_o = 32'h450d69a2 /* 0x09d4 */; + 630: data_o = 32'h80826145 /* 0x09d8 */; + 631: data_o = 32'h0085a903 /* 0x09dc */; + 632: data_o = 32'h0185d483 /* 0x09e0 */; + 633: data_o = 32'h44136785 /* 0x09e4 */; + 634: data_o = 32'h67050014 /* 0x09e8 */; + 635: data_o = 32'h0094141b /* 0x09ec */; + 636: data_o = 32'hc0070713 /* 0x09f0 */; + 637: data_o = 32'h00a9191b /* 0x09f4 */; + 638: data_o = 32'h00e97933 /* 0x09f8 */; + 639: data_o = 32'h34fd8fc1 /* 0x09fc */; + 640: data_o = 32'h0009b703 /* 0x0a00 */; + 641: data_o = 32'h0127e7b3 /* 0x0a04 */; + 642: data_o = 32'h1ff4f493 /* 0x0a08 */; + 643: data_o = 32'h740270a2 /* 0x0a0c */; + 644: data_o = 32'h27818fc5 /* 0x0a10 */; + 645: data_o = 32'h64e2d71c /* 0x0a14 */; + 646: data_o = 32'h69a26942 /* 0x0a18 */; + 647: data_o = 32'h61454501 /* 0x0a1c */; + 648: data_o = 32'hd4838082 /* 0x0a20 */; + 649: data_o = 32'h698c0185 /* 0x0a24 */; + 650: data_o = 32'h0087a903 /* 0x0a28 */; + 651: data_o = 32'hf0ef8626 /* 0x0a2c */; + 652: data_o = 32'h6789ed1f /* 0x0a30 */; + 653: data_o = 32'hd483bf4d /* 0x0a34 */; + 654: data_o = 32'h698c0205 /* 0x0a38 */; + 655: data_o = 32'h0087a903 /* 0x0a3c */; + 656: data_o = 32'hf0ef8626 /* 0x0a40 */; + 657: data_o = 32'h678debdf /* 0x0a44 */; + 658: data_o = 32'h0a63bf79 /* 0x0a48 */; + 659: data_o = 32'h87631605 /* 0x0a4c */; + 660: data_o = 32'h11411405 /* 0x0a50 */; + 661: data_o = 32'he402e002 /* 0x0a54 */; + 662: data_o = 32'h0035f793 /* 0x0a58 */; + 663: data_o = 32'h4701c78d /* 0x0a5c */; + 664: data_o = 32'h5663c641 /* 0x0a60 */; + 665: data_o = 32'h377d08e0 /* 0x0a64 */; + 666: data_o = 32'h00814783 /* 0x0a68 */; + 667: data_o = 32'h367d0585 /* 0x0a6c */; + 668: data_o = 32'hfef58fa3 /* 0x0a70 */; + 669: data_o = 32'h164267a2 /* 0x0a74 */; + 670: data_o = 32'h83a1c03a /* 0x0a78 */; + 671: data_o = 32'hf793e43e /* 0x0a7c */; + 672: data_o = 32'h92410035 /* 0x0a80 */; + 673: data_o = 32'h478dfff1 /* 0x0a84 */; + 674: data_o = 32'h12c7fd63 /* 0x0a88 */; + 675: data_o = 32'hffc6069b /* 0x0a8c */; + 676: data_o = 32'h92c916c2 /* 0x0a90 */; + 677: data_o = 32'h068a4702 /* 0x0a94 */; + 678: data_o = 32'h00458793 /* 0x0a98 */; + 679: data_o = 32'h488d96be /* 0x0a9c */; + 680: data_o = 32'h08e8d863 /* 0x0aa0 */; + 681: data_o = 32'h48223771 /* 0x0aa4 */; + 682: data_o = 32'hc03a47b2 /* 0x0aa8 */; + 683: data_o = 32'h0105a023 /* 0x0aac */; + 684: data_o = 32'h0591c43e /* 0x0ab0 */; + 685: data_o = 32'hfed596e3 /* 0x0ab4 */; + 686: data_o = 32'hc61d8a0d /* 0x0ab8 */; + 687: data_o = 32'h9e398736 /* 0x0abc */; + 688: data_o = 32'h16424682 /* 0x0ac0 */; + 689: data_o = 32'h58639241 /* 0x0ac4 */; + 690: data_o = 32'h36fd0ad0 /* 0x0ac8 */; + 691: data_o = 32'h00814783 /* 0x0acc */; + 692: data_o = 32'hc0360705 /* 0x0ad0 */; + 693: data_o = 32'hfef70fa3 /* 0x0ad4 */; + 694: data_o = 32'h83a167a2 /* 0x0ad8 */; + 695: data_o = 32'h1793e43e /* 0x0adc */; + 696: data_o = 32'h93c10307 /* 0x0ae0 */; + 697: data_o = 32'hfef611e3 /* 0x0ae4 */; + 698: data_o = 32'h01414501 /* 0x0ae8 */; + 699: data_o = 32'h61148082 /* 0x0aec */; + 700: data_o = 32'hd79b4adc /* 0x0af0 */; + 701: data_o = 32'hf7930087 /* 0x0af4 */; + 702: data_o = 32'hdbfd0ff7 /* 0x0af8 */; + 703: data_o = 32'h769356dc /* 0x0afc */; + 704: data_o = 32'h27810037 /* 0x0b00 */; + 705: data_o = 32'h0741ea81 /* 0x0b04 */; + 706: data_o = 32'h2c23970a /* 0x0b08 */; + 707: data_o = 32'h4702fef7 /* 0x0b0c */; + 708: data_o = 32'hbf99270d /* 0x0b10 */; + 709: data_o = 32'h00410813 /* 0x0b14 */; + 710: data_o = 32'h00e106b3 /* 0x0b18 */; + 711: data_o = 32'h8423983a /* 0x0b1c */; + 712: data_o = 32'h068500f6 /* 0x0b20 */; + 713: data_o = 32'h0087d79b /* 0x0b24 */; + 714: data_o = 32'hff069be3 /* 0x0b28 */; + 715: data_o = 32'hbf2d270d /* 0x0b2c */; + 716: data_o = 32'h00053803 /* 0x0b30 */; + 717: data_o = 32'h01482783 /* 0x0b34 */; + 718: data_o = 32'h0087d79b /* 0x0b38 */; + 719: data_o = 32'h0ff7f793 /* 0x0b3c */; + 720: data_o = 32'h2783dbf5 /* 0x0b40 */; + 721: data_o = 32'h781302c8 /* 0x0b44 */; + 722: data_o = 32'h27810037 /* 0x0b48 */; + 723: data_o = 32'h00081863 /* 0x0b4c */; + 724: data_o = 32'h970a0741 /* 0x0b50 */; + 725: data_o = 32'hfef72c23 /* 0x0b54 */; + 726: data_o = 32'hb7b14702 /* 0x0b58 */; + 727: data_o = 32'h00410313 /* 0x0b5c */; + 728: data_o = 32'h00e10833 /* 0x0b60 */; + 729: data_o = 32'h0423933a /* 0x0b64 */; + 730: data_o = 32'h080500f8 /* 0x0b68 */; + 731: data_o = 32'h0087d79b /* 0x0b6c */; + 732: data_o = 32'hfe681be3 /* 0x0b70 */; + 733: data_o = 32'h610cbf0d /* 0x0b74 */; + 734: data_o = 32'hd79b49dc /* 0x0b78 */; + 735: data_o = 32'hf7930087 /* 0x0b7c */; + 736: data_o = 32'hdbfd0ff7 /* 0x0b80 */; + 737: data_o = 32'hf59355dc /* 0x0b84 */; + 738: data_o = 32'h27810036 /* 0x0b88 */; + 739: data_o = 32'h06c1e999 /* 0x0b8c */; + 740: data_o = 32'hac23968a /* 0x0b90 */; + 741: data_o = 32'h4682fef6 /* 0x0b94 */; + 742: data_o = 32'hbf0d268d /* 0x0b98 */; + 743: data_o = 32'h4501e20d /* 0x0b9c */; + 744: data_o = 32'h08138082 /* 0x0ba0 */; + 745: data_o = 32'h05b30041 /* 0x0ba4 */; + 746: data_o = 32'h983600d1 /* 0x0ba8 */; + 747: data_o = 32'h00f58423 /* 0x0bac */; + 748: data_o = 32'hd79b0585 /* 0x0bb0 */; + 749: data_o = 32'h1be30087 /* 0x0bb4 */; + 750: data_o = 32'h268dfeb8 /* 0x0bb8 */; + 751: data_o = 32'h450dbf01 /* 0x0bbc */; + 752: data_o = 32'h86ae8082 /* 0x0bc0 */; + 753: data_o = 32'h6518bddd /* 0x0bc4 */; + 754: data_o = 32'hf7b7712d /* 0x0bc8 */; + 755: data_o = 32'hee0602fa /* 0x0bcc */; + 756: data_o = 32'he626ea22 /* 0x0bd0 */; + 757: data_o = 32'hfdcee24a /* 0x0bd4 */; + 758: data_o = 32'hf5d6f9d2 /* 0x0bd8 */; + 759: data_o = 32'heddef1da /* 0x0bdc */; + 760: data_o = 32'he5e6e9e2 /* 0x0be0 */; + 761: data_o = 32'hfd6ee1ea /* 0x0be4 */; + 762: data_o = 32'h07f78793 /* 0x0be8 */; + 763: data_o = 32'hf432f02e /* 0x0bec */; + 764: data_o = 32'hed63e436 /* 0x0bf0 */; + 765: data_o = 32'h67a21ce7 /* 0x0bf4 */; + 766: data_o = 32'h88634c01 /* 0x0bf8 */; + 767: data_o = 32'h6a851207 /* 0x0bfc */; + 768: data_o = 32'hc00a8793 /* 0x0c00 */; + 769: data_o = 32'h44858d2a /* 0x0c04 */; + 770: data_o = 32'h4985e83e /* 0x0c08 */; + 771: data_o = 32'hf88277a2 /* 0x0c0c */; + 772: data_o = 32'h073be082 /* 0x0c10 */; + 773: data_o = 32'h778200fc /* 0x0c14 */; + 774: data_o = 32'hf482f082 /* 0x0c18 */; + 775: data_o = 32'hed3e97e2 /* 0x0c1c */; + 776: data_o = 32'he50267a2 /* 0x0c20 */; + 777: data_o = 32'hd8ba46cd /* 0x0c24 */; + 778: data_o = 32'hc53a4711 /* 0x0c28 */; + 779: data_o = 32'he482fc02 /* 0x0c2c */; + 780: data_o = 32'hec82e882 /* 0x0c30 */; + 781: data_o = 32'he102fc82 /* 0x0c34 */; + 782: data_o = 32'hf502e902 /* 0x0c38 */; + 783: data_o = 32'h04d10023 /* 0x0c3c */; + 784: data_o = 32'hd6a6d0a6 /* 0x0c40 */; + 785: data_o = 32'h418787b3 /* 0x0c44 */; + 786: data_o = 32'h10000713 /* 0x0c48 */; + 787: data_o = 32'h00f77463 /* 0x0c4c */; + 788: data_o = 32'h10000793 /* 0x0c50 */; + 789: data_o = 32'h010d2703 /* 0x0c54 */; + 790: data_o = 32'h000d3403 /* 0x0c58 */; + 791: data_o = 32'h03810d93 /* 0x0c5c */; + 792: data_o = 32'hd058f13e /* 0x0c60 */; + 793: data_o = 32'h47018a6e /* 0x0c64 */; + 794: data_o = 32'h4b894a81 /* 0x0c68 */; + 795: data_o = 32'h04800c93 /* 0x0c6c */; + 796: data_o = 32'h4b0d6909 /* 0x0c70 */; + 797: data_o = 32'hffea8613 /* 0x0c74 */; + 798: data_o = 32'h00163613 /* 0x0c78 */; + 799: data_o = 32'hd79b485c /* 0x0c7c */; + 800: data_o = 32'hdfed01f7 /* 0x0c80 */; + 801: data_o = 32'h11770d63 /* 0x0c84 */; + 802: data_o = 32'h0eebe063 /* 0x0c88 */; + 803: data_o = 32'h485cc34d /* 0x0c8c */; + 804: data_o = 32'h0ff7f793 /* 0x0c90 */; + 805: data_o = 32'hff978de3 /* 0x0c94 */; + 806: data_o = 32'h010a2503 /* 0x0c98 */; + 807: data_o = 32'hf0efec32 /* 0x0c9c */; + 808: data_o = 32'h2783cdef /* 0x0ca0 */; + 809: data_o = 32'h666200ca /* 0x0ca4 */; + 810: data_o = 32'h10978f63 /* 0x0ca8 */; + 811: data_o = 32'h0085551b /* 0x0cac */; + 812: data_o = 32'h4709d808 /* 0x0cb0 */; + 813: data_o = 32'h008a2783 /* 0x0cb4 */; + 814: data_o = 32'h863b66c2 /* 0x0cb8 */; + 815: data_o = 32'h979b40c9 /* 0x0cbc */; + 816: data_o = 32'h161b00a7 /* 0x0cc0 */; + 817: data_o = 32'h8ff50096 /* 0x0cc4 */; + 818: data_o = 32'h8fd98fd1 /* 0x0cc8 */; + 819: data_o = 32'h0127e7b3 /* 0x0ccc */; + 820: data_o = 32'hd41c2781 /* 0x0cd0 */; + 821: data_o = 32'h0a130a85 /* 0x0cd4 */; + 822: data_o = 32'h9263028a /* 0x0cd8 */; + 823: data_o = 32'h8c93096a /* 0x0cdc */; + 824: data_o = 32'h4911078d /* 0x0ce0 */; + 825: data_o = 32'ha8314415 /* 0x0ce4 */; + 826: data_o = 32'h9863856a /* 0x0ce8 */; + 827: data_o = 32'hd6030087 /* 0x0cec */; + 828: data_o = 32'hb583020d /* 0x0cf0 */; + 829: data_o = 32'hf0ef018d /* 0x0cf4 */; + 830: data_o = 32'h8d93d55f /* 0x0cf8 */; + 831: data_o = 32'h8163028d /* 0x0cfc */; + 832: data_o = 32'ha78303bc /* 0x0d00 */; + 833: data_o = 32'h91e3000d /* 0x0d04 */; + 834: data_o = 32'hd603ff27 /* 0x0d08 */; + 835: data_o = 32'hb583018d /* 0x0d0c */; + 836: data_o = 32'h856a010d /* 0x0d10 */; + 837: data_o = 32'h028d8d93 /* 0x0d14 */; + 838: data_o = 32'hd33ff0ef /* 0x0d18 */; + 839: data_o = 32'hffbc93e3 /* 0x0d1c */; + 840: data_o = 32'h0c1367a2 /* 0x0d20 */; + 841: data_o = 32'h63e3100c /* 0x0d24 */; + 842: data_o = 32'h4501eefc /* 0x0d28 */; + 843: data_o = 32'h485ca891 /* 0x0d2c */; + 844: data_o = 32'h0ff7f793 /* 0x0d30 */; + 845: data_o = 32'hff978de3 /* 0x0d34 */; + 846: data_o = 32'h008a4703 /* 0x0d38 */; + 847: data_o = 32'h40c987bb /* 0x0d3c */; + 848: data_o = 32'h0097979b /* 0x0d40 */; + 849: data_o = 32'h02e40823 /* 0x0d44 */; + 850: data_o = 32'h000d3703 /* 0x0d48 */; + 851: data_o = 32'h0127e7b3 /* 0x0d4c */; + 852: data_o = 32'hd71c2781 /* 0x0d50 */; + 853: data_o = 32'h0a130a85 /* 0x0d54 */; + 854: data_o = 32'h82e3028a /* 0x0d58 */; + 855: data_o = 32'h3403f96a /* 0x0d5c */; + 856: data_o = 32'h2703000d /* 0x0d60 */; + 857: data_o = 32'hb739000a /* 0x0d64 */; + 858: data_o = 32'hea633775 /* 0x0d68 */; + 859: data_o = 32'h85d200eb /* 0x0d6c */; + 860: data_o = 32'hf0ef856a /* 0x0d70 */; + 861: data_o = 32'h2501c35f /* 0x0d74 */; + 862: data_o = 32'h2501dd71 /* 0x0d78 */; + 863: data_o = 32'h450da011 /* 0x0d7c */; + 864: data_o = 32'h645260f2 /* 0x0d80 */; + 865: data_o = 32'h691264b2 /* 0x0d84 */; + 866: data_o = 32'h7a4e79ee /* 0x0d88 */; + 867: data_o = 32'h7b0e7aae /* 0x0d8c */; + 868: data_o = 32'h6c4e6bee /* 0x0d90 */; + 869: data_o = 32'h6d0e6cae /* 0x0d94 */; + 870: data_o = 32'h61157dea /* 0x0d98 */; + 871: data_o = 32'h27838082 /* 0x0d9c */; + 872: data_o = 32'h5703008a /* 0x0da0 */; + 873: data_o = 32'h66c2010a /* 0x0da4 */; + 874: data_o = 32'h40c9863b /* 0x0da8 */; + 875: data_o = 32'h00a7979b /* 0x0dac */; + 876: data_o = 32'h161b8ff5 /* 0x0db0 */; + 877: data_o = 32'h377d0096 /* 0x0db4 */; + 878: data_o = 32'h77138fd1 /* 0x0db8 */; + 879: data_o = 32'h8fd91ff7 /* 0x0dbc */; + 880: data_o = 32'hd41c2781 /* 0x0dc0 */; + 881: data_o = 32'hd808bf41 /* 0x0dc4 */; + 882: data_o = 32'hb5ed470d /* 0x0dc8 */; + 883: data_o = 32'hbf4d4555 /* 0x0dcc */; + 884: data_o = 32'h11016118 /* 0x0dd0 */; + 885: data_o = 32'he426e822 /* 0x0dd4 */; + 886: data_o = 32'h84aaec06 /* 0x0dd8 */; + 887: data_o = 32'hd34c8432 /* 0x0ddc */; + 888: data_o = 32'hd79b4b5c /* 0x0de0 */; + 889: data_o = 32'hdfed01f7 /* 0x0de4 */; + 890: data_o = 32'h4689401c /* 0x0de8 */; + 891: data_o = 32'h08d78a63 /* 0x0dec */; + 892: data_o = 32'h02f6eb63 /* 0x0df0 */; + 893: data_o = 32'h4601c3bd /* 0x0df4 */; + 894: data_o = 32'h852685a2 /* 0x0df8 */; + 895: data_o = 32'ha93ff0ef /* 0x0dfc */; + 896: data_o = 32'h4711401c /* 0x0e00 */; + 897: data_o = 32'h02e78f63 /* 0x0e04 */; + 898: data_o = 32'h92634715 /* 0x0e08 */; + 899: data_o = 32'h560304e7 /* 0x0e0c */; + 900: data_o = 32'h6c0c0204 /* 0x0e10 */; + 901: data_o = 32'hf0ef8526 /* 0x0e14 */; + 902: data_o = 32'h4501c35f /* 0x0e18 */; + 903: data_o = 32'h644260e2 /* 0x0e1c */; + 904: data_o = 32'h610564a2 /* 0x0e20 */; + 905: data_o = 32'h37f58082 /* 0x0e24 */; + 906: data_o = 32'h04f6ea63 /* 0x0e28 */; + 907: data_o = 32'h85a24601 /* 0x0e2c */; + 908: data_o = 32'hf0ef8526 /* 0x0e30 */; + 909: data_o = 32'h2501b75f /* 0x0e34 */; + 910: data_o = 32'h401cf175 /* 0x0e38 */; + 911: data_o = 32'h95e34711 /* 0x0e3c */; + 912: data_o = 32'h5603fce7 /* 0x0e40 */; + 913: data_o = 32'h680c0184 /* 0x0e44 */; + 914: data_o = 32'hf0ef8526 /* 0x0e48 */; + 915: data_o = 32'h60e2c01f /* 0x0e4c */; + 916: data_o = 32'h64a26442 /* 0x0e50 */; + 917: data_o = 32'h61054501 /* 0x0e54 */; + 918: data_o = 32'h06938082 /* 0x0e58 */; + 919: data_o = 32'h4b5c0480 /* 0x0e5c */; + 920: data_o = 32'h0ff7f793 /* 0x0e60 */; + 921: data_o = 32'hfed78de3 /* 0x0e64 */; + 922: data_o = 32'h00844783 /* 0x0e68 */; + 923: data_o = 32'h02f70823 /* 0x0e6c */; + 924: data_o = 32'h67896098 /* 0x0e70 */; + 925: data_o = 32'h20078793 /* 0x0e74 */; + 926: data_o = 32'hb759d71c /* 0x0e78 */; + 927: data_o = 32'hbf79450d /* 0x0e7c */; + 928: data_o = 32'h01045783 /* 0x0e80 */; + 929: data_o = 32'h66054414 /* 0x0e84 */; + 930: data_o = 32'h969b37fd /* 0x0e88 */; + 931: data_o = 32'h061300a6 /* 0x0e8c */; + 932: data_o = 32'hf793c006 /* 0x0e90 */; + 933: data_o = 32'h8ef11ff7 /* 0x0e94 */; + 934: data_o = 32'he7938fd5 /* 0x0e98 */; + 935: data_o = 32'h27812007 /* 0x0e9c */; + 936: data_o = 32'hbfb9d71c /* 0x0ea0 */; + 937: data_o = 32'he42e7175 /* 0x0ea4 */; + 938: data_o = 32'h478dec02 /* 0x0ea8 */; + 939: data_o = 32'hcc3e490c /* 0x0eac */; + 940: data_o = 32'hf0d2003c /* 0x0eb0 */; + 941: data_o = 32'hf43ee8da /* 0x0eb4 */; + 942: data_o = 32'h47998b32 /* 0x0eb8 */; + 943: data_o = 32'h08308a36 /* 0x0ebc */; + 944: data_o = 32'he1224685 /* 0x0ec0 */; + 945: data_o = 32'hf4cef8ca /* 0x0ec4 */; + 946: data_o = 32'hfca6e506 /* 0x0ec8 */; + 947: data_o = 32'he4deecd6 /* 0x0ecc */; + 948: data_o = 32'h893a89aa /* 0x0ed0 */; + 949: data_o = 32'hfc02f002 /* 0x0ed4 */; + 950: data_o = 32'hf0eff83e /* 0x0ed8 */; + 951: data_o = 32'h041bef7f /* 0x0edc */; + 952: data_o = 32'he4210005 /* 0x0ee0 */; + 953: data_o = 32'h00814703 /* 0x0ee4 */; + 954: data_o = 32'h04c00793 /* 0x0ee8 */; + 955: data_o = 32'h0109a583 /* 0x0eec */; + 956: data_o = 32'h0af70663 /* 0x0ef0 */; + 957: data_o = 32'h4b9144a1 /* 0x0ef4 */; + 958: data_o = 32'ha0294a85 /* 0x0ef8 */; + 959: data_o = 32'h000a0783 /* 0x0efc */; + 960: data_o = 32'h0407d163 /* 0x0f00 */; + 961: data_o = 32'h0109a583 /* 0x0f04 */; + 962: data_o = 32'h4685ec02 /* 0x0f08 */; + 963: data_o = 32'h854e0830 /* 0x0f0c */; + 964: data_o = 32'hfc02f002 /* 0x0f10 */; + 965: data_o = 32'hf452cc5e /* 0x0f14 */; + 966: data_o = 32'hf0eff856 /* 0x0f18 */; + 967: data_o = 32'h041beb7f /* 0x0f1c */; + 968: data_o = 32'h34fd0005 /* 0x0f20 */; + 969: data_o = 32'hf8f9e019 /* 0x0f24 */; + 970: data_o = 32'h60aa4449 /* 0x0f28 */; + 971: data_o = 32'h640a8522 /* 0x0f2c */; + 972: data_o = 32'h794674e6 /* 0x0f30 */; + 973: data_o = 32'h7a0679a6 /* 0x0f34 */; + 974: data_o = 32'h6b466ae6 /* 0x0f38 */; + 975: data_o = 32'h61496ba6 /* 0x0f3c */; + 976: data_o = 32'h16938082 /* 0x0f40 */; + 977: data_o = 32'h8793020b /* 0x0f44 */; + 978: data_o = 32'hd7131541 /* 0x0f48 */; + 979: data_o = 32'h97ba01d6 /* 0x0f4c */; + 980: data_o = 32'h0863639c /* 0x0f50 */; + 981: data_o = 32'h17fd075b /* 0x0f54 */; + 982: data_o = 32'h18e3e385 /* 0x0f58 */; + 983: data_o = 32'ha783fc09 /* 0x0f5c */; + 984: data_o = 32'hb7030149 /* 0x0f60 */; + 985: data_o = 32'hd35c0009 /* 0x0f64 */; + 986: data_o = 32'hd79b4b5c /* 0x0f68 */; + 987: data_o = 32'hdfed01f7 /* 0x0f6c */; + 988: data_o = 32'hd71c479d /* 0x0f70 */; + 989: data_o = 32'hbf554401 /* 0x0f74 */; + 990: data_o = 32'h0109a583 /* 0x0f78 */; + 991: data_o = 32'h0a05ec02 /* 0x0f7c */; + 992: data_o = 32'h08304685 /* 0x0f80 */; + 993: data_o = 32'hf002854e /* 0x0f84 */; + 994: data_o = 32'hcc5efc02 /* 0x0f88 */; + 995: data_o = 32'hf83ef452 /* 0x0f8c */; + 996: data_o = 32'he41ff0ef /* 0x0f90 */; + 997: data_o = 32'hd1712501 /* 0x0f94 */; + 998: data_o = 32'hbf41842a /* 0x0f98 */; + 999: data_o = 32'h4791ec02 /* 0x0f9c */; + 1000: data_o = 32'h0793cc3e /* 0x0fa0 */; + 1001: data_o = 32'hf43e0171 /* 0x0fa4 */; + 1002: data_o = 32'h47854685 /* 0x0fa8 */; + 1003: data_o = 32'h854e0830 /* 0x0fac */; + 1004: data_o = 32'hfc02f002 /* 0x0fb0 */; + 1005: data_o = 32'hf0eff83e /* 0x0fb4 */; + 1006: data_o = 32'h041be1bf /* 0x0fb8 */; + 1007: data_o = 32'hd81d0005 /* 0x0fbc */; + 1008: data_o = 32'h6489b7ad /* 0x0fc0 */; + 1009: data_o = 32'h71048493 /* 0x0fc4 */; + 1010: data_o = 32'h0a934b11 /* 0x0fc8 */; + 1011: data_o = 32'h4a050171 /* 0x0fcc */; + 1012: data_o = 32'hc49da029 /* 0x0fd0 */; + 1013: data_o = 32'h01714783 /* 0x0fd4 */; + 1014: data_o = 32'ha583f3c9 /* 0x0fd8 */; + 1015: data_o = 32'hec020109 /* 0x0fdc */; + 1016: data_o = 32'h08304685 /* 0x0fe0 */; + 1017: data_o = 32'hf002854e /* 0x0fe4 */; + 1018: data_o = 32'hcc5afc02 /* 0x0fe8 */; + 1019: data_o = 32'hf852f456 /* 0x0fec */; + 1020: data_o = 32'hde1ff0ef /* 0x0ff0 */; + 1021: data_o = 32'h0005079b /* 0x0ff4 */; + 1022: data_o = 32'hdfe134fd /* 0x0ff8 */; + 1023: data_o = 32'hb735843e /* 0x0ffc */; + 1024: data_o = 32'hb725444d /* 0x1000 */; + 1025: data_o = 32'hec267179 /* 0x1004 */; + 1026: data_o = 32'h84b6e84a /* 0x1008 */; + 1027: data_o = 32'h0034893a /* 0x100c */; + 1028: data_o = 32'hf0224701 /* 0x1010 */; + 1029: data_o = 32'h8432f406 /* 0x1014 */; + 1030: data_o = 32'he8dff0ef /* 0x1018 */; + 1031: data_o = 32'hc485e50d /* 0x101c */; + 1032: data_o = 32'h02041713 /* 0x1020 */; + 1033: data_o = 32'h01d75613 /* 0x1024 */; + 1034: data_o = 32'h15418793 /* 0x1028 */; + 1035: data_o = 32'h639897b2 /* 0x102c */; + 1036: data_o = 32'h478566a2 /* 0x1030 */; + 1037: data_o = 32'h0037171b /* 0x1034 */; + 1038: data_o = 32'h00e797bb /* 0x1038 */; + 1039: data_o = 32'hc73337fd /* 0x103c */; + 1040: data_o = 32'h8f7d0126 /* 0x1040 */; + 1041: data_o = 32'h70a2e719 /* 0x1044 */; + 1042: data_o = 32'h64e27402 /* 0x1048 */; + 1043: data_o = 32'h61456942 /* 0x104c */; + 1044: data_o = 32'h70a28082 /* 0x1050 */; + 1045: data_o = 32'h8ff57402 /* 0x1054 */; + 1046: data_o = 32'h694264e2 /* 0x1058 */; + 1047: data_o = 32'h0007851b /* 0x105c */; 1048: data_o = 32'h80826145 /* 0x1060 */; - 1049: data_o = 32'h740270a2 /* 0x1064 */; - 1050: data_o = 32'h64e28ff5 /* 0x1068 */; - 1051: data_o = 32'h851b6942 /* 0x106c */; - 1052: data_o = 32'h61450007 /* 0x1070 */; - 1053: data_o = 32'h01138082 /* 0x1074 */; - 1054: data_o = 32'h3023d401 /* 0x1078 */; - 1055: data_o = 32'h0b332961 /* 0x107c */; - 1056: data_o = 32'h342300d6 /* 0x1080 */; - 1057: data_o = 32'h3c232951 /* 0x1084 */; - 1058: data_o = 32'h30232771 /* 0x1088 */; - 1059: data_o = 32'h3c2327a1 /* 0x108c */; - 1060: data_o = 32'h38232a11 /* 0x1090 */; - 1061: data_o = 32'h34232a81 /* 0x1094 */; - 1062: data_o = 32'h30232a91 /* 0x1098 */; - 1063: data_o = 32'h3c232b21 /* 0x109c */; - 1064: data_o = 32'h38232931 /* 0x10a0 */; - 1065: data_o = 32'h38232941 /* 0x10a4 */; - 1066: data_o = 32'h34232781 /* 0x10a8 */; - 1067: data_o = 32'h3c232791 /* 0x10ac */; - 1068: data_o = 32'h7b1325b1 /* 0x10b0 */; - 1069: data_o = 32'h8d2a1ffb /* 0x10b4 */; - 1070: data_o = 32'h7b938aae /* 0x10b8 */; - 1071: data_o = 32'h14631ff6 /* 0x10bc */; - 1072: data_o = 32'h0b13000b /* 0x10c0 */; - 1073: data_o = 32'h84132000 /* 0x10c4 */; - 1074: data_o = 32'h945e1ff6 /* 0x10c8 */; - 1075: data_o = 32'hfaa00793 /* 0x10cc */; - 1076: data_o = 32'h02a38025 /* 0x10d0 */; - 1077: data_o = 32'h0a6302f1 /* 0x10d4 */; - 1078: data_o = 32'h47852404 /* 0x10d8 */; - 1079: data_o = 32'h10f40b63 /* 0x10dc */; - 1080: data_o = 32'h05200593 /* 0x10e0 */; - 1081: data_o = 32'h579b8225 /* 0x10e4 */; - 1082: data_o = 32'h76930186 /* 0x10e8 */; - 1083: data_o = 32'h16820ff6 /* 0x10ec */; - 1084: data_o = 32'h8fd507a2 /* 0x10f0 */; - 1085: data_o = 32'h00ff06b7 /* 0x10f4 */; - 1086: data_o = 32'h0086571b /* 0x10f8 */; - 1087: data_o = 32'h8e5d8e75 /* 0x10fc */; - 1088: data_o = 32'h076257fd /* 0x1100 */; - 1089: data_o = 32'h8ff99381 /* 0x1104 */; - 1090: data_o = 32'h8e4d8e5d /* 0x1108 */; - 1091: data_o = 32'h0894e8b2 /* 0x110c */; - 1092: data_o = 32'h05510513 /* 0x1110 */; - 1093: data_o = 32'h85934701 /* 0x1114 */; - 1094: data_o = 32'hc7830541 /* 0x1118 */; - 1095: data_o = 32'h171b0006 /* 0x111c */; - 1096: data_o = 32'h06850017 /* 0x1120 */; - 1097: data_o = 32'hf7938fb9 /* 0x1124 */; - 1098: data_o = 32'h97ae0ff7 /* 0x1128 */; - 1099: data_o = 32'h0007c703 /* 0x112c */; - 1100: data_o = 32'hfed515e3 /* 0x1130 */; - 1101: data_o = 32'h00171793 /* 0x1134 */; - 1102: data_o = 32'h0017e793 /* 0x1138 */; - 1103: data_o = 32'h8fd117a2 /* 0x113c */; - 1104: data_o = 32'hf43ee882 /* 0x1140 */; - 1105: data_o = 32'h010d2583 /* 0x1144 */; - 1106: data_o = 32'hc8be478d /* 0x1148 */; - 1107: data_o = 32'hf0be103c /* 0x114c */; - 1108: data_o = 32'h47994685 /* 0x1150 */; - 1109: data_o = 32'h856a0890 /* 0x1154 */; - 1110: data_o = 32'hf882ec82 /* 0x1158 */; - 1111: data_o = 32'hf0eff4be /* 0x115c */; - 1112: data_o = 32'h0d9bc85f /* 0x1160 */; - 1113: data_o = 32'h98630005 /* 0x1164 */; - 1114: data_o = 32'h4703040d /* 0x1168 */; - 1115: data_o = 32'h07930281 /* 0x116c */; - 1116: data_o = 32'h258304c0 /* 0x1170 */; - 1117: data_o = 32'h0e63010d /* 0x1174 */; - 1118: data_o = 32'h44a120f7 /* 0x1178 */; - 1119: data_o = 32'h09934a11 /* 0x117c */; - 1120: data_o = 32'h49050251 /* 0x1180 */; - 1121: data_o = 32'h0783a029 /* 0x1184 */; - 1122: data_o = 32'hd7630251 /* 0x1188 */; - 1123: data_o = 32'h25830607 /* 0x118c */; - 1124: data_o = 32'he882010d /* 0x1190 */; - 1125: data_o = 32'h08904685 /* 0x1194 */; - 1126: data_o = 32'hec82856a /* 0x1198 */; - 1127: data_o = 32'hc8d2f882 /* 0x119c */; - 1128: data_o = 32'hf4caf0ce /* 0x11a0 */; - 1129: data_o = 32'hc3fff0ef /* 0x11a4 */; - 1130: data_o = 32'h00050d9b /* 0x11a8 */; - 1131: data_o = 32'h946334fd /* 0x11ac */; - 1132: data_o = 32'hf8f1000d /* 0x11b0 */; - 1133: data_o = 32'h30834dc9 /* 0x11b4 */; - 1134: data_o = 32'h34032b81 /* 0x11b8 */; - 1135: data_o = 32'h34832b01 /* 0x11bc */; - 1136: data_o = 32'h39032a81 /* 0x11c0 */; - 1137: data_o = 32'h39832a01 /* 0x11c4 */; - 1138: data_o = 32'h3a032981 /* 0x11c8 */; - 1139: data_o = 32'h3a832901 /* 0x11cc */; - 1140: data_o = 32'h3b032881 /* 0x11d0 */; - 1141: data_o = 32'h3b832801 /* 0x11d4 */; - 1142: data_o = 32'h3c032781 /* 0x11d8 */; - 1143: data_o = 32'h3c832701 /* 0x11dc */; - 1144: data_o = 32'h3d032681 /* 0x11e0 */; - 1145: data_o = 32'h856e2601 /* 0x11e4 */; - 1146: data_o = 32'h25813d83 /* 0x11e8 */; - 1147: data_o = 32'h2c010113 /* 0x11ec */; - 1148: data_o = 32'h05938082 /* 0x11f0 */; - 1149: data_o = 32'hb5fd0510 /* 0x11f4 */; - 1150: data_o = 32'h017037b3 /* 0x11f8 */; - 1151: data_o = 32'hec3e6c85 /* 0x11fc */; - 1152: data_o = 32'h800c8793 /* 0x1200 */; - 1153: data_o = 32'h089ce43e /* 0x1204 */; - 1154: data_o = 32'h8ab397de /* 0x1208 */; - 1155: data_o = 32'h4c01417a /* 0x120c */; - 1156: data_o = 32'h6709e83e /* 0x1210 */; - 1157: data_o = 32'h71070c93 /* 0x1214 */; - 1158: data_o = 32'h09134991 /* 0x1218 */; - 1159: data_o = 32'h44850251 /* 0x121c */; - 1160: data_o = 32'h0ff00a13 /* 0x1220 */; - 1161: data_o = 32'h8463a039 /* 0x1224 */; - 1162: data_o = 32'h4683160c /* 0x1228 */; - 1163: data_o = 32'h95630251 /* 0x122c */; - 1164: data_o = 32'h25830346 /* 0x1230 */; - 1165: data_o = 32'hf402010d /* 0x1234 */; - 1166: data_o = 32'h10304685 /* 0x1238 */; - 1167: data_o = 32'hf802856a /* 0x123c */; - 1168: data_o = 32'hd44ee482 /* 0x1240 */; - 1169: data_o = 32'he0a6fc4a /* 0x1244 */; - 1170: data_o = 32'hb9bff0ef /* 0x1248 */; - 1171: data_o = 32'h00050d9b /* 0x124c */; - 1172: data_o = 32'h8ae33cfd /* 0x1250 */; - 1173: data_o = 32'hb785fc0d /* 0x1254 */; - 1174: data_o = 32'h0fe00713 /* 0x1258 */; - 1175: data_o = 32'h18e69163 /* 0x125c */; - 1176: data_o = 32'h100c0e63 /* 0x1260 */; - 1177: data_o = 32'hfff40713 /* 0x1264 */; - 1178: data_o = 32'h10ec0163 /* 0x1268 */; - 1179: data_o = 32'he00288d6 /* 0x126c */; - 1180: data_o = 32'h8a138cc6 /* 0x1270 */; - 1181: data_o = 32'h89c62008 /* 0x1274 */; - 1182: data_o = 32'h04934911 /* 0x1278 */; - 1183: data_o = 32'hf4021000 /* 0x127c */; - 1184: data_o = 32'h8663f802 /* 0x1280 */; - 1185: data_o = 32'he4820a09 /* 0x1284 */; - 1186: data_o = 32'hfc4ed44a /* 0x1288 */; - 1187: data_o = 32'h2583e0a6 /* 0x128c */; - 1188: data_o = 32'h4685010d /* 0x1290 */; - 1189: data_o = 32'h856a1030 /* 0x1294 */; - 1190: data_o = 32'hb4bff0ef /* 0x1298 */; - 1191: data_o = 32'h89932501 /* 0x129c */; - 1192: data_o = 32'he1711009 /* 0x12a0 */; - 1193: data_o = 32'hfd3a1de3 /* 0x12a4 */; - 1194: data_o = 32'h4711f402 /* 0x12a8 */; - 1195: data_o = 32'h010d2583 /* 0x12ac */; - 1196: data_o = 32'h0713d43a /* 0x12b0 */; - 1197: data_o = 32'hfc3a0261 /* 0x12b4 */; - 1198: data_o = 32'h47094685 /* 0x12b8 */; - 1199: data_o = 32'h856a1030 /* 0x12bc */; - 1200: data_o = 32'he482f802 /* 0x12c0 */; - 1201: data_o = 32'hf0efe0ba /* 0x12c4 */; - 1202: data_o = 32'h2501b1df /* 0x12c8 */; - 1203: data_o = 32'h4681ed49 /* 0x12cc */; - 1204: data_o = 32'he5418593 /* 0x12d0 */; - 1205: data_o = 32'h000cc703 /* 0x12d4 */; - 1206: data_o = 32'h0086d61b /* 0x12d8 */; - 1207: data_o = 32'h0086969b /* 0x12dc */; - 1208: data_o = 32'h17028f31 /* 0x12e0 */; - 1209: data_o = 32'h972e837d /* 0x12e4 */; - 1210: data_o = 32'h00075703 /* 0x12e8 */; - 1211: data_o = 32'h92c116c2 /* 0x12ec */; - 1212: data_o = 32'h8eb90c85 /* 0x12f0 */; - 1213: data_o = 32'hff9a10e3 /* 0x12f4 */; - 1214: data_o = 32'h0086971b /* 0x12f8 */; - 1215: data_o = 32'h0086d69b /* 0x12fc */; - 1216: data_o = 32'h56038f55 /* 0x1300 */; - 1217: data_o = 32'h17420261 /* 0x1304 */; - 1218: data_o = 32'h1d639341 /* 0x1308 */; - 1219: data_o = 32'h67820ce6 /* 0x130c */; - 1220: data_o = 32'h8533c795 /* 0x1310 */; - 1221: data_o = 32'h9863015b /* 0x1314 */; - 1222: data_o = 32'h65c20a0d /* 0x1318 */; - 1223: data_o = 32'h20000613 /* 0x131c */; - 1224: data_o = 32'h41760633 /* 0x1320 */; - 1225: data_o = 32'he91fe0ef /* 0x1324 */; - 1226: data_o = 32'h4d81a821 /* 0x1328 */; - 1227: data_o = 32'h4789b569 /* 0x132c */; - 1228: data_o = 32'h67a2d43e /* 0x1330 */; - 1229: data_o = 32'he482e082 /* 0x1334 */; - 1230: data_o = 32'hbf91fc3e /* 0x1338 */; - 1231: data_o = 32'h060d9f63 /* 0x133c */; - 1232: data_o = 32'h8a930c05 /* 0x1340 */; - 1233: data_o = 32'h16e3200a /* 0x1344 */; - 1234: data_o = 32'h4785ed84 /* 0x1348 */; - 1235: data_o = 32'h0af40263 /* 0x134c */; - 1236: data_o = 32'h06100593 /* 0x1350 */; - 1237: data_o = 32'h470115a2 /* 0x1354 */; - 1238: data_o = 32'h46051034 /* 0x1358 */; - 1239: data_o = 32'h04c58593 /* 0x135c */; - 1240: data_o = 32'hf0ef856a /* 0x1360 */; - 1241: data_o = 32'h8daab55f /* 0x1364 */; - 1242: data_o = 32'h0713b5b9 /* 0x1368 */; - 1243: data_o = 32'h0fe32000 /* 0x136c */; - 1244: data_o = 32'he06eeeeb /* 0x1370 */; - 1245: data_o = 32'h05010893 /* 0x1374 */; - 1246: data_o = 32'hbddd4d85 /* 0x1378 */; - 1247: data_o = 32'h04940b63 /* 0x137c */; - 1248: data_o = 32'h060b8563 /* 0x1380 */; - 1249: data_o = 32'he03e4785 /* 0x1384 */; - 1250: data_o = 32'h05010893 /* 0x1388 */; - 1251: data_o = 32'h4de5b5d5 /* 0x138c */; - 1252: data_o = 32'he882b51d /* 0x1390 */; - 1253: data_o = 32'hc8be4791 /* 0x1394 */; - 1254: data_o = 32'h02610793 /* 0x1398 */; - 1255: data_o = 32'h4685f0be /* 0x139c */; - 1256: data_o = 32'h08904785 /* 0x13a0 */; - 1257: data_o = 32'hec82856a /* 0x13a4 */; - 1258: data_o = 32'hf4bef882 /* 0x13a8 */; - 1259: data_o = 32'ha37ff0ef /* 0x13ac */; - 1260: data_o = 32'h00050d9b /* 0x13b0 */; - 1261: data_o = 32'hdc0d83e3 /* 0x13b4 */; - 1262: data_o = 32'h865abbfd /* 0x13b8 */; - 1263: data_o = 32'h8556088c /* 0x13bc */; - 1264: data_o = 32'hdf5fe0ef /* 0x13c0 */; - 1265: data_o = 32'h65c2bfb5 /* 0x13c4 */; - 1266: data_o = 32'h417b0633 /* 0x13c8 */; - 1267: data_o = 32'hde9fe0ef /* 0x13cc */; - 1268: data_o = 32'h0713bf85 /* 0x13d0 */; - 1269: data_o = 32'h05e32000 /* 0x13d4 */; - 1270: data_o = 32'h6de2faeb /* 0x13d8 */; - 1271: data_o = 32'h0d93bf59 /* 0x13dc */; - 1272: data_o = 32'hbbd10200 /* 0x13e0 */; - 1273: data_o = 32'h02100d93 /* 0x13e4 */; - 1274: data_o = 32'he002b3f9 /* 0x13e8 */; - 1275: data_o = 32'hb54988d6 /* 0x13ec */; - 1276: data_o = 32'h014d2783 /* 0x13f0 */; - 1277: data_o = 32'h000d3703 /* 0x13f4 */; - 1278: data_o = 32'h4b5cd35c /* 0x13f8 */; - 1279: data_o = 32'h01f7d79b /* 0x13fc */; - 1280: data_o = 32'h479ddfed /* 0x1400 */; - 1281: data_o = 32'h4d81d71c /* 0x1404 */; - 1282: data_o = 32'hc291b37d /* 0x1408 */; - 1283: data_o = 32'h4501b1ad /* 0x140c */; - 1284: data_o = 32'h71598082 /* 0x1410 */; - 1285: data_o = 32'h84aeeca6 /* 0x1414 */; - 1286: data_o = 32'hf486e8ca /* 0x1418 */; - 1287: data_o = 32'he4cef0a2 /* 0x141c */; - 1288: data_o = 32'hfc56e0d2 /* 0x1420 */; - 1289: data_o = 32'h892af85a /* 0x1424 */; - 1290: data_o = 32'h061346a1 /* 0x1428 */; - 1291: data_o = 32'h100c2000 /* 0x142c */; - 1292: data_o = 32'h99028526 /* 0x1430 */; - 1293: data_o = 32'h1797ed51 /* 0x1434 */; - 1294: data_o = 32'h77020000 /* 0x1438 */; - 1295: data_o = 32'h8827b783 /* 0x143c */; - 1296: data_o = 32'h08f71863 /* 0x1440 */; - 1297: data_o = 32'h061346c1 /* 0x1444 */; - 1298: data_o = 32'h858a2480 /* 0x1448 */; - 1299: data_o = 32'h99028526 /* 0x144c */; - 1300: data_o = 32'he14d87aa /* 0x1450 */; - 1301: data_o = 32'h099347a2 /* 0x1454 */; - 1302: data_o = 32'h4a0105f0 /* 0x1458 */; - 1303: data_o = 32'h4b01cfad /* 0x145c */; - 1304: data_o = 32'h05f00a93 /* 0x1460 */; - 1305: data_o = 32'h00c16783 /* 0x1464 */; - 1306: data_o = 32'h46c16402 /* 0x1468 */; - 1307: data_o = 32'h036787b3 /* 0x146c */; - 1308: data_o = 32'h080c0426 /* 0x1470 */; - 1309: data_o = 32'h943e8526 /* 0x1474 */; - 1310: data_o = 32'h02040613 /* 0x1478 */; - 1311: data_o = 32'h87aa9902 /* 0x147c */; - 1312: data_o = 32'h862246c1 /* 0x1480 */; - 1313: data_o = 32'h8526100c /* 0x1484 */; - 1314: data_o = 32'h6742e7b5 /* 0x1488 */; - 1315: data_o = 32'h186367e2 /* 0x148c */; - 1316: data_o = 32'h0993000b /* 0x1490 */; - 1317: data_o = 32'hf36305f7 /* 0x1494 */; - 1318: data_o = 32'h89be0137 /* 0x1498 */; - 1319: data_o = 32'h8f998a3a /* 0x149c */; - 1320: data_o = 32'h00faec63 /* 0x14a0 */; - 1321: data_o = 32'h87aa9902 /* 0x14a4 */; - 1322: data_o = 32'h1797e531 /* 0x14a8 */; - 1323: data_o = 32'hb7830000 /* 0x14ac */; - 1324: data_o = 32'h77028167 /* 0x14b0 */; - 1325: data_o = 32'h08f70e63 /* 0x14b4 */; - 1326: data_o = 32'h00816783 /* 0x14b8 */; - 1327: data_o = 32'h43e30b05 /* 0x14bc */; - 1328: data_o = 32'h6783fafb /* 0x14c0 */; - 1329: data_o = 32'h08630081 /* 0x14c4 */; - 1330: data_o = 32'h6a4200fb /* 0x14c8 */; - 1331: data_o = 32'ha02169e2 /* 0x14cc */; - 1332: data_o = 32'h05f00993 /* 0x14d0 */; - 1333: data_o = 32'h86934a01 /* 0x14d4 */; - 1334: data_o = 32'h86b30019 /* 0x14d8 */; - 1335: data_o = 32'hf5974146 /* 0x14dc */; - 1336: data_o = 32'h06a60dff /* 0x14e0 */; - 1337: data_o = 32'h009a1613 /* 0x14e4 */; - 1338: data_o = 32'hb2258593 /* 0x14e8 */; - 1339: data_o = 32'h99028526 /* 0x14ec */; - 1340: data_o = 32'hcd0187aa /* 0x14f0 */; - 1341: data_o = 32'h740670a6 /* 0x14f4 */; - 1342: data_o = 32'h694664e6 /* 0x14f8 */; - 1343: data_o = 32'h6a0669a6 /* 0x14fc */; - 1344: data_o = 32'h7b427ae2 /* 0x1500 */; - 1345: data_o = 32'h6165853e /* 0x1504 */; - 1346: data_o = 32'h69138082 /* 0x1508 */; - 1347: data_o = 32'h29010019 /* 0x150c */; - 1348: data_o = 32'h00fff797 /* 0x1510 */; - 1349: data_o = 32'haf27a823 /* 0x1514 */; - 1350: data_o = 32'h00fff797 /* 0x1518 */; - 1351: data_o = 32'h87932481 /* 0x151c */; - 1352: data_o = 32'hc3c4ae87 /* 0x1520 */; - 1353: data_o = 32'hf797870e /* 0x1524 */; - 1354: data_o = 32'h740600ff /* 0x1528 */; - 1355: data_o = 32'h64e670a6 /* 0x152c */; - 1356: data_o = 32'h69a66946 /* 0x1530 */; - 1357: data_o = 32'h7ae26a06 /* 0x1534 */; - 1358: data_o = 32'h27017b42 /* 0x1538 */; - 1359: data_o = 32'hada78793 /* 0x153c */; - 1360: data_o = 32'h0dfff517 /* 0x1540 */; - 1361: data_o = 32'h0513c7d8 /* 0x1544 */; - 1362: data_o = 32'h6165ac05 /* 0x1548 */; - 1363: data_o = 32'hb6dfe06f /* 0x154c */; - 1364: data_o = 32'h00000797 /* 0x1550 */; - 1365: data_o = 32'h7787b783 /* 0x1554 */; - 1366: data_o = 32'h1fe37722 /* 0x1558 */; - 1367: data_o = 32'hb795f4f7 /* 0x155c */; - 1368: data_o = 32'h00fff797 /* 0x1560 */; - 1369: data_o = 32'h87937119 /* 0x1564 */; - 1370: data_o = 32'hf0caaa07 /* 0x1568 */; - 1371: data_o = 32'h0407a903 /* 0x156c */; - 1372: data_o = 32'h00fff797 /* 0x1570 */; - 1373: data_o = 32'ha9078793 /* 0x1574 */; - 1374: data_o = 32'h43e0f8a2 /* 0x1578 */; - 1375: data_o = 32'heccef4a6 /* 0x157c */; - 1376: data_o = 32'h90011402 /* 0x1580 */; - 1377: data_o = 32'hfc868522 /* 0x1584 */; - 1378: data_o = 32'he0ef2901 /* 0x1588 */; - 1379: data_o = 32'h4989fadf /* 0x158c */; - 1380: data_o = 32'h086384aa /* 0x1590 */; - 1381: data_o = 32'h478d1d39 /* 0x1594 */; - 1382: data_o = 32'h26f90e63 /* 0x1598 */; - 1383: data_o = 32'h1f634785 /* 0x159c */; - 1384: data_o = 32'h37b73cf9 /* 0x15a0 */; - 1385: data_o = 32'h8713016e /* 0x15a4 */; - 1386: data_o = 32'hd0026007 /* 0x15a8 */; - 1387: data_o = 32'hd24eec3a /* 0x15ac */; - 1388: data_o = 32'h5ff78793 /* 0x15b0 */; - 1389: data_o = 32'hff634561 /* 0x15b4 */; - 1390: data_o = 32'h35171897 /* 0x15b8 */; - 1391: data_o = 32'h05130100 /* 0x15bc */; - 1392: data_o = 32'he82aa465 /* 0x15c0 */; - 1393: data_o = 32'h9eaff0ef /* 0x15c4 */; - 1394: data_o = 32'h000317b7 /* 0x15c8 */; - 1395: data_o = 32'hd4078793 /* 0x15cc */; - 1396: data_o = 32'hc226c03e /* 0x15d0 */; - 1397: data_o = 32'h46816582 /* 0x15d4 */; - 1398: data_o = 32'h08084601 /* 0x15d8 */; - 1399: data_o = 32'he0efe402 /* 0x15dc */; - 1400: data_o = 32'h2501ecdf /* 0x15e0 */; - 1401: data_o = 32'h16051863 /* 0x15e4 */; - 1402: data_o = 32'h65825692 /* 0x15e8 */; - 1403: data_o = 32'h08086622 /* 0x15ec */; - 1404: data_o = 32'hebbfe0ef /* 0x15f0 */; - 1405: data_o = 32'h1f632501 /* 0x15f4 */; - 1406: data_o = 32'h37971405 /* 0x15f8 */; - 1407: data_o = 32'h87930100 /* 0x15fc */; - 1408: data_o = 32'h0737a067 /* 0x1600 */; - 1409: data_o = 32'hcb988000 /* 0x1604 */; - 1410: data_o = 32'h01003797 /* 0x1608 */; - 1411: data_o = 32'h9f878793 /* 0x160c */; - 1412: data_o = 32'h07374b9c /* 0x1610 */; - 1413: data_o = 32'h177de000 /* 0x1614 */; - 1414: data_o = 32'h07378ff9 /* 0x1618 */; - 1415: data_o = 32'h8fd92000 /* 0x161c */; - 1416: data_o = 32'h01003717 /* 0x1620 */; - 1417: data_o = 32'h9e070713 /* 0x1624 */; - 1418: data_o = 32'h5582cb1c /* 0x1628 */; - 1419: data_o = 32'h0793f402 /* 0x162c */; - 1420: data_o = 32'h46850500 /* 0x1630 */; - 1421: data_o = 32'h08081030 /* 0x1634 */; - 1422: data_o = 32'he082f802 /* 0x1638 */; - 1423: data_o = 32'hd44ee482 /* 0x163c */; - 1424: data_o = 32'hf0effc3e /* 0x1640 */; - 1425: data_o = 32'h2501fa0f /* 0x1644 */; - 1426: data_o = 32'h10051663 /* 0x1648 */; - 1427: data_o = 32'h09500593 /* 0x164c */; - 1428: data_o = 32'h470515a2 /* 0x1650 */; - 1429: data_o = 32'h46014685 /* 0x1654 */; - 1430: data_o = 32'h04058593 /* 0x1658 */; - 1431: data_o = 32'hf0ef0808 /* 0x165c */; - 1432: data_o = 32'h19639b9f /* 0x1660 */; - 1433: data_o = 32'h07970e05 /* 0x1664 */; - 1434: data_o = 32'h17370000 /* 0x1668 */; - 1435: data_o = 32'hb5830aa0 /* 0x166c */; - 1436: data_o = 32'h073266a7 /* 0x1670 */; - 1437: data_o = 32'h46850705 /* 0x1674 */; - 1438: data_o = 32'h08084611 /* 0x1678 */; - 1439: data_o = 32'h99bff0ef /* 0x167c */; - 1440: data_o = 32'h0493e971 /* 0x1680 */; - 1441: data_o = 32'h14a20650 /* 0x1684 */; - 1442: data_o = 32'h03210423 /* 0x1688 */; - 1443: data_o = 32'h07748493 /* 0x168c */; - 1444: data_o = 32'h46814701 /* 0x1690 */; - 1445: data_o = 32'h85a64601 /* 0x1694 */; - 1446: data_o = 32'hf0ef0808 /* 0x1698 */; - 1447: data_o = 32'he95d97df /* 0x169c */; - 1448: data_o = 32'h00000797 /* 0x16a0 */; - 1449: data_o = 32'h6387b583 /* 0x16a4 */; - 1450: data_o = 32'h10344701 /* 0x16a8 */; - 1451: data_o = 32'h08084601 /* 0x16ac */; - 1452: data_o = 32'h807ff0ef /* 0x16b0 */; - 1453: data_o = 32'h4783e145 /* 0x16b4 */; - 1454: data_o = 32'hfbf90281 /* 0x16b8 */; - 1455: data_o = 32'h0fd00593 /* 0x16bc */; - 1456: data_o = 32'h470115a2 /* 0x16c0 */; - 1457: data_o = 32'h460d4681 /* 0x16c4 */; - 1458: data_o = 32'h07a58593 /* 0x16c8 */; - 1459: data_o = 32'hf0ef0808 /* 0x16cc */; - 1460: data_o = 32'he149949f /* 0x16d0 */; - 1461: data_o = 32'h00000797 /* 0x16d4 */; - 1462: data_o = 32'h60c7b583 /* 0x16d8 */; - 1463: data_o = 32'h46854701 /* 0x16dc */; - 1464: data_o = 32'h08084601 /* 0x16e0 */; - 1465: data_o = 32'h933ff0ef /* 0x16e4 */; - 1466: data_o = 32'h64c2e535 /* 0x16e8 */; - 1467: data_o = 32'he0000937 /* 0x16ec */; - 1468: data_o = 32'h489c197d /* 0x16f0 */; - 1469: data_o = 32'h08086622 /* 0x16f4 */; - 1470: data_o = 32'h0127f7b3 /* 0x16f8 */; - 1471: data_o = 32'h67e2c89c /* 0x16fc */; - 1472: data_o = 32'hc03e5682 /* 0x1700 */; - 1473: data_o = 32'he0ef6582 /* 0x1704 */; - 1474: data_o = 32'h2501da5f /* 0x1708 */; - 1475: data_o = 32'h5692e521 /* 0x170c */; - 1476: data_o = 32'h66226582 /* 0x1710 */; - 1477: data_o = 32'he0ef0808 /* 0x1714 */; - 1478: data_o = 32'h2501d95f /* 0x1718 */; - 1479: data_o = 32'h0513ed05 /* 0x171c */; - 1480: data_o = 32'h05333e80 /* 0x1720 */; - 1481: data_o = 32'h489c02a4 /* 0x1724 */; - 1482: data_o = 32'h20000737 /* 0x1728 */; - 1483: data_o = 32'h0127f7b3 /* 0x172c */; - 1484: data_o = 32'hc89c8fd9 /* 0x1730 */; - 1485: data_o = 32'h000f47b7 /* 0x1734 */; - 1486: data_o = 32'h24078793 /* 0x1738 */; - 1487: data_o = 32'h02f55533 /* 0x173c */; - 1488: data_o = 32'he0ef0505 /* 0x1740 */; - 1489: data_o = 32'h0517a89f /* 0x1744 */; - 1490: data_o = 32'h080c0000 /* 0x1748 */; - 1491: data_o = 32'hcc450513 /* 0x174c */; - 1492: data_o = 32'hcc3ff0ef /* 0x1750 */; - 1493: data_o = 32'h744670e6 /* 0x1754 */; - 1494: data_o = 32'h790674a6 /* 0x1758 */; - 1495: data_o = 32'h610969e6 /* 0x175c */; - 1496: data_o = 32'h67b78082 /* 0x1760 */; - 1497: data_o = 32'hfc020989 /* 0x1764 */; - 1498: data_o = 32'h7ff78793 /* 0x1768 */; - 1499: data_o = 32'h00255913 /* 0x176c */; - 1500: data_o = 32'h00a7f663 /* 0x1770 */; - 1501: data_o = 32'h02626937 /* 0x1774 */; - 1502: data_o = 32'ha0090913 /* 0x1778 */; - 1503: data_o = 32'hf84a4785 /* 0x177c */; - 1504: data_o = 32'h454ddc3e /* 0x1780 */; - 1505: data_o = 32'hfc0908e3 /* 0x1784 */; - 1506: data_o = 32'he5e34551 /* 0x1788 */; - 1507: data_o = 32'h3517fd24 /* 0x178c */; - 1508: data_o = 32'h05130100 /* 0x1790 */; - 1509: data_o = 32'hf42a8725 /* 0x1794 */; - 1510: data_o = 32'h816ff0ef /* 0x1798 */; - 1511: data_o = 32'h000f17b7 /* 0x179c */; - 1512: data_o = 32'hf0f78793 /* 0x17a0 */; - 1513: data_o = 32'hca26c84a /* 0x17a4 */; - 1514: data_o = 32'h1e23cc3e /* 0x17a8 */; - 1515: data_o = 32'h65c20001 /* 0x17ac */; - 1516: data_o = 32'h46856662 /* 0x17b0 */; - 1517: data_o = 32'he0ef1028 /* 0x17b4 */; - 1518: data_o = 32'h2501cf5f /* 0x17b8 */; - 1519: data_o = 32'h3797fd41 /* 0x17bc */; - 1520: data_o = 32'h87930100 /* 0x17c0 */; - 1521: data_o = 32'h07378427 /* 0x17c4 */; - 1522: data_o = 32'hcb988000 /* 0x17c8 */; - 1523: data_o = 32'h01003797 /* 0x17cc */; - 1524: data_o = 32'h83478793 /* 0x17d0 */; - 1525: data_o = 32'h07374b9c /* 0x17d4 */; - 1526: data_o = 32'h177de000 /* 0x17d8 */; - 1527: data_o = 32'h07378ff9 /* 0x17dc */; - 1528: data_o = 32'h8fd92000 /* 0x17e0 */; - 1529: data_o = 32'h01003717 /* 0x17e4 */; - 1530: data_o = 32'h81c70713 /* 0x17e8 */; - 1531: data_o = 32'h0793cb1c /* 0x17ec */; - 1532: data_o = 32'h053315e0 /* 0x17f0 */; - 1533: data_o = 32'h47b702f4 /* 0x17f4 */; - 1534: data_o = 32'h8793000f /* 0x17f8 */; - 1535: data_o = 32'h55332407 /* 0x17fc */; - 1536: data_o = 32'h050502f5 /* 0x1800 */; - 1537: data_o = 32'h9c7fe0ef /* 0x1804 */; - 1538: data_o = 32'hfffff517 /* 0x1808 */; - 1539: data_o = 32'h0513102c /* 0x180c */; - 1540: data_o = 32'hbf3d3d05 /* 0x1810 */; - 1541: data_o = 32'hdc9d4549 /* 0x1814 */; - 1542: data_o = 32'h3b9ad5b7 /* 0x1818 */; - 1543: data_o = 32'ha0058593 /* 0x181c */; - 1544: data_o = 32'h0295d5b3 /* 0x1820 */; - 1545: data_o = 32'h01001797 /* 0x1824 */; - 1546: data_o = 32'h7dc78793 /* 0x1828 */; - 1547: data_o = 32'h1797f43e /* 0x182c */; - 1548: data_o = 32'h87930100 /* 0x1830 */; - 1549: data_o = 32'h4b987d27 /* 0x1834 */; - 1550: data_o = 32'h01001797 /* 0x1838 */; - 1551: data_o = 32'h7c878793 /* 0x183c */; - 1552: data_o = 32'hcb989b79 /* 0x1840 */; - 1553: data_o = 32'h01001797 /* 0x1844 */; - 1554: data_o = 32'h7bc78793 /* 0x1848 */; - 1555: data_o = 32'h17975398 /* 0x184c */; - 1556: data_o = 32'h87930100 /* 0x1850 */; - 1557: data_o = 32'h67137b27 /* 0x1854 */; - 1558: data_o = 32'hd3980807 /* 0x1858 */; - 1559: data_o = 32'h01001797 /* 0x185c */; - 1560: data_o = 32'h7a478793 /* 0x1860 */; - 1561: data_o = 32'h17975398 /* 0x1864 */; - 1562: data_o = 32'h87930100 /* 0x1868 */; - 1563: data_o = 32'h671379a7 /* 0x186c */; - 1564: data_o = 32'hd3980027 /* 0x1870 */; - 1565: data_o = 32'h01001797 /* 0x1874 */; - 1566: data_o = 32'h78c78793 /* 0x1878 */; - 1567: data_o = 32'h17975398 /* 0x187c */; - 1568: data_o = 32'h87930100 /* 0x1880 */; - 1569: data_o = 32'h67137827 /* 0x1884 */; - 1570: data_o = 32'hd3980017 /* 0x1888 */; - 1571: data_o = 32'h01001797 /* 0x188c */; - 1572: data_o = 32'h77478793 /* 0x1890 */; - 1573: data_o = 32'h17975398 /* 0x1894 */; - 1574: data_o = 32'h87930100 /* 0x1898 */; - 1575: data_o = 32'h671376a7 /* 0x189c */; - 1576: data_o = 32'h05131007 /* 0x18a0 */; - 1577: data_o = 32'h06135130 /* 0x18a4 */; - 1578: data_o = 32'hd3980630 /* 0x18a8 */; - 1579: data_o = 32'h07136685 /* 0x18ac */; - 1580: data_o = 32'h869b12b0 /* 0x18b0 */; - 1581: data_o = 32'h07939c36 /* 0x18b4 */; - 1582: data_o = 32'h553b2570 /* 0x18b8 */; - 1583: data_o = 32'h563b02b5 /* 0x18bc */; - 1584: data_o = 32'h154202b6 /* 0x18c0 */; - 1585: data_o = 32'h081b9141 /* 0x18c4 */; - 1586: data_o = 32'h181b0015 /* 0x18c8 */; - 1587: data_o = 32'h573b0108 /* 0x18cc */; - 1588: data_o = 32'h260502b7 /* 0x18d0 */; - 1589: data_o = 32'h92411642 /* 0x18d4 */; - 1590: data_o = 32'h02b6d6bb /* 0x18d8 */; - 1591: data_o = 32'h17422705 /* 0x18dc */; - 1592: data_o = 32'hd7bb9341 /* 0x18e0 */; - 1593: data_o = 32'h9e8902b7 /* 0x18e4 */; - 1594: data_o = 32'h9e999e91 /* 0x18e8 */; - 1595: data_o = 32'h16c285b6 /* 0x18ec */; - 1596: data_o = 32'h278592c1 /* 0x18f0 */; - 1597: data_o = 32'h93c117c2 /* 0x18f4 */; - 1598: data_o = 32'h00f6f363 /* 0x18f8 */; - 1599: data_o = 32'h959b85be /* 0x18fc */; - 1600: data_o = 32'hd59b0105 /* 0x1900 */; - 1601: data_o = 32'he5b30105 /* 0x1904 */; - 1602: data_o = 32'h16970105 /* 0x1908 */; - 1603: data_o = 32'h25810100 /* 0x190c */; + 1049: data_o = 32'hd4010113 /* 0x1064 */; + 1050: data_o = 32'h29613023 /* 0x1068 */; + 1051: data_o = 32'h00d60b33 /* 0x106c */; + 1052: data_o = 32'h29513423 /* 0x1070 */; + 1053: data_o = 32'h27713c23 /* 0x1074 */; + 1054: data_o = 32'h27a13023 /* 0x1078 */; + 1055: data_o = 32'h2a113c23 /* 0x107c */; + 1056: data_o = 32'h2a813823 /* 0x1080 */; + 1057: data_o = 32'h2a913423 /* 0x1084 */; + 1058: data_o = 32'h2b213023 /* 0x1088 */; + 1059: data_o = 32'h29313c23 /* 0x108c */; + 1060: data_o = 32'h29413823 /* 0x1090 */; + 1061: data_o = 32'h27813823 /* 0x1094 */; + 1062: data_o = 32'h27913423 /* 0x1098 */; + 1063: data_o = 32'h25b13c23 /* 0x109c */; + 1064: data_o = 32'h1ffb7b13 /* 0x10a0 */; + 1065: data_o = 32'h8aae8d2a /* 0x10a4 */; + 1066: data_o = 32'h1ff67b93 /* 0x10a8 */; + 1067: data_o = 32'h000b1463 /* 0x10ac */; + 1068: data_o = 32'h20000b13 /* 0x10b0 */; + 1069: data_o = 32'h1ff68413 /* 0x10b4 */; + 1070: data_o = 32'h0793945e /* 0x10b8 */; + 1071: data_o = 32'h8025faa0 /* 0x10bc */; + 1072: data_o = 32'h02f102a3 /* 0x10c0 */; + 1073: data_o = 32'h24040a63 /* 0x10c4 */; + 1074: data_o = 32'h0b634785 /* 0x10c8 */; + 1075: data_o = 32'h059310f4 /* 0x10cc */; + 1076: data_o = 32'h82250520 /* 0x10d0 */; + 1077: data_o = 32'h0186579b /* 0x10d4 */; + 1078: data_o = 32'h0ff67693 /* 0x10d8 */; + 1079: data_o = 32'h07a21682 /* 0x10dc */; + 1080: data_o = 32'h06b78fd5 /* 0x10e0 */; + 1081: data_o = 32'h571b00ff /* 0x10e4 */; + 1082: data_o = 32'h8e750086 /* 0x10e8 */; + 1083: data_o = 32'h57fd8e5d /* 0x10ec */; + 1084: data_o = 32'h93810762 /* 0x10f0 */; + 1085: data_o = 32'h8e5d8ff9 /* 0x10f4 */; + 1086: data_o = 32'he8b28e4d /* 0x10f8 */; + 1087: data_o = 32'h05130894 /* 0x10fc */; + 1088: data_o = 32'h47010551 /* 0x1100 */; + 1089: data_o = 32'h05418593 /* 0x1104 */; + 1090: data_o = 32'h0006c783 /* 0x1108 */; + 1091: data_o = 32'h0017171b /* 0x110c */; + 1092: data_o = 32'h8fb90685 /* 0x1110 */; + 1093: data_o = 32'h0ff7f793 /* 0x1114 */; + 1094: data_o = 32'hc70397ae /* 0x1118 */; + 1095: data_o = 32'h15e30007 /* 0x111c */; + 1096: data_o = 32'h1793fed5 /* 0x1120 */; + 1097: data_o = 32'he7930017 /* 0x1124 */; + 1098: data_o = 32'h17a20017 /* 0x1128 */; + 1099: data_o = 32'he8828fd1 /* 0x112c */; + 1100: data_o = 32'h2583f43e /* 0x1130 */; + 1101: data_o = 32'h478d010d /* 0x1134 */; + 1102: data_o = 32'h103cc8be /* 0x1138 */; + 1103: data_o = 32'h4685f0be /* 0x113c */; + 1104: data_o = 32'h08904799 /* 0x1140 */; + 1105: data_o = 32'hec82856a /* 0x1144 */; + 1106: data_o = 32'hf4bef882 /* 0x1148 */; + 1107: data_o = 32'hc85ff0ef /* 0x114c */; + 1108: data_o = 32'h00050d9b /* 0x1150 */; + 1109: data_o = 32'h040d9863 /* 0x1154 */; + 1110: data_o = 32'h02814703 /* 0x1158 */; + 1111: data_o = 32'h04c00793 /* 0x115c */; + 1112: data_o = 32'h010d2583 /* 0x1160 */; + 1113: data_o = 32'h20f70e63 /* 0x1164 */; + 1114: data_o = 32'h4a1144a1 /* 0x1168 */; + 1115: data_o = 32'h02510993 /* 0x116c */; + 1116: data_o = 32'ha0294905 /* 0x1170 */; + 1117: data_o = 32'h02510783 /* 0x1174 */; + 1118: data_o = 32'h0607d763 /* 0x1178 */; + 1119: data_o = 32'h010d2583 /* 0x117c */; + 1120: data_o = 32'h4685e882 /* 0x1180 */; + 1121: data_o = 32'h856a0890 /* 0x1184 */; + 1122: data_o = 32'hf882ec82 /* 0x1188 */; + 1123: data_o = 32'hf0cec8d2 /* 0x118c */; + 1124: data_o = 32'hf0eff4ca /* 0x1190 */; + 1125: data_o = 32'h0d9bc3ff /* 0x1194 */; + 1126: data_o = 32'h34fd0005 /* 0x1198 */; + 1127: data_o = 32'h000d9463 /* 0x119c */; + 1128: data_o = 32'h4dc9f8f1 /* 0x11a0 */; + 1129: data_o = 32'h2b813083 /* 0x11a4 */; + 1130: data_o = 32'h2b013403 /* 0x11a8 */; + 1131: data_o = 32'h2a813483 /* 0x11ac */; + 1132: data_o = 32'h2a013903 /* 0x11b0 */; + 1133: data_o = 32'h29813983 /* 0x11b4 */; + 1134: data_o = 32'h29013a03 /* 0x11b8 */; + 1135: data_o = 32'h28813a83 /* 0x11bc */; + 1136: data_o = 32'h28013b03 /* 0x11c0 */; + 1137: data_o = 32'h27813b83 /* 0x11c4 */; + 1138: data_o = 32'h27013c03 /* 0x11c8 */; + 1139: data_o = 32'h26813c83 /* 0x11cc */; + 1140: data_o = 32'h26013d03 /* 0x11d0 */; + 1141: data_o = 32'h3d83856e /* 0x11d4 */; + 1142: data_o = 32'h01132581 /* 0x11d8 */; + 1143: data_o = 32'h80822c01 /* 0x11dc */; + 1144: data_o = 32'h05100593 /* 0x11e0 */; + 1145: data_o = 32'h37b3b5fd /* 0x11e4 */; + 1146: data_o = 32'h6c850170 /* 0x11e8 */; + 1147: data_o = 32'h8793ec3e /* 0x11ec */; + 1148: data_o = 32'he43e800c /* 0x11f0 */; + 1149: data_o = 32'h97de089c /* 0x11f4 */; + 1150: data_o = 32'h417a8ab3 /* 0x11f8 */; + 1151: data_o = 32'he83e4c01 /* 0x11fc */; + 1152: data_o = 32'h0c936709 /* 0x1200 */; + 1153: data_o = 32'h49917107 /* 0x1204 */; + 1154: data_o = 32'h02510913 /* 0x1208 */; + 1155: data_o = 32'h0a134485 /* 0x120c */; + 1156: data_o = 32'ha0390ff0 /* 0x1210 */; + 1157: data_o = 32'h160c8463 /* 0x1214 */; + 1158: data_o = 32'h02514683 /* 0x1218 */; + 1159: data_o = 32'h03469563 /* 0x121c */; + 1160: data_o = 32'h010d2583 /* 0x1220 */; + 1161: data_o = 32'h4685f402 /* 0x1224 */; + 1162: data_o = 32'h856a1030 /* 0x1228 */; + 1163: data_o = 32'he482f802 /* 0x122c */; + 1164: data_o = 32'hfc4ad44e /* 0x1230 */; + 1165: data_o = 32'hf0efe0a6 /* 0x1234 */; + 1166: data_o = 32'h0d9bb9bf /* 0x1238 */; + 1167: data_o = 32'h3cfd0005 /* 0x123c */; + 1168: data_o = 32'hfc0d8ae3 /* 0x1240 */; + 1169: data_o = 32'h0713b785 /* 0x1244 */; + 1170: data_o = 32'h91630fe0 /* 0x1248 */; + 1171: data_o = 32'h0e6318e6 /* 0x124c */; + 1172: data_o = 32'h0713100c /* 0x1250 */; + 1173: data_o = 32'h0163fff4 /* 0x1254 */; + 1174: data_o = 32'h88d610ec /* 0x1258 */; + 1175: data_o = 32'h8cc6e002 /* 0x125c */; + 1176: data_o = 32'h20088a13 /* 0x1260 */; + 1177: data_o = 32'h491189c6 /* 0x1264 */; + 1178: data_o = 32'h10000493 /* 0x1268 */; + 1179: data_o = 32'hf802f402 /* 0x126c */; + 1180: data_o = 32'h0a098663 /* 0x1270 */; + 1181: data_o = 32'hd44ae482 /* 0x1274 */; + 1182: data_o = 32'he0a6fc4e /* 0x1278 */; + 1183: data_o = 32'h010d2583 /* 0x127c */; + 1184: data_o = 32'h10304685 /* 0x1280 */; + 1185: data_o = 32'hf0ef856a /* 0x1284 */; + 1186: data_o = 32'h2501b4bf /* 0x1288 */; + 1187: data_o = 32'h10098993 /* 0x128c */; + 1188: data_o = 32'h1de3e171 /* 0x1290 */; + 1189: data_o = 32'hf402fd3a /* 0x1294 */; + 1190: data_o = 32'h25834711 /* 0x1298 */; + 1191: data_o = 32'hd43a010d /* 0x129c */; + 1192: data_o = 32'h02610713 /* 0x12a0 */; + 1193: data_o = 32'h4685fc3a /* 0x12a4 */; + 1194: data_o = 32'h10304709 /* 0x12a8 */; + 1195: data_o = 32'hf802856a /* 0x12ac */; + 1196: data_o = 32'he0bae482 /* 0x12b0 */; + 1197: data_o = 32'hb1dff0ef /* 0x12b4 */; + 1198: data_o = 32'hed492501 /* 0x12b8 */; + 1199: data_o = 32'h85934681 /* 0x12bc */; + 1200: data_o = 32'hc703e541 /* 0x12c0 */; + 1201: data_o = 32'hd61b000c /* 0x12c4 */; + 1202: data_o = 32'h969b0086 /* 0x12c8 */; + 1203: data_o = 32'h8f310086 /* 0x12cc */; + 1204: data_o = 32'h837d1702 /* 0x12d0 */; + 1205: data_o = 32'h5703972e /* 0x12d4 */; + 1206: data_o = 32'h16c20007 /* 0x12d8 */; + 1207: data_o = 32'h0c8592c1 /* 0x12dc */; + 1208: data_o = 32'h10e38eb9 /* 0x12e0 */; + 1209: data_o = 32'h971bff9a /* 0x12e4 */; + 1210: data_o = 32'hd69b0086 /* 0x12e8 */; + 1211: data_o = 32'h8f550086 /* 0x12ec */; + 1212: data_o = 32'h02615603 /* 0x12f0 */; + 1213: data_o = 32'h93411742 /* 0x12f4 */; + 1214: data_o = 32'h0ce61d63 /* 0x12f8 */; + 1215: data_o = 32'hc7956782 /* 0x12fc */; + 1216: data_o = 32'h015b8533 /* 0x1300 */; + 1217: data_o = 32'h0a0d9863 /* 0x1304 */; + 1218: data_o = 32'h061365c2 /* 0x1308 */; + 1219: data_o = 32'h06332000 /* 0x130c */; + 1220: data_o = 32'he0ef4176 /* 0x1310 */; + 1221: data_o = 32'ha821e93f /* 0x1314 */; + 1222: data_o = 32'hb5694d81 /* 0x1318 */; + 1223: data_o = 32'hd43e4789 /* 0x131c */; + 1224: data_o = 32'he08267a2 /* 0x1320 */; + 1225: data_o = 32'hfc3ee482 /* 0x1324 */; + 1226: data_o = 32'h9f63bf91 /* 0x1328 */; + 1227: data_o = 32'h0c05060d /* 0x132c */; + 1228: data_o = 32'h200a8a93 /* 0x1330 */; + 1229: data_o = 32'hed8416e3 /* 0x1334 */; + 1230: data_o = 32'h02634785 /* 0x1338 */; + 1231: data_o = 32'h05930af4 /* 0x133c */; + 1232: data_o = 32'h15a20610 /* 0x1340 */; + 1233: data_o = 32'h10344701 /* 0x1344 */; + 1234: data_o = 32'h85934605 /* 0x1348 */; + 1235: data_o = 32'h856a04c5 /* 0x134c */; + 1236: data_o = 32'hb55ff0ef /* 0x1350 */; + 1237: data_o = 32'hb5b98daa /* 0x1354 */; + 1238: data_o = 32'h20000713 /* 0x1358 */; + 1239: data_o = 32'heeeb0fe3 /* 0x135c */; + 1240: data_o = 32'h0893e06e /* 0x1360 */; + 1241: data_o = 32'h4d850501 /* 0x1364 */; + 1242: data_o = 32'h0b63bddd /* 0x1368 */; + 1243: data_o = 32'h85630494 /* 0x136c */; + 1244: data_o = 32'h4785060b /* 0x1370 */; + 1245: data_o = 32'h0893e03e /* 0x1374 */; + 1246: data_o = 32'hb5d50501 /* 0x1378 */; + 1247: data_o = 32'hb51d4de5 /* 0x137c */; + 1248: data_o = 32'h4791e882 /* 0x1380 */; + 1249: data_o = 32'h0793c8be /* 0x1384 */; + 1250: data_o = 32'hf0be0261 /* 0x1388 */; + 1251: data_o = 32'h47854685 /* 0x138c */; + 1252: data_o = 32'h856a0890 /* 0x1390 */; + 1253: data_o = 32'hf882ec82 /* 0x1394 */; + 1254: data_o = 32'hf0eff4be /* 0x1398 */; + 1255: data_o = 32'h0d9ba37f /* 0x139c */; + 1256: data_o = 32'h83e30005 /* 0x13a0 */; + 1257: data_o = 32'hbbfddc0d /* 0x13a4 */; + 1258: data_o = 32'h088c865a /* 0x13a8 */; + 1259: data_o = 32'he0ef8556 /* 0x13ac */; + 1260: data_o = 32'hbfb5df7f /* 0x13b0 */; + 1261: data_o = 32'h063365c2 /* 0x13b4 */; + 1262: data_o = 32'he0ef417b /* 0x13b8 */; + 1263: data_o = 32'hbf85debf /* 0x13bc */; + 1264: data_o = 32'h20000713 /* 0x13c0 */; + 1265: data_o = 32'hfaeb05e3 /* 0x13c4 */; + 1266: data_o = 32'hbf596de2 /* 0x13c8 */; + 1267: data_o = 32'h02000d93 /* 0x13cc */; + 1268: data_o = 32'h0d93bbd1 /* 0x13d0 */; + 1269: data_o = 32'hb3f90210 /* 0x13d4 */; + 1270: data_o = 32'h88d6e002 /* 0x13d8 */; + 1271: data_o = 32'h2783b549 /* 0x13dc */; + 1272: data_o = 32'h3703014d /* 0x13e0 */; + 1273: data_o = 32'hd35c000d /* 0x13e4 */; + 1274: data_o = 32'hd79b4b5c /* 0x13e8 */; + 1275: data_o = 32'hdfed01f7 /* 0x13ec */; + 1276: data_o = 32'hd71c479d /* 0x13f0 */; + 1277: data_o = 32'hb37d4d81 /* 0x13f4 */; + 1278: data_o = 32'hb1adc291 /* 0x13f8 */; + 1279: data_o = 32'h80824501 /* 0x13fc */; + 1280: data_o = 32'heca67159 /* 0x1400 */; + 1281: data_o = 32'he8ca84ae /* 0x1404 */; + 1282: data_o = 32'hf0a2f486 /* 0x1408 */; + 1283: data_o = 32'he0d2e4ce /* 0x140c */; + 1284: data_o = 32'hf85afc56 /* 0x1410 */; + 1285: data_o = 32'h46a1892a /* 0x1414 */; + 1286: data_o = 32'h20000613 /* 0x1418 */; + 1287: data_o = 32'h8526100c /* 0x141c */; + 1288: data_o = 32'hed519902 /* 0x1420 */; + 1289: data_o = 32'h00001797 /* 0x1424 */; + 1290: data_o = 32'hb7837702 /* 0x1428 */; + 1291: data_o = 32'h18638847 /* 0x142c */; + 1292: data_o = 32'h46c108f7 /* 0x1430 */; + 1293: data_o = 32'h24800613 /* 0x1434 */; + 1294: data_o = 32'h8526858a /* 0x1438 */; + 1295: data_o = 32'h87aa9902 /* 0x143c */; + 1296: data_o = 32'h47a2e14d /* 0x1440 */; + 1297: data_o = 32'h05f00993 /* 0x1444 */; + 1298: data_o = 32'hcfad4a01 /* 0x1448 */; + 1299: data_o = 32'h0a934b01 /* 0x144c */; + 1300: data_o = 32'h678305f0 /* 0x1450 */; + 1301: data_o = 32'h640200c1 /* 0x1454 */; + 1302: data_o = 32'h87b346c1 /* 0x1458 */; + 1303: data_o = 32'h04260367 /* 0x145c */; + 1304: data_o = 32'h8526080c /* 0x1460 */; + 1305: data_o = 32'h0613943e /* 0x1464 */; + 1306: data_o = 32'h99020204 /* 0x1468 */; + 1307: data_o = 32'h46c187aa /* 0x146c */; + 1308: data_o = 32'h100c8622 /* 0x1470 */; + 1309: data_o = 32'he7b58526 /* 0x1474 */; + 1310: data_o = 32'h67e26742 /* 0x1478 */; + 1311: data_o = 32'h000b1863 /* 0x147c */; + 1312: data_o = 32'h05f70993 /* 0x1480 */; + 1313: data_o = 32'h0137f363 /* 0x1484 */; + 1314: data_o = 32'h8a3a89be /* 0x1488 */; + 1315: data_o = 32'hec638f99 /* 0x148c */; + 1316: data_o = 32'h990200fa /* 0x1490 */; + 1317: data_o = 32'he53187aa /* 0x1494 */; + 1318: data_o = 32'h00001797 /* 0x1498 */; + 1319: data_o = 32'h8187b783 /* 0x149c */; + 1320: data_o = 32'h0e637702 /* 0x14a0 */; + 1321: data_o = 32'h678308f7 /* 0x14a4 */; + 1322: data_o = 32'h0b050081 /* 0x14a8 */; + 1323: data_o = 32'hfafb43e3 /* 0x14ac */; + 1324: data_o = 32'h00816783 /* 0x14b0 */; + 1325: data_o = 32'h00fb0863 /* 0x14b4 */; + 1326: data_o = 32'h69e26a42 /* 0x14b8 */; + 1327: data_o = 32'h0993a021 /* 0x14bc */; + 1328: data_o = 32'h4a0105f0 /* 0x14c0 */; + 1329: data_o = 32'h00198693 /* 0x14c4 */; + 1330: data_o = 32'h414686b3 /* 0x14c8 */; + 1331: data_o = 32'h0dfff597 /* 0x14cc */; + 1332: data_o = 32'h161306a6 /* 0x14d0 */; + 1333: data_o = 32'h8593009a /* 0x14d4 */; + 1334: data_o = 32'h8526b345 /* 0x14d8 */; + 1335: data_o = 32'h87aa9902 /* 0x14dc */; + 1336: data_o = 32'h70a6cd01 /* 0x14e0 */; + 1337: data_o = 32'h64e67406 /* 0x14e4 */; + 1338: data_o = 32'h69a66946 /* 0x14e8 */; + 1339: data_o = 32'h7ae26a06 /* 0x14ec */; + 1340: data_o = 32'h853e7b42 /* 0x14f0 */; + 1341: data_o = 32'h80826165 /* 0x14f4 */; + 1342: data_o = 32'h00196913 /* 0x14f8 */; + 1343: data_o = 32'hf7972901 /* 0x14fc */; + 1344: data_o = 32'ha12300ff /* 0x1500 */; + 1345: data_o = 32'hf797b127 /* 0x1504 */; + 1346: data_o = 32'h248100ff /* 0x1508 */; + 1347: data_o = 32'hafa78793 /* 0x150c */; + 1348: data_o = 32'h870ec3c4 /* 0x1510 */; + 1349: data_o = 32'h00fff797 /* 0x1514 */; + 1350: data_o = 32'h70a67406 /* 0x1518 */; + 1351: data_o = 32'h694664e6 /* 0x151c */; + 1352: data_o = 32'h6a0669a6 /* 0x1520 */; + 1353: data_o = 32'h7b427ae2 /* 0x1524 */; + 1354: data_o = 32'h87932701 /* 0x1528 */; + 1355: data_o = 32'hf517aec7 /* 0x152c */; + 1356: data_o = 32'hc7d80dff /* 0x1530 */; + 1357: data_o = 32'had250513 /* 0x1534 */; + 1358: data_o = 32'he06f6165 /* 0x1538 */; + 1359: data_o = 32'h0797b7ff /* 0x153c */; + 1360: data_o = 32'hb7830000 /* 0x1540 */; + 1361: data_o = 32'h772277a7 /* 0x1544 */; + 1362: data_o = 32'hf4f71fe3 /* 0x1548 */; + 1363: data_o = 32'hf797b795 /* 0x154c */; + 1364: data_o = 32'h711900ff /* 0x1550 */; + 1365: data_o = 32'hab278793 /* 0x1554 */; + 1366: data_o = 32'ha903f0ca /* 0x1558 */; + 1367: data_o = 32'hf7970407 /* 0x155c */; + 1368: data_o = 32'h879300ff /* 0x1560 */; + 1369: data_o = 32'hf8a2aa27 /* 0x1564 */; + 1370: data_o = 32'hf4a643e0 /* 0x1568 */; + 1371: data_o = 32'h1402ecce /* 0x156c */; + 1372: data_o = 32'h85229001 /* 0x1570 */; + 1373: data_o = 32'h2901fc86 /* 0x1574 */; + 1374: data_o = 32'hfaffe0ef /* 0x1578 */; + 1375: data_o = 32'h84aa4989 /* 0x157c */; + 1376: data_o = 32'h1d390863 /* 0x1580 */; + 1377: data_o = 32'h0e63478d /* 0x1584 */; + 1378: data_o = 32'h478526f9 /* 0x1588 */; + 1379: data_o = 32'h3cf91f63 /* 0x158c */; + 1380: data_o = 32'h016e37b7 /* 0x1590 */; + 1381: data_o = 32'h60078713 /* 0x1594 */; + 1382: data_o = 32'hec3ad002 /* 0x1598 */; + 1383: data_o = 32'h8793d24e /* 0x159c */; + 1384: data_o = 32'h45615ff7 /* 0x15a0 */; + 1385: data_o = 32'h1897ff63 /* 0x15a4 */; + 1386: data_o = 32'h01003517 /* 0x15a8 */; + 1387: data_o = 32'ha5850513 /* 0x15ac */; + 1388: data_o = 32'hf0efe82a /* 0x15b0 */; + 1389: data_o = 32'h17b79ecf /* 0x15b4 */; + 1390: data_o = 32'h87930003 /* 0x15b8 */; + 1391: data_o = 32'hc03ed407 /* 0x15bc */; + 1392: data_o = 32'h6582c226 /* 0x15c0 */; + 1393: data_o = 32'h46014681 /* 0x15c4 */; + 1394: data_o = 32'he4020808 /* 0x15c8 */; + 1395: data_o = 32'hecffe0ef /* 0x15cc */; + 1396: data_o = 32'h18632501 /* 0x15d0 */; + 1397: data_o = 32'h56921605 /* 0x15d4 */; + 1398: data_o = 32'h66226582 /* 0x15d8 */; + 1399: data_o = 32'he0ef0808 /* 0x15dc */; + 1400: data_o = 32'h2501ebdf /* 0x15e0 */; + 1401: data_o = 32'h14051f63 /* 0x15e4 */; + 1402: data_o = 32'h01003797 /* 0x15e8 */; + 1403: data_o = 32'ha1878793 /* 0x15ec */; + 1404: data_o = 32'h80000737 /* 0x15f0 */; + 1405: data_o = 32'h3797cb98 /* 0x15f4 */; + 1406: data_o = 32'h87930100 /* 0x15f8 */; + 1407: data_o = 32'h4b9ca0a7 /* 0x15fc */; + 1408: data_o = 32'he0000737 /* 0x1600 */; + 1409: data_o = 32'h8ff9177d /* 0x1604 */; + 1410: data_o = 32'h20000737 /* 0x1608 */; + 1411: data_o = 32'h37178fd9 /* 0x160c */; + 1412: data_o = 32'h07130100 /* 0x1610 */; + 1413: data_o = 32'hcb1c9f27 /* 0x1614 */; + 1414: data_o = 32'hf4025582 /* 0x1618 */; + 1415: data_o = 32'h05000793 /* 0x161c */; + 1416: data_o = 32'h10304685 /* 0x1620 */; + 1417: data_o = 32'hf8020808 /* 0x1624 */; + 1418: data_o = 32'he482e082 /* 0x1628 */; + 1419: data_o = 32'hfc3ed44e /* 0x162c */; + 1420: data_o = 32'hfa0ff0ef /* 0x1630 */; + 1421: data_o = 32'h16632501 /* 0x1634 */; + 1422: data_o = 32'h05931005 /* 0x1638 */; + 1423: data_o = 32'h15a20950 /* 0x163c */; + 1424: data_o = 32'h46854705 /* 0x1640 */; + 1425: data_o = 32'h85934601 /* 0x1644 */; + 1426: data_o = 32'h08080405 /* 0x1648 */; + 1427: data_o = 32'h9b9ff0ef /* 0x164c */; + 1428: data_o = 32'h0e051963 /* 0x1650 */; + 1429: data_o = 32'h00000797 /* 0x1654 */; + 1430: data_o = 32'h0aa01737 /* 0x1658 */; + 1431: data_o = 32'h66c7b583 /* 0x165c */; + 1432: data_o = 32'h07050732 /* 0x1660 */; + 1433: data_o = 32'h46114685 /* 0x1664 */; + 1434: data_o = 32'hf0ef0808 /* 0x1668 */; + 1435: data_o = 32'he97199bf /* 0x166c */; + 1436: data_o = 32'h06500493 /* 0x1670 */; + 1437: data_o = 32'h042314a2 /* 0x1674 */; + 1438: data_o = 32'h84930321 /* 0x1678 */; + 1439: data_o = 32'h47010774 /* 0x167c */; + 1440: data_o = 32'h46014681 /* 0x1680 */; + 1441: data_o = 32'h080885a6 /* 0x1684 */; + 1442: data_o = 32'h97dff0ef /* 0x1688 */; + 1443: data_o = 32'h0797e95d /* 0x168c */; + 1444: data_o = 32'hb5830000 /* 0x1690 */; + 1445: data_o = 32'h470163a7 /* 0x1694 */; + 1446: data_o = 32'h46011034 /* 0x1698 */; + 1447: data_o = 32'hf0ef0808 /* 0x169c */; + 1448: data_o = 32'he145807f /* 0x16a0 */; + 1449: data_o = 32'h02814783 /* 0x16a4 */; + 1450: data_o = 32'h0593fbf9 /* 0x16a8 */; + 1451: data_o = 32'h15a20fd0 /* 0x16ac */; + 1452: data_o = 32'h46814701 /* 0x16b0 */; + 1453: data_o = 32'h8593460d /* 0x16b4 */; + 1454: data_o = 32'h080807a5 /* 0x16b8 */; + 1455: data_o = 32'h949ff0ef /* 0x16bc */; + 1456: data_o = 32'h0797e149 /* 0x16c0 */; + 1457: data_o = 32'hb5830000 /* 0x16c4 */; + 1458: data_o = 32'h470160e7 /* 0x16c8 */; + 1459: data_o = 32'h46014685 /* 0x16cc */; + 1460: data_o = 32'hf0ef0808 /* 0x16d0 */; + 1461: data_o = 32'he535933f /* 0x16d4 */; + 1462: data_o = 32'h093764c2 /* 0x16d8 */; + 1463: data_o = 32'h197de000 /* 0x16dc */; + 1464: data_o = 32'h6622489c /* 0x16e0 */; + 1465: data_o = 32'hf7b30808 /* 0x16e4 */; + 1466: data_o = 32'hc89c0127 /* 0x16e8 */; + 1467: data_o = 32'h568267e2 /* 0x16ec */; + 1468: data_o = 32'h6582c03e /* 0x16f0 */; + 1469: data_o = 32'hda7fe0ef /* 0x16f4 */; + 1470: data_o = 32'he5212501 /* 0x16f8 */; + 1471: data_o = 32'h65825692 /* 0x16fc */; + 1472: data_o = 32'h08086622 /* 0x1700 */; + 1473: data_o = 32'hd97fe0ef /* 0x1704 */; + 1474: data_o = 32'hed052501 /* 0x1708 */; + 1475: data_o = 32'h3e800513 /* 0x170c */; + 1476: data_o = 32'h02a40533 /* 0x1710 */; + 1477: data_o = 32'h0737489c /* 0x1714 */; + 1478: data_o = 32'hf7b32000 /* 0x1718 */; + 1479: data_o = 32'h8fd90127 /* 0x171c */; + 1480: data_o = 32'h47b7c89c /* 0x1720 */; + 1481: data_o = 32'h8793000f /* 0x1724 */; + 1482: data_o = 32'h55332407 /* 0x1728 */; + 1483: data_o = 32'h050502f5 /* 0x172c */; + 1484: data_o = 32'ha8bfe0ef /* 0x1730 */; + 1485: data_o = 32'h00000517 /* 0x1734 */; + 1486: data_o = 32'h0513080c /* 0x1738 */; + 1487: data_o = 32'hf0efcc45 /* 0x173c */; + 1488: data_o = 32'h70e6cc3f /* 0x1740 */; + 1489: data_o = 32'h74a67446 /* 0x1744 */; + 1490: data_o = 32'h69e67906 /* 0x1748 */; + 1491: data_o = 32'h80826109 /* 0x174c */; + 1492: data_o = 32'h098967b7 /* 0x1750 */; + 1493: data_o = 32'h8793fc02 /* 0x1754 */; + 1494: data_o = 32'h59137ff7 /* 0x1758 */; + 1495: data_o = 32'hf6630025 /* 0x175c */; + 1496: data_o = 32'h693700a7 /* 0x1760 */; + 1497: data_o = 32'h09130262 /* 0x1764 */; + 1498: data_o = 32'h4785a009 /* 0x1768 */; + 1499: data_o = 32'hdc3ef84a /* 0x176c */; + 1500: data_o = 32'h08e3454d /* 0x1770 */; + 1501: data_o = 32'h4551fc09 /* 0x1774 */; + 1502: data_o = 32'hfd24e5e3 /* 0x1778 */; + 1503: data_o = 32'h01003517 /* 0x177c */; + 1504: data_o = 32'h88450513 /* 0x1780 */; + 1505: data_o = 32'hf0eff42a /* 0x1784 */; + 1506: data_o = 32'h17b7818f /* 0x1788 */; + 1507: data_o = 32'h8793000f /* 0x178c */; + 1508: data_o = 32'hc84af0f7 /* 0x1790 */; + 1509: data_o = 32'hcc3eca26 /* 0x1794 */; + 1510: data_o = 32'h00011e23 /* 0x1798 */; + 1511: data_o = 32'h666265c2 /* 0x179c */; + 1512: data_o = 32'h10284685 /* 0x17a0 */; + 1513: data_o = 32'hcf7fe0ef /* 0x17a4 */; + 1514: data_o = 32'hfd412501 /* 0x17a8 */; + 1515: data_o = 32'h01003797 /* 0x17ac */; + 1516: data_o = 32'h85478793 /* 0x17b0 */; + 1517: data_o = 32'h80000737 /* 0x17b4 */; + 1518: data_o = 32'h3797cb98 /* 0x17b8 */; + 1519: data_o = 32'h87930100 /* 0x17bc */; + 1520: data_o = 32'h4b9c8467 /* 0x17c0 */; + 1521: data_o = 32'he0000737 /* 0x17c4 */; + 1522: data_o = 32'h8ff9177d /* 0x17c8 */; + 1523: data_o = 32'h20000737 /* 0x17cc */; + 1524: data_o = 32'h37178fd9 /* 0x17d0 */; + 1525: data_o = 32'h07130100 /* 0x17d4 */; + 1526: data_o = 32'hcb1c82e7 /* 0x17d8 */; + 1527: data_o = 32'h15e00793 /* 0x17dc */; + 1528: data_o = 32'h02f40533 /* 0x17e0 */; + 1529: data_o = 32'h000f47b7 /* 0x17e4 */; + 1530: data_o = 32'h24078793 /* 0x17e8 */; + 1531: data_o = 32'h02f55533 /* 0x17ec */; + 1532: data_o = 32'he0ef0505 /* 0x17f0 */; + 1533: data_o = 32'hf5179c9f /* 0x17f4 */; + 1534: data_o = 32'h102cffff /* 0x17f8 */; + 1535: data_o = 32'h3d050513 /* 0x17fc */; + 1536: data_o = 32'h4549bf3d /* 0x1800 */; + 1537: data_o = 32'hd5b7dc9d /* 0x1804 */; + 1538: data_o = 32'h85933b9a /* 0x1808 */; + 1539: data_o = 32'hd5b3a005 /* 0x180c */; + 1540: data_o = 32'h17970295 /* 0x1810 */; + 1541: data_o = 32'h87930100 /* 0x1814 */; + 1542: data_o = 32'hf43e7ee7 /* 0x1818 */; + 1543: data_o = 32'h01001797 /* 0x181c */; + 1544: data_o = 32'h7e478793 /* 0x1820 */; + 1545: data_o = 32'h17974b98 /* 0x1824 */; + 1546: data_o = 32'h87930100 /* 0x1828 */; + 1547: data_o = 32'h9b797da7 /* 0x182c */; + 1548: data_o = 32'h1797cb98 /* 0x1830 */; + 1549: data_o = 32'h87930100 /* 0x1834 */; + 1550: data_o = 32'h53987ce7 /* 0x1838 */; + 1551: data_o = 32'h01001797 /* 0x183c */; + 1552: data_o = 32'h7c478793 /* 0x1840 */; + 1553: data_o = 32'h08076713 /* 0x1844 */; + 1554: data_o = 32'h1797d398 /* 0x1848 */; + 1555: data_o = 32'h87930100 /* 0x184c */; + 1556: data_o = 32'h53987b67 /* 0x1850 */; + 1557: data_o = 32'h01001797 /* 0x1854 */; + 1558: data_o = 32'h7ac78793 /* 0x1858 */; + 1559: data_o = 32'h00276713 /* 0x185c */; + 1560: data_o = 32'h1797d398 /* 0x1860 */; + 1561: data_o = 32'h87930100 /* 0x1864 */; + 1562: data_o = 32'h539879e7 /* 0x1868 */; + 1563: data_o = 32'h01001797 /* 0x186c */; + 1564: data_o = 32'h79478793 /* 0x1870 */; + 1565: data_o = 32'h00176713 /* 0x1874 */; + 1566: data_o = 32'h1797d398 /* 0x1878 */; + 1567: data_o = 32'h87930100 /* 0x187c */; + 1568: data_o = 32'h53987867 /* 0x1880 */; + 1569: data_o = 32'h01001797 /* 0x1884 */; + 1570: data_o = 32'h77c78793 /* 0x1888 */; + 1571: data_o = 32'h10076713 /* 0x188c */; + 1572: data_o = 32'h51300513 /* 0x1890 */; + 1573: data_o = 32'h06300613 /* 0x1894 */; + 1574: data_o = 32'h6685d398 /* 0x1898 */; + 1575: data_o = 32'h12b00713 /* 0x189c */; + 1576: data_o = 32'h9c36869b /* 0x18a0 */; + 1577: data_o = 32'h25700793 /* 0x18a4 */; + 1578: data_o = 32'h02b5553b /* 0x18a8 */; + 1579: data_o = 32'h02b6563b /* 0x18ac */; + 1580: data_o = 32'h91411542 /* 0x18b0 */; + 1581: data_o = 32'h0015081b /* 0x18b4 */; + 1582: data_o = 32'h0108181b /* 0x18b8 */; + 1583: data_o = 32'h02b7573b /* 0x18bc */; + 1584: data_o = 32'h16422605 /* 0x18c0 */; + 1585: data_o = 32'hd6bb9241 /* 0x18c4 */; + 1586: data_o = 32'h270502b6 /* 0x18c8 */; + 1587: data_o = 32'h93411742 /* 0x18cc */; + 1588: data_o = 32'h02b7d7bb /* 0x18d0 */; + 1589: data_o = 32'h9e919e89 /* 0x18d4 */; + 1590: data_o = 32'h85b69e99 /* 0x18d8 */; + 1591: data_o = 32'h92c116c2 /* 0x18dc */; + 1592: data_o = 32'h17c22785 /* 0x18e0 */; + 1593: data_o = 32'hf36393c1 /* 0x18e4 */; + 1594: data_o = 32'h85be00f6 /* 0x18e8 */; + 1595: data_o = 32'h0105959b /* 0x18ec */; + 1596: data_o = 32'h0105d59b /* 0x18f0 */; + 1597: data_o = 32'h0105e5b3 /* 0x18f4 */; + 1598: data_o = 32'h01001697 /* 0x18f8 */; + 1599: data_o = 32'h86932581 /* 0x18fc */; + 1600: data_o = 32'h171b7086 /* 0x1900 */; + 1601: data_o = 32'hda8c0107 /* 0x1904 */; + 1602: data_o = 32'h16978f51 /* 0x1908 */; + 1603: data_o = 32'h27010100 /* 0x190c */; 1604: data_o = 32'h6f668693 /* 0x1910 */; - 1605: data_o = 32'h0107171b /* 0x1914 */; - 1606: data_o = 32'h8f51da8c /* 0x1918 */; + 1605: data_o = 32'h971bdad8 /* 0x1914 */; + 1606: data_o = 32'h8f5d0107 /* 0x1918 */; 1607: data_o = 32'h01001697 /* 0x191c */; 1608: data_o = 32'h86932701 /* 0x1920 */; - 1609: data_o = 32'hdad86e46 /* 0x1924 */; - 1610: data_o = 32'h0107971b /* 0x1928 */; - 1611: data_o = 32'h16978f5d /* 0x192c */; - 1612: data_o = 32'h27010100 /* 0x1930 */; - 1613: data_o = 32'h6d268693 /* 0x1934 */; - 1614: data_o = 32'h6741de98 /* 0x1938 */; - 1615: data_o = 32'h17178e59 /* 0x193c */; - 1616: data_o = 32'h07130100 /* 0x1940 */; - 1617: data_o = 32'hdf506c27 /* 0x1944 */; - 1618: data_o = 32'h0107e7b3 /* 0x1948 */; - 1619: data_o = 32'h01001717 /* 0x194c */; - 1620: data_o = 32'h07132781 /* 0x1950 */; - 1621: data_o = 32'hc33c6b47 /* 0x1954 */; - 1622: data_o = 32'h01001797 /* 0x1958 */; - 1623: data_o = 32'h6a878793 /* 0x195c */; - 1624: data_o = 32'h17974b98 /* 0x1960 */; - 1625: data_o = 32'h87930100 /* 0x1964 */; - 1626: data_o = 32'h671369e7 /* 0x1968 */; - 1627: data_o = 32'hf5170017 /* 0x196c */; - 1628: data_o = 32'hcb98ffff /* 0x1970 */; - 1629: data_o = 32'h0513102c /* 0x1974 */; - 1630: data_o = 32'hbbd9ac45 /* 0x1978 */; - 1631: data_o = 32'h70e67446 /* 0x197c */; - 1632: data_o = 32'h790674a6 /* 0x1980 */; - 1633: data_o = 32'h610969e6 /* 0x1984 */; - 1634: data_o = 32'he4bfe06f /* 0x1988 */; - 1635: data_o = 32'h00000000 /* 0x198c */; - 1636: data_o = 32'h10210000 /* 0x1990 */; - 1637: data_o = 32'h30632042 /* 0x1994 */; - 1638: data_o = 32'h50a54084 /* 0x1998 */; - 1639: data_o = 32'h70e760c6 /* 0x199c */; - 1640: data_o = 32'h91298108 /* 0x19a0 */; - 1641: data_o = 32'hb16ba14a /* 0x19a4 */; - 1642: data_o = 32'hd1adc18c /* 0x19a8 */; - 1643: data_o = 32'hf1efe1ce /* 0x19ac */; - 1644: data_o = 32'h02101231 /* 0x19b0 */; - 1645: data_o = 32'h22523273 /* 0x19b4 */; - 1646: data_o = 32'h429452b5 /* 0x19b8 */; - 1647: data_o = 32'h62d672f7 /* 0x19bc */; - 1648: data_o = 32'h83189339 /* 0x19c0 */; - 1649: data_o = 32'ha35ab37b /* 0x19c4 */; - 1650: data_o = 32'hc39cd3bd /* 0x19c8 */; - 1651: data_o = 32'he3def3ff /* 0x19cc */; - 1652: data_o = 32'h34432462 /* 0x19d0 */; - 1653: data_o = 32'h14010420 /* 0x19d4 */; - 1654: data_o = 32'h74c764e6 /* 0x19d8 */; - 1655: data_o = 32'h548544a4 /* 0x19dc */; - 1656: data_o = 32'hb54ba56a /* 0x19e0 */; - 1657: data_o = 32'h95098528 /* 0x19e4 */; - 1658: data_o = 32'hf5cfe5ee /* 0x19e8 */; - 1659: data_o = 32'hd58dc5ac /* 0x19ec */; - 1660: data_o = 32'h26723653 /* 0x19f0 */; - 1661: data_o = 32'h06301611 /* 0x19f4 */; - 1662: data_o = 32'h66f676d7 /* 0x19f8 */; - 1663: data_o = 32'h46b45695 /* 0x19fc */; - 1664: data_o = 32'ha77ab75b /* 0x1a00 */; - 1665: data_o = 32'h87389719 /* 0x1a04 */; - 1666: data_o = 32'he7fef7df /* 0x1a08 */; - 1667: data_o = 32'hc7bcd79d /* 0x1a0c */; - 1668: data_o = 32'h58e548c4 /* 0x1a10 */; - 1669: data_o = 32'h78a76886 /* 0x1a14 */; - 1670: data_o = 32'h18610840 /* 0x1a18 */; - 1671: data_o = 32'h38232802 /* 0x1a1c */; - 1672: data_o = 32'hd9edc9cc /* 0x1a20 */; - 1673: data_o = 32'hf9afe98e /* 0x1a24 */; - 1674: data_o = 32'h99698948 /* 0x1a28 */; - 1675: data_o = 32'hb92ba90a /* 0x1a2c */; - 1676: data_o = 32'h4ad45af5 /* 0x1a30 */; - 1677: data_o = 32'h6a967ab7 /* 0x1a34 */; - 1678: data_o = 32'h0a501a71 /* 0x1a38 */; - 1679: data_o = 32'h2a123a33 /* 0x1a3c */; - 1680: data_o = 32'hcbdcdbfd /* 0x1a40 */; - 1681: data_o = 32'heb9efbbf /* 0x1a44 */; - 1682: data_o = 32'h8b589b79 /* 0x1a48 */; - 1683: data_o = 32'hab1abb3b /* 0x1a4c */; - 1684: data_o = 32'h7c876ca6 /* 0x1a50 */; - 1685: data_o = 32'h5cc54ce4 /* 0x1a54 */; - 1686: data_o = 32'h3c032c22 /* 0x1a58 */; - 1687: data_o = 32'h1c410c60 /* 0x1a5c */; - 1688: data_o = 32'hfd8fedae /* 0x1a60 */; - 1689: data_o = 32'hddcdcdec /* 0x1a64 */; - 1690: data_o = 32'hbd0bad2a /* 0x1a68 */; - 1691: data_o = 32'h9d498d68 /* 0x1a6c */; - 1692: data_o = 32'h6eb67e97 /* 0x1a70 */; - 1693: data_o = 32'h4ef45ed5 /* 0x1a74 */; - 1694: data_o = 32'h2e323e13 /* 0x1a78 */; - 1695: data_o = 32'h0e701e51 /* 0x1a7c */; - 1696: data_o = 32'hefbeff9f /* 0x1a80 */; - 1697: data_o = 32'hcffcdfdd /* 0x1a84 */; - 1698: data_o = 32'haf3abf1b /* 0x1a88 */; - 1699: data_o = 32'h8f789f59 /* 0x1a8c */; - 1700: data_o = 32'h81a99188 /* 0x1a90 */; - 1701: data_o = 32'ha1ebb1ca /* 0x1a94 */; - 1702: data_o = 32'hc12dd10c /* 0x1a98 */; - 1703: data_o = 32'he16ff14e /* 0x1a9c */; - 1704: data_o = 32'h00a11080 /* 0x1aa0 */; - 1705: data_o = 32'h20e330c2 /* 0x1aa4 */; - 1706: data_o = 32'h40255004 /* 0x1aa8 */; - 1707: data_o = 32'h60677046 /* 0x1aac */; - 1708: data_o = 32'h939883b9 /* 0x1ab0 */; - 1709: data_o = 32'hb3daa3fb /* 0x1ab4 */; - 1710: data_o = 32'hd31cc33d /* 0x1ab8 */; - 1711: data_o = 32'hf35ee37f /* 0x1abc */; - 1712: data_o = 32'h129002b1 /* 0x1ac0 */; - 1713: data_o = 32'h32d222f3 /* 0x1ac4 */; - 1714: data_o = 32'h52144235 /* 0x1ac8 */; - 1715: data_o = 32'h72566277 /* 0x1acc */; - 1716: data_o = 32'ha5cbb5ea /* 0x1ad0 */; - 1717: data_o = 32'h858995a8 /* 0x1ad4 */; - 1718: data_o = 32'he54ff56e /* 0x1ad8 */; - 1719: data_o = 32'hc50dd52c /* 0x1adc */; - 1720: data_o = 32'h24c334e2 /* 0x1ae0 */; - 1721: data_o = 32'h048114a0 /* 0x1ae4 */; - 1722: data_o = 32'h64477466 /* 0x1ae8 */; - 1723: data_o = 32'h44055424 /* 0x1aec */; - 1724: data_o = 32'hb7faa7db /* 0x1af0 */; - 1725: data_o = 32'h97b88799 /* 0x1af4 */; - 1726: data_o = 32'hf77ee75f /* 0x1af8 */; - 1727: data_o = 32'hd73cc71d /* 0x1afc */; - 1728: data_o = 32'h36f226d3 /* 0x1b00 */; - 1729: data_o = 32'h16b00691 /* 0x1b04 */; - 1730: data_o = 32'h76766657 /* 0x1b08 */; - 1731: data_o = 32'h56344615 /* 0x1b0c */; - 1732: data_o = 32'hc96dd94c /* 0x1b10 */; - 1733: data_o = 32'he92ff90e /* 0x1b14 */; - 1734: data_o = 32'h89e999c8 /* 0x1b18 */; - 1735: data_o = 32'ha9abb98a /* 0x1b1c */; - 1736: data_o = 32'h48655844 /* 0x1b20 */; - 1737: data_o = 32'h68277806 /* 0x1b24 */; - 1738: data_o = 32'h08e118c0 /* 0x1b28 */; - 1739: data_o = 32'h28a33882 /* 0x1b2c */; - 1740: data_o = 32'hdb5ccb7d /* 0x1b30 */; - 1741: data_o = 32'hfb1eeb3f /* 0x1b34 */; - 1742: data_o = 32'h9bd88bf9 /* 0x1b38 */; - 1743: data_o = 32'hbb9aabbb /* 0x1b3c */; - 1744: data_o = 32'h5a544a75 /* 0x1b40 */; - 1745: data_o = 32'h7a166a37 /* 0x1b44 */; - 1746: data_o = 32'h1ad00af1 /* 0x1b48 */; - 1747: data_o = 32'h3a922ab3 /* 0x1b4c */; - 1748: data_o = 32'hed0ffd2e /* 0x1b50 */; - 1749: data_o = 32'hcd4ddd6c /* 0x1b54 */; - 1750: data_o = 32'had8bbdaa /* 0x1b58 */; - 1751: data_o = 32'h8dc99de8 /* 0x1b5c */; - 1752: data_o = 32'h6c077c26 /* 0x1b60 */; - 1753: data_o = 32'h4c455c64 /* 0x1b64 */; - 1754: data_o = 32'h2c833ca2 /* 0x1b68 */; - 1755: data_o = 32'h0cc11ce0 /* 0x1b6c */; - 1756: data_o = 32'hff3eef1f /* 0x1b70 */; - 1757: data_o = 32'hdf7ccf5d /* 0x1b74 */; - 1758: data_o = 32'hbfbaaf9b /* 0x1b78 */; - 1759: data_o = 32'h9ff88fd9 /* 0x1b7c */; - 1760: data_o = 32'h7e366e17 /* 0x1b80 */; - 1761: data_o = 32'h5e744e55 /* 0x1b84 */; - 1762: data_o = 32'h3eb22e93 /* 0x1b88 */; - 1763: data_o = 32'h1ef00ed1 /* 0x1b8c */; - 1764: data_o = 32'h36241200 /* 0x1b90 */; - 1765: data_o = 32'h7e6c5a48 /* 0x1b94 */; - 1766: data_o = 32'ha6b48290 /* 0x1b98 */; - 1767: data_o = 32'heefccad8 /* 0x1b9c */; - 1768: data_o = 32'h04162032 /* 0x1ba0 */; - 1769: data_o = 32'h4c5e687a /* 0x1ba4 */; - 1770: data_o = 32'h9486b0a2 /* 0x1ba8 */; - 1771: data_o = 32'hdccef8ea /* 0x1bac */; - 1772: data_o = 32'h52407664 /* 0x1bb0 */; - 1773: data_o = 32'h1a083e2c /* 0x1bb4 */; - 1774: data_o = 32'hc2d0e6f4 /* 0x1bb8 */; - 1775: data_o = 32'h8a98aebc /* 0x1bbc */; - 1776: data_o = 32'h60724456 /* 0x1bc0 */; - 1777: data_o = 32'h283a0c1e /* 0x1bc4 */; - 1778: data_o = 32'hf0e2d4c6 /* 0x1bc8 */; - 1779: data_o = 32'hb8aa9c8e /* 0x1bcc */; - 1780: data_o = 32'hfeecdac8 /* 0x1bd0 */; - 1781: data_o = 32'hb6a49280 /* 0x1bd4 */; - 1782: data_o = 32'h6e7c4a58 /* 0x1bd8 */; - 1783: data_o = 32'h26340210 /* 0x1bdc */; - 1784: data_o = 32'hccdee8fa /* 0x1be0 */; - 1785: data_o = 32'h8496a0b2 /* 0x1be4 */; - 1786: data_o = 32'h5c4e786a /* 0x1be8 */; - 1787: data_o = 32'h14063022 /* 0x1bec */; - 1788: data_o = 32'h9a88beac /* 0x1bf0 */; - 1789: data_o = 32'hd2c0f6e4 /* 0x1bf4 */; - 1790: data_o = 32'h0a182e3c /* 0x1bf8 */; - 1791: data_o = 32'h42506674 /* 0x1bfc */; - 1792: data_o = 32'ha8ba8c9e /* 0x1c00 */; - 1793: data_o = 32'he0f2c4d6 /* 0x1c04 */; - 1794: data_o = 32'h382a1c0e /* 0x1c08 */; - 1795: data_o = 32'h70625446 /* 0x1c0c */; - 1796: data_o = 32'hb4a69082 /* 0x1c10 */; - 1797: data_o = 32'hfceed8ca /* 0x1c14 */; - 1798: data_o = 32'h24360012 /* 0x1c18 */; - 1799: data_o = 32'h6c7e485a /* 0x1c1c */; - 1800: data_o = 32'h8694a2b0 /* 0x1c20 */; - 1801: data_o = 32'hcedceaf8 /* 0x1c24 */; - 1802: data_o = 32'h16043220 /* 0x1c28 */; - 1803: data_o = 32'h5e4c7a68 /* 0x1c2c */; - 1804: data_o = 32'hd0c2f4e6 /* 0x1c30 */; - 1805: data_o = 32'h988abcae /* 0x1c34 */; - 1806: data_o = 32'h40526476 /* 0x1c38 */; - 1807: data_o = 32'h081a2c3e /* 0x1c3c */; - 1808: data_o = 32'he2f0c6d4 /* 0x1c40 */; - 1809: data_o = 32'haab88e9c /* 0x1c44 */; - 1810: data_o = 32'h72605644 /* 0x1c48 */; - 1811: data_o = 32'h3a281e0c /* 0x1c4c */; - 1812: data_o = 32'h7c6e584a /* 0x1c50 */; - 1813: data_o = 32'h34261002 /* 0x1c54 */; - 1814: data_o = 32'hecfec8da /* 0x1c58 */; - 1815: data_o = 32'ha4b68092 /* 0x1c5c */; - 1816: data_o = 32'h4e5c6a78 /* 0x1c60 */; - 1817: data_o = 32'h06142230 /* 0x1c64 */; - 1818: data_o = 32'hdeccfae8 /* 0x1c68 */; - 1819: data_o = 32'h9684b2a0 /* 0x1c6c */; - 1820: data_o = 32'h180a3c2e /* 0x1c70 */; - 1821: data_o = 32'h50427466 /* 0x1c74 */; - 1822: data_o = 32'h889aacbe /* 0x1c78 */; - 1823: data_o = 32'hc0d2e4f6 /* 0x1c7c */; - 1824: data_o = 32'h2a380e1c /* 0x1c80 */; - 1825: data_o = 32'h62704654 /* 0x1c84 */; - 1826: data_o = 32'hbaa89e8c /* 0x1c88 */; - 1827: data_o = 32'hf2e0d6c4 /* 0x1c8c */; - 1828: data_o = 32'h00000001 /* 0x1c90 */; + 1609: data_o = 32'hde986e46 /* 0x1924 */; + 1610: data_o = 32'h8e596741 /* 0x1928 */; + 1611: data_o = 32'h01001717 /* 0x192c */; + 1612: data_o = 32'h6d470713 /* 0x1930 */; + 1613: data_o = 32'he7b3df50 /* 0x1934 */; + 1614: data_o = 32'h17170107 /* 0x1938 */; + 1615: data_o = 32'h27810100 /* 0x193c */; + 1616: data_o = 32'h6c670713 /* 0x1940 */; + 1617: data_o = 32'h1797c33c /* 0x1944 */; + 1618: data_o = 32'h87930100 /* 0x1948 */; + 1619: data_o = 32'h4b986ba7 /* 0x194c */; + 1620: data_o = 32'h01001797 /* 0x1950 */; + 1621: data_o = 32'h6b078793 /* 0x1954 */; + 1622: data_o = 32'h00176713 /* 0x1958 */; + 1623: data_o = 32'hfffff517 /* 0x195c */; + 1624: data_o = 32'h102ccb98 /* 0x1960 */; + 1625: data_o = 32'hac650513 /* 0x1964 */; + 1626: data_o = 32'h7446bbd9 /* 0x1968 */; + 1627: data_o = 32'h74a670e6 /* 0x196c */; + 1628: data_o = 32'h69e67906 /* 0x1970 */; + 1629: data_o = 32'he06f6109 /* 0x1974 */; + 1630: data_o = 32'h0000e4df /* 0x1978 */; + 1631: data_o = 32'h00000000 /* 0x197c */; + 1632: data_o = 32'h10210000 /* 0x1980 */; + 1633: data_o = 32'h30632042 /* 0x1984 */; + 1634: data_o = 32'h50a54084 /* 0x1988 */; + 1635: data_o = 32'h70e760c6 /* 0x198c */; + 1636: data_o = 32'h91298108 /* 0x1990 */; + 1637: data_o = 32'hb16ba14a /* 0x1994 */; + 1638: data_o = 32'hd1adc18c /* 0x1998 */; + 1639: data_o = 32'hf1efe1ce /* 0x199c */; + 1640: data_o = 32'h02101231 /* 0x19a0 */; + 1641: data_o = 32'h22523273 /* 0x19a4 */; + 1642: data_o = 32'h429452b5 /* 0x19a8 */; + 1643: data_o = 32'h62d672f7 /* 0x19ac */; + 1644: data_o = 32'h83189339 /* 0x19b0 */; + 1645: data_o = 32'ha35ab37b /* 0x19b4 */; + 1646: data_o = 32'hc39cd3bd /* 0x19b8 */; + 1647: data_o = 32'he3def3ff /* 0x19bc */; + 1648: data_o = 32'h34432462 /* 0x19c0 */; + 1649: data_o = 32'h14010420 /* 0x19c4 */; + 1650: data_o = 32'h74c764e6 /* 0x19c8 */; + 1651: data_o = 32'h548544a4 /* 0x19cc */; + 1652: data_o = 32'hb54ba56a /* 0x19d0 */; + 1653: data_o = 32'h95098528 /* 0x19d4 */; + 1654: data_o = 32'hf5cfe5ee /* 0x19d8 */; + 1655: data_o = 32'hd58dc5ac /* 0x19dc */; + 1656: data_o = 32'h26723653 /* 0x19e0 */; + 1657: data_o = 32'h06301611 /* 0x19e4 */; + 1658: data_o = 32'h66f676d7 /* 0x19e8 */; + 1659: data_o = 32'h46b45695 /* 0x19ec */; + 1660: data_o = 32'ha77ab75b /* 0x19f0 */; + 1661: data_o = 32'h87389719 /* 0x19f4 */; + 1662: data_o = 32'he7fef7df /* 0x19f8 */; + 1663: data_o = 32'hc7bcd79d /* 0x19fc */; + 1664: data_o = 32'h58e548c4 /* 0x1a00 */; + 1665: data_o = 32'h78a76886 /* 0x1a04 */; + 1666: data_o = 32'h18610840 /* 0x1a08 */; + 1667: data_o = 32'h38232802 /* 0x1a0c */; + 1668: data_o = 32'hd9edc9cc /* 0x1a10 */; + 1669: data_o = 32'hf9afe98e /* 0x1a14 */; + 1670: data_o = 32'h99698948 /* 0x1a18 */; + 1671: data_o = 32'hb92ba90a /* 0x1a1c */; + 1672: data_o = 32'h4ad45af5 /* 0x1a20 */; + 1673: data_o = 32'h6a967ab7 /* 0x1a24 */; + 1674: data_o = 32'h0a501a71 /* 0x1a28 */; + 1675: data_o = 32'h2a123a33 /* 0x1a2c */; + 1676: data_o = 32'hcbdcdbfd /* 0x1a30 */; + 1677: data_o = 32'heb9efbbf /* 0x1a34 */; + 1678: data_o = 32'h8b589b79 /* 0x1a38 */; + 1679: data_o = 32'hab1abb3b /* 0x1a3c */; + 1680: data_o = 32'h7c876ca6 /* 0x1a40 */; + 1681: data_o = 32'h5cc54ce4 /* 0x1a44 */; + 1682: data_o = 32'h3c032c22 /* 0x1a48 */; + 1683: data_o = 32'h1c410c60 /* 0x1a4c */; + 1684: data_o = 32'hfd8fedae /* 0x1a50 */; + 1685: data_o = 32'hddcdcdec /* 0x1a54 */; + 1686: data_o = 32'hbd0bad2a /* 0x1a58 */; + 1687: data_o = 32'h9d498d68 /* 0x1a5c */; + 1688: data_o = 32'h6eb67e97 /* 0x1a60 */; + 1689: data_o = 32'h4ef45ed5 /* 0x1a64 */; + 1690: data_o = 32'h2e323e13 /* 0x1a68 */; + 1691: data_o = 32'h0e701e51 /* 0x1a6c */; + 1692: data_o = 32'hefbeff9f /* 0x1a70 */; + 1693: data_o = 32'hcffcdfdd /* 0x1a74 */; + 1694: data_o = 32'haf3abf1b /* 0x1a78 */; + 1695: data_o = 32'h8f789f59 /* 0x1a7c */; + 1696: data_o = 32'h81a99188 /* 0x1a80 */; + 1697: data_o = 32'ha1ebb1ca /* 0x1a84 */; + 1698: data_o = 32'hc12dd10c /* 0x1a88 */; + 1699: data_o = 32'he16ff14e /* 0x1a8c */; + 1700: data_o = 32'h00a11080 /* 0x1a90 */; + 1701: data_o = 32'h20e330c2 /* 0x1a94 */; + 1702: data_o = 32'h40255004 /* 0x1a98 */; + 1703: data_o = 32'h60677046 /* 0x1a9c */; + 1704: data_o = 32'h939883b9 /* 0x1aa0 */; + 1705: data_o = 32'hb3daa3fb /* 0x1aa4 */; + 1706: data_o = 32'hd31cc33d /* 0x1aa8 */; + 1707: data_o = 32'hf35ee37f /* 0x1aac */; + 1708: data_o = 32'h129002b1 /* 0x1ab0 */; + 1709: data_o = 32'h32d222f3 /* 0x1ab4 */; + 1710: data_o = 32'h52144235 /* 0x1ab8 */; + 1711: data_o = 32'h72566277 /* 0x1abc */; + 1712: data_o = 32'ha5cbb5ea /* 0x1ac0 */; + 1713: data_o = 32'h858995a8 /* 0x1ac4 */; + 1714: data_o = 32'he54ff56e /* 0x1ac8 */; + 1715: data_o = 32'hc50dd52c /* 0x1acc */; + 1716: data_o = 32'h24c334e2 /* 0x1ad0 */; + 1717: data_o = 32'h048114a0 /* 0x1ad4 */; + 1718: data_o = 32'h64477466 /* 0x1ad8 */; + 1719: data_o = 32'h44055424 /* 0x1adc */; + 1720: data_o = 32'hb7faa7db /* 0x1ae0 */; + 1721: data_o = 32'h97b88799 /* 0x1ae4 */; + 1722: data_o = 32'hf77ee75f /* 0x1ae8 */; + 1723: data_o = 32'hd73cc71d /* 0x1aec */; + 1724: data_o = 32'h36f226d3 /* 0x1af0 */; + 1725: data_o = 32'h16b00691 /* 0x1af4 */; + 1726: data_o = 32'h76766657 /* 0x1af8 */; + 1727: data_o = 32'h56344615 /* 0x1afc */; + 1728: data_o = 32'hc96dd94c /* 0x1b00 */; + 1729: data_o = 32'he92ff90e /* 0x1b04 */; + 1730: data_o = 32'h89e999c8 /* 0x1b08 */; + 1731: data_o = 32'ha9abb98a /* 0x1b0c */; + 1732: data_o = 32'h48655844 /* 0x1b10 */; + 1733: data_o = 32'h68277806 /* 0x1b14 */; + 1734: data_o = 32'h08e118c0 /* 0x1b18 */; + 1735: data_o = 32'h28a33882 /* 0x1b1c */; + 1736: data_o = 32'hdb5ccb7d /* 0x1b20 */; + 1737: data_o = 32'hfb1eeb3f /* 0x1b24 */; + 1738: data_o = 32'h9bd88bf9 /* 0x1b28 */; + 1739: data_o = 32'hbb9aabbb /* 0x1b2c */; + 1740: data_o = 32'h5a544a75 /* 0x1b30 */; + 1741: data_o = 32'h7a166a37 /* 0x1b34 */; + 1742: data_o = 32'h1ad00af1 /* 0x1b38 */; + 1743: data_o = 32'h3a922ab3 /* 0x1b3c */; + 1744: data_o = 32'hed0ffd2e /* 0x1b40 */; + 1745: data_o = 32'hcd4ddd6c /* 0x1b44 */; + 1746: data_o = 32'had8bbdaa /* 0x1b48 */; + 1747: data_o = 32'h8dc99de8 /* 0x1b4c */; + 1748: data_o = 32'h6c077c26 /* 0x1b50 */; + 1749: data_o = 32'h4c455c64 /* 0x1b54 */; + 1750: data_o = 32'h2c833ca2 /* 0x1b58 */; + 1751: data_o = 32'h0cc11ce0 /* 0x1b5c */; + 1752: data_o = 32'hff3eef1f /* 0x1b60 */; + 1753: data_o = 32'hdf7ccf5d /* 0x1b64 */; + 1754: data_o = 32'hbfbaaf9b /* 0x1b68 */; + 1755: data_o = 32'h9ff88fd9 /* 0x1b6c */; + 1756: data_o = 32'h7e366e17 /* 0x1b70 */; + 1757: data_o = 32'h5e744e55 /* 0x1b74 */; + 1758: data_o = 32'h3eb22e93 /* 0x1b78 */; + 1759: data_o = 32'h1ef00ed1 /* 0x1b7c */; + 1760: data_o = 32'h36241200 /* 0x1b80 */; + 1761: data_o = 32'h7e6c5a48 /* 0x1b84 */; + 1762: data_o = 32'ha6b48290 /* 0x1b88 */; + 1763: data_o = 32'heefccad8 /* 0x1b8c */; + 1764: data_o = 32'h04162032 /* 0x1b90 */; + 1765: data_o = 32'h4c5e687a /* 0x1b94 */; + 1766: data_o = 32'h9486b0a2 /* 0x1b98 */; + 1767: data_o = 32'hdccef8ea /* 0x1b9c */; + 1768: data_o = 32'h52407664 /* 0x1ba0 */; + 1769: data_o = 32'h1a083e2c /* 0x1ba4 */; + 1770: data_o = 32'hc2d0e6f4 /* 0x1ba8 */; + 1771: data_o = 32'h8a98aebc /* 0x1bac */; + 1772: data_o = 32'h60724456 /* 0x1bb0 */; + 1773: data_o = 32'h283a0c1e /* 0x1bb4 */; + 1774: data_o = 32'hf0e2d4c6 /* 0x1bb8 */; + 1775: data_o = 32'hb8aa9c8e /* 0x1bbc */; + 1776: data_o = 32'hfeecdac8 /* 0x1bc0 */; + 1777: data_o = 32'hb6a49280 /* 0x1bc4 */; + 1778: data_o = 32'h6e7c4a58 /* 0x1bc8 */; + 1779: data_o = 32'h26340210 /* 0x1bcc */; + 1780: data_o = 32'hccdee8fa /* 0x1bd0 */; + 1781: data_o = 32'h8496a0b2 /* 0x1bd4 */; + 1782: data_o = 32'h5c4e786a /* 0x1bd8 */; + 1783: data_o = 32'h14063022 /* 0x1bdc */; + 1784: data_o = 32'h9a88beac /* 0x1be0 */; + 1785: data_o = 32'hd2c0f6e4 /* 0x1be4 */; + 1786: data_o = 32'h0a182e3c /* 0x1be8 */; + 1787: data_o = 32'h42506674 /* 0x1bec */; + 1788: data_o = 32'ha8ba8c9e /* 0x1bf0 */; + 1789: data_o = 32'he0f2c4d6 /* 0x1bf4 */; + 1790: data_o = 32'h382a1c0e /* 0x1bf8 */; + 1791: data_o = 32'h70625446 /* 0x1bfc */; + 1792: data_o = 32'hb4a69082 /* 0x1c00 */; + 1793: data_o = 32'hfceed8ca /* 0x1c04 */; + 1794: data_o = 32'h24360012 /* 0x1c08 */; + 1795: data_o = 32'h6c7e485a /* 0x1c0c */; + 1796: data_o = 32'h8694a2b0 /* 0x1c10 */; + 1797: data_o = 32'hcedceaf8 /* 0x1c14 */; + 1798: data_o = 32'h16043220 /* 0x1c18 */; + 1799: data_o = 32'h5e4c7a68 /* 0x1c1c */; + 1800: data_o = 32'hd0c2f4e6 /* 0x1c20 */; + 1801: data_o = 32'h988abcae /* 0x1c24 */; + 1802: data_o = 32'h40526476 /* 0x1c28 */; + 1803: data_o = 32'h081a2c3e /* 0x1c2c */; + 1804: data_o = 32'he2f0c6d4 /* 0x1c30 */; + 1805: data_o = 32'haab88e9c /* 0x1c34 */; + 1806: data_o = 32'h72605644 /* 0x1c38 */; + 1807: data_o = 32'h3a281e0c /* 0x1c3c */; + 1808: data_o = 32'h7c6e584a /* 0x1c40 */; + 1809: data_o = 32'h34261002 /* 0x1c44 */; + 1810: data_o = 32'hecfec8da /* 0x1c48 */; + 1811: data_o = 32'ha4b68092 /* 0x1c4c */; + 1812: data_o = 32'h4e5c6a78 /* 0x1c50 */; + 1813: data_o = 32'h06142230 /* 0x1c54 */; + 1814: data_o = 32'hdeccfae8 /* 0x1c58 */; + 1815: data_o = 32'h9684b2a0 /* 0x1c5c */; + 1816: data_o = 32'h180a3c2e /* 0x1c60 */; + 1817: data_o = 32'h50427466 /* 0x1c64 */; + 1818: data_o = 32'h889aacbe /* 0x1c68 */; + 1819: data_o = 32'hc0d2e4f6 /* 0x1c6c */; + 1820: data_o = 32'h2a380e1c /* 0x1c70 */; + 1821: data_o = 32'h62704654 /* 0x1c74 */; + 1822: data_o = 32'hbaa89e8c /* 0x1c78 */; + 1823: data_o = 32'hf2e0d6c4 /* 0x1c7c */; + 1824: data_o = 32'h00000001 /* 0x1c80 */; + 1825: data_o = 32'h00000000 /* 0x1c84 */; + 1826: data_o = 32'h00000001 /* 0x1c88 */; + 1827: data_o = 32'h00000000 /* 0x1c8c */; + 1828: data_o = 32'h00000002 /* 0x1c90 */; 1829: data_o = 32'h00000000 /* 0x1c94 */; - 1830: data_o = 32'h00000001 /* 0x1c98 */; + 1830: data_o = 32'h00000005 /* 0x1c98 */; 1831: data_o = 32'h00000000 /* 0x1c9c */; - 1832: data_o = 32'h00000002 /* 0x1ca0 */; + 1832: data_o = 32'h00000005 /* 0x1ca0 */; 1833: data_o = 32'h00000000 /* 0x1ca4 */; - 1834: data_o = 32'h00000005 /* 0x1ca8 */; - 1835: data_o = 32'h00000000 /* 0x1cac */; - 1836: data_o = 32'h00000005 /* 0x1cb0 */; - 1837: data_o = 32'h00000000 /* 0x1cb4 */; - 1838: data_o = 32'h20494645 /* 0x1cb8 */; - 1839: data_o = 32'h54524150 /* 0x1cbc */; - 1840: data_o = 32'h0269b26a /* 0x1cc0 */; - 1841: data_o = 32'h4ce4fd95 /* 0x1cc4 */; - 1842: data_o = 32'h1494cf98 /* 0x1cc8 */; - 1843: data_o = 32'h622c4101 /* 0x1ccc */; - 1844: data_o = 32'h01000048 /* 0x1cd0 */; - 1845: data_o = 32'h000087aa /* 0x1cd4 */; - 1846: data_o = 32'h00004069 /* 0x1cd8 */; - 1847: data_o = 32'h00007700 /* 0x1cdc */; - 1848: data_o = 32'h02000050 /* 0x1ce0 */; - 1849: data_o = 32'h00001500 /* 0x1ce4 */; + 1834: data_o = 32'h20494645 /* 0x1ca8 */; + 1835: data_o = 32'h54524150 /* 0x1cac */; + 1836: data_o = 32'h0269b26a /* 0x1cb0 */; + 1837: data_o = 32'h4ce4fd95 /* 0x1cb4 */; + 1838: data_o = 32'h1494cf98 /* 0x1cb8 */; + 1839: data_o = 32'h622c4101 /* 0x1cbc */; + 1840: data_o = 32'h01000048 /* 0x1cc0 */; + 1841: data_o = 32'h000087aa /* 0x1cc4 */; + 1842: data_o = 32'h00004069 /* 0x1cc8 */; + 1843: data_o = 32'h00007700 /* 0x1ccc */; + 1844: data_o = 32'h02000050 /* 0x1cd0 */; + 1845: data_o = 32'h00001500 /* 0x1cd4 */; + 1846: data_o = 32'h00000000 /* 0x1cd8 */; + 1847: data_o = 32'h00000000 /* 0x1cdc */; + 1848: data_o = 32'h00000000 /* 0x1ce0 */; + 1849: data_o = 32'h00000000 /* 0x1ce4 */; 1850: data_o = 32'h00000000 /* 0x1ce8 */; 1851: data_o = 32'h00000000 /* 0x1cec */; 1852: data_o = 32'h00000000 /* 0x1cf0 */; @@ -2081,4 +2081,4 @@ module cheshire_bootrom #( endcase end -endmodule +endmodule \ No newline at end of file diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 97f6eb04..d8808eb7 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -85,11 +85,6 @@ package cheshire_pkg; byte_bt NumExtOutIntrTgts; shrt_bt NumExtOutIntrs; shrt_bt ClicIntCtlBits; - bit ClicUseSMode; - bit ClicUseUMode; - bit ClicUseVsMode; - bit ClicUseVsModePrio; - byte_bt ClicNumVsCtxts; shrt_bt NumExtIntrSyncs; // AXI parameters aw_bt AddrWidth; @@ -145,10 +140,6 @@ package cheshire_pkg; bit Clic; bit IrqRouter; bit BusErr; - bit HmrUnit; - bit Cva6DMR; - bit Cva6DMRFixed; - bit RapidRecovery; // Parameters for Debug Module jtag_idcode_t DbgIdCode; dw_bt DbgMaxReqs; @@ -161,9 +152,6 @@ package cheshire_pkg; shrt_bt LlcSetAssoc; shrt_bt LlcNumLines; shrt_bt LlcNumBlocks; - bit LlcCachePartition; - shrt_bt LlcMaxPartition; - axi_llc_pkg::algorithm_e LlcRemapHash; dw_bt LlcMaxReadTxns; dw_bt LlcMaxWriteTxns; aw_bt LlcAmoNumCuts; @@ -171,8 +159,6 @@ package cheshire_pkg; bit LlcOutConnect; doub_bt LlcOutRegionStart; doub_bt LlcOutRegionEnd; - dw_bt LlcUserMsb; - dw_bt LlcUserLsb; // Parameters for VGA byte_bt VgaRedWidth; byte_bt VgaGreenWidth; @@ -285,16 +271,14 @@ package cheshire_pkg; endfunction // Static addresses (defined here only if multiply used) - localparam doub_bt AmDbg = 'h0000_0000; // Base of AXI peripherals - localparam doub_bt AmBrom = 'h0200_0000; // Base of reg peripherals - localparam doub_bt AmRegs = 'h0300_0000; - localparam doub_bt AmLlc = 'h0300_1000; - localparam doub_bt AmSlink = 'h0300_6000; - localparam doub_bt AmBusErr = 'h0300_8000; - localparam doub_bt AmTagger = 'h0300_A000; - localparam doub_bt AmHmrUnit = 'h0300_B000; - localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top - localparam doub_bt AmClic = 'h0800_0000; + localparam doub_bt AmDbg = 'h0000_0000; // Base of AXI peripherals + localparam doub_bt AmBrom = 'h0200_0000; // Base of reg peripherals + localparam doub_bt AmRegs = 'h0300_0000; + localparam doub_bt AmLlc = 'h0300_1000; + localparam doub_bt AmSlink = 'h0300_6000; + localparam doub_bt AmBusErr = 'h0300_8000; + localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top + localparam doub_bt AmClic = 'h0800_0000; // Static masks localparam doub_bt AmSpmBaseUncached = 'h1400_0000; @@ -412,7 +396,6 @@ package cheshire_pkg; aw_bt irq_router; aw_bt [2**MaxCoresWidth-1:0] bus_err; aw_bt [2**MaxCoresWidth-1:0] clic; - aw_bt [2**MaxCoresWidth-1:0] tagger; aw_bt hmr_unit; aw_bt ext_base; aw_bt num_out; @@ -443,12 +426,6 @@ package cheshire_pkg; if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40, AmBusErr + (j+1)*'h40}; end - if (cfg.LlcCachePartition) for (int j = 0; j < cfg.NumCores; j++) begin - i++; ret.tagger[j] = i; r++; ret.map[r] = '{i, AmTagger + j*'h100, AmTagger + (j+1)*'h100}; - end - if (cfg.HmrUnit) begin - i++; ret.hmr_unit = i; r++; ret.map[r] = '{i, AmHmrUnit, AmHmrUnit+'h400}; - end i++; r++; ret.ext_base = i; ret.num_out = i + cfg.RegExtNumSlv; @@ -598,11 +575,6 @@ package cheshire_pkg; NumExtOutIntrTgts : 0, NumExtOutIntrs : 0, ClicIntCtlBits : 8, - ClicUseSMode : 0, - ClicUseUMode : 0, - ClicUseVsMode : 0, - ClicUseVsModePrio : 0, - ClicNumVsCtxts : 0, NumExtIntrSyncs : 2, // Interconnect AddrWidth : 48, @@ -617,7 +589,6 @@ package cheshire_pkg; AxiUserErrBits : 0, AxiUserErrLsb : 0, AxiUserDefault : 0, - CorePostCut : 0, RegMaxReadTxns : 8, RegMaxWriteTxns : 8, AxiToRegCut : 0, @@ -640,10 +611,6 @@ package cheshire_pkg; Clic : 0, IrqRouter : 0, BusErr : 1, - HmrUnit : 1, - Cva6DMR : 1, - Cva6DMRFixed : 0, - RapidRecovery : 0, // Debug DbgIdCode : CheshireIdCode, DbgMaxReqs : 4, @@ -663,12 +630,6 @@ package cheshire_pkg; LlcOutConnect : 1, LlcOutRegionStart : 'h8000_0000, LlcOutRegionEnd : 'h1_0000_0000, - LlcUserMsb : 0, - LlcUserLsb : 0, - // LLC Partitioning - LlcCachePartition : 0, - LlcMaxPartition : 0, - LlcRemapHash : axi_llc_pkg::Modulo, // VGA: RGB332 VgaRedWidth : 3, VgaGreenWidth : 3, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index daf8bbeb..973d4366 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -340,7 +340,6 @@ module cheshire_soc import cheshire_pkg::*; #( .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), .RiscvWordWidth ( 64 ), .NAxiCuts ( Cfg.RegAmoNumCuts ), - .FullBandwidth ( 1 ), .axi_req_t ( axi_slv_req_t ), .axi_rsp_t ( axi_slv_rsp_t ) ) i_reg_atomics ( @@ -519,15 +518,10 @@ module cheshire_soc import cheshire_pkg::*; #( .SetAssociativity ( Cfg.LlcSetAssoc ), .NumLines ( Cfg.LlcNumLines ), .NumBlocks ( Cfg.LlcNumBlocks ), - .CachePartition ( Cfg.LlcCachePartition ), - .MaxPartition ( Cfg.LlcMaxPartition ), - .RemapHash ( Cfg.LlcRemapHash ), .AxiIdWidth ( AxiSlvIdWidth ), .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiUserIdMsb ( Cfg.LlcUserMsb ), - .AxiUserIdLsb ( Cfg.LlcUserLsb ), .slv_req_t ( axi_slv_req_t ), .slv_resp_t ( axi_slv_rsp_t ), .mst_req_t ( axi_ext_llc_req_t ), @@ -599,73 +593,50 @@ module cheshire_soc import cheshire_pkg::*; #( assign intr.intn.bus_err.cores = core_bus_err_intr_comb; - axi_mst_req_t [AxiIn.num_in-1:0] tagger_req; - axi_mst_rsp_t [AxiIn.num_in-1:0] tagger_rsp; - - axi_cva6_req_t [NumIntHarts-1:0] core_out_req, core_out_cut_req, core_ur_req; - axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp, core_out_cut_rsp, core_ur_rsp; - - // CLIC interface - logic [NumIntHarts-1:0] clic_irq_valid, clic_irq_ready; - logic [NumIntHarts-1:0] clic_irq_kill_req, clic_irq_kill_ack; - logic [NumIntHarts-1:0] clic_irq_shv; - logic [NumIntHarts-1:0] clic_irq_v; - logic [NumIntHarts-1:0] [$clog2(NumClicIntrs)-1:0] clic_irq_id; - logic [NumIntHarts-1:0] [7:0] clic_irq_level; - logic [NumIntHarts-1:0] [5:0] clic_irq_vsid; - riscv::priv_lvl_t [NumIntHarts-1:0] clic_irq_priv; - - reg_req_t reg_out_core_req; - reg_rsp_t reg_out_core_rsp; - - // Additional register intergace bus for the HMR unit configuration - if (Cfg.HmrUnit == 1) begin : gen_hmr_unit_reg_intf - assign reg_out_core_req = reg_out_req[RegOut.hmr_unit]; - assign reg_out_rsp[RegOut.hmr_unit] = reg_out_core_rsp; - end else begin : gen_no_hmr_unit_reg_intf - assign reg_out_core_req = '0; - end - - cva6_wrap #( - .Cfg ( Cfg ), - .Cva6Cfg ( Cva6Cfg ), - .NumHarts ( NumIntHarts ), - .reg_req_t ( reg_req_t ), - .reg_rsp_t ( reg_rsp_t ), - .axi_ar_chan_t ( axi_cva6_ar_chan_t ), - .axi_aw_chan_t ( axi_cva6_aw_chan_t ), - .axi_w_chan_t ( axi_cva6_w_chan_t ), - .b_chan_t ( axi_cva6_b_chan_t ), - .r_chan_t ( axi_cva6_r_chan_t ), - .axi_req_t ( axi_cva6_req_t ), - .axi_rsp_t ( axi_cva6_rsp_t ) - ) i_core_wrap ( - .clk_i ( clk_i ), - .rstn_i ( rst_ni ), - .bootaddress_i ( BootAddr ), - .hart_id_i ( '0 ), - .harts_sync_req_i ( reg_reg2hw.harts_sync.q ), - .irq_i ( xeip[NumIntHarts-1:0] ), - .ipi_i ( msip[NumIntHarts-1:0] ), - .time_irq_i ( mtip[NumIntHarts-1:0] ), - .debug_req_i ( dbg_int_req ), - .clic_irq_valid_i ( clic_irq_valid ), - .clic_irq_id_i ( clic_irq_id[NumIntHarts-1:0] ), - .clic_irq_level_i ( clic_irq_level[NumIntHarts-1:0] ), - .clic_irq_priv_i ( clic_irq_priv ), - .clic_irq_shv_i ( clic_irq_shv ), - .clic_irq_v_i ( clic_irq_v ), - .clic_irq_vsid_i ( clic_irq_vsid[NumIntHarts-1:0] ), - .clic_irq_ready_o ( clic_irq_ready ), - .clic_kill_req_i ( clic_irq_kill_req ), - .clic_kill_ack_o ( clic_irq_kill_ack ), - .reg_req_i ( reg_out_core_req ), - .reg_rsp_o ( reg_out_core_rsp ), - .axi_req_o ( core_out_req ), - .axi_rsp_i ( core_out_rsp ) - ); - - for (genvar i = 0; i < NumIntHarts; i++) begin : gen_core_surroundings + for (genvar i = 0; i < NumIntHarts; i++) begin : gen_cva6_cores + axi_cva6_req_t core_out_req, core_ur_req; + axi_cva6_rsp_t core_out_rsp, core_ur_rsp; + + // CLIC interface + logic clic_irq_valid, clic_irq_ready; + logic clic_irq_kill_req, clic_irq_kill_ack; + logic clic_irq_shv; + logic [$clog2(NumClicIntrs)-1:0] clic_irq_id; + logic [7:0] clic_irq_level; + riscv::priv_lvl_t clic_irq_priv; + + cva6 #( + .CVA6Cfg ( Cva6Cfg ), + .axi_ar_chan_t ( axi_cva6_ar_chan_t ), + .axi_aw_chan_t ( axi_cva6_aw_chan_t ), + .axi_w_chan_t ( axi_cva6_w_chan_t ), + .b_chan_t ( axi_cva6_b_chan_t ), + .r_chan_t ( axi_cva6_r_chan_t ), + .noc_req_t ( axi_cva6_req_t ), + .noc_resp_t ( axi_cva6_rsp_t ) + ) i_core_cva6 ( + .clk_i, + .rst_ni, + .boot_addr_i ( BootAddr ), + .hart_id_i ( 64'(i) ), + .irq_i ( xeip[i] ), + .ipi_i ( msip[i] ), + .time_irq_i ( mtip[i] ), + .debug_req_i ( dbg_int_req[i] ), + .clic_irq_valid_i ( clic_irq_valid ), + .clic_irq_id_i ( clic_irq_id ), + .clic_irq_level_i ( clic_irq_level ), + .clic_irq_priv_i ( clic_irq_priv ), + .clic_irq_shv_i ( clic_irq_shv ), + .clic_irq_ready_o ( clic_irq_ready ), + .clic_kill_req_i ( clic_irq_kill_req ), + .clic_kill_ack_o ( clic_irq_kill_ack ), + .rvfi_probes_o ( ), + .cvxif_req_o ( ), + .cvxif_resp_i ( '0 ), + .noc_req_o ( core_out_req ), + .noc_resp_i ( core_out_rsp ) + ); if (Cfg.BusErr) begin : gen_cva6_bus_err axi_err_unit_wrap #( @@ -683,9 +654,9 @@ module cheshire_soc import cheshire_pkg::*; #( ) i_cva6_bus_err ( .clk_i, .rst_ni, - .testmode_i ( test_mode_i ), - .axi_req_i ( core_out_req[i] ), - .axi_rsp_i ( core_out_rsp[i] ), + .testmode_i ( test_mode_i ), + .axi_req_i ( core_out_req ), + .axi_rsp_i ( core_out_rsp ), .err_irq_o ( core_bus_err_intr[i] ), .reg_req_i ( reg_out_req[RegOut.bus_err[RegBusErrCoresBase+i]] ), .reg_rsp_o ( reg_out_rsp[RegOut.bus_err[RegBusErrCoresBase+i]] ) @@ -714,71 +685,46 @@ module cheshire_soc import cheshire_pkg::*; #( .INTCTLBITS ( Cfg.ClicIntCtlBits ), .reg_req_t ( reg_req_t ), .reg_rsp_t ( reg_rsp_t ), - .SSCLIC ( Cfg.ClicUseSMode ), - .USCLIC ( Cfg.ClicUseUMode ), - .VSCLIC ( Cfg.ClicUseVsMode ), - .VSPRIO ( Cfg.ClicUseVsModePrio ), - .N_VSCTXTS ( Cfg.ClicNumVsCtxts ) + .SSCLIC ( 1 ), + .USCLIC ( 0 ) ) i_clic ( .clk_i, .rst_ni, .reg_req_i ( reg_out_req[RegOut.clic[i]] ), .reg_rsp_o ( reg_out_rsp[RegOut.clic[i]] ), - .intr_src_i ( clic_intr ), - .irq_valid_o ( clic_irq_valid[i] ), - .irq_ready_i ( clic_irq_ready[i] ), - .irq_id_o ( clic_irq_id[i] ), - .irq_level_o ( clic_irq_level[i] ), - .irq_shv_o ( clic_irq_shv[i] ), - .irq_priv_o ( clic_irq_priv[i] ), - .irq_v_o ( clic_irq_v[i] ), - .irq_vsid_o ( clic_irq_vsid[i] ), - .irq_kill_req_o ( clic_irq_kill_req[i] ), - .irq_kill_ack_i ( clic_irq_kill_ack[i] ) + .intr_src_i ( clic_intr ), + .irq_valid_o ( clic_irq_valid ), + .irq_ready_i ( clic_irq_ready ), + .irq_id_o ( clic_irq_id ), + .irq_level_o ( clic_irq_level ), + .irq_shv_o ( clic_irq_shv ), + .irq_priv_o ( clic_irq_priv ), + .irq_kill_req_o ( clic_irq_kill_req ), + .irq_kill_ack_i ( clic_irq_kill_ack ) ); end else begin : gen_no_clic - assign clic_irq_valid[i] = '0; - assign clic_irq_id[i] = '0; - assign clic_irq_level[i] = '0; - assign clic_irq_shv[i] = '0; - assign clic_irq_priv[i] = riscv::priv_lvl_t'(0); - assign clic_irq_v[i] = '0; - assign clic_irq_vsid[i] = '0; - assign clic_irq_kill_req[i] = '0; + assign clic_irq_valid = '0; + assign clic_irq_id = '0; + assign clic_irq_level = '0; + assign clic_irq_shv = '0; + assign clic_irq_priv = riscv::priv_lvl_t'(0); + assign clic_irq_kill_req = '0; end - axi_cut #( - .Bypass ( ~Cfg.CorePostCut ), - .aw_chan_t ( axi_cva6_aw_chan_t ), - .w_chan_t ( axi_cva6_w_chan_t ), - .b_chan_t ( axi_cva6_b_chan_t ), - .ar_chan_t ( axi_cva6_ar_chan_t ), - .r_chan_t ( axi_cva6_r_chan_t ), - .axi_req_t ( axi_cva6_req_t ), - .axi_resp_t ( axi_cva6_rsp_t ) - ) i_core_axi_cut ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( core_out_req[i] ), - .slv_resp_o ( core_out_rsp[i] ), - .mst_req_o ( core_out_cut_req[i] ), - .mst_resp_i ( core_out_cut_rsp[i] ) - ); - // Map user to AMO domain as we are an atomics-capable master. // Within the provided AMO user range, we count up from the provided core AMO offset. always_comb begin - core_ur_req[i] = core_out_cut_req[i]; - core_ur_req[i].aw.user = Cfg.AxiUserDefault; - core_ur_req[i].ar.user = Cfg.AxiUserDefault; - core_ur_req[i].w.user = Cfg.AxiUserDefault; - core_ur_req[i].aw.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; - core_ur_req[i].ar.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; - core_ur_req[i].w.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; - core_out_cut_rsp[i] = core_ur_rsp[i]; + core_ur_req = core_out_req; + core_ur_req.aw.user = Cfg.AxiUserDefault; + core_ur_req.ar.user = Cfg.AxiUserDefault; + core_ur_req.w.user = Cfg.AxiUserDefault; + core_ur_req.aw.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; + core_ur_req.ar.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; + core_ur_req.w.user [Cfg.AxiUserAmoMsb:Cfg.AxiUserAmoLsb] = Cfg.CoreUserAmoOffs + i; + core_out_rsp = core_ur_rsp; end // CVA6's ID encoding is wasteful; remap it statically pack into available bits @@ -802,38 +748,11 @@ module cheshire_soc import cheshire_pkg::*; #( ) i_axi_id_serialize ( .clk_i, .rst_ni, - .slv_req_i ( core_ur_req[i] ), - .slv_resp_o ( core_ur_rsp[i] ), - .mst_req_o ( tagger_req[i] ), - .mst_resp_i ( tagger_rsp[i] ) + .slv_req_i ( core_ur_req ), + .slv_resp_o ( core_ur_rsp ), + .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), + .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] ) ); - - if (Cfg.LlcCachePartition) begin : gen_tagger - tagger #( - .DATA_WIDTH ( Cfg.AxiDataWidth ), - .ADDR_WIDTH ( Cfg.AddrWidth ), - .MAXPARTITION ( Cfg.LlcMaxPartition ), - .AXI_USER_ID_MSB ( Cfg.LlcUserMsb ), - .AXI_USER_ID_LSB ( Cfg.LlcUserLsb ), - .TAGGER_GRAN ( 3 ), - .axi_req_t ( axi_mst_req_t ), - .axi_rsp_t ( axi_mst_rsp_t ), - .reg_req_t ( reg_req_t ), - .reg_rsp_t ( reg_rsp_t ) - ) i_tagger ( - .clk_i, - .rst_ni, - .slv_req_i ( tagger_req[i] ), - .slv_rsp_o ( tagger_rsp[i] ), - .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), - .mst_rsp_i ( axi_in_rsp[AxiIn.cores[i]] ), - .cfg_req_i ( reg_out_req[RegOut.tagger[i]] ), - .cfg_rsp_o ( reg_out_rsp[RegOut.tagger[i]] ) - ); - end else begin : gen_no_tagger - assign axi_in_req[AxiIn.cores[i]] = tagger_req[i]; - assign tagger_rsp[i] = axi_in_rsp[AxiIn.cores[i]]; - end end ///////////////////////// @@ -1072,7 +991,6 @@ module cheshire_soc import cheshire_pkg::*; #( ///////////////////// cheshire_reg_pkg::cheshire_hw2reg_t reg_hw2reg; - cheshire_reg_pkg::cheshire_reg2hw_t reg_reg2hw; assign reg_hw2reg = '{ boot_mode : boot_mode_i, @@ -1111,7 +1029,6 @@ module cheshire_soc import cheshire_pkg::*; #( .reg_req_i ( reg_out_req[RegOut.regs] ), .reg_rsp_o ( reg_out_rsp[RegOut.regs] ), .hw2reg ( reg_hw2reg ), - .reg2hw ( reg_reg2hw ), .devmode_i ( 1'b1 ) ); diff --git a/hw/regs/cheshire_reg_pkg.sv b/hw/regs/cheshire_reg_pkg.sv index bd43166c..e2a44ade 100644 --- a/hw/regs/cheshire_reg_pkg.sv +++ b/hw/regs/cheshire_reg_pkg.sv @@ -13,11 +13,6 @@ package cheshire_reg_pkg; // Typedefs for registers // //////////////////////////// - typedef struct packed { - logic [31:0] q; - logic qe; - } cheshire_reg2hw_harts_sync_reg_t; - typedef struct packed { logic [1:0] d; } cheshire_hw2reg_boot_mode_reg_t; @@ -92,11 +87,6 @@ package cheshire_reg_pkg; } blue_width; } cheshire_hw2reg_vga_params_reg_t; - // Register -> HW type - typedef struct packed { - cheshire_reg2hw_harts_sync_reg_t harts_sync; // [32:0] - } cheshire_reg2hw_t; - // HW -> register type typedef struct packed { cheshire_hw2reg_boot_mode_reg_t boot_mode; // [166:165] @@ -132,7 +122,6 @@ package cheshire_reg_pkg; parameter logic [BlockAw-1:0] CHESHIRE_HW_FEATURES_OFFSET = 7'h 50; parameter logic [BlockAw-1:0] CHESHIRE_LLC_SIZE_OFFSET = 7'h 54; parameter logic [BlockAw-1:0] CHESHIRE_VGA_PARAMS_OFFSET = 7'h 58; - parameter logic [BlockAw-1:0] CHESHIRE_HARTS_SYNC_OFFSET = 7'h 5c; // Reset values for hwext registers and their fields parameter logic [1:0] CHESHIRE_BOOT_MODE_RESVAL = 2'h 0; @@ -167,12 +156,11 @@ package cheshire_reg_pkg; CHESHIRE_NUM_INT_HARTS, CHESHIRE_HW_FEATURES, CHESHIRE_LLC_SIZE, - CHESHIRE_VGA_PARAMS, - CHESHIRE_HARTS_SYNC + CHESHIRE_VGA_PARAMS } cheshire_id_e; // Register width information to check illegal writes - parameter logic [3:0] CHESHIRE_PERMIT [24] = '{ + parameter logic [3:0] CHESHIRE_PERMIT [23] = '{ 4'b 1111, // index[ 0] CHESHIRE_SCRATCH_0 4'b 1111, // index[ 1] CHESHIRE_SCRATCH_1 4'b 1111, // index[ 2] CHESHIRE_SCRATCH_2 @@ -195,8 +183,7 @@ package cheshire_reg_pkg; 4'b 1111, // index[19] CHESHIRE_NUM_INT_HARTS 4'b 0011, // index[20] CHESHIRE_HW_FEATURES 4'b 1111, // index[21] CHESHIRE_LLC_SIZE - 4'b 0111, // index[22] CHESHIRE_VGA_PARAMS - 4'b 1111 // index[23] CHESHIRE_HARTS_SYNC + 4'b 0111 // index[22] CHESHIRE_VGA_PARAMS }; endpackage diff --git a/hw/regs/cheshire_reg_top.sv b/hw/regs/cheshire_reg_top.sv index e39fe687..bd9f2e27 100644 --- a/hw/regs/cheshire_reg_top.sv +++ b/hw/regs/cheshire_reg_top.sv @@ -17,7 +17,6 @@ module cheshire_reg_top #( input reg_req_t reg_req_i, output reg_rsp_t reg_rsp_o, // To HW - output cheshire_reg_pkg::cheshire_reg2hw_t reg2hw, // Write input cheshire_reg_pkg::cheshire_hw2reg_t hw2reg, // Read @@ -158,9 +157,6 @@ module cheshire_reg_top #( logic vga_params_green_width_re; logic [7:0] vga_params_blue_width_qs; logic vga_params_blue_width_re; - logic [31:0] harts_sync_qs; - logic [31:0] harts_sync_wd; - logic harts_sync_we; // Register instances @@ -921,36 +917,9 @@ module cheshire_reg_top #( ); - // R[harts_sync]: V(False) - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_harts_sync ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (harts_sync_we), - .wd (harts_sync_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - // to internal hardware - .qe (reg2hw.harts_sync.qe), - .q (reg2hw.harts_sync.q ), - - // to register interface (read) - .qs (harts_sync_qs) - ); - - - - - logic [23:0] addr_hit; + logic [22:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CHESHIRE_SCRATCH_0_OFFSET); @@ -976,7 +945,6 @@ module cheshire_reg_top #( addr_hit[20] = (reg_addr == CHESHIRE_HW_FEATURES_OFFSET); addr_hit[21] = (reg_addr == CHESHIRE_LLC_SIZE_OFFSET); addr_hit[22] = (reg_addr == CHESHIRE_VGA_PARAMS_OFFSET); - addr_hit[23] = (reg_addr == CHESHIRE_HARTS_SYNC_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1006,8 +974,7 @@ module cheshire_reg_top #( (addr_hit[19] & (|(CHESHIRE_PERMIT[19] & ~reg_be))) | (addr_hit[20] & (|(CHESHIRE_PERMIT[20] & ~reg_be))) | (addr_hit[21] & (|(CHESHIRE_PERMIT[21] & ~reg_be))) | - (addr_hit[22] & (|(CHESHIRE_PERMIT[22] & ~reg_be))) | - (addr_hit[23] & (|(CHESHIRE_PERMIT[23] & ~reg_be))))); + (addr_hit[22] & (|(CHESHIRE_PERMIT[22] & ~reg_be))))); end assign scratch_0_we = addr_hit[0] & reg_we & !reg_error; @@ -1100,9 +1067,6 @@ module cheshire_reg_top #( assign vga_params_blue_width_re = addr_hit[22] & reg_re & !reg_error; - assign harts_sync_we = addr_hit[23] & reg_we & !reg_error; - assign harts_sync_wd = reg_wdata[31:0]; - // Read data return always_comb begin reg_rdata_next = '0; @@ -1213,10 +1177,6 @@ module cheshire_reg_top #( reg_rdata_next[23:16] = vga_params_blue_width_qs; end - addr_hit[23]: begin - reg_rdata_next[31:0] = harts_sync_qs; - end - default: begin reg_rdata_next = '1; end @@ -1246,7 +1206,6 @@ module cheshire_reg_top_intf input logic rst_ni, REG_BUS.in regbus_slave, // To HW - output cheshire_reg_pkg::cheshire_reg2hw_t reg2hw, // Write input cheshire_reg_pkg::cheshire_hw2reg_t hw2reg, // Read // Config input devmode_i // If 1, explicit error return for unmapped register access @@ -1280,7 +1239,6 @@ module cheshire_reg_top_intf .rst_ni, .reg_req_i(s_reg_req), .reg_rsp_o(s_reg_rsp), - .reg2hw, // Write .hw2reg, // Read .devmode_i ); diff --git a/hw/regs/cheshire_regs.hjson b/hw/regs/cheshire_regs.hjson index 364dd45e..42091a40 100644 --- a/hw/regs/cheshire_regs.hjson +++ b/hw/regs/cheshire_regs.hjson @@ -131,14 +131,5 @@ ] } - { name: "harts_sync" - desc: "Available harts' synchronization request." - swaccess: "rw" - hwaccess: "hro" - hwqe: "true" - fields: [ - { bits: "31:0", name: "hart_sync", desc: "Harts sync request." } - ] - } ] -} +} \ No newline at end of file diff --git a/sw/include/cheshire_io.h b/sw/include/cheshire_io.h deleted file mode 100644 index ab1e8cc6..00000000 --- a/sw/include/cheshire_io.h +++ /dev/null @@ -1,11 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "regs/cheshire.h" -#include "dif/clint.h" -#include "dif/uart.h" -#include "util.h" -#include "params.h" - -void cheshire_init_io(); diff --git a/sw/include/init.h b/sw/include/init.h deleted file mode 100644 index fbbc7a60..00000000 --- a/sw/include/init.h +++ /dev/null @@ -1,7 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "cheshire_io.h" - -void soc_init(); diff --git a/sw/include/params.h b/sw/include/params.h index 0af5e9b6..5477689e 100644 --- a/sw/include/params.h +++ b/sw/include/params.h @@ -23,7 +23,6 @@ extern void *__base_gpio; extern void *__base_slink; extern void *__base_vga; extern void *__base_clint; -extern void *__base_hmr; extern void *__base_plic; extern void *__base_dma; extern void *__base_axirt; diff --git a/sw/include/regs/axi_llc.h b/sw/include/regs/axi_llc.h index a1b6f589..79a2c7c4 100644 --- a/sw/include/regs/axi_llc.h +++ b/sw/include/regs/axi_llc.h @@ -72,74 +72,6 @@ extern "C" { #define AXI_LLC_BIST_STATUS_REG_OFFSET 0x48 #define AXI_LLC_BIST_STATUS_DONE_BIT 0 -// Index-based Partition Flush Configuration [31:0] (lower 32 bit) -#define AXI_LLC_CFG_FLUSH_PARTITION_LOW_REG_OFFSET 0x4c - -// Index-based Partition Flush Configuration [63:32] (upper 32 bit) -#define AXI_LLC_CFG_FLUSH_PARTITION_HIGH_REG_OFFSET 0x50 - -// Index-based Partition Configuration [31:0] (lower 32 bit) (common -// parameters) -#define AXI_LLC_CFG_SET_PARTITION_LOW_LOW_FIELD_WIDTH 32 -#define AXI_LLC_CFG_SET_PARTITION_LOW_LOW_FIELDS_PER_REG 1 -#define AXI_LLC_CFG_SET_PARTITION_LOW_MULTIREG_COUNT 2 - -// Index-based Partition Configuration [31:0] (lower 32 bit) -#define AXI_LLC_CFG_SET_PARTITION_LOW_0_REG_OFFSET 0x54 - -// Index-based Partition Configuration [31:0] (lower 32 bit) -#define AXI_LLC_CFG_SET_PARTITION_LOW_1_REG_OFFSET 0x58 - -// Index-based Partition Configuration [63:32] (higher 32 bit) (common -// parameters) -#define AXI_LLC_CFG_SET_PARTITION_HIGH_HIGH_FIELD_WIDTH 32 -#define AXI_LLC_CFG_SET_PARTITION_HIGH_HIGH_FIELDS_PER_REG 1 -#define AXI_LLC_CFG_SET_PARTITION_HIGH_MULTIREG_COUNT 2 - -// Index-based Partition Configuration [63:32] (higher 32 bit) -#define AXI_LLC_CFG_SET_PARTITION_HIGH_0_REG_OFFSET 0x5c - -// Index-based Partition Configuration [63:32] (higher 32 bit) -#define AXI_LLC_CFG_SET_PARTITION_HIGH_1_REG_OFFSET 0x60 - -// Commit the set partition configuration -#define AXI_LLC_COMMIT_PARTITION_CFG_REG_OFFSET 0x64 -#define AXI_LLC_COMMIT_PARTITION_CFG_COMMIT_BIT 0 - -// Index-based Flushed Flag (lower 32 bit) (common parameters) -#define AXI_LLC_FLUSHED_SET_LOW_LOW_FIELD_WIDTH 32 -#define AXI_LLC_FLUSHED_SET_LOW_LOW_FIELDS_PER_REG 1 -#define AXI_LLC_FLUSHED_SET_LOW_MULTIREG_COUNT 4 - -// Index-based Flushed Flag (lower 32 bit) -#define AXI_LLC_FLUSHED_SET_LOW_0_REG_OFFSET 0x6c - -// Index-based Flushed Flag (lower 32 bit) -#define AXI_LLC_FLUSHED_SET_LOW_1_REG_OFFSET 0x70 - -// Index-based Flushed Flag (lower 32 bit) -#define AXI_LLC_FLUSHED_SET_LOW_2_REG_OFFSET 0x74 - -// Index-based Flushed Flag (lower 32 bit) -#define AXI_LLC_FLUSHED_SET_LOW_3_REG_OFFSET 0x78 - -// Index-based Flushed Flag (upper 32 bit) (common parameters) -#define AXI_LLC_FLUSHED_SET_HIGH_HIGH_FIELD_WIDTH 32 -#define AXI_LLC_FLUSHED_SET_HIGH_HIGH_FIELDS_PER_REG 1 -#define AXI_LLC_FLUSHED_SET_HIGH_MULTIREG_COUNT 4 - -// Index-based Flushed Flag (upper 32 bit) -#define AXI_LLC_FLUSHED_SET_HIGH_0_REG_OFFSET 0x7c - -// Index-based Flushed Flag (upper 32 bit) -#define AXI_LLC_FLUSHED_SET_HIGH_1_REG_OFFSET 0x80 - -// Index-based Flushed Flag (upper 32 bit) -#define AXI_LLC_FLUSHED_SET_HIGH_2_REG_OFFSET 0x84 - -// Index-based Flushed Flag (upper 32 bit) -#define AXI_LLC_FLUSHED_SET_HIGH_3_REG_OFFSET 0x88 - #ifdef __cplusplus } // extern "C" #endif diff --git a/sw/include/regs/cheshire.h b/sw/include/regs/cheshire.h index 0483f2b5..542d621e 100644 --- a/sw/include/regs/cheshire.h +++ b/sw/include/regs/cheshire.h @@ -123,9 +123,6 @@ extern "C" { #define CHESHIRE_VGA_PARAMS_BLUE_WIDTH_FIELD \ ((bitfield_field32_t) { .mask = CHESHIRE_VGA_PARAMS_BLUE_WIDTH_MASK, .index = CHESHIRE_VGA_PARAMS_BLUE_WIDTH_OFFSET }) -// Available harts' synchronization request. -#define CHESHIRE_HARTS_SYNC_REG_OFFSET 0x5c - #ifdef __cplusplus } // extern "C" #endif diff --git a/sw/lib/cheshire_io.c b/sw/lib/cheshire_io.c deleted file mode 100644 index 1d723032..00000000 --- a/sw/lib/cheshire_io.c +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Yvan Tortorella -// -// Library containing IO init/close functions. - -#include "cheshire_io.h" - -void cheshire_init_io() { - // Initialize UART first - uart_open(); - - // Initialize other IOs - // . - // . - // . -}; diff --git a/sw/lib/crt0.S b/sw/lib/crt0.S index 073fc181..1f9e0de2 100644 --- a/sw/lib/crt0.S +++ b/sw/lib/crt0.S @@ -15,10 +15,8 @@ _start: csrrc x0, mstatus, 10 // Park SMP harts - // csrr t0, mhartid - // beqz t0, 2f - // All harts continue. - beq t0, t0, 2f + csrr t0, mhartid + beqz t0, 2f 1: wfi j 1b @@ -112,18 +110,8 @@ _fp_init: // Set FS state to "Clean" csrrc x0, mstatus, t1 - // Non SMP Hart initializes the SoC - // SMP Harts jump to main - csrr t0, mhartid - beqz t0, _soc_init - j _program_start - -_soc_init: - // Init SoC, than jump to main - jal x1, soc_init -_program_start: - // Full fence, then go to main + // Full fence, then jump to main fence call main @@ -188,4 +176,4 @@ _trap_handler_wrap: .global trap_vector .weak trap_vector trap_vector: - j trap_vector + j trap_vector \ No newline at end of file diff --git a/sw/lib/init.c b/sw/lib/init.c deleted file mode 100644 index a0f5dc02..00000000 --- a/sw/lib/init.c +++ /dev/null @@ -1,14 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Yvan Tortorella -// -// Library containing general SoC init/close functions. - -#include "init.h" - -void soc_init() { - // IO initialization - cheshire_init_io(); -}; diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index c8aada3d..27a5ef11 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -128,7 +128,7 @@ module fixture_cheshire_soc #( .i2c_scl_o ( i2c_scl_o ), .i2c_scl_i ( i2c_scl_i ), .i2c_scl_en_o ( i2c_scl_en ), - .eth_clk_i ( eth_clk_125 ), + .eth_clk125_i ( eth_clk_125 ), .eth_rxck_i ( eth_rxck ), .eth_rxd_i ( eth_rxd ), .eth_rxctl_i ( eth_rxctl ), From 6a47f103c1f9cde22b25e966d9fac50d27f215a7 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sun, 19 May 2024 00:41:06 +0200 Subject: [PATCH 23/48] external clks --- Bender.lock | 2 +- Bender.yml | 4 ++-- hw/cheshire_soc.sv | 4 +++- target/sim/src/fixture_cheshire_soc.sv | 6 ++++-- target/sim/src/vip_cheshire_soc.sv | 27 +++++++++++++++++++------- 5 files changed, 30 insertions(+), 13 deletions(-) diff --git a/Bender.lock b/Bender.lock index 3da77531..ef8a4a6d 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: bf5fc0055a4d3258361e38ee977566fa312570f0 + revision: 28fd13f7887c9bf0e9548b56a8706378c9cc01cd version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 32c29e56..71f1f2af 100644 --- a/Bender.yml +++ b/Bender.yml @@ -23,14 +23,14 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 } - iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.6.2 } + iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.6.0 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "bf5fc00" } # branch: cl/eth_idma + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "28fd13f" } # branch: cl/eth_idma export_include_dirs: - hw/include diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 973d4366..cfccb3b4 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -29,6 +29,7 @@ module cheshire_soc import cheshire_pkg::*; #( input logic [1:0] boot_mode_i, input logic rtc_i, input logic eth_clk125_i, + input logic eth_clk125q_i, input logic eth_clk200_i, // External AXI LLC (DRAM) port output axi_ext_llc_req_t axi_llc_mst_req_o, @@ -1312,7 +1313,8 @@ module cheshire_soc import cheshire_pkg::*; #( ) i_tx_eth_idma_wrap ( .clk_i, .rst_ni, - .eth_clk_i ( eth_clk125_i ), + .eth_clk125_i ( eth_clk125_i ), + .eth_clk125q_i ( eth_clk125q_i), .eth_clk200_i ( eth_clk200_i ), .phy_rx_clk_i ( eth_rxck_i ), .phy_rxd_i ( eth_rxd_i ), diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 27a5ef11..8124f494 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -49,7 +49,8 @@ module fixture_cheshire_soc #( logic i2c_scl_i; logic i2c_scl_en; - logic eth_clk_125; + logic eth_clk125; + logic eth_clk125q; logic eth_rxck; logic [3:0] eth_rxd; logic eth_rxctl; @@ -128,7 +129,8 @@ module fixture_cheshire_soc #( .i2c_scl_o ( i2c_scl_o ), .i2c_scl_i ( i2c_scl_i ), .i2c_scl_en_o ( i2c_scl_en ), - .eth_clk125_i ( eth_clk_125 ), + .eth_clk125_i ( eth_clk125 ), + .eth_clk125q_i ( eth_clk125q ), .eth_rxck_i ( eth_rxck ), .eth_rxd_i ( eth_rxd ), .eth_rxctl_i ( eth_rxctl ), diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 823e5bee..76685f5f 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -21,7 +21,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( parameter time ClkPeriodSys = 5ns, parameter time ClkPeriodJtag = 20ns, parameter time ClkPeriodRtc = 30518ns, - parameter time ClkPeriodEth125 = 8ns, + parameter time ClkPeriodEth = 8ns, parameter int unsigned RstCycles = 5, parameter real TAppl = 0.1, parameter real TTest = 0.9, @@ -70,7 +70,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( inout wire [SpihNumCs-1:0] spih_csb, inout wire [ 3:0] spih_sd, // Ethernet interface - output logic eth_clk_125, + output logic eth_clk125, + output logic eth_clk125q, input logic [ 3:0] eth_txd, output logic [ 3:0] eth_rxd, input logic eth_txck, @@ -653,7 +654,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( ) i_rx_eth_idma_wrap ( .clk_i ( clk ), .rst_ni ( rst_n ), - .eth_clk_i ( eth_clk_125 ), + .eth_clk125_i ( eth_clk125 ), + .eth_clk125q_i ( eth_clk125q ), .phy_rx_clk_i ( eth_txck ), .phy_rxd_i ( eth_txd ), .phy_rx_ctl_i ( eth_txctl ), @@ -709,10 +711,21 @@ module vip_cheshire_soc import cheshire_pkg::*; #( initial begin forever begin - eth_clk_125 <= 0; - #(ClkPeriodEth125/2); - eth_clk_125 <= 1; - #(ClkPeriodEth125/2); + eth_clk125 <= 1; + #(ClkPeriodEth/2); + eth_clk125 <= 0; + #(ClkPeriodEth/2); + end + end + + initial begin + forever begin + eth_clk125q <= 0; + #(ClkPeriodEth/4); + eth_clk125q <= 1; + #(ClkPeriodEth/2); + eth_clk125q <= 0; + #(ClkPeriodEth/4); end end From 7a809f2f1ac63bb710f5587c2d03143d90cd02fd Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sun, 19 May 2024 00:50:16 +0200 Subject: [PATCH 24/48] xilinx fix --- target/xilinx/constraints/genesys2.xdc | 30 ++++++++++++++++++++++++ target/xilinx/src/cheshire_top_xilinx.sv | 8 ++++--- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index 18debabc..8ee87fb4 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -126,6 +126,36 @@ set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_i set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk_o }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk +# Ethernet +set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0] +set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1] +set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2] +set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3] +set_property -dict {PACKAGE_PIN A26 IOSTANDARD LVCMOS18} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk +set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0] +set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1] +set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2] +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3] +set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS18} [get_ports { eth_txctl }]; #IO_L20P_T3_33 Sch=eth_tx_en +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk +set_property -dict {PACKAGE_PIN C27 IOSTANDARD LVCMOS18} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc +#set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb +#set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb +set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n + +############################################# +# Ethernet Constraints for 1Gb/s +############################################# +# Modified for 125MHz receive clock +create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_rxck_IBUF] + +set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_clkwiz/clk_125]] + + # VGA Connector set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 3fc87696..3908af9e 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -125,6 +125,7 @@ module cheshire_top_xilinx ( wire soc_clk; logic eth_clk_125; logic eth_clk_90; + logic eth_clk_200; IBUFDS #( .IBUF_LOW_PWR ("FALSE") @@ -138,7 +139,7 @@ module cheshire_top_xilinx ( .clk_in1 ( sys_clk ), .reset ( '0 ), .locked ( ), - .clk_200 ( ), + .clk_200 ( eth_clk_200 ), .clk_50 ( soc_clk ), .clk_125 ( eth_clk_125 ), .clk_125_90 ( eth_clk_90 ) @@ -485,8 +486,9 @@ module cheshire_top_xilinx ( .i2c_scl_o ( i2c_scl_soc_out ), .i2c_scl_i ( i2c_scl_soc_in ), .i2c_scl_en_o ( i2c_scl_en ), - .eth_clk_125 ( eth_clk_125 ), - .eth_clk_90 ( eth_clk_90 ), + .eth_clk125_i ( eth_clk_125 ), + .eth_clk125q_i ( eth_clk_90 ), + .eth_clk200_i ( eth_clk_200 ), .eth_rxck_i ( eth_rxck ), .eth_rxd_i ( eth_rxd ), .eth_rxctl_i ( eth_rxctl ), From 903658b972109a996e244bd460a2aed6ed24d02e Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 21 May 2024 18:56:33 +0200 Subject: [PATCH 25/48] fix constraints --- target/xilinx/constraints/genesys2.xdc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index 8ee87fb4..e5bf3098 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -14,6 +14,8 @@ # 200 MHz input clock set SYS_TCK 5 create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clk] + # SoC clock is generated by clock wizard and its constraints set SOC_TCK 20.0 @@ -54,6 +56,9 @@ set MIG_RST_O [get_pins i_dram_wrapper/i_dram/ui_clk_sync_rst] set_false_path -hold -through $MIG_RST_O set_max_delay -through $MIG_RST_O $MIG_TCK +set_false_path -from [get_pins i_vio/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/Probe_out_reg[*]/C] -to [get_pins i_dram_wrapper/i_dram/u_mig7s_mig/u_ddr3_infrastructure/rstdiv0_sync_r*_reg_rep__*/PRE] + + # Limit delay across DRAM CDC (hold already false-pathed) set_max_delay -datapath_only \ -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ @@ -104,14 +109,15 @@ set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_cl set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { sys_resetn }]; #IO_0_14 Sch=cpu_resetn ## Switches -set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[0] }]; #IO_0_17 Sch=sw[0] -set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[1] }]; #IO_25_16 Sch=sw[1] -set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[0] }]; #IO_L19P_T3_16 Sch=sw[2] -set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[1] }]; #IO_L6P_T0_17 Sch=sw[3] -set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] -set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] +set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS18 } [get_ports { boot_mode_i[0] }]; #IO_0_17 Sch=sw[0] +set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS18 } [get_ports { boot_mode_i[1] }]; #IO_25_16 Sch=sw[1] +set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS18 } [get_ports { fan_sw[0] }]; #IO_L19P_T3_16 Sch=sw[2] +set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS18 } [get_ports { fan_sw[1] }]; #IO_L6P_T0_17 Sch=sw[3] +set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS18 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] +set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS18 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { test_mode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] + # UART set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L1P_T0_12 Sch=uart_rx_out set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_0_12 Sch=uart_tx_in From 7c9a8733704adefd6b1d0d16607769a9e488047b Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 18 Jun 2024 16:52:06 +0200 Subject: [PATCH 26/48] chs eth with rx irq --- Bender.lock | 2 +- Bender.yml | 2 +- hw/cheshire_soc.sv | 3 +++ sw/tests/ethernet.c | 40 +++++++++++++++--------------- target/sim/src/vip_cheshire_soc.sv | 12 ++++++--- 5 files changed, 33 insertions(+), 26 deletions(-) diff --git a/Bender.lock b/Bender.lock index ef8a4a6d..997eb417 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 28fd13f7887c9bf0e9548b56a8706378c9cc01cd + revision: cd99b5eda5f2fa7a3a5d3bad78f207f618fd9ded version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 71f1f2af..3426d684 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "28fd13f" } # branch: cl/eth_idma + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "cd99b5e" } # branch: cl/chs-driver export_include_dirs: - hw/include diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index cfccb3b4..4ae10715 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1340,6 +1340,9 @@ module cheshire_soc import cheshire_pkg::*; #( end else begin : gen_no_ethernet assign intr.intn.ethernet = 1'b0; assign eth_txck_o = 1'b0; + assign eth_rstn_o = 1'b0; + assign eth_txctl_o = 1'b0; + assign eth_txd_o = 4'b0; end //////////////// diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 80b9b709..890c0970 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -40,38 +40,38 @@ int main(void) { *reg32(PLIC_BASE, RV_PLIC_PRIO19_REG_OFFSET) = 1; *reg32(PLIC_BASE, RV_PLIC_IE0_0_REG_OFFSET) |= (1 << (RV_PLIC_IE0_0_E_19_BIT)); // Enable interrupt number ; - volatile uint64_t data_to_write[8] = { - 0x1032207098001032, - 0x3210E20020709800, - 0x1716151413121110, - 0x2726252423222120, - 0x3736353433323130, - 0x4746454443424140, - 0x5756555453525150, - 0x6766656463626160 - }; + // volatile uint64_t data_to_write[8] = { + // 0x1032207098001032, + // 0x3210E20020709800, + // 0x1716151413121110, + // 0x2726252423222120, + // 0x3736353433323130, + // 0x4746454443424140, + // 0x5756555453525150, + // 0x6766656463626160 + // }; + + // // load data into mem + // for (int i = 0; i < 8; ++i) { + // volatile uint64_t *tx_addr = (volatile uint64_t*)(0x14000000 + i * sizeof(uint64_t)); + // *tx_addr = data_to_write[i]; + // } + + while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); - // load data into mem - for (int i = 0; i < 8; ++i) { - volatile uint64_t *tx_addr = (volatile uint64_t*)(0x14000000 + i * sizeof(uint64_t)); - *tx_addr = data_to_write[i]; - } - *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x14000000; *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = 0x40; - *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x0; - *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x5; + *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x5; + *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1; - while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); - printf ("Ethernet test pass...\n\r"); return 0; } diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 76685f5f..12079d3b 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -731,7 +731,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( initial begin @(posedge clk); - $readmemh("rx_mem_init.vmem", i_rx_axi_sim_mem.mem); + $readmemh("eth_frame.vmem", i_rx_axi_sim_mem.mem); @(posedge clk); reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address @@ -749,16 +749,20 @@ module vip_cheshire_soc import cheshire_pkg::*; #( reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes @(posedge clk); - reg_drv_rx.send_write( 'h0300c020, 32'h5,'hf , reg_error); // src protocol + reg_drv_rx.send_write( 'h0300c020, 32'h0,'hf , reg_error); // src protocol @(posedge clk); - reg_drv_rx.send_write( 'h0300c024, 32'h0,'hf , reg_error); // dst protocol + reg_drv_rx.send_write( 'h0300c024, 32'h5,'hf , reg_error); // dst protocol @(posedge clk); reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid @(posedge clk); - reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf, reg_error); + reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf, reg_error); // rsp ready + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid + @(posedge clk); while(1) begin reg_drv_rx.send_read( 'h0300c048, rx_rsp_valid, reg_error); From 0dc7d2a5727b8278fc29c63a6f68da80eb2c456b Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 19 Jun 2024 17:45:19 +0200 Subject: [PATCH 27/48] eth mdio_i --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 997eb417..bc65749d 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: cd99b5eda5f2fa7a3a5d3bad78f207f618fd9ded + revision: 300b4fd21740f37e5f44102d5b828eba7277f6c9 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 3426d684..4e9ba4b1 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "cd99b5e" } # branch: cl/chs-driver + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "300b4fd" } # branch: cl/chs-driver export_include_dirs: - hw/include From 9a17a02c20433917de38b5a22518f6466451b2ac Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sun, 7 Jul 2024 18:41:14 +0200 Subject: [PATCH 28/48] add hardcoded dma contrl signals --- Bender.lock | 10 +- Bender.yml | 2 +- hw/cheshire_soc.sv | 17 +++- sw/tests/ethernet.c | 83 +++++++++++----- target/sim/src/vip_cheshire_soc.sv | 128 +++++++++++++------------ target/sim/vsim/start.cheshire_soc.tcl | 2 +- 6 files changed, 147 insertions(+), 95 deletions(-) diff --git a/Bender.lock b/Bender.lock index bc65749d..237afb75 100644 --- a/Bender.lock +++ b/Bender.lock @@ -44,8 +44,8 @@ packages: - common_cells - common_verification axi_rt: - revision: 56074a195b1c8b05f4bdd73674e437bbcb35f2cd - version: 0.0.0-alpha.7 + revision: d5f857e74d0a5db4e4a2cc3652ca4f40f29a1484 + version: 0.0.0-alpha.8 source: Git: https://github.com/pulp-platform/axi_rt.git dependencies: @@ -124,8 +124,8 @@ packages: dependencies: - common_cells idma: - revision: 95f366e56f7e772c283fb3c8b343afc4a3978375 - version: 0.6.2 + revision: c12caf59bb482fe44b27361f6924ad346b2d22fe + version: 0.6.3 source: Git: https://github.com/pulp-platform/iDMA.git dependencies: @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 300b4fd21740f37e5f44102d5b828eba7277f6c9 + revision: f01aacf5746751d57f0b8340f21756791fd3a2aa version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 4e9ba4b1..d683708d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "300b4fd" } # branch: cl/chs-driver + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "f01aacf" } # branch: chs-hs export_include_dirs: - hw/include diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 4ae10715..824f4546 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1306,6 +1306,12 @@ module cheshire_soc import cheshire_pkg::*; #( .AddrWidth ( Cfg.AddrWidth ), .UserWidth ( Cfg.AxiUserWidth ), .AxiIdWidth ( Cfg.AxiMstIdWidth ), + .NumAxInFlight ( 32'd15 ), + .BufferDepth ( 32'd2 ), + .TFLenWidth ( 32'd20 ), + .MemSysDepth ( 32'd0 ), + .TxFifoLogDepth ( 32'd2 ), + .RxFifoLogDepth ( 32'd3 ), .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), .reg_req_t ( reg_req_t ), @@ -1334,15 +1340,18 @@ module cheshire_soc import cheshire_pkg::*; #( .axi_rsp_i ( axi_in_rsp[AxiIn.eth] ), .reg_req_i ( reg_out_req[RegOut.ethernet] ), .reg_rsp_o ( reg_out_rsp[RegOut.ethernet] ), - .eth_irq_o ( intr.intn.ethernet ) + .eth_rx_irq_o ( intr.intn.ethernet ) ); end else begin : gen_no_ethernet assign intr.intn.ethernet = 1'b0; - assign eth_txck_o = 1'b0; - assign eth_rstn_o = 1'b0; + assign eth_txck_o = 1'b0; + assign eth_rstn_o = 1'b0; assign eth_txctl_o = 1'b0; - assign eth_txd_o = 4'b0; + assign eth_txd_o = 4'b0; + assign eth_mdio_o = '0; + assign eth_mdio_oe = '0; + assign eth_mdc_o = '0; end //////////////// diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 890c0970..be23e820 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -4,7 +4,7 @@ #include "printf.h" #include "util.h" -#define ETH_BASE 0x0300c000 +#define ETH_BASE 0x0300c000 #define MACLO_OFFSET 0x0 #define MACHI_OFFSET 0x4 @@ -29,6 +29,13 @@ #define RV_PLIC_IP_0_OFFSET 0x1000 +#define DATA_CHUNK 8 + +#define BYTE_SIZE 8 + +#define TX_BASE 0x14000000 +#define RX_BASE 0x14001000 + #define PRINTF_ON int main(void) { @@ -40,39 +47,65 @@ int main(void) { *reg32(PLIC_BASE, RV_PLIC_PRIO19_REG_OFFSET) = 1; *reg32(PLIC_BASE, RV_PLIC_IE0_0_REG_OFFSET) |= (1 << (RV_PLIC_IE0_0_E_19_BIT)); // Enable interrupt number ; - // volatile uint64_t data_to_write[8] = { - // 0x1032207098001032, - // 0x3210E20020709800, - // 0x1716151413121110, - // 0x2726252423222120, - // 0x3736353433323130, - // 0x4746454443424140, - // 0x5756555453525150, - // 0x6766656463626160 - // }; - - // // load data into mem - // for (int i = 0; i < 8; ++i) { - // volatile uint64_t *tx_addr = (volatile uint64_t*)(0x14000000 + i * sizeof(uint64_t)); - // *tx_addr = data_to_write[i]; - // } + volatile uint64_t data_to_write[DATA_CHUNK] = { + 0x1032207098001032, + 0x3210E20020709800, + 0x1716151413121110, + 0x2726252423222120, + 0x3736353433323130, + 0x4746454443424140, + 0x5756555453525150, + 0x6766656463626160 + }; + + // load data into mem + for (int i = 0; i < DATA_CHUNK; ++i) { + volatile uint64_t *tx_addr = (volatile uint64_t*)(TX_BASE + i * sizeof(uint64_t)); + *tx_addr = data_to_write[i]; + } + + *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; + // High 16 bit Mac Address + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00002070; + // DMA Source Address + *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = TX_BASE; + // DMA Destination Address + *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = 0x0; + // Data length + *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; + // Source Protocol + *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; + // Destination Protocol + *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x5; + // Validate Request to DMA + *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; + + // rx irq while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; - *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x14000000; - *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = 0x0; - *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = 0x40; + *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x0; + *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = RX_BASE; + *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x5; *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; - *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; - *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; - *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1; - printf ("Ethernet test pass...\n\r"); - return 0; + // wait until DMA moves all data + while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET))); + + uint32_t error = 0; + + for (int i = 0; i < DATA_CHUNK; ++i) { + volatile uint64_t *rx_addr = (volatile uint64_t*)(RX_BASE + i * sizeof(uint64_t)); + uint64_t data_read = *rx_addr; + + if (data_read != data_to_write[i]) error ++; + } + + return error; } diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 12079d3b..6794d263 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -616,8 +616,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( typedef reg_test::reg_driver #( .AW(REG_BUS_AW), .DW(REG_BUS_DW), - .TT(ClkPeriodJtag * TTest), - .TA(ClkPeriodJtag * TAppl) + .TT(ClkPeriodSys * TTest), + .TA(ClkPeriodSys * TAppl) ) reg_bus_drv_t; REG_BUS #( @@ -627,8 +627,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .clk_i(clk) ); - logic reg_error; - logic [REG_BUS_DW-1:0] rx_req_ready, rx_rsp_valid; + logic reg_error, eth_rx_irq; + logic [REG_BUS_DW-1:0] rx_rsp_valid; reg_bus_drv_t reg_drv_rx = new(reg_bus_rx); @@ -640,13 +640,18 @@ module vip_cheshire_soc import cheshire_pkg::*; #( axi_mst_req_t axi_req_mem; axi_mst_rsp_t axi_rsp_mem; - idma_pkg::idma_busy_t idma_busy_o; eth_idma_wrap#( .DataWidth ( DutCfg.AxiDataWidth ), .AddrWidth ( DutCfg.AddrWidth ), .UserWidth ( DutCfg.AxiUserWidth ), .AxiIdWidth ( DutCfg.AxiMstIdWidth ), + .NumAxInFlight ( 32'd15 ), + .BufferDepth ( 32'd2 ), + .TFLenWidth ( 32'd20 ), + .MemSysDepth ( 32'd0 ), + .TxFifoLogDepth ( 32'd2 ), + .RxFifoLogDepth ( 32'd3 ), .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), .reg_req_t ( reg_req_t ), @@ -674,7 +679,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .testmode_i ( 1'b0 ), .axi_req_o ( axi_req_mem ), .axi_rsp_i ( axi_rsp_mem ), - .idma_busy_o ( tx_busy ) + .eth_rx_irq_o ( eth_rx_irq ) ); axi_sim_mem #( @@ -682,31 +687,18 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .DataWidth ( DutCfg.AxiDataWidth ), .IdWidth ( DutCfg.AxiMstIdWidth ), .UserWidth ( DutCfg.AxiUserWidth ), - .axi_req_t ( axi_slv_req_t ), - .axi_rsp_t ( axi_slv_rsp_t ), + .axi_req_t ( axi_mst_req_t ), + .axi_rsp_t ( axi_mst_rsp_t ), .WarnUninitialized ( 1'b0 ), .ClearErrOnAccess ( 1'b1 ), - .ApplDelay ( ClkPeriodJtag * TAppl ), - .AcqDelay ( ClkPeriodJtag * TTest ) + .ApplDelay ( ClkPeriodSys * TAppl ), + .AcqDelay ( ClkPeriodSys * TTest ), + .UninitializedData ( "zeros" ) ) i_rx_axi_sim_mem ( .clk_i ( clk ), .rst_ni ( rst_n ), .axi_req_i ( axi_req_mem ), - .axi_rsp_o ( axi_rsp_mem ), - .mon_r_last_o ( /* NOT CONNECTED */ ), - .mon_r_beat_count_o ( /* NOT CONNECTED */ ), - .mon_r_user_o ( /* NOT CONNECTED */ ), - .mon_r_id_o ( /* NOT CONNECTED */ ), - .mon_r_data_o ( /* NOT CONNECTED */ ), - .mon_r_addr_o ( /* NOT CONNECTED */ ), - .mon_r_valid_o ( /* NOT CONNECTED */ ), - .mon_w_last_o ( /* NOT CONNECTED */ ), - .mon_w_beat_count_o ( /* NOT CONNECTED */ ), - .mon_w_user_o ( /* NOT CONNECTED */ ), - .mon_w_id_o ( /* NOT CONNECTED */ ), - .mon_w_data_o ( /* NOT CONNECTED */ ), - .mon_w_addr_o ( /* NOT CONNECTED */ ), - .mon_w_valid_o ( /* NOT CONNECTED */ ) + .axi_rsp_o ( axi_rsp_mem ) ); initial begin @@ -730,51 +722,69 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end initial begin - @(posedge clk); - $readmemh("eth_frame.vmem", i_rx_axi_sim_mem.mem); - - @(posedge clk); - reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address - @(posedge clk); + + @(posedge eth_rx_irq); + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + @(posedge clk); - reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 - @(posedge clk); + reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + @(posedge clk); - reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error ); // SRC_ADDR - @(posedge clk); + reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error ); // SRC_ADDR + @(posedge clk); - reg_drv_rx.send_write( 'h0300c018, 32'h0, 'hf, reg_error); // DST_ADDR - @(posedge clk); + reg_drv_rx.send_write( 'h0300c018, 32'h0, 'hf, reg_error); // DST_ADDR + @(posedge clk); - reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes - @(posedge clk); + reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes + @(posedge clk); - reg_drv_rx.send_write( 'h0300c020, 32'h0,'hf , reg_error); // src protocol - @(posedge clk); + reg_drv_rx.send_write( 'h0300c020, 32'h5,'hf , reg_error); // src protocol + @(posedge clk); - reg_drv_rx.send_write( 'h0300c024, 32'h5,'hf , reg_error); // dst protocol - @(posedge clk); + reg_drv_rx.send_write( 'h0300c024, 32'h0,'hf , reg_error); // dst protocol + @(posedge clk); - reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid - @(posedge clk); + reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid + @(posedge clk); + + //wait till all data written into rx_axi_sim_mem + while(1) begin + reg_drv_rx.send_read( 'h0300c048, rx_rsp_valid, reg_error); + if( rx_rsp_valid ) begin + break; + end + @(posedge clk); + end + + // Tx test starts here: external back to core + reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + @(posedge clk); - reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf, reg_error); // rsp ready - @(posedge clk); + reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error ); // SRC_ADDR + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c018, 32'h0, 'hf, reg_error); // DST_ADDR + @(posedge clk); - reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid - @(posedge clk); + reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c020, 32'h0,'hf , reg_error); // src protocol + @(posedge clk); - while(1) begin - reg_drv_rx.send_read( 'h0300c048, rx_rsp_valid, reg_error); - if(rx_rsp_valid) begin - reg_drv_rx.send_write( 'h0300c044, 32'h0, 'hf , reg_error); - @(posedge clk); - break; - end + reg_drv_rx.send_write( 'h0300c024, 32'h5,'hf , reg_error); // dst protocol @(posedge clk); - end -end - + + reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid + @(posedge clk); + end + /////////////////// // Serial Link // /////////////////// diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index f9d6cad2..91082a27 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -12,7 +12,7 @@ set TESTBENCH tb_cheshire_soc # Set voptargs only if not already set to make overridable. # Default on fast simulation flags. if {![info exists VOPTARGS]} { - set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" + set VOPTARGS "-O5 +acc" } set flags "-permissive -suppress 3009 -suppress 8386 -error 7 " From 93a05836826b81a5ef0d8bdda633ec551d5298d1 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 17 Jul 2024 09:11:22 +0200 Subject: [PATCH 29/48] ethernet with hw packet length to dma --- Bender.lock | 6 +++--- Bender.yml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 237afb75..d3a85291 100644 --- a/Bender.lock +++ b/Bender.lock @@ -85,8 +85,8 @@ packages: - common_cells - register_interface common_cells: - revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 - version: 1.35.0 + revision: be3866eb3ed5b8ac7bc9a9ec9f8ae86137cd0a45 + version: 1.36.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: f01aacf5746751d57f0b8340f21756791fd3a2aa + revision: 85679c62d4433ec2eafa6cec1482af99a98ad461 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index d683708d..c309a7fc 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "f01aacf" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "85679c6" } # branch: chs-hs export_include_dirs: - hw/include From effd127cc2da4c19bc4d8a58ee3edba6ba1d3e39 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sun, 21 Jul 2024 22:25:20 +0200 Subject: [PATCH 30/48] udapte ethernet with dma_en after obtaining length --- Bender.lock | 10 +++++----- Bender.yml | 2 +- hw/cheshire_soc.sv | 4 ++-- sw/tests/ethernet.c | 4 ++-- target/sim/src/vip_cheshire_soc.sv | 12 ++++++++---- 5 files changed, 18 insertions(+), 14 deletions(-) diff --git a/Bender.lock b/Bender.lock index d3a85291..e7765e3b 100644 --- a/Bender.lock +++ b/Bender.lock @@ -85,8 +85,8 @@ packages: - common_cells - register_interface common_cells: - revision: be3866eb3ed5b8ac7bc9a9ec9f8ae86137cd0a45 - version: 1.36.0 + revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb + version: 1.37.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -145,8 +145,8 @@ packages: - common_cells - register_interface obi: - revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636 - version: 0.1.2 + revision: c2141a653c755461ff44f61d12aeb5d99fc8e760 + version: 0.1.3 source: Git: https://github.com/pulp-platform/obi.git dependencies: @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 85679c62d4433ec2eafa6cec1482af99a98ad461 + revision: 15a25c963d093edb1f1fad93199ff26645dbef49 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index c309a7fc..3c2db8db 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "85679c6" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "15a25c9" } # branch: chs-hs export_include_dirs: - hw/include diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 824f4546..48d9d6a0 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1310,8 +1310,8 @@ module cheshire_soc import cheshire_pkg::*; #( .BufferDepth ( 32'd2 ), .TFLenWidth ( 32'd20 ), .MemSysDepth ( 32'd0 ), - .TxFifoLogDepth ( 32'd2 ), - .RxFifoLogDepth ( 32'd3 ), + .TxFifoLogDepth ( 32'd5 ), + .RxFifoLogDepth ( 32'd6 ), .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), .reg_req_t ( reg_req_t ), diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index be23e820..627b625a 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -49,7 +49,7 @@ int main(void) { volatile uint64_t data_to_write[DATA_CHUNK] = { 0x1032207098001032, - 0x3210E20020709800, + 0x3210400020709800, 0x1716151413121110, 0x2726252423222120, 0x3736353433323130, @@ -89,7 +89,7 @@ int main(void) { *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = RX_BASE; - *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; + // *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x5; *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 6794d263..e5214d28 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -628,6 +628,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( ); logic reg_error, eth_rx_irq; + logic dma_en; logic [REG_BUS_DW-1:0] rx_rsp_valid; reg_bus_drv_t reg_drv_rx = new(reg_bus_rx); @@ -679,7 +680,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .testmode_i ( 1'b0 ), .axi_req_o ( axi_req_mem ), .axi_rsp_i ( axi_rsp_mem ), - .eth_rx_irq_o ( eth_rx_irq ) + .eth_rx_irq_o ( eth_rx_irq ), + .dma_rx_en ( dma_en ) ); axi_sim_mem #( @@ -731,15 +733,17 @@ module vip_cheshire_soc import cheshire_pkg::*; #( reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); - + + @(posedge dma_en); + reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); reg_drv_rx.send_write( 'h0300c018, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge clk); - reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes - @(posedge clk); + // reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes + // @(posedge clk); reg_drv_rx.send_write( 'h0300c020, 32'h5,'hf , reg_error); // src protocol @(posedge clk); From 2b98c99451de98b4d9ffa599b43f0d4d4b8d8c26 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 24 Jul 2024 14:59:01 +0200 Subject: [PATCH 31/48] idma_rx_en into reg --- Bender.lock | 2 +- Bender.yml | 2 +- sw/tests/ethernet.c | 5 ++++- target/sim/src/vip_cheshire_soc.sv | 10 +++++++--- 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/Bender.lock b/Bender.lock index e7765e3b..74ea01e2 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 15a25c963d093edb1f1fad93199ff26645dbef49 + revision: 985d5255fa65d01741cbdd5010b6bea28dfb655b version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 3c2db8db..1c9440be 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "15a25c9" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "985d525" } # branch: chs-hs export_include_dirs: - hw/include diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 627b625a..27f9af00 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -18,6 +18,7 @@ #define IDMA_REQ_READY_OFFSET 0x40 #define IDMA_RSP_READY_OFFSET 0x44 #define IDMA_RSP_VALID_OFFSET 0x48 +#define IDMA_RX_EN_OFFSET 0x50 #define PLIC_BASE 0x04000000 #define RV_PLIC_PRIO19_REG_OFFSET 0x4c @@ -83,9 +84,11 @@ int main(void) { // rx irq while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); - + // configure ethernet *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; + // dma length ready, dma can be configured now + while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET))); *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = RX_BASE; diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index e5214d28..82e3127e 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -680,8 +680,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .testmode_i ( 1'b0 ), .axi_req_o ( axi_req_mem ), .axi_rsp_i ( axi_rsp_mem ), - .eth_rx_irq_o ( eth_rx_irq ), - .dma_rx_en ( dma_en ) + .eth_rx_irq_o ( eth_rx_irq ) ); axi_sim_mem #( @@ -734,7 +733,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #( reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); - @(posedge dma_en); + while(1) begin + reg_drv_rx.send_read( 'h0300c050, dma_en, reg_error); // req ready + if( dma_en ) + break; + @(posedge clk); + end reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); From 60c8cf0eb1f4190d1f4e8d21fe0346905aa0459e Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 24 Jul 2024 18:15:23 +0200 Subject: [PATCH 32/48] fix typo in ethernet --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 74ea01e2..8d646051 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 985d5255fa65d01741cbdd5010b6bea28dfb655b + revision: d97e8e8d0cd26ae6f9ecd9403b370857465a5f59 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 1c9440be..5349f8e9 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "985d525" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "d97e8e8" } # branch: chs-hs export_include_dirs: - hw/include From a01cbb10fe6aa4d07a242d8ebaf2d53bbcf97bb1 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sun, 28 Jul 2024 19:24:11 +0200 Subject: [PATCH 33/48] rm ethernet latch --- Bender.lock | 6 +++--- Bender.yml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 8d646051..382e7921 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,8 +15,8 @@ packages: - apb - register_interface axi: - revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 - version: 0.39.3 + revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7 + version: 0.39.4 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: d97e8e8d0cd26ae6f9ecd9403b370857465a5f59 + revision: 7cb866430b38fc5281a6ada345146d49d17b977a version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 5349f8e9..89f98e36 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "d97e8e8" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "7cb8664" } # branch: chs-hs export_include_dirs: - hw/include From 77c879d305e6d7269b65e5245f20da9bf1dd7fec Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Thu, 8 Aug 2024 14:23:33 +0200 Subject: [PATCH 34/48] update ethernet with added regs --- Bender.lock | 2 +- Bender.yml | 2 +- sw/tests/ethernet.c | 32 +++++++++++++------------- target/sim/src/vip_cheshire_soc.sv | 37 ++++++++++++++---------------- 4 files changed, 35 insertions(+), 38 deletions(-) diff --git a/Bender.lock b/Bender.lock index 382e7921..e809b799 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 7cb866430b38fc5281a6ada345146d49d17b977a + revision: 19a8d32a5fa8e234a710a22d179da6b56e21bb58 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 89f98e36..aee27cfc 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "7cb8664" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "19a8d32" } # branch: chs-hs export_include_dirs: - hw/include diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 27f9af00..56bcf9c3 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -8,17 +8,17 @@ #define MACLO_OFFSET 0x0 #define MACHI_OFFSET 0x4 -#define IRQ_OFFSET 0x10 -#define IDMA_SRC_ADDR_OFFSET 0x14 -#define IDMA_DST_ADDR_OFFSET 0x18 -#define IDMA_LENGTH_OFFSET 0x1c -#define IDMA_SRC_PROTO_OFFSET 0x20 -#define IDMA_DST_PROTO_OFFSET 0x24 -#define IDMA_REQ_VALID_OFFSET 0x3c -#define IDMA_REQ_READY_OFFSET 0x40 -#define IDMA_RSP_READY_OFFSET 0x44 -#define IDMA_RSP_VALID_OFFSET 0x48 -#define IDMA_RX_EN_OFFSET 0x50 +#define IRQ_OFFSET 0x18 +#define IDMA_SRC_ADDR_OFFSET 0x1c +#define IDMA_DST_ADDR_OFFSET 0x20 +#define IDMA_LENGTH_OFFSET 0x24 +#define IDMA_SRC_PROTO_OFFSET 0x28 +#define IDMA_DST_PROTO_OFFSET 0x2c +#define IDMA_REQ_VALID_OFFSET 0x44 +#define IDMA_REQ_READY_OFFSET 0x48 +#define IDMA_RSP_READY_OFFSET 0x4c +#define IDMA_RSP_VALID_OFFSET 0x50 +#define IDMA_RX_EN_OFFSET 0x54 #define PLIC_BASE 0x04000000 #define RV_PLIC_PRIO19_REG_OFFSET 0x4c @@ -49,7 +49,7 @@ int main(void) { *reg32(PLIC_BASE, RV_PLIC_IE0_0_REG_OFFSET) |= (1 << (RV_PLIC_IE0_0_E_19_BIT)); // Enable interrupt number ; volatile uint64_t data_to_write[DATA_CHUNK] = { - 0x1032207098001032, + 0x0207230100890702, 0x3210400020709800, 0x1716151413121110, 0x2726252423222120, @@ -65,9 +65,9 @@ int main(void) { *tx_addr = data_to_write[i]; } - *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; + *reg32(ETH_BASE, MACLO_OFFSET) = 0x00890702; // High 16 bit Mac Address - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00002070; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00002301; // DMA Source Address *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = TX_BASE; // DMA Destination Address @@ -85,8 +85,8 @@ int main(void) { // rx irq while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); // configure ethernet - *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; + *reg32(ETH_BASE, MACLO_OFFSET) = 0x00890702; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00002301; // dma length ready, dma can be configured now while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET))); diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 82e3127e..676ec232 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -727,40 +727,37 @@ module vip_cheshire_soc import cheshire_pkg::*; #( @(posedge eth_rx_irq); @(posedge clk); - reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + reg_drv_rx.send_write( 'h0300c004, 16'h2301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); while(1) begin - reg_drv_rx.send_read( 'h0300c050, dma_en, reg_error); // req ready + reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error); // req ready if( dma_en ) break; @(posedge clk); end - reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error ); // SRC_ADDR + reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); - reg_drv_rx.send_write( 'h0300c018, 32'h0, 'hf, reg_error); // DST_ADDR + reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge clk); - - // reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes - // @(posedge clk); - reg_drv_rx.send_write( 'h0300c020, 32'h5,'hf , reg_error); // src protocol + reg_drv_rx.send_write( 'h0300c028, 32'h5,'hf , reg_error); // src protocol @(posedge clk); - reg_drv_rx.send_write( 'h0300c024, 32'h0,'hf , reg_error); // dst protocol + reg_drv_rx.send_write( 'h0300c02c, 32'h0,'hf , reg_error); // dst protocol @(posedge clk); - reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid + reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error); // req valid @(posedge clk); //wait till all data written into rx_axi_sim_mem while(1) begin - reg_drv_rx.send_read( 'h0300c048, rx_rsp_valid, reg_error); + reg_drv_rx.send_read( 'h0300c050, rx_rsp_valid, reg_error); if( rx_rsp_valid ) begin break; end @@ -768,28 +765,28 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end // Tx test starts here: external back to core - reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - reg_drv_rx.send_write( 'h0300c004, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + reg_drv_rx.send_write( 'h0300c004, 16'h2301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); - reg_drv_rx.send_write( 'h0300c014, 32'h0, 'hf, reg_error ); // SRC_ADDR + reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); - reg_drv_rx.send_write( 'h0300c018, 32'h0, 'hf, reg_error); // DST_ADDR + reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge clk); - reg_drv_rx.send_write( 'h0300c01c, 32'h40,'hf , reg_error); // Size in bytes + reg_drv_rx.send_write( 'h0300c024, 32'h40,'hf , reg_error); // Size in bytes @(posedge clk); - reg_drv_rx.send_write( 'h0300c020, 32'h0,'hf , reg_error); // src protocol + reg_drv_rx.send_write( 'h0300c028, 32'h0,'hf , reg_error); // src protocol @(posedge clk); - reg_drv_rx.send_write( 'h0300c024, 32'h5,'hf , reg_error); // dst protocol + reg_drv_rx.send_write( 'h0300c02c, 32'h5,'hf , reg_error); // dst protocol @(posedge clk); - reg_drv_rx.send_write( 'h0300c03c, 'h1, 'hf , reg_error); // req valid + reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error); // req valid @(posedge clk); end From d93c93f6823acc58e503cbf33a1d41f987e28ae0 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 4 Sep 2024 14:01:55 +0200 Subject: [PATCH 35/48] mdio sw RW to RO --- Bender.lock | 10 +++++----- Bender.yml | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Bender.lock b/Bender.lock index e809b799..759b9176 100644 --- a/Bender.lock +++ b/Bender.lock @@ -145,8 +145,8 @@ packages: - common_cells - register_interface obi: - revision: c2141a653c755461ff44f61d12aeb5d99fc8e760 - version: 0.1.3 + revision: 5321106817e177d6c16ecc4daa922b96b1bc946b + version: 0.1.5 source: Git: https://github.com/pulp-platform/obi.git dependencies: @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 19a8d32a5fa8e234a710a22d179da6b56e21bb58 + revision: db28e88102bea25ac585d493158c0f0ab2585b3e version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git @@ -192,8 +192,8 @@ packages: - common_cells - tech_cells_generic serial_link: - revision: 5a25f5a71074f1ebb6de7b5280f2b16924bcc666 - version: 1.1.1 + revision: c55df03a1da06b00e567cf968b1b1a5f40c9f802 + version: 1.1.2 source: Git: https://github.com/pulp-platform/serial_link.git dependencies: diff --git a/Bender.yml b/Bender.yml index aee27cfc..6f663b7d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "19a8d32" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "db28e88" } # branch: chs-hs export_include_dirs: - hw/include From e7255091fcc19a8a17054b72bb621e07a7d34129 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 4 Sep 2024 19:46:03 +0200 Subject: [PATCH 36/48] ethernet payload cycle fix --- Bender.lock | 2 +- Bender.yml | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Bender.lock b/Bender.lock index 759b9176..45b68f00 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: db28e88102bea25ac585d493158c0f0ab2585b3e + revision: 674fe92a3fcdbde3afe818570a685d7f0923f020 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 6f663b7d..72cfaa6e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "db28e88" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "674fe92" } # branch: chs-hs export_include_dirs: - hw/include @@ -57,4 +57,4 @@ sources: - target/xilinx/src/phy_definitions.svh - target/xilinx/src/dram_wrapper_xilinx.sv - target/xilinx/src/fan_ctrl.sv - - target/xilinx/src/cheshire_top_xilinx.sv + - target/xilinx/src/cheshire_top_xilinx.sv \ No newline at end of file From 1bb87e3976632a1103fb77f08a819b128ee5688e Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Thu, 5 Sep 2024 10:15:43 +0200 Subject: [PATCH 37/48] rm conditional iobuf --- hw/cheshire_soc.sv | 3 --- target/xilinx/src/cheshire_top_xilinx.sv | 3 --- 2 files changed, 6 deletions(-) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 48d9d6a0..e1916777 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1349,9 +1349,6 @@ module cheshire_soc import cheshire_pkg::*; #( assign eth_rstn_o = 1'b0; assign eth_txctl_o = 1'b0; assign eth_txd_o = 4'b0; - assign eth_mdio_o = '0; - assign eth_mdio_oe = '0; - assign eth_mdc_o = '0; end //////////////// diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 3908af9e..0de7a755 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -259,8 +259,6 @@ module cheshire_top_xilinx ( /////////////////////// // Ethernet Adaption // ////////////////////// -`ifdef USE_ETHERNET - logic eth_mdio_i; logic eth_mdio_o; logic eth_mdio_oe; @@ -276,7 +274,6 @@ module cheshire_top_xilinx ( .I ( eth_mdio_o ), // Buffer input .T ( ~eth_mdio_oe ) // 3-state enable input, high=input, low=output ); - `endif /////////////// // SPI to SD // From dcc85c442950be3c8edaccedc8b7d566d4b24334 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Thu, 5 Sep 2024 19:38:28 +0200 Subject: [PATCH 38/48] io buf fast --- target/xilinx/src/cheshire_top_xilinx.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 0de7a755..7befecc3 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -495,7 +495,7 @@ module cheshire_top_xilinx ( .eth_rstn_o ( eth_rstn ), .eth_mdio_i ( eth_mdio_i ), .eth_mdio_o ( eth_mdio_o ), - .eth_mdio_oe ( eth_mdio_en ), + .eth_mdio_oe ( eth_mdio_oe ), .eth_mdc_o ( eth_mdc ), .spih_sck_o ( spi_sck_soc ), .spih_sck_en_o ( spi_sck_en ), From 523e02fc326dfcec0e12703ba1b2388dcec35472 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Thu, 5 Sep 2024 19:51:56 +0200 Subject: [PATCH 39/48] enlarge tx rx fifo depth --- hw/cheshire_soc.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index e1916777..1520e3a6 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1310,8 +1310,8 @@ module cheshire_soc import cheshire_pkg::*; #( .BufferDepth ( 32'd2 ), .TFLenWidth ( 32'd20 ), .MemSysDepth ( 32'd0 ), - .TxFifoLogDepth ( 32'd5 ), - .RxFifoLogDepth ( 32'd6 ), + .TxFifoLogDepth ( 32'd10 ), + .RxFifoLogDepth ( 32'd10 ), .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), .reg_req_t ( reg_req_t ), From 1d04d66634d049e1d778c9880dd67fc1dbd98570 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Thu, 5 Sep 2024 19:55:11 +0200 Subject: [PATCH 40/48] restore conditional io bud --- target/xilinx/src/cheshire_top_xilinx.sv | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 7befecc3..03938d7f 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -259,10 +259,12 @@ module cheshire_top_xilinx ( /////////////////////// // Ethernet Adaption // ////////////////////// - logic eth_mdio_i; - logic eth_mdio_o; - logic eth_mdio_oe; - + logic eth_mdio_i; + logic eth_mdio_o; + logic eth_mdio_oe; + + //`ifdef USE_ETHERNET + IOBUF #( .DRIVE ( 12 ), // Specify the output drive strength .IBUF_LOW_PWR ( "FALSE" ), // Low Power - "TRUE", High Performance = "FALSE" @@ -275,6 +277,8 @@ module cheshire_top_xilinx ( .T ( ~eth_mdio_oe ) // 3-state enable input, high=input, low=output ); + //`endif + /////////////// // SPI to SD // /////////////// From f729c20f989a09046cb06d2dd1c7d248e7c33f20 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Thu, 12 Sep 2024 12:32:03 +0200 Subject: [PATCH 41/48] minor fixes --- Bender.lock | 10 +++---- Bender.yml | 2 +- hw/cheshire_soc.sv | 4 +-- sw/tests/ethernet.c | 17 +++++++---- target/sim/src/fixture_cheshire_soc.sv | 2 +- target/sim/src/vip_cheshire_soc.sv | 40 +++++++++++++++----------- 6 files changed, 44 insertions(+), 31 deletions(-) diff --git a/Bender.lock b/Bender.lock index 45b68f00..68ba293e 100644 --- a/Bender.lock +++ b/Bender.lock @@ -60,8 +60,8 @@ packages: dependencies: - common_cells axi_vga: - revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 - version: 0.1.3 + revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e + version: 0.1.4 source: Git: https://github.com/pulp-platform/axi_vga.git dependencies: @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 674fe92a3fcdbde3afe818570a685d7f0923f020 + revision: a8e69091528d5e8d2a7091082643e5a7c81d2ffd version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git @@ -174,8 +174,8 @@ packages: - idma - register_interface register_interface: - revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d - version: 0.4.4 + revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 + version: 0.4.5 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index 72cfaa6e..fb465c6a 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "674fe92" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "a8e6909" } # branch: chs-hs export_include_dirs: - hw/include diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 1520e3a6..e8fade18 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1310,8 +1310,8 @@ module cheshire_soc import cheshire_pkg::*; #( .BufferDepth ( 32'd2 ), .TFLenWidth ( 32'd20 ), .MemSysDepth ( 32'd0 ), - .TxFifoLogDepth ( 32'd10 ), - .RxFifoLogDepth ( 32'd10 ), + .TxFifoLogDepth ( 32'd5 ), + .RxFifoLogDepth ( 32'd5 ), .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), .reg_req_t ( reg_req_t ), diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 56bcf9c3..c52bfe91 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -19,6 +19,7 @@ #define IDMA_RSP_READY_OFFSET 0x4c #define IDMA_RSP_VALID_OFFSET 0x50 #define IDMA_RX_EN_OFFSET 0x54 +#define ETH_MDIO_OFFSET 0x8 #define PLIC_BASE 0x04000000 #define RV_PLIC_PRIO19_REG_OFFSET 0x4c @@ -37,7 +38,7 @@ #define TX_BASE 0x14000000 #define RX_BASE 0x14001000 -#define PRINTF_ON +//#define PRINTF_ON int main(void) { @@ -67,7 +68,7 @@ int main(void) { *reg32(ETH_BASE, MACLO_OFFSET) = 0x00890702; // High 16 bit Mac Address - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00002301; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00802301; // DMA Source Address *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = TX_BASE; // DMA Destination Address @@ -81,12 +82,18 @@ int main(void) { // Validate Request to DMA *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; + + uint32_t *mdio; + // mdio = reg32(ETH_BASE, ETH_MDIO_OFFSET); + mdio = 0x0300c008; + printf("MDIO value: 0x%08X\n", *mdio); - // rx irq - while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); // configure ethernet *reg32(ETH_BASE, MACLO_OFFSET) = 0x00890702; - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00002301; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00802301; + // rx irq + while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); + // dma length ready, dma can be configured now while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET))); diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 8124f494..e0fa0a93 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -138,7 +138,7 @@ module fixture_cheshire_soc #( .eth_txd_o ( eth_txd ), .eth_txctl_o ( eth_txctl ), .eth_rstn_o ( eth_rstn ), - .eth_mdio_i ( eth_mdio_i ), + .eth_mdio_i ( 1'b0 ),// eth_mdio_i .eth_mdio_o ( eth_mdio_o ), .eth_mdio_oe ( eth_mdio_en ), .eth_mdc_o ( eth_mdc ), diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 676ec232..0f91bc54 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -723,35 +723,38 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end initial begin - - @(posedge eth_rx_irq); + @(posedge clk); - - reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address + $display("0"); + reg_drv_rx.send_write( 'h0300c000, 32'h00222222, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - - reg_drv_rx.send_write( 'h0300c004, 16'h2301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + $display("1"); + reg_drv_rx.send_write( 'h0300c004, 'h801111, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); + $display("2"); - while(1) begin - reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error); // req ready - if( dma_en ) - break; - @(posedge clk); - end + @(posedge clk); + + // while(1) begin + // reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error); // req ready + // if( dma_en ) + // break; + // @(posedge clk); + // end reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); - + + $display("3"); reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge clk); - + $display("4"); reg_drv_rx.send_write( 'h0300c028, 32'h5,'hf , reg_error); // src protocol @(posedge clk); - + $display("5"); reg_drv_rx.send_write( 'h0300c02c, 32'h0,'hf , reg_error); // dst protocol @(posedge clk); - + $display("6"); reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error); // req valid @(posedge clk); @@ -764,11 +767,14 @@ module vip_cheshire_soc import cheshire_pkg::*; #( @(posedge clk); end + @(posedge eth_rx_irq); + + // Tx test starts here: external back to core reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - reg_drv_rx.send_write( 'h0300c004, 16'h2301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + reg_drv_rx.send_write( 'h0300c004, 32'h00802301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR From 515bbac87ca8f206280ca677c441198f4e963565 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Sat, 12 Oct 2024 23:59:51 +0200 Subject: [PATCH 42/48] ethernet dependency update --- Bender.lock | 2 +- Bender.yml | 2 +- sw/tests/ethernet.c | 15 +++-------- target/sim/src/vip_cheshire_soc.sv | 43 ++++++++++++++---------------- 4 files changed, 26 insertions(+), 36 deletions(-) diff --git a/Bender.lock b/Bender.lock index 68ba293e..041038db 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: a8e69091528d5e8d2a7091082643e5a7c81d2ffd + revision: 85739c2d1ccd6c1c2ea1c5b95effcace234baa81 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index fb465c6a..24c6b5f5 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "a8e6909" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "85739c2" } # branch: chs-hs export_include_dirs: - hw/include diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index c52bfe91..9e25f4c8 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -66,9 +66,9 @@ int main(void) { *tx_addr = data_to_write[i]; } - *reg32(ETH_BASE, MACLO_OFFSET) = 0x00890702; + *reg32(ETH_BASE, MACLO_OFFSET) = 0x89000123; // High 16 bit Mac Address - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00802301; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00800207; // DMA Source Address *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = TX_BASE; // DMA Destination Address @@ -83,23 +83,16 @@ int main(void) { // Validate Request to DMA *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; - uint32_t *mdio; - // mdio = reg32(ETH_BASE, ETH_MDIO_OFFSET); - mdio = 0x0300c008; - printf("MDIO value: 0x%08X\n", *mdio); - // configure ethernet - *reg32(ETH_BASE, MACLO_OFFSET) = 0x00890702; - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00802301; + *reg32(ETH_BASE, MACLO_OFFSET) = 0x89000123; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00800207; // rx irq while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); - // dma length ready, dma can be configured now while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET))); *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = RX_BASE; - // *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x5; *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 0f91bc54..57828058 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -724,37 +724,37 @@ module vip_cheshire_soc import cheshire_pkg::*; #( initial begin + wait_for_reset(); + + @(posedge clk) + + reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - $display("0"); - reg_drv_rx.send_write( 'h0300c000, 32'h00222222, 'hf, reg_error); //lower 32bits of MAC address - @(posedge clk); - $display("1"); - reg_drv_rx.send_write( 'h0300c004, 'h801111, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 - @(posedge clk); - $display("2"); - + + reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); - // while(1) begin - // reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error); // req ready - // if( dma_en ) - // break; - // @(posedge clk); - // end + @(posedge eth_rx_irq); + + while(1) begin + reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error); // req ready with packet length + if( dma_en ) + break; + @(posedge clk); + end reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); - $display("3"); reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge clk); - $display("4"); + reg_drv_rx.send_write( 'h0300c028, 32'h5,'hf , reg_error); // src protocol @(posedge clk); - $display("5"); + reg_drv_rx.send_write( 'h0300c02c, 32'h0,'hf , reg_error); // dst protocol @(posedge clk); - $display("6"); + reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error); // req valid @(posedge clk); @@ -766,15 +766,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end @(posedge clk); end - - @(posedge eth_rx_irq); - // Tx test starts here: external back to core - reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address + reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - reg_drv_rx.send_write( 'h0300c004, 32'h00802301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR From 8c25a3a383c54f611255c7975ee8f58a38007b5f Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 29 Oct 2024 14:54:10 +0100 Subject: [PATCH 43/48] eth test typo fix --- sw/tests/ethernet.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 9e25f4c8..a3b0d051 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -3,7 +3,7 @@ #include #include "printf.h" #include "util.h" - + #define ETH_BASE 0x0300c000 #define MACLO_OFFSET 0x0 @@ -40,23 +40,23 @@ //#define PRINTF_ON -int main(void) { - +int main(void) { + #ifdef PRINTF_ON printf ("Start test Ethernet...\n\r"); - #endif + #endif *reg32(PLIC_BASE, RV_PLIC_PRIO19_REG_OFFSET) = 1; *reg32(PLIC_BASE, RV_PLIC_IE0_0_REG_OFFSET) |= (1 << (RV_PLIC_IE0_0_E_19_BIT)); // Enable interrupt number ; volatile uint64_t data_to_write[DATA_CHUNK] = { - 0x0207230100890702, + 0x0207230100890702, 0x3210400020709800, - 0x1716151413121110, + 0x1716151413121110, 0x2726252423222120, - 0x3736353433323130, + 0x3736353433323130, 0x4746454443424140, - 0x5756555453525150, + 0x5756555453525150, 0x6766656463626160 }; @@ -76,7 +76,7 @@ int main(void) { // Data length *reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; // Source Protocol - *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; + *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x0; // Destination Protocol *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x5; @@ -85,13 +85,13 @@ int main(void) { // configure ethernet *reg32(ETH_BASE, MACLO_OFFSET) = 0x89000123; - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00800207; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00800207; // rx irq while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); // dma length ready, dma can be configured now while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET))); - *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x0; + *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = RX_BASE; *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x5; *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; @@ -111,4 +111,3 @@ int main(void) { return error; } - From 2ebc5c63256e0111e5b7b4ae18092601978aa1b1 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 29 Oct 2024 16:51:26 +0100 Subject: [PATCH 44/48] req_ready check in test --- sw/tests/ethernet.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index a3b0d051..f6e1c09e 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -80,6 +80,7 @@ int main(void) { // Destination Protocol *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x5; + while(!(*reg32(ETH_BASE, IDMA_REQ_READY_OFFSET))); // Validate Request to DMA *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; @@ -87,7 +88,7 @@ int main(void) { *reg32(ETH_BASE, MACLO_OFFSET) = 0x89000123; *reg32(ETH_BASE, MACHI_OFFSET) = 0x00800207; // rx irq - while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); + while (!((*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) )); // dma length ready, dma can be configured now while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET))); @@ -97,6 +98,7 @@ int main(void) { *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; + while(!(*reg32(ETH_BASE, IDMA_REQ_READY_OFFSET))); // wait until DMA moves all data while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET))); From 912c9a997c2f5137f27fc171a288364dd5faa290 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 29 Oct 2024 23:56:02 +0100 Subject: [PATCH 45/48] restore req sw --- Bender.lock | 10 +++--- Bender.yml | 4 +-- sw/tests/ethernet.c | 16 ++++++--- target/sim/src/vip_cheshire_soc.sv | 58 ++++++++++++++++-------------- 4 files changed, 51 insertions(+), 37 deletions(-) diff --git a/Bender.lock b/Bender.lock index 041038db..96c40a3b 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,8 +15,8 @@ packages: - apb - register_interface axi: - revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7 - version: 0.39.4 + revision: 853ede23b2a9837951b74dbdc6d18c3eef5bac7d + version: 0.39.5 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -44,8 +44,8 @@ packages: - common_cells - common_verification axi_rt: - revision: d5f857e74d0a5db4e4a2cc3652ca4f40f29a1484 - version: 0.0.0-alpha.8 + revision: 641ea950e24722af747033f2ab85f0e48ea8d7f8 + version: 0.0.0-alpha.9 source: Git: https://github.com/pulp-platform/axi_rt.git dependencies: @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 85739c2d1ccd6c1c2ea1c5b95effcace234baa81 + revision: 97ad4987ce2bc3846413fc90c0ac293ef1d66bf8 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 24c6b5f5..069eb483 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "85739c2" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "97ad498" } # branch: chs-hs export_include_dirs: - hw/include @@ -57,4 +57,4 @@ sources: - target/xilinx/src/phy_definitions.svh - target/xilinx/src/dram_wrapper_xilinx.sv - target/xilinx/src/fan_ctrl.sv - - target/xilinx/src/cheshire_top_xilinx.sv \ No newline at end of file + - target/xilinx/src/cheshire_top_xilinx.sv diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index f6e1c09e..d23803d3 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -83,6 +83,9 @@ int main(void) { while(!(*reg32(ETH_BASE, IDMA_REQ_READY_OFFSET))); // Validate Request to DMA *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; + *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; + // DMA completes data moving + while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET))); // configure ethernet *reg32(ETH_BASE, MACLO_OFFSET) = 0x89000123; @@ -96,19 +99,24 @@ int main(void) { *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = RX_BASE; *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x5; *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; - *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; while(!(*reg32(ETH_BASE, IDMA_REQ_READY_OFFSET))); + *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; + *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; + // wait until DMA moves all data while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET))); - uint32_t error = 0; + volatile uint32_t error = 0; for (int i = 0; i < DATA_CHUNK; ++i) { volatile uint64_t *rx_addr = (volatile uint64_t*)(RX_BASE + i * sizeof(uint64_t)); - uint64_t data_read = *rx_addr; + volatile uint64_t data_read = *rx_addr; - if (data_read != data_to_write[i]) error ++; + if (data_read != data_to_write[i]) { + printf("Error at index %d: expected 0x%lx, got 0x%lx\n", i, data_to_write[i], data_read); + error++; + } } return error; diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 57828058..dae761b0 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -612,7 +612,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( import idma_pkg::*; localparam REG_BUS_AW = 32; localparam REG_BUS_DW = 32; - + typedef reg_test::reg_driver #( .AW(REG_BUS_AW), .DW(REG_BUS_DW), @@ -626,24 +626,24 @@ module vip_cheshire_soc import cheshire_pkg::*; #( ) reg_bus_rx ( .clk_i(clk) ); - + logic reg_error, eth_rx_irq; logic dma_en; logic [REG_BUS_DW-1:0] rx_rsp_valid; reg_bus_drv_t reg_drv_rx = new(reg_bus_rx); - + reg_req_t reg_bus_rx_req; reg_rsp_t reg_bus_rx_rsp; `REG_BUS_ASSIGN_TO_REQ (reg_bus_rx_req, reg_bus_rx) `REG_BUS_ASSIGN_FROM_RSP (reg_bus_rx, reg_bus_rx_rsp) - + axi_mst_req_t axi_req_mem; axi_mst_rsp_t axi_rsp_mem; - + eth_idma_wrap#( - .DataWidth ( DutCfg.AxiDataWidth ), + .DataWidth ( DutCfg.AxiDataWidth ), .AddrWidth ( DutCfg.AddrWidth ), .UserWidth ( DutCfg.AxiUserWidth ), .AxiIdWidth ( DutCfg.AxiMstIdWidth ), @@ -659,7 +659,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .reg_rsp_t ( reg_rsp_t ) ) i_rx_eth_idma_wrap ( .clk_i ( clk ), - .rst_ni ( rst_n ), + .rst_ni ( rst_n ), .eth_clk125_i ( eth_clk125 ), .eth_clk125q_i ( eth_clk125q ), .phy_rx_clk_i ( eth_txck ), @@ -668,7 +668,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .phy_tx_clk_o ( eth_rxck ), .phy_txd_o ( eth_rxd ), .phy_tx_ctl_o ( eth_rxctl ), - .phy_resetn_o ( eth_rstn ), + .phy_resetn_o ( eth_rstn ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), .phy_mdio_i ( 1'b0 ), @@ -701,7 +701,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .axi_req_i ( axi_req_mem ), .axi_rsp_o ( axi_rsp_mem ) ); - + initial begin forever begin eth_clk125 <= 1; @@ -723,7 +723,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end initial begin - + wait_for_reset(); @(posedge clk) @@ -733,7 +733,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); - + @(posedge eth_rx_irq); while(1) begin @@ -742,10 +742,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #( break; @(posedge clk); end - - reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR + + reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); - + reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge clk); @@ -757,7 +757,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #( reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error); // req valid @(posedge clk); - + + reg_drv_rx.send_write( 'h0300c044, 'h0, 'hf , reg_error); // req valid + @(posedge clk); + //wait till all data written into rx_axi_sim_mem while(1) begin reg_drv_rx.send_read( 'h0300c050, rx_rsp_valid, reg_error); @@ -770,19 +773,19 @@ module vip_cheshire_soc import cheshire_pkg::*; #( // Tx test starts here: external back to core reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - + reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); - reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR + reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge clk); - + reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge clk); - reg_drv_rx.send_write( 'h0300c024, 32'h40,'hf , reg_error); // Size in bytes + reg_drv_rx.send_write( 'h0300c024, 32'h40,'hf , reg_error); // Size in bytes @(posedge clk); - + reg_drv_rx.send_write( 'h0300c028, 32'h0,'hf , reg_error); // src protocol @(posedge clk); @@ -790,9 +793,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #( @(posedge clk); reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error); // req valid - @(posedge clk); - end - + @(posedge clk); + + reg_drv_rx.send_write( 'h0300c044, 'h0, 'hf , reg_error); // req valid + @(posedge clk); + end + /////////////////// // Serial Link // /////////////////// @@ -1134,7 +1140,7 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( // Ethernet pad IO input logic eth_mdio_o, output logic eth_mdio_i, - input logic eth_mdio_en, + input logic eth_mdio_en, // I2C wires inout wire i2c_sda, inout wire i2c_scl, @@ -1170,7 +1176,7 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( end // Ethernet - bufif1 (eth_mdio_i, eth_mdio, ~eth_mdio_en); - bufif1 (eth_mdio, eth_mdio_o, eth_mdio_en); + bufif1 (eth_mdio_i, eth_mdio, ~eth_mdio_en); + bufif1 (eth_mdio, eth_mdio_o, eth_mdio_en); endmodule From 063813be13d7d7cba3b64dcb17e1dda710c14626 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Fri, 8 Nov 2024 15:34:44 +0100 Subject: [PATCH 46/48] enlarged rx fifo --- hw/cheshire_pkg.sv | 2 +- hw/cheshire_soc.sv | 10 +++++----- sw/tests/ethernet.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index d8808eb7..ea8df5e8 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -621,7 +621,7 @@ package cheshire_pkg; // LLC: 128 KiB, up to 2 GiB DRAM LlcNotBypass : 1, LlcSetAssoc : 8, - LlcNumLines : 256, + LlcNumLines : 128, // from 256 LlcNumBlocks : 8, LlcMaxReadTxns : 16, LlcMaxWriteTxns : 16, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index e8fade18..2f1db2d5 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1302,7 +1302,7 @@ module cheshire_soc import cheshire_pkg::*; #( //////////////// if (Cfg.Ethernet) begin : gen_ethernet eth_idma_wrap#( - .DataWidth ( Cfg.AxiDataWidth ), + .DataWidth ( Cfg.AxiDataWidth ), .AddrWidth ( Cfg.AddrWidth ), .UserWidth ( Cfg.AxiUserWidth ), .AxiIdWidth ( Cfg.AxiMstIdWidth ), @@ -1311,14 +1311,14 @@ module cheshire_soc import cheshire_pkg::*; #( .TFLenWidth ( 32'd20 ), .MemSysDepth ( 32'd0 ), .TxFifoLogDepth ( 32'd5 ), - .RxFifoLogDepth ( 32'd5 ), + .RxFifoLogDepth ( 32'd10 ), .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), .reg_req_t ( reg_req_t ), .reg_rsp_t ( reg_rsp_t ) ) i_tx_eth_idma_wrap ( .clk_i, - .rst_ni, + .rst_ni, .eth_clk125_i ( eth_clk125_i ), .eth_clk125q_i ( eth_clk125q_i), .eth_clk200_i ( eth_clk200_i ), @@ -1328,13 +1328,13 @@ module cheshire_soc import cheshire_pkg::*; #( .phy_tx_clk_o ( eth_txck_o ), .phy_txd_o ( eth_txd_o ), .phy_tx_ctl_o ( eth_txctl_o ), - .phy_resetn_o ( eth_rstn_o ), + .phy_resetn_o ( eth_rstn_o ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), .phy_mdio_i ( eth_mdio_i ), .phy_mdio_o ( eth_mdio_o ), .phy_mdio_oe ( eth_mdio_oe ), - .phy_mdc_o ( eth_mdc_o ), + .phy_mdc_o ( eth_mdc_o ), .testmode_i ( testmode_i ), .axi_req_o ( axi_in_req[AxiIn.eth] ), .axi_rsp_i ( axi_in_rsp[AxiIn.eth] ), diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index d23803d3..24caf635 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -114,7 +114,7 @@ int main(void) { volatile uint64_t data_read = *rx_addr; if (data_read != data_to_write[i]) { - printf("Error at index %d: expected 0x%lx, got 0x%lx\n", i, data_to_write[i], data_read); + //printf("Error at index %d: expected 0x%lx, got 0x%lx\n", i, data_to_write[i], data_read); error++; } } From 397d29cd1ecdd12907a4b8af51f617e8d4d27493 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Fri, 8 Nov 2024 17:28:34 +0100 Subject: [PATCH 47/48] test cleanup --- sw/tests/ethernet.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 24caf635..adefe5b1 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -83,7 +83,6 @@ int main(void) { while(!(*reg32(ETH_BASE, IDMA_REQ_READY_OFFSET))); // Validate Request to DMA *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; - *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; // DMA completes data moving while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET))); @@ -102,7 +101,6 @@ int main(void) { while(!(*reg32(ETH_BASE, IDMA_REQ_READY_OFFSET))); *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; - *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; // wait until DMA moves all data while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET))); From fd98482e0addae7b20954d43a084521232238e67 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Fri, 8 Nov 2024 17:52:37 +0100 Subject: [PATCH 48/48] update ethernet dependency --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 96c40a3b..49ee12bb 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: 97ad4987ce2bc3846413fc90c0ac293ef1d66bf8 + revision: e6e4c8eb7a1dc739492818e45b7ef8196e345b0c version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index 069eb483..4bd4648b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "97ad498" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "e6e4c8e" } # branch: chs-hs export_include_dirs: - hw/include