From 9d0e3b20559798397d8161d91f95ce42915eb4e1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jannis=20Sch=C3=B6nleber?= <joennlae@gmail.com>
Date: Tue, 23 May 2023 16:38:48 +0200
Subject: [PATCH 1/6] feat(verilator): add `verilator` target

---
 Bender.yml                                    |   4 +
 Makefile                                      |   2 +-
 cheshire.mk                                   |  12 ++
 target/verilator/.gitignore                   |   3 +
 target/verilator/patches/permutations.patch   |  59 ++++++++
 .../patches/reg_bus_interface_ugly_copy.sv    |  22 +++
 target/verilator/scripts/install-verilator.sh | 110 +++++++++++++++
 target/verilator/src/cheshire.cpp             | 109 +++++++++++++++
 target/verilator/src/cheshire_testharness.sv  | 131 ++++++++++++++++++
 target/verilator/tools.mk                     |   6 +
 target/verilator/verilator.mk                 |  71 ++++++++++
 11 files changed, 528 insertions(+), 1 deletion(-)
 create mode 100644 target/verilator/.gitignore
 create mode 100644 target/verilator/patches/permutations.patch
 create mode 100644 target/verilator/patches/reg_bus_interface_ugly_copy.sv
 create mode 100755 target/verilator/scripts/install-verilator.sh
 create mode 100644 target/verilator/src/cheshire.cpp
 create mode 100644 target/verilator/src/cheshire_testharness.sv
 create mode 100644 target/verilator/tools.mk
 create mode 100644 target/verilator/verilator.mk

diff --git a/Bender.yml b/Bender.yml
index 7a156aaa..2defd9b1 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -49,3 +49,7 @@ sources:
     files:
       - target/xilinx/src/fan_ctrl.sv
       - target/xilinx/src/cheshire_top_xilinx.sv
+
+  - target: verilator
+    files:
+      - target/verilator/src/cheshire_testharness.sv
diff --git a/Makefile b/Makefile
index 05ef98ea..a1f5f34d 100644
--- a/Makefile
+++ b/Makefile
@@ -6,7 +6,7 @@
 # Christopher Reinwardt <creinwar@student.ethz.ch>
 # Paul Scheffler <paulsc@iis.ee.ethz.ch>
 
-CHS_ROOT ?= .
+CHS_ROOT ?= $(shell pwd)
 
 include cheshire.mk
 
diff --git a/cheshire.mk b/cheshire.mk
index ce114900..baf22dbe 100644
--- a/cheshire.mk
+++ b/cheshire.mk
@@ -151,3 +151,15 @@ $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml
 	$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@
 
 chs-xilinx-all: $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
+
+
+#############
+# Verilator #
+#############
+
+.PHONY: chs-source-env
+
+chs-install-verilator:
+	$(CHS_ROOT)/target/verilator/scripts/install-verilator.sh
+
+include $(CHS_ROOT)/target/verilator/verilator.mk
\ No newline at end of file
diff --git a/target/verilator/.gitignore b/target/verilator/.gitignore
new file mode 100644
index 00000000..97548c97
--- /dev/null
+++ b/target/verilator/.gitignore
@@ -0,0 +1,3 @@
+install/
+obj_dir/
+build/
\ No newline at end of file
diff --git a/target/verilator/patches/permutations.patch b/target/verilator/patches/permutations.patch
new file mode 100644
index 00000000..2a7ca14a
--- /dev/null
+++ b/target/verilator/patches/permutations.patch
@@ -0,0 +1,59 @@
+--- target/verilator/build/cheshire_testharness.pickle.sv	2023-05-23 16:31:40.575735498 +0200
++++ target/verilator/build/cheshire_testharness.pickle_2.sv	2023-05-23 16:32:14.127033084 +0200
+@@ -2330,31 +2330,31 @@
+     longint unsigned rand_number = (A * seed + C) % M;
+ 
+     // do it for each round
+-    for (int unsigned r = 0; r < NoRounds; r++) begin
+-      // initialize the index array
+-      for (int unsigned i = 0; i < InpWidth; i++) begin
+-        indices[r][i] = i;
+-      end
+-      // do the shuffling
+-      for (int unsigned i = 0; i < InpWidth; i++) begin
+-        // get the 'random' number
+-        if (i > 0) begin
+-          rand_number = (A * rand_number + C) % M;
+-          index = rand_number % i;
+-        end
+-        // do the shuffling
+-        if (i != index) begin
+-          perm_array[r][i]     = perm_array[r][index];
+-          perm_array[r][index] = indices[r][i];
+-        end
+-      end
+-      // advance the PRG a bit
+-      rand_number = (A * rand_number + C) % M;
+-      advance     = rand_number % NoRounds;
+-      for (int unsigned i = 0; i < advance; i++) begin
+-        rand_number = (A * rand_number + C) % M;
+-      end
+-    end
++    // for (int unsigned r = 0; r < NoRounds; r++) begin
++    //   // initialize the index array
++    //   for (int unsigned i = 0; i < InpWidth; i++) begin
++    //     indices[r][i] = i;
++    //   end
++    //   // do the shuffling
++    //   for (int unsigned i = 0; i < InpWidth; i++) begin
++    //     // get the 'random' number
++    //     if (i > 0) begin
++    //       rand_number = (A * rand_number + C) % M;
++    //       index = rand_number % i;
++    //     end
++    //     // do the shuffling
++    //     if (i != index) begin
++    //       perm_array[r][i]     = perm_array[r][index];
++    //       perm_array[r][index] = indices[r][i];
++    //     end
++    //   end
++    //   // advance the PRG a bit
++    //   rand_number = (A * rand_number + C) % M;
++    //   advance     = rand_number % NoRounds;
++    //   for (int unsigned i = 0; i < advance; i++) begin
++    //     rand_number = (A * rand_number + C) % M;
++    //   end
++    // end
+     return perm_array;
+   endfunction : get_permutations
+ 
diff --git a/target/verilator/patches/reg_bus_interface_ugly_copy.sv b/target/verilator/patches/reg_bus_interface_ugly_copy.sv
new file mode 100644
index 00000000..5d5684a5
--- /dev/null
+++ b/target/verilator/patches/reg_bus_interface_ugly_copy.sv
@@ -0,0 +1,22 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+interface REG_BUS #(
+  /// The width of the address.
+  parameter int ADDR_WIDTH = -1,
+  /// The width of the data.
+  parameter int DATA_WIDTH = -1
+)(
+  input logic clk_i
+);
+  logic [ADDR_WIDTH-1:0]   addr;
+  logic                    write; // 0=read, 1=write
+  logic [DATA_WIDTH-1:0]   rdata;
+  logic [DATA_WIDTH-1:0]   wdata;
+  logic [DATA_WIDTH/8-1:0] wstrb; // byte-wise strobe
+  logic                    error; // 0=ok, 1=error
+  logic                    valid;
+  logic                    ready;
+  modport in  (input  addr, write, wdata, wstrb, valid, output rdata, error, ready);
+  modport out (output addr, write, wdata, wstrb, valid, input  rdata, error, ready);
+endinterface
\ No newline at end of file
diff --git a/target/verilator/scripts/install-verilator.sh b/target/verilator/scripts/install-verilator.sh
new file mode 100755
index 00000000..509bab82
--- /dev/null
+++ b/target/verilator/scripts/install-verilator.sh
@@ -0,0 +1,110 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+set -e
+
+export RISCV="/usr/pack/riscv-1.0-kgf/riscv64-gcc-11.2.0"
+export PATH="${RISCV}/bin/:$PATH"    # 64-bit
+
+export LIBRARY_PATH=$RISCV/lib
+export LD_LIBRARY_PATH=$RISCV/lib
+export C_INCLUDE_PATH=$RISCV/include
+export CPLUS_INCLUDE_PATH=$RISCV/include
+
+export TOP=${PWD}
+
+export VERILATOR_BUILD_DIR=${TOP}/target/verilator/install/verilator
+export PATH="$VERILATOR_INSTALL_DIR/bin:$PATH"
+
+
+
+# install help2man on our internal machines it is not installed
+# check if help2man is installed
+if ! command -v help2man &> /dev/null
+then
+    echo "help2man could not be found, installing it"
+    HELP2MAN_INSTALL_DIR=${TOP}/target/verilator/install/help2man
+    wget https://ftp.gnu.org/gnu/help2man/help2man-1.49.3.tar.xz -O /tmp/help2man.tar.xz
+    tar -xf /tmp/help2man.tar.xz -C /tmp
+    cd /tmp/help2man-1.49.3
+    ./configure  --prefix=${HELP2MAN_INSTALL_DIR}
+    make
+    make install
+    export PATH=${HELP2MAN_INSTALL_DIR}/bin:$PATH
+fi
+
+
+# number of parallel jobs to use for make commands and simulation
+export NUM_JOBS=16
+
+if [ -z ${NUM_JOBS} ]; then
+    NUM_JOBS=1
+fi
+
+# Ensure the location of tools is known (usually, .../core-v-verif/tools).
+if [ -z "$TOP" ]; then
+  echo "Error: location of core-v-verif 'tools' tree (\$TOP) is not defined."
+  return
+fi
+
+VERILATOR_REPO="https://github.com/verilator/verilator.git"
+VERILATOR_BRANCH="master"
+# Use the release tag instead of a full SHA1 hash.
+VERILATOR_HASH="v5.010"
+VERILATOR_PATCH="$TOP/target/verilator/patches/verilator-v5.patch"
+
+# Unset historical variable VERILATOR_ROOT as it collides with the build process.
+if [ -n "$VERILATOR_ROOT" ]; then
+  unset VERILATOR_ROOT
+fi
+
+# Define the default src+build location of Verilator.
+# No need to force this location in Continuous Integration scripts.
+if [ -z "$VERILATOR_BUILD_DIR" ]; then
+  export VERILATOR_BUILD_DIR=${TOP}/target/verilator/install/verilator
+fi
+
+# Define the default installation location of Verilator: one level up
+# from the source tree in the core-v-verif tree.
+# Continuous Integration may need to override this particular variable
+# to use a preinstalled build of Verilator.
+if [ -z "$VERILATOR_INSTALL_DIR" ]; then
+  export VERILATOR_INSTALL_DIR=$(dirname ${VERILATOR_BUILD_DIR})
+fi
+
+# Build and install Verilator only if not already installed at the expected
+# location $VERILATOR_INSTALL_DIR.
+if [ ! -f "$VERILATOR_INSTALL_DIR/bin/verilator" ]; then
+    echo "Building Verilator in $VERILATOR_BUILD_DIR..."
+    echo "Verilator will be installed in $VERILATOR_INSTALL_DIR"
+    echo "VERILATOR_REPO=$VERILATOR_REPO"
+    echo "VERILATOR_BRANCH=$VERILATOR_BRANCH"
+    echo "VERILATOR_HASH=$VERILATOR_HASH"
+    echo "VERILATOR_PATCH=$VERILATOR_PATCH"
+    mkdir -p $VERILATOR_BUILD_DIR
+    cd $VERILATOR_BUILD_DIR
+    # Clone only if the ".git" directory does not exist.
+    # Do not remove the content arbitrarily if ".git" does not exist in order
+    # to preserve user content - let git fail instead.
+    [ -d .git ] || git clone $VERILATOR_REPO -b $VERILATOR_BRANCH .
+    git checkout $VERILATOR_HASH
+    # if [ ! -z "$VERILATOR_PATCH" ] ; then
+    #   # git apply $VERILATOR_PATCH || true
+    # fi
+    # Generate the config script and configure Verilator.
+    autoconf && ./configure --prefix="$VERILATOR_INSTALL_DIR" && make -j${NUM_JOBS}
+    # FORNOW: Accept failure in 'make test' (segfault issue on Debian10)
+    # make test || true
+    echo "Installing Verilator in $VERILATOR_INSTALL_DIR..."
+    make install
+    echo "VERILATOR is installed"
+else
+    echo "Using Verilator from cached directory $VERILATOR_INSTALL_DIR."
+fi
+
diff --git a/target/verilator/src/cheshire.cpp b/target/verilator/src/cheshire.cpp
new file mode 100644
index 00000000..a292091e
--- /dev/null
+++ b/target/verilator/src/cheshire.cpp
@@ -0,0 +1,109 @@
+// Licensed to the Apache Software Foundation (ASF) under one
+// or more contributor license agreements.  See the NOTICE file
+// distributed with this work for additional information
+// regarding copyright ownership.  The ASF licenses this file
+// to you under the Apache License, Version 2.0 (the
+// "License"); you may not use this file except in compliance
+// with the License.  You may obtain a copy of the License at
+
+//   http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing,
+// software distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+
+// #include "verilator.h"
+//#include "elfloader.h"
+#include "verilated.h"
+#include "Vcheshire_testharness.h"
+#include <verilated_vcd_c.h>
+#if (VERILATOR_VERSION_INTEGER >= 5000000)
+  // Verilator v5 adds $root wrapper that provides rootp pointer.
+  #include "Vcheshire_testharness___024root.h"
+#endif
+
+// #include <fesvr/dtm.h>
+#include <fesvr/htif_hexwriter.h>
+#include <fesvr/elfloader.h>
+#include <string>
+#include <cstring>
+#include <cassert>
+#include <stdio.h>
+#include <iostream>
+#include <iomanip>
+#include <string>
+#include <getopt.h>
+#include <chrono>
+#include <ctime>
+#include <signal.h>
+#include <unistd.h>
+
+// This software is heavily based on Rocket Chip
+// Checkout this awesome project:
+// https://github.com/freechipsproject/rocket-chip/
+
+
+// This is a 64-bit integer to reduce wrap over issues and
+// allow modulus.  You can also use a double, if you wish.
+static vluint64_t main_time = 0;
+int clk_ratio = 2;
+
+static void cycle_start(std::shared_ptr<Vcheshire_testharness> top){
+  top->rtc_i = 1;
+  top->jtag_tck = 1;
+  for (int i = 0; i < clk_ratio; i++){
+    top->clk_i = 1;
+    top->rtc_i = 1;
+    printf("tick\n");
+    top->eval();
+    main_time += 2500;
+    top->clk_i = 0;
+    top->rtc_i = 0;
+    top->eval();
+    main_time += 2500;
+  }
+}
+
+static void cycle_end(std::shared_ptr<Vcheshire_testharness> top){
+  top->rtc_i = 0;
+  for (int i = 0; i < clk_ratio; i++){
+    top->clk_i = 1;
+    top->rtc_i = 1;
+    top->eval();
+    main_time += 2500;
+    top->clk_i = 0;
+    top->rtc_i = 0;
+    top->eval();
+    main_time += 2500;
+  }
+}
+
+static void wait_cycles(std::shared_ptr<Vcheshire_testharness> top, 
+                        int cycles){
+  for(int i = 0; i < cycles; i++){
+      cycle_start(top);
+      cycle_end(top);
+  }
+}
+
+
+int main(int argc, char **argv) {
+
+  Verilated::commandArgs(argc, argv);
+  std::shared_ptr<Vcheshire_testharness> top(new Vcheshire_testharness);
+
+  // reset 
+  for (int i = 0; i < 10; i++) {
+    top->rst_ni = 0;
+    top->rtc_i = 0;
+    wait_cycles(top, 5);
+  }
+  top->rst_ni = 1;
+
+  top->final();
+
+  return 0;
+}
\ No newline at end of file
diff --git a/target/verilator/src/cheshire_testharness.sv b/target/verilator/src/cheshire_testharness.sv
new file mode 100644
index 00000000..a3428cfa
--- /dev/null
+++ b/target/verilator/src/cheshire_testharness.sv
@@ -0,0 +1,131 @@
+module cheshire_testharness import cheshire_pkg::*; (
+  input  logic             clk_i,
+  input  logic             rtc_i,
+  input  logic             rst_ni,
+  
+  input  logic             jtag_tck,
+  input  logic             jtag_tms,
+  input  logic             jtag_trst_n,
+  input  logic             jtag_tdi,
+  output logic             jtag_tdo,
+  
+  output logic [31:0]      exit_o,
+
+  input   logic               test_mode_i,
+
+  // Boot mode selection
+  input   logic [1:0]         boot_mode_i,
+
+  // Serial Link
+  input   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0]  slink_i,
+  output  logic [SlinkNumChan-1:0][SlinkNumLanes-1:0]  slink_o,
+  input   logic [SlinkNumChan-1:0]                     slink_rcv_clk_i,
+  output  logic [SlinkNumChan-1:0]                     slink_rcv_clk_o,
+
+  // VGA Controller
+  output  logic                                   vga_hsync_o,
+  output  logic                                   vga_vsync_o,
+  output  logic [DefaultCfg.VgaRedWidth-1:0]      vga_red_o,
+  output  logic [DefaultCfg.VgaGreenWidth-1:0]    vga_green_o,
+  output  logic [DefaultCfg.VgaBlueWidth-1:0]     vga_blue_o,
+
+  // UART Interface
+  output logic                uart_tx_o,
+  input  logic                uart_rx_i,
+
+  // I2C Interface
+  output logic                i2c_sda_o,
+  input  logic                i2c_sda_i,
+  output logic                i2c_sda_en_o,
+  output logic                i2c_scl_o,
+  input  logic                i2c_scl_i,
+  output logic                i2c_scl_en_o,
+
+  // SPI Host Interface
+  output logic                spih_sck_o,
+  output logic                spih_sck_en_o,
+  output logic [ SpihNumCs-1:0]         spih_csb_o,
+  output logic [ SpihNumCs-1:0]         spih_csb_en_o,
+  output logic [ 3:0]         spih_sd_o,
+  output logic [ 3:0]         spih_sd_en_o,
+  input  logic [ 3:0]         spih_sd_i,
+
+
+  // GPIO interface
+  input  logic [ 7:0]         gpio_i,
+  output logic [ 7:0]         gpio_o,
+  output logic [ 7:0]         gpio_en_o
+);
+
+
+  `include "cheshire/typedef.svh"
+
+  import cheshire_pkg::*;
+
+  localparam cheshire_cfg_t DutCfg = DefaultCfg;
+  `CHESHIRE_TYPEDEF_ALL(, DutCfg)
+
+  cheshire_soc #(
+    .Cfg                ( DutCfg ),
+    .ExtHartinfo        ( '0 ),
+    .axi_ext_llc_req_t  ( axi_llc_req_t ),
+    .axi_ext_llc_rsp_t  ( axi_llc_rsp_t ),
+    .axi_ext_mst_req_t  ( axi_mst_req_t ),
+    .axi_ext_mst_rsp_t  ( axi_mst_rsp_t ),
+    .axi_ext_slv_req_t  ( axi_slv_req_t ),
+    .axi_ext_slv_rsp_t  ( axi_slv_rsp_t ),
+    .reg_ext_req_t      ( reg_req_t ),
+    .reg_ext_rsp_t      ( reg_rsp_t )
+  ) i_cheshire (
+      .clk_i                  ( clk_i                 ),
+      .rst_ni                 ( rst_ni                ),
+
+      .test_mode_i            ( test_mode_i           ),
+
+      .jtag_tck_i             ( jtag_tck              ),
+      .jtag_trst_ni           ( jtag_trst_n           ),
+      .jtag_tms_i             ( jtag_tms              ),
+      .jtag_tdi_i             ( jtag_tdi              ),
+      .jtag_tdo_o             ( jtag_tdo              ),
+
+      .rtc_i                  ( rtc_i                 ),
+
+      .boot_mode_i            ( boot_mode_i           ),
+
+      .slink_i                ( slink_i               ),
+      .slink_o                ( slink_o               ),
+
+      .slink_rcv_clk_i        ( slink_rcv_clk_i       ),
+      .slink_rcv_clk_o        ( slink_rcv_clk_o       ),
+
+      .vga_hsync_o            ( vga_hsync_o           ),
+      .vga_vsync_o            ( vga_vsync_o           ),
+      .vga_red_o              ( vga_red_o             ),
+      .vga_green_o            ( vga_green_o           ),
+      .vga_blue_o             ( vga_blue_o            ),
+
+      .uart_tx_o              ( uart_tx_o             ),
+      .uart_rx_i              ( uart_rx_i             ),
+
+      .i2c_sda_o              ( i2c_sda_o             ),
+      .i2c_sda_i              ( i2c_sda_i             ),
+      .i2c_sda_en_o           ( i2c_sda_en_o          ),
+      .i2c_scl_o              ( i2c_scl_o             ),
+      .i2c_scl_i              ( i2c_scl_i             ),
+      .i2c_scl_en_o           ( i2c_scl_en_o          ),
+
+      .spih_sck_o             ( spih_sck_o            ),
+      .spih_sck_en_o          (  spih_sck_en_o        ),
+      .spih_csb_o             ( spih_csb_o            ),
+      .spih_csb_en_o          ( spih_csb_en_o         ),
+      .spih_sd_o              ( spih_sd_o             ),
+      .spih_sd_en_o           ( spih_sd_en_o          ),
+      .spih_sd_i              ( spih_sd_i             ),
+
+      .gpio_i                 ( gpio_o                ),
+      .gpio_o                 ( gpio_o                ),
+      .gpio_en_o              ( gpio_en_o             )
+  );
+
+
+endmodule
diff --git a/target/verilator/tools.mk b/target/verilator/tools.mk
new file mode 100644
index 00000000..3b3b1a63
--- /dev/null
+++ b/target/verilator/tools.mk
@@ -0,0 +1,6 @@
+# TODO change once we have correct tools installed with DZ
+OPENROAD_ROOT := /usr/scratch/schneematt/janniss/Documents/openroad-build/install
+# sourcing yosys and sv2v
+export PATH := $(OPENROAD_ROOT)/bin:$(PATH)
+# sourcing svase and morty
+export PATH := $(PATH):/usr/scratch/pisoc11/sem23f30/tools/bin
diff --git a/target/verilator/verilator.mk b/target/verilator/verilator.mk
new file mode 100644
index 00000000..78ec5236
--- /dev/null
+++ b/target/verilator/verilator.mk
@@ -0,0 +1,71 @@
+VERILATOR_ROOT = $(CHS_ROOT)/target/verilator/install/verilator
+VERILATOR_SRC_PATH = $(CHS_ROOT)/target/verilator/src
+export VERILATOR_ROOT
+VERILATOR = $(VERILATOR_ROOT)/bin/verilator
+
+RISCV = /usr/pack/riscv-1.0-kgf/riscv64-gcc-11.2.0
+
+C_INCLUDE_PATH=${RISCV}/include
+CPLUS_INCLUDE_PATH=${RISCV}/include
+export C_INCLUDE_PATH
+export CPLUS_INCLUDE_PATH
+
+BENDER 		?= bender	# https://github.com/pulp-platform/bender
+MORTY			?= morty	# https://github.com/pulp-platform/morty
+
+include $(CHS_ROOT)/target/verilator/tools.mk
+
+VERILATOR_FLAGS += --cc --no-timing
+VERILATOR_FLAGS += --error-limit 4419 --unroll-count 256 -Wno-fatal
+VERILATOR_FLAGS += -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-PINMISSING -Wno-MODDUP -Wno-UNOPTFLAT -Wno-BLKANDNBLK -Wno-UNUSED -Wno-ASCRANGE
+VERILATOR_EXE += --exe cheshire.cpp
+
+VERILATOR_CFILES += $(VERILATOR_SRC_PATH)/cheshire.cpp
+VERILATOR_FESVR = -LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr"
+
+VERILATOR_OUTPUT = --Mdir $(CHS_ROOT)/target/verilator/obj_dir
+
+BENDER = bender
+BENDER_FLIST = bender script flist -t sim -t cv64a6_imafdc_sv39 -t test -t verilator -t cva6 -D VERILATOR=1 > flist.txt
+BENDER_SCRIPT = $(shell bender script verilator -t sim -t cv64a6_imafdc_sv39 -t verilator -t cva6 -D VERILATOR=1)
+
+# VERILATOR_INPUT = $(VERILATOR_SRC_PATH)/cheshire_testharness.sv
+VERILATOR_TOPMODULE = --top-module cheshire_testharness
+
+# Project variables
+TOP_DESIGN	= cheshire_testharness
+PICKLE_FILE := $(CHS_ROOT)/target/verilator/build/$(TOP_DESIGN).pickle.sv
+
+
+$(CHS_ROOT)/target/verilator/build/sources.json:
+	@mkdir -p $(@D)
+	$(BENDER) sources -f -t sim -t cv64a6_imafdc_sv39 -t cva6 -t verilator > $@
+
+chs-verilate-pickle: $(CHS_ROOT)/target/verilator/build/sources.json
+	@mkdir -p $(@D)
+	sed "s| << riscv::XLEN-2| << (riscv::XLEN-2)|g" $(shell $(BENDER) path cva6)/core/include/ariane_pkg.sv > ariane_pkg.tmp
+	mv ariane_pkg.tmp $(shell $(BENDER) path cva6)/core/include/ariane_pkg.sv
+	$(MORTY) -f $< -q -o $(PICKLE_FILE) -D VERILATOR=1 --keep_defines --top $(TOP_DESIGN)
+	# applying patches
+	cat $(CHS_ROOT)/target/verilator/patches/reg_bus_interface_ugly_copy.sv >> $(PICKLE_FILE)  	# Todo: fix REGBUS copy in morty
+	sed -i "s/\s*req_q <= (store_req_t'.*/      req_q <= (store_req_t'{mode: axi_llc_pkg::tag_mode_e'(2'b0), default: '0});/g" $(PICKLE_FILE)
+	patch -u $(PICKLE_FILE) -i $(CHS_ROOT)/target/verilator/patches/permutations.patch
+
+chs-verilate-command := \
+	$(VERILATOR) \
+	$(VERILATOR_FLAGS) \
+	$(VERILATOR_FESVR) \
+	$(PICKLE_FILE) \
+	$(VERILATOR_INPUT) \
+	$(VERILATOR_TOPMODULE) \
+	$(VERILATOR_EXE) \
+	$(VERILATOR_CFILES) \
+	$(VERILATOR_OUTPUT)
+
+chs-verilate: chs-verilate-pickle
+	rm -rf $(CHS_ROOT)/target/verilator/obj_dir 
+	$(chs-verilate-command)
+	cd $(CHS_ROOT)/target/verilator/obj_dir && $(MAKE) -f Vcheshire_testharness.mk Vcheshire_testharness
+
+chs-verilate-run: chs-verilate
+	$(CHS_ROOT)/target/verilator/obj_dir/Vcheshire_testharness

From c50a67a172caa6957480873df40dd67657fa022d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jannis=20Sch=C3=B6nleber?= <joennlae@gmail.com>
Date: Tue, 23 May 2023 16:40:04 +0200
Subject: [PATCH 2/6] style: use correct 64bit wide assignment

---
 hw/cheshire_pkg.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
index 0b7aa3f7..6fdee6dc 100644
--- a/hw/cheshire_pkg.sv
+++ b/hw/cheshire_pkg.sv
@@ -431,7 +431,7 @@ package cheshire_pkg;
     LlcAmoPostCut     : 1,
     LlcOutConnect     : 1,
     LlcOutRegionStart : 'h8000_0000,
-    LlcOutRegionEnd   : 'h1_0000_0000,
+    LlcOutRegionEnd   : 64'h1_0000_0000,
     // VGA: RGB332
     VgaRedWidth       : 3,
     VgaGreenWidth     : 3,
@@ -442,8 +442,8 @@ package cheshire_pkg;
     SlinkMaxTxnsPerId : 4,
     SlinkMaxUniqIds   : 4,
     SlinkMaxClkDiv    : 1024,
-    SlinkRegionStart  : 'h1_0000_0000,
-    SlinkRegionEnd    : 'h2_0000_0000,
+    SlinkRegionStart  : 64'h1_0000_0000,
+    SlinkRegionEnd    : 64'h2_0000_0000,
     SlinkTxAddrMask   : 'hFFFF_FFFF,
     SlinkTxAddrDomain : 'h0000_0000,
     SlinkUserAmoBit   : 1,  // Upper atomics bit for serial link

From 91e892087ef1d359f1a76b665845a8be103a1823 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jannis=20Sch=C3=B6nleber?= <joennlae@gmail.com>
Date: Tue, 23 May 2023 17:09:33 +0200
Subject: [PATCH 3/6] chore: add license headers

---
 target/verilator/scripts/install-verilator.sh | 11 ++++----
 target/verilator/src/cheshire.cpp             | 26 ++++++-------------
 target/verilator/src/cheshire_testharness.sv  |  6 +++++
 target/verilator/tools.mk                     |  4 +++
 target/verilator/verilator.mk                 |  6 +++++
 5 files changed, 29 insertions(+), 24 deletions(-)

diff --git a/target/verilator/scripts/install-verilator.sh b/target/verilator/scripts/install-verilator.sh
index 509bab82..178cc3e8 100755
--- a/target/verilator/scripts/install-verilator.sh
+++ b/target/verilator/scripts/install-verilator.sh
@@ -1,11 +1,10 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+# inspired from https://github.com/zchamski/core-v-verif/blob/046a50d58648bafdb2263dee53e1043e83057284/cva6/regress/install-verilator.sh
 # Copyright 2021 Thales DIS design services SAS
-#
-# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-# You may obtain a copy of the License at https://solderpad.org/licenses/
-#
 # Original Author: Jean-Roch COULON - Thales
+# Heavily adapted by Jannis Schönleber - ETH Zurich
 
 set -e
 
diff --git a/target/verilator/src/cheshire.cpp b/target/verilator/src/cheshire.cpp
index a292091e..be4cb065 100644
--- a/target/verilator/src/cheshire.cpp
+++ b/target/verilator/src/cheshire.cpp
@@ -1,22 +1,12 @@
-// Licensed to the Apache Software Foundation (ASF) under one
-// or more contributor license agreements.  See the NOTICE file
-// distributed with this work for additional information
-// regarding copyright ownership.  The ASF licenses this file
-// to you under the Apache License, Version 2.0 (the
-// "License"); you may not use this file except in compliance
-// with the License.  You may obtain a copy of the License at
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Modified version of the CVA6 testbench
+// (https://github.com/openhwgroup/cva6, 99acdc271b90ce5abeb1b682eff4f999d0977ff4)
+//
+// Jannis Schönleber
 
-//   http://www.apache.org/licenses/LICENSE-2.0
-
-// Unless required by applicable law or agreed to in writing,
-// software distributed under the License is distributed on an
-// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-// KIND, either express or implied.  See the License for the
-// specific language governing permissions and limitations
-// under the License.
-
-// #include "verilator.h"
-//#include "elfloader.h"
 #include "verilated.h"
 #include "Vcheshire_testharness.h"
 #include <verilated_vcd_c.h>
diff --git a/target/verilator/src/cheshire_testharness.sv b/target/verilator/src/cheshire_testharness.sv
index a3428cfa..dd2f038b 100644
--- a/target/verilator/src/cheshire_testharness.sv
+++ b/target/verilator/src/cheshire_testharness.sv
@@ -1,3 +1,9 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Jannis Schönleber <janniss@iis.ee.ethz.ch>
+
 module cheshire_testharness import cheshire_pkg::*; (
   input  logic             clk_i,
   input  logic             rtc_i,
diff --git a/target/verilator/tools.mk b/target/verilator/tools.mk
index 3b3b1a63..2db60b0f 100644
--- a/target/verilator/tools.mk
+++ b/target/verilator/tools.mk
@@ -1,3 +1,7 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
 # TODO change once we have correct tools installed with DZ
 OPENROAD_ROOT := /usr/scratch/schneematt/janniss/Documents/openroad-build/install
 # sourcing yosys and sv2v
diff --git a/target/verilator/verilator.mk b/target/verilator/verilator.mk
index 78ec5236..a1aaf18f 100644
--- a/target/verilator/verilator.mk
+++ b/target/verilator/verilator.mk
@@ -1,3 +1,9 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Jannis Schönleber, ETH Zurich
+
 VERILATOR_ROOT = $(CHS_ROOT)/target/verilator/install/verilator
 VERILATOR_SRC_PATH = $(CHS_ROOT)/target/verilator/src
 export VERILATOR_ROOT

From 1b6208a4fd50502b532e65feb5cf53fd9fb5bf1c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jannis=20Sch=C3=B6nleber?= <joennlae@gmail.com>
Date: Tue, 23 May 2023 17:09:57 +0200
Subject: [PATCH 4/6] style: clang-format verilator testbench

---
 target/verilator/src/cheshire.cpp | 48 +++++++++++++++----------------
 1 file changed, 23 insertions(+), 25 deletions(-)

diff --git a/target/verilator/src/cheshire.cpp b/target/verilator/src/cheshire.cpp
index be4cb065..6ca25884 100644
--- a/target/verilator/src/cheshire.cpp
+++ b/target/verilator/src/cheshire.cpp
@@ -3,48 +3,47 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 // Modified version of the CVA6 testbench
-// (https://github.com/openhwgroup/cva6, 99acdc271b90ce5abeb1b682eff4f999d0977ff4)
+// (https://github.com/openhwgroup/cva6,
+// 99acdc271b90ce5abeb1b682eff4f999d0977ff4)
 //
 // Jannis Schönleber
 
-#include "verilated.h"
 #include "Vcheshire_testharness.h"
+#include "verilated.h"
 #include <verilated_vcd_c.h>
 #if (VERILATOR_VERSION_INTEGER >= 5000000)
-  // Verilator v5 adds $root wrapper that provides rootp pointer.
-  #include "Vcheshire_testharness___024root.h"
+// Verilator v5 adds $root wrapper that provides rootp pointer.
+#include "Vcheshire_testharness___024root.h"
 #endif
 
 // #include <fesvr/dtm.h>
-#include <fesvr/htif_hexwriter.h>
-#include <fesvr/elfloader.h>
-#include <string>
-#include <cstring>
 #include <cassert>
-#include <stdio.h>
-#include <iostream>
-#include <iomanip>
-#include <string>
-#include <getopt.h>
 #include <chrono>
+#include <cstring>
 #include <ctime>
+#include <fesvr/elfloader.h>
+#include <fesvr/htif_hexwriter.h>
+#include <getopt.h>
+#include <iomanip>
+#include <iostream>
 #include <signal.h>
+#include <stdio.h>
+#include <string>
 #include <unistd.h>
 
 // This software is heavily based on Rocket Chip
 // Checkout this awesome project:
 // https://github.com/freechipsproject/rocket-chip/
 
-
 // This is a 64-bit integer to reduce wrap over issues and
 // allow modulus.  You can also use a double, if you wish.
 static vluint64_t main_time = 0;
 int clk_ratio = 2;
 
-static void cycle_start(std::shared_ptr<Vcheshire_testharness> top){
+static void cycle_start(std::shared_ptr<Vcheshire_testharness> top) {
   top->rtc_i = 1;
   top->jtag_tck = 1;
-  for (int i = 0; i < clk_ratio; i++){
+  for (int i = 0; i < clk_ratio; i++) {
     top->clk_i = 1;
     top->rtc_i = 1;
     printf("tick\n");
@@ -57,9 +56,9 @@ static void cycle_start(std::shared_ptr<Vcheshire_testharness> top){
   }
 }
 
-static void cycle_end(std::shared_ptr<Vcheshire_testharness> top){
+static void cycle_end(std::shared_ptr<Vcheshire_testharness> top) {
   top->rtc_i = 0;
-  for (int i = 0; i < clk_ratio; i++){
+  for (int i = 0; i < clk_ratio; i++) {
     top->clk_i = 1;
     top->rtc_i = 1;
     top->eval();
@@ -71,21 +70,20 @@ static void cycle_end(std::shared_ptr<Vcheshire_testharness> top){
   }
 }
 
-static void wait_cycles(std::shared_ptr<Vcheshire_testharness> top, 
-                        int cycles){
-  for(int i = 0; i < cycles; i++){
-      cycle_start(top);
-      cycle_end(top);
+static void wait_cycles(std::shared_ptr<Vcheshire_testharness> top,
+                        int cycles) {
+  for (int i = 0; i < cycles; i++) {
+    cycle_start(top);
+    cycle_end(top);
   }
 }
 
-
 int main(int argc, char **argv) {
 
   Verilated::commandArgs(argc, argv);
   std::shared_ptr<Vcheshire_testharness> top(new Vcheshire_testharness);
 
-  // reset 
+  // reset
   for (int i = 0; i < 10; i++) {
     top->rst_ni = 0;
     top->rtc_i = 0;

From 33760aa1c115cf4438d5ae83391e60f82606e80e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jannis=20Sch=C3=B6nleber?= <joennlae@gmail.com>
Date: Tue, 23 May 2023 17:13:51 +0200
Subject: [PATCH 5/6] style: add `clang-format` file representing the style
 checked in ci

---
 .clang-format | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 .clang-format

diff --git a/.clang-format b/.clang-format
new file mode 100644
index 00000000..ef853095
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,7 @@
+IndentWidth: 4
+ColumnLimit: 100
+AlignEscapedNewlines: DontAlign
+SortIncludes: false
+AllowShortFunctionsOnASingleLine: None
+AllowShortIfStatementsOnASingleLine: true
+AllowShortLoopsOnASingleLine: true

From f000c395582e0a200a1b0c02e838abdb122204c0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jannis=20Sch=C3=B6nleber?= <joennlae@gmail.com>
Date: Tue, 23 May 2023 17:14:22 +0200
Subject: [PATCH 6/6] style: clang-format

---
 target/verilator/src/cheshire.cpp | 77 +++++++++++++++----------------
 1 file changed, 38 insertions(+), 39 deletions(-)

diff --git a/target/verilator/src/cheshire.cpp b/target/verilator/src/cheshire.cpp
index 6ca25884..d65ec1f7 100644
--- a/target/verilator/src/cheshire.cpp
+++ b/target/verilator/src/cheshire.cpp
@@ -41,57 +41,56 @@ static vluint64_t main_time = 0;
 int clk_ratio = 2;
 
 static void cycle_start(std::shared_ptr<Vcheshire_testharness> top) {
-  top->rtc_i = 1;
-  top->jtag_tck = 1;
-  for (int i = 0; i < clk_ratio; i++) {
-    top->clk_i = 1;
     top->rtc_i = 1;
-    printf("tick\n");
-    top->eval();
-    main_time += 2500;
-    top->clk_i = 0;
-    top->rtc_i = 0;
-    top->eval();
-    main_time += 2500;
-  }
+    top->jtag_tck = 1;
+    for (int i = 0; i < clk_ratio; i++) {
+        top->clk_i = 1;
+        top->rtc_i = 1;
+        printf("tick\n");
+        top->eval();
+        main_time += 2500;
+        top->clk_i = 0;
+        top->rtc_i = 0;
+        top->eval();
+        main_time += 2500;
+    }
 }
 
 static void cycle_end(std::shared_ptr<Vcheshire_testharness> top) {
-  top->rtc_i = 0;
-  for (int i = 0; i < clk_ratio; i++) {
-    top->clk_i = 1;
-    top->rtc_i = 1;
-    top->eval();
-    main_time += 2500;
-    top->clk_i = 0;
     top->rtc_i = 0;
-    top->eval();
-    main_time += 2500;
-  }
+    for (int i = 0; i < clk_ratio; i++) {
+        top->clk_i = 1;
+        top->rtc_i = 1;
+        top->eval();
+        main_time += 2500;
+        top->clk_i = 0;
+        top->rtc_i = 0;
+        top->eval();
+        main_time += 2500;
+    }
 }
 
-static void wait_cycles(std::shared_ptr<Vcheshire_testharness> top,
-                        int cycles) {
-  for (int i = 0; i < cycles; i++) {
-    cycle_start(top);
-    cycle_end(top);
-  }
+static void wait_cycles(std::shared_ptr<Vcheshire_testharness> top, int cycles) {
+    for (int i = 0; i < cycles; i++) {
+        cycle_start(top);
+        cycle_end(top);
+    }
 }
 
 int main(int argc, char **argv) {
 
-  Verilated::commandArgs(argc, argv);
-  std::shared_ptr<Vcheshire_testharness> top(new Vcheshire_testharness);
+    Verilated::commandArgs(argc, argv);
+    std::shared_ptr<Vcheshire_testharness> top(new Vcheshire_testharness);
 
-  // reset
-  for (int i = 0; i < 10; i++) {
-    top->rst_ni = 0;
-    top->rtc_i = 0;
-    wait_cycles(top, 5);
-  }
-  top->rst_ni = 1;
+    // reset
+    for (int i = 0; i < 10; i++) {
+        top->rst_ni = 0;
+        top->rtc_i = 0;
+        wait_cycles(top, 5);
+    }
+    top->rst_ni = 1;
 
-  top->final();
+    top->final();
 
-  return 0;
+    return 0;
 }
\ No newline at end of file