From 0968e28d3b8c8131e526356b4bbfaa57a62c5f34 Mon Sep 17 00:00:00 2001 From: Gianna Paulin Date: Mon, 31 Jul 2023 17:09:23 +0200 Subject: [PATCH] ci: Add first github and gitlab CI checks --- .github/workflows/ci.yml | 126 +++++++++++++++++ .github/workflows/gitlab-ci.yaml | 27 ++++ .github/workflows/lint.yml | 118 ++++++++++++++++ .gitlab-ci.yml | 236 +++++++++++++++++++++++++++++++ deps/snitch_cluster | 1 - util/lint/.yamllint.yml | 25 ++++ util/occamygen/occamy.py | 2 +- util/occamygen/occamygen.py | 17 ++- util/solder/solder.py | 14 +- 9 files changed, 552 insertions(+), 14 deletions(-) create mode 100644 .github/workflows/ci.yml create mode 100644 .github/workflows/gitlab-ci.yaml create mode 100644 .github/workflows/lint.yml create mode 100644 .gitlab-ci.yml delete mode 120000 deps/snitch_cluster create mode 100644 util/lint/.yamllint.yml diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 000000000..f09009e8d --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,126 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Run functional regression checks +name: ci +on: [push, pull_request] +jobs: + + ######## + # Docs # + ######## + + # docs: + # name: Build documentation + # runs-on: ubuntu-22.04 + # container: + # image: ghcr.io/pulp-platform/snitch_cluster + # steps: + # - uses: actions/checkout@v2 + # - name: Build docs + # run: mkdocs build + + ###################################### + # Simulate SW on Occamy w/ Verilator # + ###################################### + + sw-occamy-vlt: + name: Simulate SW on Occamy w/ Verilator + runs-on: ubuntu-22.04 + container: + image: ghcr.io/pulp-platform/snitch_cluster + steps: + - uses: actions/checkout@v2 + with: + submodules: 'recursive' + # - name: Build MUSL dependency + # run: | + # cd sw/deps + # mkdir install + # cd musl + # CC=$LLVM_BINROOT/clang ./configure --disable-shared \ + # --prefix=../install/ --enable-wrapper=all \ + # CFLAGS="-mcpu=snitch -menable-experimental-extensions" + # make -j4 + # make install + # cd ../../../ + - name: Get Bender dependencies + run: | + export SNITCH_CLUSTER_ROOT=$($BENDER path snitch_cluster) + - name: Build Software + run: | + make -C target/sim sw + - name: Build Hardware + run: | + make -C target/sim bin/occamy.vlt + # - name: Run Unit Tests + # working-directory: target/sim + # run: |- + # ./sw/tests/run.py sw/tests/passing-apps.list --simulator verilator \ + # 2>&1 | tee tests.log + # - name: Run Test Applications + # working-directory: target/sim + # env: + # SNITCH_LOG: info + # run: |- + # ./sw/apps/run.py sw/apps/passing-apps.list --simulator verilator \ + # 2>&1 | tee apps.log + # - name: Check Unit Tests + # working-directory: target/sim + # run: |- + # grep -zoP 'All tests passed' tests.log + # - name: Check Test Applications + # working-directory: target/sim + # run: |- + # grep -zoP 'All tests passed' apps.log + + ############################################ + # Build SW on Snitch Cluster w/ Banshee # + ############################################ + + # sw-snitch-cluster-banshee: + # name: Simulate SW on Snitch Cluster w/ Banshee + # runs-on: ubuntu-22.04 + # container: + # image: ghcr.io/pulp-platform/snitch_cluster + # steps: + # - uses: actions/checkout@v2 + # with: + # submodules: 'recursive' + # - name: Build MUSL dependency + # run: | + # cd sw/deps + # mkdir install + # cd musl + # CC=$LLVM_BINROOT/clang ./configure --disable-shared \ + # --prefix=../install/ --enable-wrapper=all \ + # CFLAGS="-mcpu=snitch -menable-experimental-extensions" + # make -j4 + # make install + # cd ../../../ + # - name: Build Software + # run: | + # make -C target/snitch_cluster SELECT_RUNTIME=banshee sw + # - name: Run Unit Tests + # working-directory: target/snitch_cluster + # env: + # SNITCH_LOG: info + # run: |- + # ./sw/tests/run.py sw/tests/banshee-apps.list --simulator banshee \ + # 2>&1 | tee tests.log + # - name: Run Test Applications + # working-directory: target/snitch_cluster + # env: + # SNITCH_LOG: info + # run: |- + # ./sw/apps/run.py sw/apps/passing-apps.list --simulator banshee \ + # 2>&1 | tee apps.log + # - name: Check Unit Tests + # working-directory: target/snitch_cluster + # run: |- + # grep -zoP 'All tests passed' tests.log + # - name: Check Test Applications + # working-directory: target/snitch_cluster + # run: |- + # grep -zoP 'All tests passed' apps.log diff --git a/.github/workflows/gitlab-ci.yaml b/.github/workflows/gitlab-ci.yaml new file mode 100644 index 000000000..c2a2649c6 --- /dev/null +++ b/.github/workflows/gitlab-ci.yaml @@ -0,0 +1,27 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Some CI tests run on our GitLab servers due to licenses and tools +name: gitlab-ci +on: [push, pull_request, workflow_dispatch] +jobs: + gitlab-ci: + name: Internal Gitlab CI + runs-on: ubuntu-22.04 + steps: + - name: Check Gitlab CI + uses: pulp-platform/pulp-actions/gitlab-ci@v2.1.0 + # Skip on forks or pull requests from forks due to missing secrets. + if: + # yamllint disable rule:line-length + github.repository == 'pulp-platform/occamy' && (github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name == github.repository) + # yamllint enable rule:line-length + with: + domain: iis-git.ee.ethz.ch + repo: github-mirror/occamy + token: ${{ secrets.GITLAB_TOKEN }} + poll-period: 20 + poll-count: 1000 + retry-count: 100 + retry-period: 50 diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml new file mode 100644 index 000000000..59dfc8bfc --- /dev/null +++ b/.github/workflows/lint.yml @@ -0,0 +1,118 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Run all lint checks +name: lint +on: [push, pull_request] + +jobs: + + ################ + # Verible Lint # + ################ + verible-lint: + name: Lint Verilog sources + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + - uses: chipsalliance/verible-linter-action@main + with: + paths: | + ./hw + github_token: ${{ secrets.GITHUB_TOKEN }} + fail_on_error: true + reviewdog_reporter: github-check + extra_args: "--waiver_files util/lint/waiver.verible" + verible_version: "v0.0-3318-g8d254167" + + ##################### + # Vendor Up-to-Date # + ##################### + bender-vendor-up-to-date: + name: Check bender vendor up-to-date + runs-on: ubuntu-latest + steps: + - name: Check bender vendor up-to-date + uses: pulp-platform/pulp-actions/bender-vendor-up-to-date@v2.1.0 + + ################# + # Check License # + ################# + license-lint: + name: Check License headers + runs-on: ubuntu-latest + steps: + - name: Check License + uses: pulp-platform/pulp-actions/lint-license@v2.1.0 + with: + patches: 0001-Allow-hash-comments-in-assembly.patch + # We cover ETH Zurich and lowRISC licenses and Apache 2.0 + # (mostly for SW) and Solderpad for the hardware. + # yamllint disable rule:line-length + license: | + Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors). + (Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details. + SPDX-License-Identifier: (SHL-0.51|Apache-2.0) + # yamllint enable rule:line-length + match_regex: true + exclude_paths: | + sw/snRuntime/src/omp/interface.h + hw/vendor/openhwgroup_cva6 + util/solder/solder.*.tpl + + ################## + # Lint YML Files # + ################## + yaml-lint: + name: Lint YAML Sources + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + - name: yaml-lint + uses: ibiqlik/action-yamllint@v3 + with: + config_file: util/lint/.yamllint.yml + + ######################## + # Check Python Sources # + ######################## + python-lint: + runs-on: ubuntu-latest + name: Lint Python Sources + steps: + - name: Check out source repository + uses: actions/checkout@v3 + - name: Set up Python environment + uses: actions/setup-python@v4 + with: + python-version: "3.11" + - name: flake8 Lint + uses: py-actions/flake8@v2 + with: + max-line-length: "100" + + ###################### + # Clang-Format Check # + ###################### + # Check C/C++ files for correct formatting. + clangfmt: + name: Lint C/C++ Sources + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + - uses: DoozyX/clang-format-lint-action@v0.16.2 + with: + clangFormatVersion: 10 + + ###################### + # Lint Editor Config # + ###################### + # Detect trailing whitespaces, missing new lines and wrong file encodings. + editorconfig-lint: + name: Lint Editorconfig + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + - uses: editorconfig-checker/action-editorconfig-checker@main + - run: editorconfig-checker diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100644 index 000000000..86c0ecf20 --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,236 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +variables: + GIT_STRATEGY: clone + GIT_SUBMODULE_STRATEGY: recursive + PYTHON: /usr/local/anaconda3-2022.05/bin/python3 + BENDER: bender-0.27.1 + CC: gcc-9.2.0 + CXX: g++-9.2.0 + VCS: vcs-2020.12 + VERILATOR: verilator-4.110 + QUESTA: questa-2022.3 + LLVM_BINROOT: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin + CLANG: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang + CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_LINKER: /usr/pack/gcc-9.2.0-af/linux-x64/bin/gcc + LLVM_SYS_120_PREFIX: /usr/pack/llvm-12.0.1-af + SNITCH_LOG: info + CMAKE: cmake-3.18.1 + VIVADO: vitis-2020.2 vivado + VERIBLE_FMT: $CI_PROJECT_DIR/.local/bin/verible-verilog-format + CVA6_SDK: /usr/scratch2/dolent1/gitlabci/tmp/cva6-sdk + RISCV: ${CVA6_SDK}/install + UBOOT_SPL_BIN: ${CVA6_SDK}/u-boot/spl/u-boot-spl.bin + UBOOT_ITB: ${CVA6_SDK}/u-boot/u-boot.itb + LINUX_UIMAGE: ${CVA6_SDK}/uImage + RISCV_LLVM: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/ + PATH: $RISCV_LLVM:$CI_PROJECT_DIR/.local/bin:${RISCV}/bin:/home/gitlabci/.cargo/bin:/usr/local/bin:/usr/bin:/bin:/usr/sbin:/sbin:/usr/local/condor/bin:/usr/sepp/bin + +before_script: + - export SNITCH_CLUSTER_ROOT=$($BENDER path snitch_cluster) + - $PYTHON -m venv .venv + - source .venv/bin/activate + - pip install -r $SNITCH_CLUSTER_ROOT/python-requirements.txt + # yamllint disable rule:line-length + - cd $CI_PROJECT_DIR && mkdir -p .local + - curl -L https://github.com/chipsalliance/verible/releases/download/v0.0-3318-g8d254167/verible-v0.0-3318-g8d254167-CentOS-7.9.2009-Core-x86_64.tar.gz | tar xz -C .local --strip-components=1 + - $VERIBLE_FMT --version + # yamllint enable rule:line-length + # - > + # if ! $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh get python; then + # $CI_PROJECT_DIR/.gitlab-ci.d/build-python.sh $CI_PROJECT_DIR + # $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh insert python + # fi + # yamllint enable rule:line-length +stages: + - occamy-sw + - occamy-sim + # - linux_prepare + # - build_fpga + # - linux_boot + +# # CVA6 SDK +# get_toolchain: +# stage: linux_prepare +# script: +# - | +# if [[ ! -d ${CVA6_SDK} ]]; then +# git clone git@github.com:openhwgroup/cva6-sdk.git $CVA6_SDK +# cd $CVA6_SDK && git checkout occamy +# git submodule update --init --recursive +# fi +# - | +# if [[ ! -f ${RISCV}/bin/riscv64-unknown-linux-gnu-gcc ]]; then +# cd $CVA6_SDK && make all +# fi +# timeout: 2h 00m +# get_linux: +# stage: linux_prepare +# script: +# - | +# if [[ ! -f ${UBOOT_ITB} ]]; then +# cd $CVA6_SDK && make u-boot/u-boot.itb +# fi +# - | +# if [[ ! -f ${LINUX_UIMAGE} ]]; then +# ln -s /home/cykoenig/bin/ld $CI_PROJECT_DIR/.local/bin/ld && hash -r +# cd $CVA6_SDK && make uImage LD_LIBRARY_PATH=/home/cykoenig/lib64 +# fi +# needs: [get_toolchain] +# timeout: 2h 00m + +# # Packages and elaborates the vivado IPs where occamy is part of. This ensures +# # that the occamy xilinx IP can be elaborated +# occamy_vivado_ip: +# stage: build_fpga +# script: +# # Make Occamy system smaller to fit on FPGA +# - ./.gitlab-ci.d/occamy_cfg_fpga.sh +# - make -C hw/system/occamy update-source +# # Package IPs and run test elaboration +# - make -C hw/system/occamy/fpga/vivado_ips occamy_xilinx EXT_JTAG=0 DEBUG=0 +# artifacts: +# expire_in: 4 days +# paths: +# - hw/system/occamy/src +# - hw/system/occamy/test +# - sw/snRuntime/include/occamy_base_addr.h + +# # The occamy on vcu128 design +# occamy_vcu128: +# stage: build_fpga +# rules: +# - if: $CI_PIPELINE_SOURCE == "web" +# - if: $CI_PIPELINE_SOURCE != "web" +# when: manual +# changes: +# - .gitlab-ci.d/occamy_cfg_fpga.sh +# - hw/ip/**/* +# - hw/vendor/**/* +# - hw/system/occamy/**/* +# - util/occamygen.py +# - util/clustergen/**/* +# - util/solder/**/* +# - util/Makefrag +# - util/reggen +# - util/regtool.py +# timeout: 11h 00m +# script: +# # yamllint disable rule:line-length +# - | +# if ! $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh --ignore-uncommitted-changes lookup occamy_vcu128; then +# make -C hw/system/occamy/fpga occamy_vcu128 EXT_JTAG=0 DEBUG=0 +# mkdir -p /usr/scratch2/dolent1/gitlabci/buildcache/snitch/snitch-incremental/ +# $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh --ignore-uncommitted-changes insert occamy_vcu128 +# fi +# # yamllint enable rule:line-length +# artifacts: +# expire_in: 4 days +# paths: [hw/system/occamy/fpga, hw/system/occamy/src] +# needs: [get_toolchain, get_linux, occamy_vivado_ip] + +# # Boot Linux on the VCU128 FPGA and check for prompt (disabled for now) +# occamy_vcu128_fpga: +# stage: linux_boot +# when: manual +# only: +# changes: +# - .gitlab-ci.d/occamy_cfg_fpga.sh +# - .gitlab-ci.d/occamy_fpga_nightly.sh +# # Only run if changes were made to anything related to Occamy +# - hw/ip/**/* +# - hw/vendor/**/* +# - hw/system/occamy/**/* +# script: +# # We need the bitstream, bootrom (tracked in the repo) and linux binaries +# - $CI_PROJECT_DIR/.gitlab-ci.d/memora_retry.sh \ +# --ignore-uncommitted-changes get occamy_vcu128 +# # Todo get linux distrib from hero and flash it +# - .gitlab-ci.d/occamy_fpga_nightly.sh +# artifacts: +# expire_in: 4 days +# paths: [console.log] +# needs: [occamy_vcu128] + +######################### +# Build Occamy Software # +######################### + +occamy-single-cluster-sw: + # needs: [occamy-sw-musl] + stage: occamy-sw + script: + - cd target/sim + - make CFG_OVERRIDE=cfg/single-cluster.hjson rtl + - make DEBUG=ON sw + artifacts: + paths: + - target/sim/sw/**/build/*.elf + expire_in: 1 day + +##################################### +# Test Snitch Cluster on IIS system # +##################################### +# Verilator +occamy-single-cluster-vlt: + # needs: [occamy-single-cluster-sw] + stage: occamy-sim + # yamllint disable rule:line-length + script: + - cd target/sim + - $VERILATOR make bin/occamy.vlt + # - $VERILATOR ./sw/tests/run.py sw/tests/passing-apps.list --simulator verilator 2>&1 | tee tests.log + # - $VERILATOR ./sw/apps/run.py sw/apps/passing-apps.list --simulator verilator 2>&1 | tee apps.log + # - grep -zoP 'All tests passed' tests.log + # - grep -zoP 'All tests passed' apps.log + # # yamllint enable rule:line-length + # artifacts: + # when: on_failure + # paths: + # - target/sim/tests.log + # - target/sim/apps.log + # expire_in: 1 day + +# VCS +occamy-single-cluster-vcs: + # needs: [occamy-single-cluster-sw] + stage: occamy-sim + # yamllint disable rule:line-length + script: + - cd target/sim + - make CFG_OVERRIDE=cfg/single-cluster.hjson rtl + - $VCS make bin/occamy.vcs + # - $VCS ./sw/tests/run.py sw/tests/passing-apps.list --simulator vcs 2>&1 | tee tests.log + # - $VCS ./sw/apps/run.py sw/apps/passing-apps.list --simulator vcs 2>&1 | tee apps.log + # - grep -zoP 'All tests passed' tests.log + # - grep -zoP 'All tests passed' apps.log + # # yamllint enable rule:line-length + # artifacts: + # when: on_failure + # paths: + # - target/sim/tests.log + # - target/sim/apps.log + # expire_in: 1 day + +# Questa +occamy-single-cluster-vsim: + # needs: [occamy-single-cluster-sw] + stage: occamy-sim + # yamllint disable rule:line-length + script: + - cd target/sim + - make CFG_OVERRIDE=cfg/single-cluster.hjson rtl + - $QUESTA make bin/occamy.vsim + # - $QUESTA ./sw/tests/run.py sw/tests/passing-apps.list --simulator vsim 2>&1 | tee tests.log + # - $QUESTA ./sw/apps/run.py sw/apps/passing-apps.list --simulator vsim 2>&1 | tee apps.log + # - grep -zoP 'All tests passed' tests.log + # - grep -zoP 'All tests passed' apps.log + # # yamllint enable rule:line-length + # artifacts: + # when: on_failure + # paths: + # - target/sim/tests.log + # - target/sim/apps.log + # expire_in: 1 day diff --git a/deps/snitch_cluster b/deps/snitch_cluster deleted file mode 120000 index efd3ffe50..000000000 --- a/deps/snitch_cluster +++ /dev/null @@ -1 +0,0 @@ -../working_dir/snitch_cluster \ No newline at end of file diff --git a/util/lint/.yamllint.yml b/util/lint/.yamllint.yml new file mode 100644 index 000000000..d1ee1ff1c --- /dev/null +++ b/util/lint/.yamllint.yml @@ -0,0 +1,25 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +extends: default + +rules: + document-start: disable + comments: + min-spaces-from-content: 1 + line-length: + allow-non-breakable-words: true + allow-non-breakable-inline-mappings: true + ignore: | + Bender.yml + workflows/lint.yml + colons: + ignore: | + Bender.yml + braces: + ignore: | + Bender.yml + commas: + ignore: | + Bender.yml diff --git a/util/occamygen/occamy.py b/util/occamygen/occamy.py index e0df42a99..73a3e748f 100644 --- a/util/occamygen/occamy.py +++ b/util/occamygen/occamy.py @@ -6,7 +6,7 @@ from pathlib import Path sys.path.append(str(Path(__file__).parent / '../../deps/snitch_cluster/util/clustergen')) -from cluster import Generator, PMA, PMACfg, SnitchCluster, clog2 +from cluster import Generator, PMA, PMACfg, SnitchCluster, clog2 # noqa: E402 class Occamy(Generator): diff --git a/util/occamygen/occamygen.py b/util/occamygen/occamygen.py index 503b347a8..7b4570fc2 100755 --- a/util/occamygen/occamygen.py +++ b/util/occamygen/occamygen.py @@ -18,7 +18,7 @@ from mako.template import Template sys.path.append(str(pathlib.Path(__file__).parent / '../')) -from solder import solder, device_tree, util +from solder import solder, device_tree, util # noqa: E402 # Compile a regex to trim trailing whitespaces on lines. re_trailws = re.compile(r'[ \t\r]+$', re.MULTILINE) @@ -32,7 +32,8 @@ def write_template(tpl_path, outdir, fname=None, **kwargs): tpl_path = pathlib.Path(tpl_path).absolute() if tpl_path.exists(): tpl = Template(filename=str(tpl_path)) - fname = tpl_path.with_suffix("").name.replace("occamy", kwargs['args'].name) if not fname else fname + fname = tpl_path.with_suffix("").name.replace("occamy", kwargs['args'].name) \ + if not fname else fname with open(outdir / fname, "w") as file: code = tpl.render_unicode(**kwargs) code = re_trailws.sub("", code) @@ -359,8 +360,10 @@ def main(): cluster_zero_mem_size = occamy.cfg["cluster"]["zero_mem_size"] * 1024 # assert memory region allocation - error_str = "ERROR: cluster peripherals, zero memory and tcdm do not fit into the allocated memory region!!!" - assert (cluster_tcdm_size + cluster_periph_size + cluster_zero_mem_size) <= cluster_base_offset, error_str + error_str = "ERROR: cluster peripherals, zero memory and tcdm \ + do not fit into the allocated memory region!!!" + assert (cluster_tcdm_size + cluster_periph_size + cluster_zero_mem_size) <= \ + cluster_base_offset, error_str cluster_base_addr = occamy.cfg["cluster"]["cluster_base_addr"] quadrant_size = cluster_base_offset * nr_s1_clusters @@ -417,7 +420,8 @@ def main(): am.new_leaf( "quad_{}_cfg".format(i), occamy.cfg["s1_quadrant"]["cfg_base_offset"], - occamy.cfg["s1_quadrant"]["cfg_base_addr"] + i * occamy.cfg["s1_quadrant"]["cfg_base_offset"] + occamy.cfg["s1_quadrant"]["cfg_base_addr"] + + i * occamy.cfg["s1_quadrant"]["cfg_base_offset"] ).attach_to( am_narrow_xbar_quadrant_s1[i] ).attach_to( @@ -866,7 +870,8 @@ def main(): "apb_hbm_cfg": apb_hbm_cfg, "cfg": occamy.cfg, "cores": nr_s1_quadrants * nr_s1_clusters * nr_cluster_cores + nr_remote_cores + 1, - "lcl_cores": nr_s1_quadrants * nr_s1_clusters * nr_cluster_cores + (0 if is_remote_quadrant else 1), + "lcl_cores": nr_s1_quadrants * nr_s1_clusters * nr_cluster_cores + + (0 if is_remote_quadrant else 1), "remote_quadrants": occamy.cfg["remote_quadrants"], "is_remote_quadrant": occamy.cfg["is_remote_quadrant"], "nr_s1_quadrants": nr_s1_quadrants, diff --git a/util/solder/solder.py b/util/solder/solder.py index 7b85f59e2..35942bcc2 100644 --- a/util/solder/solder.py +++ b/util/solder/solder.py @@ -327,8 +327,8 @@ def emit(aw, dw, iw, uw): if key in AxiStruct.configs: return AxiStruct.configs[key] name = "axi_a{}_d{}_i{}_u{}".format(*key) - code = "// AXI bus with {} bit address, {} bit data, {} bit IDs, and {} bit user data.\n".format( - *key) + code = "// AXI bus with {} bit address, {} bit data, {} bit IDs, \ + and {} bit user data.\n".format(*key) code += "`AXI_TYPEDEF_ALL_CT({}, {}_req_t, {}_resp_t, ".format(name, name, name) code += "logic [{}:0], logic [{}:0], logic [{}:0], logic [{}:0], logic [{}:0])\n".format( aw - 1, iw - 1, dw - 1, (dw + 7) // 8 - 1, max(0, uw - 1)) @@ -349,8 +349,8 @@ def emit(aw, dw): name = "axi_lite_a{}_d{}".format(*key) code = "// AXI-Lite bus with {} bit address and {} bit data.\n".format( *key) - code += "`AXI_LITE_TYPEDEF_ALL_CT({}, {}_req_t, {}_rsp_t, logic [{}:0], logic [{}:0], logic [{}:0])\n".format( - name, name, name, aw - 1, dw - 1, (dw + 7) // 8 - 1) + code += "`AXI_LITE_TYPEDEF_ALL_CT({}, {}_req_t, {}_rsp_t, logic [{}:0], logic [{}:0], \ + logic [{}:0])\n".format(name, name, name, aw - 1, dw - 1, (dw + 7) // 8 - 1) code_package += "\n" + code AxiLiteStruct.configs[key] = name return name @@ -678,8 +678,10 @@ def change_uw(self, context, target_uw, name, inst_name=None, to=None): # Emit the remapper instance. bus.declare(context) assgn = "// Change UW\n" - assgn += "`AXI_ASSIGN_REQ_STRUCT({lhs},{rhs})\n".format(lhs=bus.req_name(), rhs=self.req_name()) - assgn += "`AXI_ASSIGN_RESP_STRUCT({lhs},{rhs})\n".format(lhs=self.rsp_name(), rhs=bus.rsp_name()) + assgn += "`AXI_ASSIGN_REQ_STRUCT({lhs},{rhs})\n".format(lhs=bus.req_name(), + rhs=self.req_name()) + assgn += "`AXI_ASSIGN_RESP_STRUCT({lhs},{rhs})\n".format(lhs=self.rsp_name(), + rhs=bus.rsp_name()) context.write(assgn) return bus