issue in make build

[gagana-05]

modelsim_libs missing in sim/ directory

[FrancescoConti]

You must have QuestaSim (which includes the vlib binary) installed and in your path.

[gagana-05]

Can you tell me how to make sure it's in my path

[bluewww]

Check echo $PATH.

It's probably better that you google for these problems since they don't have much to do with pulp but rather are basic UNIX tasks.

[ashuthosh-mr]

I added the path and make build fails with issue similar to #79. Solution in the #79 of removing the rm modelsim.ini do not help either. What might be going wrong here? Thank you in advance.

[srinisy-22]

I am also facing the similar issue. Please guide us on how to resolve this.

[srinisy-22]

Modifying the Makefile didn't work

[ashuthosh-mr]

Haven't solved it yet. Try using modelsim simulator mentorgraphics version instead of intel.

[srinisy-22]

I tried loading the design manually on Modelsim and it throws an error

Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(495): (vlog-2164) Class or package 'dm' not found in jtag_pkg.sv SystemVerilog file.

These are the files in my modelsim project:
d----- 10/2/2023 4:22 PM dev_dpi
d----- 10/2/2023 4:22 PM remote_bitbang
-a---- 10/2/2023 3:55 PM 1970 cluster_bus_defines.sv
-a---- 10/2/2023 3:55 PM 18050 cluster_domain.sv
-a---- 10/2/2023 3:55 PM 36406 dbg_pkg.sv
-a---- 10/2/2023 3:55 PM 1646 debug_bus_defines.sv
-a---- 10/2/2023 3:55 PM 9689 dev_dpi.sv
-a---- 10/2/2023 3:55 PM 29 dpi_models
-a---- 10/2/2023 3:55 PM 6609 fp_defines.sv
-a---- 10/2/2023 3:55 PM 1205 instr_bus_defines.sv
-a---- 10/2/2023 3:55 PM 98284 jtag_pkg.sv
-a---- 10/2/2023 3:55 PM 4039 jtag_tap_top.sv
-a---- 10/2/2023 3:55 PM 19282 pad_control.sv
-a---- 10/2/2023 3:55 PM 20362 pad_frame.sv
-a---- 10/2/2023 3:55 PM 2585 periph_bus_defines.sv
-a---- 10/2/2023 3:55 PM 63877 pulp.sv
-a---- 10/2/2023 3:55 PM 684 pulpissimo_compliance_test.cfg
-a---- 10/2/2023 3:55 PM 694 pulpissimo_debug.cfg
-a---- 10/2/2023 3:55 PM 3984 pulp_soc_defines.sv
-a---- 10/2/2023 3:55 PM 30188 pulp_tap_pkg.sv
-a---- 10/2/2023 3:55 PM 2307 README.md
-a---- 10/2/2023 3:55 PM 23275 riscv_pkg.sv
-a---- 10/2/2023 3:55 PM 6472 rtc_clock.sv
-a---- 10/2/2023 3:55 PM 4101 rtc_date.sv
-a---- 10/2/2023 3:55 PM 26077 safe_domain.sv
-a---- 10/2/2023 3:55 PM 12377 safe_domain_reg_if.sv
-a---- 10/2/2023 3:55 PM 2178 SimDTM.sv
-a---- 10/2/2023 3:55 PM 2437 SimJTAG.sv
-a---- 10/2/2023 3:55 PM 4309 soc_bus_defines.sv
-a---- 10/2/2023 3:55 PM 12688 soc_domain.sv
-a---- 10/2/2023 3:55 PM 2219 soc_mem_map.svh
-a---- 10/2/2023 3:55 PM 344 src_files.yml
-a---- 10/2/2023 3:55 PM 1044 tb_clk_gen.sv
-a---- 10/2/2023 3:55 PM 28 tb_driver
-a---- 10/2/2023 3:55 PM 12016 tb_fs_handler.sv
-a---- 10/2/2023 3:55 PM 38460 tb_pulp.sv

[srinisy-22]

I included only the .sv and .svh files ofcourse

[srinisy-22]

Modelsim throws several errors: ** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(516): (vlog-2164) Class or package 'dm' not found.
** Error: (vlog-13069) C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(516): near "::": syntax error, unexpected ::, expecting ')'.
** Warning: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(519): (vlog-2643) Unterminated string literal continues onto next line.
** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(547): (vlog-2164) Class or package 'dm' not found.
** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(547): (vlog-2730) Undefined variable: 'dm'.
** Error: (vlog-13069) C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(547): near "::": syntax error, unexpected ::.
** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(551): (vlog-2164) Class or package 'dm' not found.
** Error: (vlog-13069) C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/jtag_pkg.sv(551): near "::": syntax error, unexpected ::, expecting ')'.

Where can I find the dm package? Because it is not available anywhere in the repo.

[FrancescoConti]

The dm package is located here, in the riscv-dbg package, which is downloaded when collecting the dependencies for the platform: https://github.com/pulp-platform/riscv-dbg/blob/master/src/dm_pkg.sv

It seems to me that:

1. you are running on Windows - not supported, as far as I know, as all scripts run on Unix
2. you are using Altera/Intel ModelSim, which is not supported due to the lack of several features
3. something has likely failed in the make checkout phase : https://github.com/pulp-platform/pulp/blob/master/README.md#building-the-rtl-simulation-platform

[srinisy-22]

make checkout worked just fine, but not make build. But my question was is it possible to manually load the design onto Model sim or any other platform like VCS to run the simulation? If so where is the .mem or .hex RAM inputs to the SoC which can modified/generated to obtain high functional coverage?

[srinisy-22]

To overcome the errors in pulp.sv which required axi packages, I downloaded and included them in the Modelsim project. It throws me this error ** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/axi_demux_simple.sv(17): Cannot open include file "common_cells/assertions.svh". ** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/axi_demux_simple.sv(18): Cannot open include file "common_cells/registers.svh"

[srinisy-22]

Additionally ; -- Compiling module axi_demux_simple
** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/axi_demux_simple.sv(69): (vlog-2164) Class or package 'cf_math_pkg' not found.
** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/axi_demux_simple.sv(69): (vlog-2730) Undefined variable: 'cf_math_pkg'. Where can I find these files?

[srinisy-22]

Further the pulp.sv throws additional errors:
-- Compiling module pulp
** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/pulp.sv(93): (vlog-2164) Class or package 'pkg_soc_interconnect' not found.
** Error: C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/pulp.sv(93): (vlog-2730) Undefined variable: 'pkg_soc_interconnect'.
** Error: (vlog-13069) C:/Users/suriy/Downloads/pulp/rtl/modelsim_sim/pulp.sv(93): near "::": syntax error, unexpected ::, expecting ';' or ','.
-- Importing package axi_pkg
Where can I find pkg_soc_interconnect?

[FrancescoConti]

As I already told you, make checkout will automatically download all dependencies and create scripts that build the simulation platform. It is highly unlikely, if not impossible, that this step has really worked flawlessly and then nothing works as you report - it is much more probable that it has failed (silently, perhaps? I have no idea) and you see cascade failures.
We cannot really help you for several reasons, including that we do not have access to a platform comparable to the one you are using (Windows + Intel Modelsim). What you are trying to do by hand with Modelsim projects is very painful, unsupported, and it might be useless. If you want to add support for other tools/platforms, I recommend using/adapting the Bender tool to generate scripts for your special use case https://github.com/pulp-platform/bender .

[srinisy-22]

If so, is it safe to assume that pulp is not a robust SoC and does not work with any/all simulators and would work for only a specific number of simulators?

[FrancescoConti]

I will assume, for now, that you are not trolling, and try to respond politely and constructively - but I do not like your tone. At all.

It is not safe to assume so. As any hardware or software project of reasonable complexity, you have to meet a set of requirements to enter a "supported" subset that as developers (for free, might I add) we can support. We support directly QuestaSim and through Bender you can rather easily add support VCS or XCelium.
You want more? You can do it yourself, that's the beauty of open-source. But do not expect support when you are trying to do something that is far off any real-world digital design flow.

[srinisy-22]

I apologize if my tone sounded rude. I was just trying to understand the full nature of the SoC and deliberate. I would also like to remind you that I am not trying to do anything out of the realm of digital design flow. Generating test vectors to improve functional coverage has been a long-standing problem statement and an important aspect of the bottleneck (several publications atone to my argument). And every processor-based design would require a RAM file as an input to perform simulations. I was just trying to understand the SoC itself.

[srinisy-22]

And for starters, I would kindly recommend you explain the bender and its robust nature to support VCS or XCelium, in the website. It is not wise to assume that all these steps are self-explanatory. A better communication would yield better understanding and widespread outreach to the developed SOC. Thank you.

[srinisy-22]

By the way you might want to Add this to your requirements:
curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh
bender-init: Warning: No release for platform 'x86_64-linux-gnu-linuxmint19.3' version 'latest' found, using latest.
sh: 315: [[: not found
bender-init: Error: Latest release not available for platform 'x86_64-linux-gnu-linuxmint19.3'!