forked from pulp-platform/ibex
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Bender.yml
150 lines (145 loc) · 5.68 KB
/
Bender.yml
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
package:
name: ibex
dependencies:
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 }
sources:
# All register file implementations are included in compilation by default,
# please select the appropriate version when instantiating ibex_core.
- rtl/ibex_register_file_latch.sv
- rtl/ibex_register_file_ff.sv
- rtl/ibex_register_file_fpga.sv
- target: not(all(any(test, ibex_include_tracer), not(ibex_exclude_tracer)))
include_dirs:
- rtl
- vendor/lowrisc_ip/ip/prim/rtl
- dv/uvm/core_ibex/common/prim
- vendor/lowrisc_ip/dv/sv/dv_utils
files:
# Source files grouped in levels. Files in level 0 have no dependencies on files in this
# package. Files in level 1 only depend on files in level 0, files in level 2 on files in
# levels 1 and 0, etc. Files within a level are ordered alphabetically.
# Level 0
- vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv
- vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
- vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
- dv/uvm/core_ibex/common/prim/prim_pkg.sv
# Level 1
- rtl/ibex_pkg.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_dec.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_enc.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_dec.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_enc.sv
- vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv
- vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
- dv/uvm/core_ibex/common/prim/prim_flop.sv
- dv/uvm/core_ibex/common/prim/prim_buf.sv
- dv/uvm/core_ibex/common/prim/prim_clock_mux2.sv
- dv/uvm/core_ibex/common/prim/prim_clock_gating.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_check.sv
- vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh
# Level 2
- rtl/ibex_alu.sv
- rtl/ibex_compressed_decoder.sv
- rtl/ibex_controller.sv
- rtl/ibex_counter.sv
- rtl/ibex_csr.sv
- rtl/ibex_decoder.sv
- rtl/ibex_fetch_fifo.sv
- rtl/ibex_load_store_unit.sv
- rtl/ibex_multdiv_fast.sv
- rtl/ibex_multdiv_slow.sv
- rtl/ibex_pmp.sv
- rtl/ibex_wb_stage.sv
- rtl/ibex_branch_predict.sv
- rtl/ibex_dummy_instr.sv
- rtl/ibex_icache.sv
- rtl/ibex_pmp_reset_default.svh
# Level 3
- rtl/ibex_cs_registers.sv
- rtl/ibex_ex_block.sv
- rtl/ibex_id_stage.sv
- rtl/ibex_prefetch_buffer.sv
# Level 4
- rtl/ibex_if_stage.sv
# Level 5
- rtl/ibex_core.sv
# Level 6
- rtl/ibex_lockstep.sv
# Level 7
- rtl/ibex_top.sv
# In case we target RTL simulation, recompile the whole core with the RISC-V
# formal interface so the tracer module works (`define RVFI).
- target: all(any(test, ibex_include_tracer), not(ibex_exclude_tracer))
include_dirs:
- rtl
- vendor/lowrisc_ip/ip/prim/rtl
- dv/uvm/core_ibex/common/prim
- vendor/lowrisc_ip/dv/sv/dv_utils
defines:
RVFI: true
files:
# Level 0
- vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv
- vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
- vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
- dv/uvm/core_ibex/common/prim/prim_pkg.sv
# Level 1
- rtl/ibex_pkg.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_dec.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_enc.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_dec.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_enc.sv
- vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv
- vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
- dv/uvm/core_ibex/common/prim/prim_flop.sv
- dv/uvm/core_ibex/common/prim/prim_buf.sv
- dv/uvm/core_ibex/common/prim/prim_clock_mux2.sv
- dv/uvm/core_ibex/common/prim/prim_clock_gating.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv
- vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_check.sv
- vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh
# Level 2
- rtl/ibex_alu.sv
- rtl/ibex_compressed_decoder.sv
- rtl/ibex_controller.sv
- rtl/ibex_counter.sv
- rtl/ibex_csr.sv
- rtl/ibex_decoder.sv
- rtl/ibex_fetch_fifo.sv
- rtl/ibex_load_store_unit.sv
- rtl/ibex_multdiv_fast.sv
- rtl/ibex_multdiv_slow.sv
- rtl/ibex_pmp.sv
- rtl/ibex_tracer_pkg.sv
- rtl/ibex_wb_stage.sv
- rtl/ibex_branch_predict.sv
- rtl/ibex_dummy_instr.sv
- rtl/ibex_icache.sv
- rtl/ibex_pmp_reset_default.svh
# Level 3
- rtl/ibex_cs_registers.sv
- rtl/ibex_ex_block.sv
- rtl/ibex_id_stage.sv
- rtl/ibex_prefetch_buffer.sv
- rtl/ibex_tracer.sv
# Level 4
- rtl/ibex_if_stage.sv
# Level 5
- rtl/ibex_core.sv
# Level 6
- rtl/ibex_lockstep.sv
# Level 7
- rtl/ibex_top.sv
# Level 8
- rtl/ibex_top_tracing.sv