This page lists gaps that have been identified by the Toolchains SIG and are planned to be addressed for 2024.
The gaps have the following properties:
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Title
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Tags
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Description
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Status
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Ticket (if existing)
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Tags: psABI
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Description: ABI breaks become inevitable at one point. We need to ensure to have a proper versioning scheme and being able to enforce that.
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Status: Open
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Tags: psABI
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Description: Alignment directive can specify 1) required alignment, 2) padding byte content and 3) the maximum number of bytes that should be skipped by the alignment directive, however RISC-V can only handle 1 correctly, but 2 and 3 do not work as expected.
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Link: https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html#SEC70
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Status: Open
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Tags: psABI, eABI
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Description: Design flexible ABI for optimizing different embedded system applications. Embedded application might has different requirements than the Linux or *BSD environment, and embedded world also have very diversity requirements, so we intend to not just define a single ABI for all embedded system, and define
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Status: Open
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Tags: psABI
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Description: medlow and medany only provide limited capability to access the address space, capability to access the whole address space is useful for specific areas. We need a code mode that has the capability to access the full address space.
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Status: open
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Tags: psABI
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Description: LLVM / compiler-rt has had inconsistent helper function names for fp16 types with gcc/libgcc for a while, and fixed that later, but why this happened is because we don’t have a standard document to follow. We need to specify the interface and semantics of compiler helper functions in libgcc/compiler-rt, we don’t have a formal specification on that, but having a de-facto standard on libgcc and compiler-rt, we need to document that down.
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Status: open
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Link: https://github.com/ARM-software/abi-aa/tree/main/rtabi32
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Tags: psABI
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Description: psABI has defined a range of relocation for non-standard use, but didn’t have a complete solution to prevent collision between different vendor relocations. Vendors might define their own custom instruction which require relocation, e.g. new branch instruction, new load/store instruction with different immediate bits.
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Status: open
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Tags: psABI
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Description: The alignment of
__int128
is defined on LP64 but not on ILP32. -
Status: open
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Tags: psABI
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Description: ABIs for RV32E/RV64E are not ratified, there are some issues when combining ILP32E with D extension.
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Status: Open
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Tags: psABI
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Description: Redzones provide some performance opportunity (e.g. eliding frame setup for leaf functions), and provide an escape hatch for compiler implementations (e.g. for having a scratch register available.) The RISCV ABI is currently specified without a redzone. Adding one in a backwards compatible manner would require some form of marker in the ELF file, and enforcement in the dynamic loader.
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Status: Open
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Tags: psABI
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Description: Portability requires a defined stack frame layout. It’s different from existing systems (so code needs risc-v-specific changes), but it’s not currently documented.
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Status: Open
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Tags: psABI
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Description: emutls is broken for rv64 (at least in llvm) 🙂and although rv64 could be the first Android architecture to use ELF TLS rather than emutls by default (because it’s the first one to come after we added ELF TLS to the system), it’s a shame we can’t use TLSDESC relocations for that.
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Status: open
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Tags: psABI
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Description: ILP32 has three use-cases 1) vserver hosting (memory bound), 2) netbooks/tablets (low memory, want performance), and 3) scientific tasks (want every % of performance).
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Status: open
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Tags: psABI
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Description: Define a mapping symbol to improve user experience of objdump
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Status: open
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Tags: psABI
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Description: ULEB128 are widely used now, and the ULEB128 will be used for encoding the address difference. Dwarf has some fields that only support uleb128, which might cause problems if we don’t have relocation to those fields when relaxation enabled.
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Status: open
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Tags: Compilers, Performance
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Description: The backend of GCC lacks a fine-grained cost model to optimize code generation for specific cores.
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Status: Open (even if the current cost model in the compilers is simplified, we need actual HW to drive this effort)
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Tags: psABI
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Description: There have been multiple attempts to establish an embedded ABI. In recent discussions a parameterized ABI has been proposed, which allows to provide a flexible ABI framework that’s suitable for all needs.
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Status: Open
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Tags: C API
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Description: RVI drives efforts for two matrix extensions. Both need intrinsics support.
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Status: Open
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Tags: psABI
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Description: We need to specify the details of pointer masking to ensure correctness and interoperability
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Status: Open
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Tags: psABI
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Description: A _BitInt ABI needs to be defined to ensure interoperability.
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Status: Open
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Tags: C API
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Description: We need to specify a few function attributes (vector CC, prestacking, multi-versioning) to ensure interoperability.
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Status: Open
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Tags: Toolchain conventions
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Description: We need profiles support in the toolchains.
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Status: Open (LLVM is done as of March 2024)
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Tags: Runtimes, Performance
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Description: Glibc offers an indirection mechanism to call target-specific implementations for functions like strlen, strcmp, memcmp. Upstream glibc does not untilize this mechanism and uses therefore unoptimized implementations (Zb*, V, Zawrs).
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Status: Open (Linux has added a mechanism to dynamically detect available extensions as runtime (
hwprobe
). This allows to include ifunc-optimizations on top of that.)
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Tags: psABI
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Description: Document atomics ABI (for A and Ztso) to ensure correctness and interoperability
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Status: Done (atomics ABIs have been defined and implemented)
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Tags: psABI
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Description: Document vector ABIs (for variable length vectors and fixed-length vectors) to ensure correctness and interoperability. This includes vector calling conversion, vector type alignment, C++ name mangling for vector type.
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Status: vector ABIs have been specified and is implemented
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Link: https://github.com/ARM-software/abi-aa/blob/main/vfabia64/vfabia64.rst
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Tags: Compilers, Performance
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Description: The (recently ratified) RISC-V vector extension allows to utilize and extend GCC’s auto-vectorization capabilities. Currently, there is no (public information about) active work in this area.
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Status: Both major compilers (GCC and LLVM) support auto-vectorization as of end 2023
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Tags: Compilers
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Description: Besides auto-vectorization, RISC-V vector instructions should be emitted by compilers via an extensions of the C language (intrinsics).
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Status: RVV intrinsics TG has been formed that works on the specification. As of Apr 2024 the spec is close to ratification and implemented in GCC and LLVM.
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Tags: Compilers, C-API
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Description: Zb* extensions have been ratified a while ago. We need to agree on intrinsics and implement them.
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Ticket: riscv-non-isa/riscv-c-api-doc#44
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Status: Intrinsics have been defined and implemented in GCC and LLVM