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Missing pseudo-instructions? #110

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AFOliveira opened this issue Oct 14, 2024 · 2 comments · May be fixed by #111
Open

Missing pseudo-instructions? #110

AFOliveira opened this issue Oct 14, 2024 · 2 comments · May be fixed by #111

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@AFOliveira
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I've been digging for pseudoinstructions in binutils and found that several pseudoinstructions implemented there are not found in the ASM Manual, is this on purpose?

For reference, these are some, but not all of those pseudo-instructions:

bs.v
vfneg.v
vmclr.m
vmfge.vv
vmfgt.vv
vmmv.m
vmnot.m
vmset.m
vmsge.vi
vmsge.vv
vmsge.vx
vmsgeu.vi
vmsgeu.vv
vmsgeu.vx
vmsgt.vv
vmsgtu.vv
vmslt.vi
vmsltu.vi
vneg.v
vnot.v
vt.maskc
vt.maskcn
vwcvt.x.x.v
vwcvtu.x.x.v

@cmuellner
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Good catch! All of them (assuming that the first one in your list (bs.v) is vfabs.v) are specified as pseudoinstructions (incl. what they translate to) in the ratified vector extension specification. Therefore, they are clearly specified, but were not added here.

Would you be interested in creating a PR that adds them?

@AFOliveira
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Definitely so! I will work on that and tag this issue. Thank you!

AFOliveira added a commit to foss-for-synopsys-dwc-arc-processors/riscv-asm-manual that referenced this issue Oct 25, 2024
AFOliveira added a commit to foss-for-synopsys-dwc-arc-processors/riscv-asm-manual that referenced this issue Oct 25, 2024
@AFOliveira AFOliveira linked a pull request Oct 25, 2024 that will close this issue
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2 participants