From cd2e3abe90ade2c28229a423ec0b899b26672604 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Fri, 3 May 2024 11:34:16 -0500 Subject: [PATCH] update step 16 of MSI trans to match spec --- iommu_ref_model/libiommu/include/iommu_translate.h | 2 +- iommu_ref_model/libiommu/src/iommu_msi_trans.c | 8 ++++---- iommu_ref_model/libiommu/src/iommu_translate.c | 2 +- iommu_ref_model/test/test_app.c | 10 +++++++++- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/iommu_ref_model/libiommu/include/iommu_translate.h b/iommu_ref_model/libiommu/include/iommu_translate.h index 802aa8ad..7e8bb318 100644 --- a/iommu_ref_model/libiommu/include/iommu_translate.h +++ b/iommu_ref_model/libiommu/include/iommu_translate.h @@ -113,6 +113,6 @@ msi_address_translation( uint64_t gpa, uint8_t is_exec, device_context_t *DC, uint8_t *is_msi, uint8_t *is_mrif, uint32_t *mrif_nid, uint64_t *dest_mrif_addr, uint32_t *cause, uint64_t *iotval2, uint64_t *pa, - uint64_t *page_sz, gpte_t *g_pte ); + uint64_t *page_sz, gpte_t *g_pte, uint8_t TTYP ); #endif // __IOMMU_TRANSLATE_H__ diff --git a/iommu_ref_model/libiommu/src/iommu_msi_trans.c b/iommu_ref_model/libiommu/src/iommu_msi_trans.c index ec930fb9..ac61b497 100644 --- a/iommu_ref_model/libiommu/src/iommu_msi_trans.c +++ b/iommu_ref_model/libiommu/src/iommu_msi_trans.c @@ -21,7 +21,7 @@ msi_address_translation( uint64_t gpa, uint8_t is_exec, device_context_t *DC, uint8_t *is_msi, uint8_t *is_mrif, uint32_t *mrif_nid, uint64_t *dest_mrif_addr, uint32_t *cause, uint64_t *iotval2, uint64_t *pa, - uint64_t *page_sz, gpte_t *g_pte ) { + uint64_t *page_sz, gpte_t *g_pte, uint8_t TTYP ) { uint64_t A, m, I; uint8_t status; @@ -168,9 +168,9 @@ msi_address_translation( // this process are equivalent to that of a regular RISC-V second-stage PTE with // R=W=U=1 and X=0. Similar to a second-stage PTE, when checking the U bit, the // transaction is treated as not requesting supervisor privilege. - //16. If the transaction is a Untranslated or Translated read-for-execute then stop - // and report "Instruction acccess fault" (cause = 1). - if ( is_exec ) { + // a. If the transaction is a Untranslated or Translated read-for-execute then stop + // and report "Instruction acccess fault" (cause = 1). + if ( is_exec && TTYP != PCIE_ATS_TRANSLATION_REQUEST ) { *cause = 1; return 1; } diff --git a/iommu_ref_model/libiommu/src/iommu_translate.c b/iommu_ref_model/libiommu/src/iommu_translate.c index 00163f44..c119c560 100644 --- a/iommu_ref_model/libiommu/src/iommu_translate.c +++ b/iommu_ref_model/libiommu/src/iommu_translate.c @@ -321,7 +321,7 @@ iommu_translate_iova( // If a fault is detected by the MSI address translation process then stop and // report the fault else the process continues at step 20. if ( msi_address_translation(gpa, is_exec, &DC, &is_msi, &is_mrif, &mrif_nid, &dest_mrif_addr, - &cause, &iotval2, &pa, &gst_page_sz, &g_pte) ) + &cause, &iotval2, &pa, &gst_page_sz, &g_pte, TTYP) ) goto stop_and_report_fault; if ( is_msi == 1 ) goto skip_gpa_trans; diff --git a/iommu_ref_model/test/test_app.c b/iommu_ref_model/test/test_app.c index 860e4876..c7c547d0 100644 --- a/iommu_ref_model/test/test_app.c +++ b/iommu_ref_model/test/test_app.c @@ -3242,7 +3242,7 @@ main(void) { START_TEST("MSI write-through mode"); - DC_addr = add_device(0x042874, 0x1974, 0, 0, 0, 0, 0, + DC_addr = add_device(0x042874, 0x1974, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, IOHGATP_Sv48x4, IOSATP_Bare, PDTP_Bare, MSIPTP_Flat, 1, 0x0000000FF, 0x280000000); @@ -3392,6 +3392,14 @@ main(void) { 1, READ, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 1, 0) < 0 ) ); + // Execute permission request using translation request + send_translation_request(0x042874, 1, 0xBABEC, 0, + 1, 0, 0, ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST, gpa, 4, READ, &req, &rsp); + fail_if( ( check_rsp_and_faults(&req, &rsp, SUCCESS, 0, 0) < 0 ) ); + fail_if( ( rsp.trsp.U == 1 ) ); + fail_if( ( rsp.trsp.R != 1 ) ); + fail_if( ( rsp.trsp.W != 1 ) ); + fail_if( ( rsp.trsp.Exe != 0 ) ); END_TEST();