diff --git a/iommu_in_memory_queues.adoc b/iommu_in_memory_queues.adoc
index f710e61e..0fcabfcb 100644
--- a/iommu_in_memory_queues.adoc
+++ b/iommu_in_memory_queues.adoc
@@ -572,6 +572,8 @@ If the `DSV` operand is 1, then a valid destination segment number is specified
 by the `DSEG` operand. If the `DSV` operand is 0, then the `DSEG` operand is
 ignored.
 
+<<<
+
 [NOTE]
 ====
 A Hierarchy is a PCI Express I/O interconnect topology, wherein the
diff --git a/iommu_intro.adoc b/iommu_intro.adoc
index acfc38a9..7b094cb8 100644
--- a/iommu_intro.adoc
+++ b/iommu_intro.adoc
@@ -587,8 +587,6 @@ and has several interfaces (see <<fig:iommu-interfaces>>):
 .IOMMU interfaces.
 image::interfaces.svg[width=800, align="center"]
 
-<<<
-
 The interfaces related to recording an incoming MSI in a memory-resident
 interrupt file (MRIF) (See RISC-V Advanced Interrupt Architecture cite:[AIA])
 are implementation-specific. The partitioning of responsibility between
diff --git a/iommu_registers.adoc b/iommu_registers.adoc
index 857352ee..1689058a 100644
--- a/iommu_registers.adoc
+++ b/iommu_registers.adoc
@@ -690,6 +690,8 @@ In RV32, only the low order 32-bits of the register (22-bit `PPN` and
 5-bit `LOG2SZ-1`) need to be written.
 ====
 
+<<<
+
 [[PQH]]
 === Page-request-queue head (`pqh`)
 
@@ -866,6 +868,8 @@ to wait for all previous commands to be committed, if so desired, before
 turning off the command-queue.
 ====
 
+<<<
+
 [[FQCSR]]
 === Fault queue CSR (`fqcsr`)
 
@@ -1134,6 +1138,8 @@ If a bit in `ipsr` is 1 then a write of 1 to the bit transitions the bit from 1-
 If the conditions to set that bit are still present (See <<IPSR_FIELD>>) or if
 they occur after the bit is cleared then that bit transitions again from 0->1.
 
+<<<
+
 [[OVF]]
 === Performance-monitoring counter overflow status (`iocountovf`)
 The performance-monitoring counter overflow status is a 32-bit read-only