From d7f462dddd687a9b31c42bbf4d21229dfb60d872 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Thu, 4 May 2023 14:43:09 +0800 Subject: [PATCH 01/14] Update reint_op_template.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- .../rvv_intrinsic_gen/templates/reint_op_template.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/reint_op_template.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/reint_op_template.py index d7cdaf516..189596fa3 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/reint_op_template.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/reint_op_template.py @@ -40,8 +40,10 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): # Variable in list means # [dst type, dst short type, src type, src short type] convert_set = [["float", "f", "int", "i"], ["float", "f", "uint", "u"], + ["bfloat", "bf", "int", "i"], ["bfloat", "bf", "uint", "u"], ["uint", "u", "int", "i"], ["int", "i", "uint", "u"], - ["int", "i", "float", "f"], ["uint", "u", "float", "f"]] + ["int", "i", "float", "f"], ["uint", "u", "float", "f"], + ["int", "i", "bfloat", "bf"], ["uint", "u", "bfloat", "bf"]] for args in prod( OP=op_list, SEW=sew_list, TYPES=convert_set, LMUL=lmul_list): From 9805fb3922216d62adfa446ba8d3950082e56551 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Thu, 4 May 2023 17:42:15 +0800 Subject: [PATCH 02/14] Update constants.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py | 1 + 1 file changed, 1 insertion(+) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py index 15915a6f6..bb1c47cd0 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py @@ -29,6 +29,7 @@ TYPES = ["float", "int", "uint"] ITYPES = ["int", "uint"] FTYPES = ["float"] +BFTYPES = ["float", "bfloat"] MTYPES = ["bool"] MLENS = [1, 2, 4, 8, 16, 32, 64] REF_DOC_URL = "../rvv-intrinsic-api.md" From f5387af55a46bf72b1c8e323f8a9e7072093789d Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Thu, 4 May 2023 17:44:18 +0800 Subject: [PATCH 03/14] Update inst.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py index bb9e3dba0..3d558dd98 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py @@ -43,7 +43,7 @@ from templates import mask_load_store_template from templates import permute_template from constants import LMULS,WLMULS,NCVTLMULS,SEWS,WSEWS,FSEWS,WFSEWS,NSEWS,\ - TYPES,ITYPES,FTYPES,MTYPES,MLENS,REF_DOC_URL + TYPES,ITYPES,FTYPES,BFTYPES,MTYPES,MLENS,REF_DOC_URL from generator import CompatibleHeaderGenerator @@ -331,7 +331,7 @@ def gen(g): "Vector Widening Floating-Point Fused Multiply-Add Functions", REF_DOC_URL + "#147-vector-widening-floating-point-fused-multiply-add-operations", - ["wmacc", "wnmacc", "wmsac", "wnmsac"], FTYPES, WFSEWS, WLMULS, + ["wmacc", "wnmacc", "wmsac", "wnmsac"], BFTYPES, WFSEWS, WLMULS, decorators.has_masking_no_maskedoff_policy) g.function_group( From 6ec7e95b383d9e79bf960dc2795dfdacbfe08db3 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Thu, 4 May 2023 17:45:04 +0800 Subject: [PATCH 04/14] Update mac_template.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- .../templates/mac_template.py | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/mac_template.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/mac_template.py index 0a44115f2..9b316a8a5 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/mac_template.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/mac_template.py @@ -41,6 +41,10 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): args["S_TYPE"] = "f" args["OP"] = "f" + op inst_type = InstType.VVF + elif data_type == "bfloat": + args["S_TYPE"] = "f" + args["OP"] = "f" + op + "bf16" + inst_type = InstType.VVF else: args["S_TYPE"] = "x" inst_type = InstType.VVX @@ -146,6 +150,30 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): vs1=type_helper.s, vs2=type_helper.v, vl=type_helper.size_t) + elif data_type == "bfloat": + if "wmacc" in op and args["SEW"] == 16: + G.func( + inst_info_vv, + name="{OP}_vv_f{WSEW}m{WLMUL}".format_map(args) + + decorator.func_suffix, + return_type="vfloat{WSEW}m{WLMUL}_t".format_map(args), + **decorator.mask_args(type_helper.m, type_helper.v), + vd="vfloat{WSEW}m{WLMUL}_t".format_map(args), + vs1=type_helper.v, + vs2=type_helper.v, + vl=type_helper.size_t) + G.func( + inst_info_vs, + name="{OP}_v{S_TYPE}_f{WSEW}m{WLMUL}".format_map(args) + + decorator.func_suffix, + return_type="vfloat{WSEW}m{WLMUL}_t".format_map(args), + **decorator.mask_args(type_helper.m, type_helper.v), + vd="vfloat{WSEW}m{WLMUL}_t".format_map(args), + vs1=type_helper.s, + vs2=type_helper.v, + vl=type_helper.size_t) + else: + continue else: G.func( inst_info_vv, From f4a721cf9a7205e95a406ed0ab4f935a60e8e1b2 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Thu, 4 May 2023 17:45:24 +0800 Subject: [PATCH 05/14] Update cvt_op_template.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- .../rvv_intrinsic_gen/templates/cvt_op_template.py | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py index 1d6580682..0258e8837 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py @@ -40,7 +40,8 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): convert_set = [["int", "x", "float", "f"], ["int", "x", "int", "x"], ["uint", "x", "uint", "x"], ["uint", "xu", "float", "f"], ["float", "f", "int", "x"], ["float", "f", "uint", "xu"], - ["float", "f", "float", "f"]] + ["float", "f", "float", "f"], ["bfloat", "bf", "float", "f"], + ["float", "f", "bfloat", "bf"]] for args in prod( OP=op_list, SEW=sew_list, TYPES=convert_set, LMUL=lmul_list): op = args["OP"] @@ -54,6 +55,13 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): if (op == "cvt" and args["TYPES1"] == args["TYPES3"]): continue + if ((args["TYPES1"] == "bf" or args["TYPES3"] == "bf") and op == "cvt"): + continue + + if ((args["TYPES3"] == "bf" and args["SEW"] != 16 ) or + (args["TYPES1"] == "bf" and args["SEW"] != 32)): + continue + args["MIDDLE"] = "v" factor = "" if op == "wcvt": @@ -68,6 +76,9 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): if args["TYPES1"] == "f" or args["TYPES3"] == "f": args["OP"] = "f" + args["OP"] + if args["TYPES1"] == "bf" or args["TYPES3"] == "bf": + args["OP"] = args["OP"] + "bf16" + if args["TYPES0"] == "uint": args["D_TYPE"] = "u" elif args["TYPES1"] == "x": From 454cedb3831c066b4775cc59673076d96c9bbf01 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Sat, 6 May 2023 15:48:59 +0800 Subject: [PATCH 06/14] Update inst.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py index 3d558dd98..46bf91aea 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py @@ -331,7 +331,14 @@ def gen(g): "Vector Widening Floating-Point Fused Multiply-Add Functions", REF_DOC_URL + "#147-vector-widening-floating-point-fused-multiply-add-operations", - ["wmacc", "wnmacc", "wmsac", "wnmsac"], BFTYPES, WFSEWS, WLMULS, + ["wmacc", "wnmacc", "wmsac", "wnmsac"], FTYPES, WFSEWS, WLMULS, + decorators.has_masking_no_maskedoff_policy) + + g.function_group( + mac_template, + "Vector BFloat16 Widening Multiply-Add Functions (draft)", + REF_DOC_URL + "#147-vector-bf16-widening-multiply-add-operations", + ["wmacc"], BFTYPES, WFSEWS, WLMULS, decorators.has_masking_no_maskedoff_policy) g.function_group( From bc766e4fd456063e348ed05a04d44fe40af28017 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Sat, 6 May 2023 15:50:02 +0800 Subject: [PATCH 07/14] Update constants.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py index bb1c47cd0..b10b180fe 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py @@ -29,7 +29,7 @@ TYPES = ["float", "int", "uint"] ITYPES = ["int", "uint"] FTYPES = ["float"] -BFTYPES = ["float", "bfloat"] +BFTYPES = ["bfloat"] MTYPES = ["bool"] MLENS = [1, 2, 4, 8, 16, 32, 64] REF_DOC_URL = "../rvv-intrinsic-api.md" From 65289d47b6a21e045dd88ed205eeb9891ccd6762 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Mon, 8 May 2023 19:53:47 +0800 Subject: [PATCH 08/14] Update cvt_op_template.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- .../rvv_intrinsic_gen/templates/cvt_op_template.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py index 0258e8837..dc2d916b1 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py @@ -112,7 +112,7 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): **decorator.tu_dest_args(rt), src=src_type, vl=type_helper.size_t) - if args["TYPES1"] != args["TYPES3"] and args["TYPES3"] == "f": + if args["TYPES1"] != args["TYPES3"] and args["TYPES3"] == "f" and args["TYPES1"] != "bf": args["OP"] = args["OP"] + "_rtz" inst_info = InstInfo.get( args, decorator, InstType.VV, extra_attr=extra_attr) From 9dae2c44eaa032f41fbc7b427565aaca66291aa0 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Tue, 16 May 2023 10:49:36 +0800 Subject: [PATCH 09/14] Introduce new types using bfloat16 Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- rvv-intrinsic-rfc.md | 48 +++++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/rvv-intrinsic-rfc.md b/rvv-intrinsic-rfc.md index b193e018b..74cce92d3 100644 --- a/rvv-intrinsic-rfc.md +++ b/rvv-intrinsic-rfc.md @@ -51,32 +51,34 @@ Further, individual intrinsic functions depend on the availability of the corres Encode `SEW` and `LMUL` into data types. We enforce the constraint `LMUL ≥ SEW/ELEN` in the implementation. There are the following data types for `ELEN` = 64. -| Types | LMUL = 1 | LMUL = 2 | LMUL = 4 | LMUL = 8 | LMUL = 1/2 | LMUL = 1/4 | LMUL = 1/8 -| ------------ | ------------ | ------------ | ------------ | ----------- | ------------- | ------------- | -------------- -| **int64_t** | vint64m1_t | vint64m2_t | vint64m4_t | vint64m8_t | N/A | N/A | N/A -| **uint64_t** | vuint64m1_t | vuint64m2_t | vuint64m4_t | vuint64m8_t | N/A | N/A | N/A -| **int32_t** | vint32m1_t | vint32m2_t | vint32m4_t | vint32m8_t | vint32mf2_t | N/A | N/A -| **uint32_t** | vuint32m1_t | vuint32m2_t | vuint32m4_t | vuint32m8_t | vuint32mf2_t | N/A | N/A -| **int16_t** | vint16m1_t | vint16m2_t | vint16m4_t | vint16m8_t | vint16mf2_t | vint16mf4_t | N/A -| **uint16_t** | vuint16m1_t | vuint16m2_t | vuint16m4_t | vuint16m8_t | vuint16mf2_t | vuint16mf4_t | N/A -| **int8_t** | vint8m1_t | vint8m2_t | vint8m4_t | vint8m8_t | vint8mf2_t | vint8mf4_t | vint8mf8_t -| **uint8_t** | vuint8m1_t | vuint8m2_t | vuint8m4_t | vuint8m8_t | vuint8mf2_t | vuint8mf4_t | vuint8mf8_t -| **vfloat64** | vfloat64m1_t | vfloat64m2_t | vfloat64m4_t | vfloat64m8_t | N/A | N/A | N/A -| **vfloat32** | vfloat32m1_t | vfloat32m2_t | vfloat32m4_t | vfloat32m8_t | vfloat32mf2_t | N/A | N/A -| **vfloat16** | vfloat16m1_t | vfloat16m2_t | vfloat16m4_t | vfloat16m8_t | vfloat16mf2_t | vfloat16mf4_t | N/A +| Types | LMUL = 1 | LMUL = 2 | LMUL = 4 | LMUL = 8 | LMUL = 1/2 | LMUL = 1/4 | LMUL = 1/8 +| ------------ | ------------ | ------------ | ------------ | ----------- | ------------- | ------------- | -------------- +| **int64_t** | vint64m1_t | vint64m2_t | vint64m4_t | vint64m8_t | N/A | N/A | N/A +| **uint64_t** | vuint64m1_t | vuint64m2_t | vuint64m4_t | vuint64m8_t | N/A | N/A | N/A +| **int32_t** | vint32m1_t | vint32m2_t | vint32m4_t | vint32m8_t | vint32mf2_t | N/A | N/A +| **uint32_t** | vuint32m1_t | vuint32m2_t | vuint32m4_t | vuint32m8_t | vuint32mf2_t | N/A | N/A +| **int16_t** | vint16m1_t | vint16m2_t | vint16m4_t | vint16m8_t | vint16mf2_t | vint16mf4_t | N/A +| **uint16_t** | vuint16m1_t | vuint16m2_t | vuint16m4_t | vuint16m8_t | vuint16mf2_t | vuint16mf4_t | N/A +| **int8_t** | vint8m1_t | vint8m2_t | vint8m4_t | vint8m8_t | vint8mf2_t | vint8mf4_t | vint8mf8_t +| **uint8_t** | vuint8m1_t | vuint8m2_t | vuint8m4_t | vuint8m8_t | vuint8mf2_t | vuint8mf4_t | vuint8mf8_t +| **vfloat64** | vfloat64m1_t | vfloat64m2_t | vfloat64m4_t | vfloat64m8_t | N/A | N/A | N/A +| **vfloat32** | vfloat32m1_t | vfloat32m2_t | vfloat32m4_t | vfloat32m8_t | vfloat32mf2_t | N/A | N/A +| **vfloat16** | vfloat16m1_t | vfloat16m2_t | vfloat16m4_t | vfloat16m8_t | vfloat16mf2_t | vfloat16mf4_t | N/A +| **vbfloat16** | vbfloat16m1_t | vbfloat16m2_t | vbfloat16m4_t | vbfloat16m8_t | vbfloat16mf2_t | vbfloat16mf4_t | N/A There are the following data types for `ELEN` = 32. -| Types | LMUL = 1 | LMUL = 2 | LMUL = 4 | LMUL = 8 | LMUL = 1/2 | LMUL = 1/4 | LMUL = 1/8 -| ------------ | ------------ | ------------ | ------------ | ----------- | ------------- | ------------- | -------------- -| **int32_t** | vint32m1_t | vint32m2_t | vint32m4_t | vint32m8_t | N/A | N/A | N/A -| **uint32_t** | vuint32m1_t | vuint32m2_t | vuint32m4_t | vuint32m8_t | N/A | N/A | N/A -| **int16_t** | vint16m1_t | vint16m2_t | vint16m4_t | vint16m8_t | vint16mf2_t | N/A | N/A -| **uint16_t** | vuint16m1_t | vuint16m2_t | vuint16m4_t | vuint16m8_t | vuint16mf2_t | N/A | N/A -| **int8_t** | vint8m1_t | vint8m2_t | vint8m4_t | vint8m8_t | vint8mf2_t | vint8mf4_t | N/A -| **uint8_t** | vuint8m1_t | vuint8m2_t | vuint8m4_t | vuint8m8_t | vuint8mf2_t | vuint8mf4_t | N/A -| **vfloat32** | vfloat32m1_t | vfloat32m2_t | vfloat32m4_t | vfloat32m8_t | N/A | N/A | N/A -| **vfloat16** | vfloat16m1_t | vfloat16m2_t | vfloat16m4_t | vfloat16m8_t | vfloat16mf2_t | N/A | N/A +| Types | LMUL = 1 | LMUL = 2 | LMUL = 4 | LMUL = 8 | LMUL = 1/2 | LMUL = 1/4 | LMUL = 1/8 +| ------------ | ------------ | ------------ | ------------ | ----------- | ------------- | ------------- | -------------- +| **int32_t** | vint32m1_t | vint32m2_t | vint32m4_t | vint32m8_t | N/A | N/A | N/A +| **uint32_t** | vuint32m1_t | vuint32m2_t | vuint32m4_t | vuint32m8_t | N/A | N/A | N/A +| **int16_t** | vint16m1_t | vint16m2_t | vint16m4_t | vint16m8_t | vint16mf2_t | N/A | N/A +| **uint16_t** | vuint16m1_t | vuint16m2_t | vuint16m4_t | vuint16m8_t | vuint16mf2_t | N/A | N/A +| **int8_t** | vint8m1_t | vint8m2_t | vint8m4_t | vint8m8_t | vint8mf2_t | vint8mf4_t | N/A +| **uint8_t** | vuint8m1_t | vuint8m2_t | vuint8m4_t | vuint8m8_t | vuint8mf2_t | vuint8mf4_t | N/A +| **vfloat32** | vfloat32m1_t | vfloat32m2_t | vfloat32m4_t | vfloat32m8_t | N/A | N/A | N/A +| **vfloat16** | vfloat16m1_t | vfloat16m2_t | vfloat16m4_t | vfloat16m8_t | vfloat16mf2_t | N/A | N/A +| **vbfloat16** | vbfloat16m1_t | vbfloat16m2_t | vbfloat16m4_t | vbfloat16m8_t | vbfloat16mf2_t | N/A | N/A ### Mask Types From fd6d264d8c32f13dae4423ac50e2322b1f591ab6 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Tue, 16 May 2023 14:39:51 +0800 Subject: [PATCH 10/14] Update inst.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- .../rvv_intrinsic_gen/inst.py | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py index 46bf91aea..02ba953c5 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py @@ -334,13 +334,6 @@ def gen(g): ["wmacc", "wnmacc", "wmsac", "wnmsac"], FTYPES, WFSEWS, WLMULS, decorators.has_masking_no_maskedoff_policy) - g.function_group( - mac_template, - "Vector BFloat16 Widening Multiply-Add Functions (draft)", - REF_DOC_URL + "#147-vector-bf16-widening-multiply-add-operations", - ["wmacc"], BFTYPES, WFSEWS, WLMULS, - decorators.has_masking_no_maskedoff_policy) - g.function_group( unary_op_template, "Vector Floating-Point Square-Root Functions", REF_DOC_URL + "#148-vector-floating-point-square-root-operations", @@ -415,6 +408,27 @@ def gen(g): "Narrowing Floating-Point/Integer Type-Convert Functions", REF_DOC_URL + "#1419-narrowing-floating-pointinteger-type-convert-operations", ["ncvt"], "", NSEWS, NCVTLMULS, decorators.has_masking_maskedoff_policy) + + #################################################################### + g.start_group("Vector BFloat16 Functions (still on the draft status)") + + g.function_group( + mac_template, "Vector BFloat16 Widening Multiply-Add Functions", + REF_DOC_URL + "#1420-vector-bf16-widening-multiply-add-operations", + ["wmacc"], BFTYPES, WFSEWS, WLMULS, + decorators.has_masking_no_maskedoff_policy) + + g.function_group( + cvt_op_template, "Widening BFloat16/FP32 Type-Convert Functions", + REF_DOC_URL + + "#1421-widening-bf16-fp32-type-convert-operations", ["wcvtbf16"], + "", WSEWS, WLMULS, decorators.has_masking_maskedoff_policy) + + g.function_group( + cvt_op_template, + "Narrowing FP32/BFloat16 Type-Convert Functions", REF_DOC_URL + + "#1422-narrowing-fp32-bf16-type-convert-operations", ["ncvtbf16"], + "", NSEWS, NCVTLMULS, decorators.has_masking_maskedoff_policy) #################################################################### g.start_group("Vector Reduction Functions") From 75ae36ba05b5a6b1bc466718b140d94432f408a0 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Tue, 16 May 2023 14:40:24 +0800 Subject: [PATCH 11/14] Update cvt_op_template.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- .../rvv_intrinsic_gen/templates/cvt_op_template.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py index dc2d916b1..a621ae41f 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py @@ -55,11 +55,12 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): if (op == "cvt" and args["TYPES1"] == args["TYPES3"]): continue - if ((args["TYPES1"] == "bf" or args["TYPES3"] == "bf") and op == "cvt"): + if ((args["TYPES1"] == "bf" or args["TYPES3"] == "bf") and + op != "wcvtbf16" and op != "ncvtbf16"): continue - if ((args["TYPES3"] == "bf" and args["SEW"] != 16 ) or - (args["TYPES1"] == "bf" and args["SEW"] != 32)): + if ((op == "wcvtbf16" and args["TYPES1"] != "bf" ) or + (op == "ncvtbf16" and args["TYPES3"] != "bf" )): continue args["MIDDLE"] = "v" @@ -76,9 +77,6 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): if args["TYPES1"] == "f" or args["TYPES3"] == "f": args["OP"] = "f" + args["OP"] - if args["TYPES1"] == "bf" or args["TYPES3"] == "bf": - args["OP"] = args["OP"] + "bf16" - if args["TYPES0"] == "uint": args["D_TYPE"] = "u" elif args["TYPES1"] == "x": From ce33add965e7bf10533de1a80fb78e4bab73c516 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Tue, 16 May 2023 14:55:56 +0800 Subject: [PATCH 12/14] Update cvt_op_template.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- .../rvv_intrinsic_gen/templates/cvt_op_template.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py index a621ae41f..a912ca39b 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/cvt_op_template.py @@ -59,15 +59,15 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list): op != "wcvtbf16" and op != "ncvtbf16"): continue - if ((op == "wcvtbf16" and args["TYPES1"] != "bf" ) or - (op == "ncvtbf16" and args["TYPES3"] != "bf" )): + if ((op == "wcvtbf16" and args["TYPES3"] != "bf" ) or + (op == "ncvtbf16" and args["TYPES1"] != "bf" )): continue args["MIDDLE"] = "v" factor = "" - if op == "wcvt": + if op == "wcvt" or op == "wcvtbf16": factor = "W" - if op == "ncvt": + if op == "ncvt" or op == "ncvtbf16": factor = "N" args["MIDDLE"] = "w" From 1035c960d28a6716dcc9156333f3f3f4de8726c3 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Wed, 17 May 2023 16:32:16 +0800 Subject: [PATCH 13/14] Update inst.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py index 02ba953c5..1cd09d542 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py @@ -43,7 +43,7 @@ from templates import mask_load_store_template from templates import permute_template from constants import LMULS,WLMULS,NCVTLMULS,SEWS,WSEWS,FSEWS,WFSEWS,NSEWS,\ - TYPES,ITYPES,FTYPES,BFTYPES,MTYPES,MLENS,REF_DOC_URL + TYPES,BTYPES,ITYPES,FTYPES,BFTYPES,MTYPES,MLENS,REF_DOC_URL from generator import CompatibleHeaderGenerator @@ -68,11 +68,11 @@ def gen(g): g.function_group(load_template, "Vector Unit-Stride Load Functions", REF_DOC_URL + "#74-vector-unit-stride-operations", ["vle"], - TYPES, SEWS, LMULS, decorators.has_masking_maskedoff_policy) + BTYPES, SEWS, LMULS, decorators.has_masking_maskedoff_policy) g.function_group(store_template, "Vector Unit-Stride Store Functions", REF_DOC_URL + "#74-vector-unit-stride-operations", ["vse"], - TYPES, SEWS, LMULS, decorators.has_masking_no_maskedoff) + BTYPES, SEWS, LMULS, decorators.has_masking_no_maskedoff) g.function_group(load_template, "Vector Strided Load Functions", REF_DOC_URL + "#75-vector-strided-loadstore-operations", From 67eeb5efbf3dc02a0717da05223465dfcd2820c5 Mon Sep 17 00:00:00 2001 From: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> Date: Wed, 17 May 2023 16:32:57 +0800 Subject: [PATCH 14/14] Update constants.py Signed-off-by: joshua-arch1 <68843032+joshua-arch1@users.noreply.github.com> --- rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py | 1 + 1 file changed, 1 insertion(+) diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py index b10b180fe..46217d902 100644 --- a/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py +++ b/rvv-intrinsic-generator/rvv_intrinsic_gen/constants.py @@ -27,6 +27,7 @@ WFSEWS = [16, 32] NSEWS = [16, 32, 64] TYPES = ["float", "int", "uint"] +TYPES = ["float", "int", "uint", "bfloat"] ITYPES = ["int", "uint"] FTYPES = ["float"] BFTYPES = ["bfloat"]