Since most of these registers are WARL, what are we using for safe vs. unsafe criteria? Is it going to be related to side-effects, e.g. mtvec pointing to a potentially invalid memory region only triggered by an interrupt/exception?

Whatever criteria we come up with, maybe we should also add a blurb to the top-level register module about them?

Adding the safe opt-out is a good approach in my opinion. I agree that the CSR writes should be unsafe by default.

what are we using for safe vs. unsafe criteria? Is it going to be related to side-effects, e.g. mtvec pointing to a potentially invalid memory region only triggered by an interrupt/exception?

Yes, let us leave all writes of CSRs that might trigger invalid states unsafe. mtvec is a good example. I guess that mstatus must also be unsafe, as it can break critical sections, for instance.