The class Timer
defines a set of core methods for timing analysis under the namespace ot.
Each method belongs to either a builder, an action, or an accessor operation.
| Command | Form | Description |
|---|---|---|
| read_celllib | builder | reads a liberty format library file |
| read_verilog | builder | reads a gate-level verilog netlist |
| read_spef | builder | reads a file of net parasitics in SPEF format |
| read_sdc | builder | reads a Synopsys Design Constraint (sdc) file of version 2.1 |
| read_timing | builder | reads a TAU15 Contest assertion file of timing constraints |
| set_at | builder | specifies the arrival time of an input port |
| set_rat | builder | specifies the required arrival time of an output port |
| set_slew | builder | specifies the transition time of an input port |
| set_load | builder | specifies the load capacitance of an output port |
| insert_gate | builder | inserts a gate (instance) to the design |
| remove_gate | builder | removes a gate (instance) from the design |
| repower_gate | builder | repowers a gate (instance) with a new cell |
| insert_net | builder | inserts an empty net to the design |
| remove_net | builder | removes a net from the design |
| connect_pin | builder | connects a pin to a net |
| disconnect_pin | builder | disconnect a pin from the net it connects to |
| enable_cppr | builder | enables common path pessimism removal analysis |
| disable_cppr | builder | disables common path pessimism removal analysis |
| update_timing | action | updates the timer to keep all timing values up-to-date |
| report_timing | action | report the critical paths of the design |
| report_at | action | reports the arrival time at a pin |
| report_slew | action | reports the transition time at a pin |
| report_rat | action | reports the required arrival time at a pin |
| report_slack | action | reports the slack at a pin |
| report_tns | action | reports the total negative slack of the design |
| report_wns | action | reports the worst negative slack of the design |
| report_fep | action | reports the total failing endpoints in the design |
| dump_graph | accessor | dumps the timing graph to an output stream |
| dump_taskflow | accessor | dumps the lineage graph to an output stream |
| dump_timer | accessor | dumps the statistics of the design |
| num_primary_inputs | accessor | queries the number of primary inputs in the design |
| num_primary_outputs | accessor | queries the number of primary outputs in the design |
| num_pins | accessor | queries the number of pins in the design |
| num_nets | accessor | queries the number of nets in the design |
| num_arcs | accessor | queries the number of arcs in the timing graph |
| num_gates | accessor | queries the number of gates in the design |
| num_tests | accessor | queries the number of timing tests (checks) in the design |
| primary_inputs | accessor | acquires a const reference to the data structure of primary inputs |
| primary_outputs | accessor | acquires a const reference to the data structure of primary outputs |
| pins | accessor | acquires a const reference to the data structure of pins |
| nets | accessor | acquires a const reference to the data structure of nets |
| gates | accessor | acquires a const reference to the data structure of gates |
| clocks | accessor | acquires a const reference to the data structure of clocks |
| tests | accessor | acquires a const reference to the data structure of tests |
| arcs | accessor | acquires a const reference to the data structure of arcs |
The above list of methods is consider stable. Other methods found in timer.hpp but not listed in the table may change in the future release.
Reads a Liberty format library file. In most cases, this is the first method to initialize a timing analysis framework.
Timer& read_celllib(std::filesystem::path path, std::optional<Split> split = {});- path: the file path of the liberty file to read
- split: use this library for either min or max delay calculation
*this
The method adds two tasks to the lineage graph; one parses the library and the other attaches the library to the timer.
Reads a gate-level verilog netlist and initializes the circuit graph from the library.
Timer& read_verilog(std::filesystem::path path);- path: the file path of the verilog netlist to read
*this
The method adds two tasks to the lineage graph; one parses the verilog file and the other initializes the circuit graph from it.
Reads a parasitics file in SPEF.
Timer& read_spef(std::filesystem::path path);- path: the path of the SPEF file to read
*this
The method adds two tasks to the lineage graph; one parses the SPEF file and the other digests the net parasitics.
Reads a Synopsys Design Constraint (SDC) file.
Timer& read_sdc(std::filesystem::path path);- path: the path of the sdc file to read
*this
The method adds two tasks to the lineage graph; one parses the sdc file and the other digests the timing constraints.
The supporting status of SDC commands is described here.
Reads a TAU15 Contest Format timing assertion file.
Timer& read_timing(std::filesystem::path path);- path: the path of the timing assertion file to read
*this
The method adds two tasks to the lineage graph; one parses the timing file and the other digests the timing constraints.
Specifies the arrival time of an input port at a given min/max split and rise/fall transition.
Timer& set_at(std::string port, Split split, Tran tran, std::optional<float> value);- port: the name of the input port
- split: the minimum or maximum arrival time
- tran: the rising or falling edge
- value: the arrival time value; use
std::nulloptto unset the arrival time of the port
*this
Specifies the required arrival time of an output port at a given min/max split and rise/fall transition.
Timer& set_rat(std::string port, Split split, Tran tran, std::optional<float> value);- port: the name of the output port
- split: the required arrival time at min or max split
- tran: the rising or falling edge
- value: the arrival time value; use
std::nulloptto unset the arrival time of the port
*this
Specifies the transition time of an input port at a given min/max split and rise/fall transition.
Timer& set_at(std::string port, Split split, Tran tran, std::optional<float> value);- port: the name of the input port
- split: the minimum or maximum transition time
- tran: the rising or falling edge
- value: the transition time value; use
std::nulloptto unset the transition time of the port
*this
Specifies the load capacitance of an output port at a given min/max split and rise/fall transition.
Timer& set_load(std::string port, Split split, Tran tran, std::optional<float> value);- port: the name of the output port
- split: the load capacitance at min or max split
- tran: the load capacitance at rising or falling edge
- value: the load capacitance value; use
std::nulloptto unset the load capacitance of the port
*this
Inserts a gate into the design. The newly inserted gate is not connected to any other gates or wires.
Timer& insert_gate(std::string gate, std::string cell);- gate: the name of the gate to insert to the design
- cell: the name of the cell to associate with the gate
*this
Removes a gate from the design. The gate will be disconnected from the design before removal.
Timer& remove_gate(std::string gate);- gate: the name of the gate to remove from the design
*this
Changes the size or the level of an existing gate, or insert a new gate if it does not exist.
Timer& repower_gate(std::string gate, std::string cell);- gate: the name of the gate to repower
- cell: the name of the cell to associate with the gate
*this
The topology of the new cell must be the same as the old cell, or it can result in undefined behavior. However the pin capacitance, for example, of the new cell can be different.
Inserts an empty net object to the design.
Timer& insert_net(std::string net);- net: the name of the net to insert to the design
*this
The net will be connected to existing pins in the design by the method connect_pin.
Removes a net from the design.
Timer& remove_net(std::string net);- net: the name of the net to remove from the design
*this
If a net is connected to pins, the pins will be automatically disconnected from the net. The corresponding parasitics will also be removed.
Connects a pin to a net.
Timer& connect_pin(std::string pin, std::string net);- pin: the name of the pin
- net: the name of the net
*this
Disconnects a pin from the net it connects to.
Timer& disconnect_pin(std::string pin);- pin: the name of the pin
*this
Enables the common path pessimism removal (CPPR) analysis.
Timer& enable_cppr();none
*this
Disables the common path pessimism removal (CPPR) analysis.
Timer& disable_cppr();none
*this
Triggers the timing update to keep all timing information (arrival time, slew, required arrival time, etc) up-to-date.
void update_timing();none
none
This is the bottom-most call of all action methods.
Reports the critical paths of the design.
1. std::vector<Path> report_timing(size_t k);
2. std::vector<Path> report_timing(size_t k, Split split, Tran tran)
3. std::vector<Path> report_timing(size_t k, Split split)
4. std::vector<Path> report_timing(size_t k, Tran tran)- reports the top-k critical paths across all endpoints
- K: the number of paths to report
- reports the top-k critical min/max paths for rising/falling endpoints
- K: the number of paths to report
- split: minimum or maximum path
- tran: rising or falling endpoints
- report the top-k critical min/max paths across both rising and falling endpoints
- K: the number of paths to report
- split: minimum or maximum path
- report the top-k critical paths for rising/falling endpoints
- K: the number of paths to report
- tran: rising or falling endpoints
A vector of paths of type Path, defined in path.hpp.
Reports the arrival time of a pin at a given min/max split and rise/fall edge.
std::optional<float> report_at(const std::string& pin, Split split, Tran tran);- pin: the name of the pin to report
- split: the minimum or maximum arrival time
- tran: the rising or falling edge
Returns the arrival time if found, or std::nullopt.
The arrival time may not be found, for example, the pin doesn't exist or the timing propagation doesn't go through the pin.
Reports the required arrival time of a pin at a given min/max split and rise/fall edge.
std::optional<float> report_rat(const std::string& pin, Split split, Tran tran);- pin: the name of the pin to report
- split: the minimum or maximum required arrival time
- tran: the rising or falling edge
Returns the required arrival time if found, or std::nullopt.
The required arrival time may not be found, for example, the pin doesn't exist or the timing propagation doesn't go through the pin.
Reports the transition time of a pin at a given min/max split and rise/fall edge.
std::optional<float> report_slew(const std::string& pin, Split split, Tran tran);- pin: the name of the pin to report
- split: the minimum or maximum transition time
- tran: the rising or falling edge
Returns the transition time if found, or std::nullopt.
The transition time may not be found, for example, the pin doesn't exist or the timing propagation doesn't go through the pin.
Reports the load capacitance of a net at a given min/max split and rise/fall edge.
std::optional<float> report_load(const std::string& pin, Split split, Tran tran);- pin: the name of the pin to report
- split: the minimum or maximum load capacitance
- tran: the rising or falling edge
Returns the load capacitance if found, or std::nullopt.
The load capacitance may not be found, for example, the net doesn't exist or the timing propagation doesn't go through the net.
Reports the total negative slack (TNS) across all endpoints.
std::optional<float> report_tns();none
Returns the total negative slack if found, or std::nullopt.
The total negative slack may not be found, for example, the timing propagation doesn't go through any endpoints.
Reports the worst negative slack (WNS) across all endpoints.
std::optional<float> report_wns();none
Returns the worst negative slack if found, or std::nullopt.
The worst negative slack may not be found, for example, the timing propagation doesn't go through any endpoints.
Reports the total number of failing endpoints (FEP) across all endpoints.
std::optional<size_t> report_fep();none
Returns the total number of failing endpoints if found, or std::nullopt.
The total number of failing endpoints may be be found, for example, the timing propagation doesn't go through any endpoints.
Dumps the timing graph to a DOT format.
void dump_graph(std::ostream& ostream) const;- ostream: the target output stream to dump
none
Dumps the lineage graph to a DOT format.
void dump_taskflow(std::ostream& ostream) const;- ostream: the target output stream to dump
none
Dumps the statistics of the design.
void dump_timer(std::ostream& ostream) const;- ostream: the target output stream to dump
none
Queries the number of primary inputs in the design.
size_t num_primary_inputs() const;none
An unsigned integer for the number of primary inputs in the design.
Queries the number of primary outputs in the design.
size_t num_primary_outputs() const;none
An unsigned integer for the number of primary outputs in the design.
Queries the number of pins in the design.
size_t num_pins() const;none
An unsigned integer for the number of pins in the design.
Queries the number of nets in the design.
size_t num_nets() const;none
An unsigned integer for the number of nets in the design.
Queries the number of arcs in the design.
size_t num_arcs() const;none
An unsigned integer for the number of arcs in the design.
Queries the number of gates in the design.
size_t num_gates() const;none
An unsigned integer for the number of gates in the design.
Queries the number of tests (checks) in the design.
size_t num_tests() const;none
An unsigned integer for the number of tests in the design.
Acquires a const reference to the data structure of primary inputs.
const std::unordered_map<std::string, Pin>& primary_inputs() const;none
A constant reference to the data structure of primary inputs.
Acquires a const reference to the data structure of primary outputs.
const std::unordered_map<std::string, Pin>& primary_outputs() const;none
A constant reference to the data structure of primary outputs.
Acquires a const reference to the data structure of pins.
const std::unordered_map<std::string, Pin>& pins() const;none
A constant reference to the data structure of pins.
Acquires a const reference to the data structure of nets.
const std::unordered_map<std::string, Net>& nets() const;none
A constant reference to the data structure of nets.
Acquires a const reference to the data structure of gates.
const std::unordered_map<std::string, Gate>& gates() const;none
A constant reference to the data structure of gates.
Acquires a const reference to the data structure of clocks.
const std::unordered_map<std::string, Clock>& clocks() const;none
A constant reference to the data structure of clocks.
Acquires a const reference to the data structure of tests (timing checks).
const std::list<Test>& tests() const;none
A constant reference to the data structure of tests.
Acquires a const reference to the data structure of arcs.
const std::list<Arc>& arcs() const;none
A constant reference to the data structure of arcs.