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symexec.c
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symexec.c
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/*******************************************************************************
*
* Chronos: A Timing Analyzer for Embedded Software
* =============================================================================
* http://www.comp.nus.edu.sg/~rpembed/chronos/
*
* Infeasible path analysis for Chronos
* Vivy Suhendra
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License as published by the Free Software
* Foundation; either version 2, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
* details.
*
* 03/2007 symexec.c
*
* Version update
* v1.1:
* _ perform sym.exec to identify constant value in register first
* then detect induction val., to handle: add $1 $1 $2, where $2 = const
* _ perform simple memory modeling with lw,sw; to deal with register spill
* _ parse disassembly file using C-string rather than shell call -> faster
* v1.0:
* _ add induction value detection of register value
* _ add merge register value from predecessors to support inter-block
* deritree construction (still intra-procedures)
* _ add other things necessary to perform register expansion for RTSS2010
******************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "cfg.h"
#include "common.h"
#include "loops.h"
#include "infeasible.h"
#include "reg.h"
#include "imm/machine.h"
#include "mem_value.h"
#define MIN_VAL (0-0xffff)
/*** MEMORY MODELING FRAMEWORK ***/
void printMemList(FILE* fp, worklist_p);
mem_p createMem(addr_t instAddr, reg_t writeAddr, reg_t regValue);
int copyMem(mem_p dst, mem_p src);
void clrMem(worklist_p memList);
void loadMem(worklist_p memList, reg_t writeAddr, reg_t *regValue);
int storeMem(worklist_p *memList, addr_t instAddr,
reg_t writeAddr, reg_t regValue);
int copyMemList(worklist_p *dstL, worklist_p srcL);
int memListEq(worklist_p list1, worklist_p list2);
int mergeMemList(worklist_p *dstList, worklist_p srcList);
/*** INDUCTION VALUE DETECTION ***/
biv_p createBIV(reg_t *regList, de_inst_t *insn);
static int regRedefined(int regName, de_inst_t *insn);
static int checkBivStride(reg_t *regList, de_inst_t *insn);
static void detectBIV(void);
static void update_cond_flags(int cond_flags, reg_t *reg_list);
/*** SYMBOLIC EXECUTION FRAMEWORK ***/
static void doSymExec(void);
static int joinBranch(inf_proc_t *iproc, inf_node_t *ib, int lpHeaderId);
static int regDerive(inf_node_t *ib, de_inst_t *insn,int ignore,char *jal,int dbg);
static void analyzeBlock(inf_node_t *ib);
static void readSymExecResult(inf_node_t *ib);
static void initAll(void);
static void freeAll(void);
int cntExec;
int conflictDetectFlag; /*Global: if do conflicting pair detection*/
int traceInductionFlag; /*Global: if trace induction value during sym.exec*/
int traceMemFlag; /*Global: if perform memory modeling during sym.exec*/
FILE* dbgExec; /*to debug the convergence*/
extern prog_t prog;
extern loop_t **loops;
extern int num_tcfg_loops;
/*** utility functions ***/
int getAddrD(dat_inst_t *d_inst) {
de_inst_t *insn;
insn = (de_inst_t*)(d_inst->insn);
return insn->addr;
}
void printDataRef(FILE *fp,dat_inst_t *d_inst) {
de_inst_t *insn;
//de_inst_t *inst;
//char *deritree;
insn = d_inst->insn;
//inst = d_inst->inst;
//deritree = d_inst->deritree;
if (fp) {
fprintf(fp, "\n\nDataRef: 0x%x %d\n",
insn->addr, insn->op_enum);
printExpr(fp,&(d_inst->addrExpr));
}
}
int isMemAccess(int inst_op) {
return (md_op2flags[inst_op] & F_LOAD) || (md_op2flags[inst_op] & F_STORE);
}
int isLoadInst(int inst_op) {
return (md_op2flags[inst_op] & F_LOAD);
}
int isStoreInst(int inst_op) {
return (md_op2flags[inst_op] & F_STORE);
}
loop_t* getIbLoop(inf_node_t *ib) {
loop_t *loop;
if (ib->loop_id==-1) return loops[0];
loop = loops[inf_loops[ib->loop_id].loop_id];
return loop;
}
static UNUSED
void copyInst(de_inst_t **dsrc, de_inst_t *ddes) {
*dsrc = ddes;
}
/*Check if regName is redefined in insn*/
static int regRedefined(int regName, de_inst_t *insn) {
/*regName is redefined if (insn r1=regName, insn is assigment*/
//if (strcmp(regName, insn->r1) != 0) return 0;
if (insn->out == NULL || regName != insn->out[0])
return 0;
int fu = md_op2flags[insn->op_enum];
if (fu & (F_ICOMP | F_FCOMP | F_MEM | F_LOAD | F_STORE))
return 1;
return 0;
}
static int checkBivStride(reg_t *regList, de_inst_t* insn) {
int k;
int regPos1,regPos2,regPos3;
regPos1 = insn->out?insn->out[0]:-1;
regPos2 = insn->in?insn->in[0]:-1;
k = INFINITY;
//if (regPos2==28 || regPos2==29) return INFINITY;/*ignore special reg*/
if (regPos1 == -1 || regPos2 == -1 || regPos1 != regPos2)
return INFINITY;
if (insn->op_enum == ADD) {
/* r1 = r1 + r3 */
if (insn->has_imm)
k = insn->imm;
else {
regPos3 = insn->in[1];
if (regList[regPos3].t != VALUE_CONST)
k = INFINITY;
else
k = regList[regPos3].val;
}
}
return k;
}
biv_p createBIV(reg_t *regList, de_inst_t *insn) {
biv_p biVar;
biVar = calloc(1,sizeof(biv_s));
//sprintf(biVar->regName,"%s",insn->r1);
//strcpy(biVar->opr,insn->op);
biVar->opr = insn->op_enum;
biVar->insn = insn;
biVar->stride = checkBivStride(regList, insn);
initReg( &(biVar->initVal));
biVar->flag = 0;
//strcpy(biVar->regName,insn->r1);
biVar->regName = insn->out[0];
return biVar;
}
static
int saved2Mem(inf_node_t *node, biv_p biv) {
int dbg = 0;
int k;
de_inst_t *insn;
unsigned bivAddr;
//check if biv saved to mem before it is redefined
//return 1 if (i) biv is saved, or (ii) biv is redefined. return 0->unknown
//because saved biv detection is unaffected by loop scope,
//it will appear in outermost loop where it belongs (not the loop using it)
bivAddr = ((de_inst_t*)(biv->insn))->addr;
if (dbg) {
}
for (k=0; k<node->num_insn; k++) {
insn = node->insnlist[k];
if (isStoreInst(insn->op_enum) && biv->regName == insn->out[0]
&& insn->addr > bivAddr) {
biv->flag |= BIV_SAVED;
if (dbg) {
fprintf(dbgExec,"\nSaved: insn 0x%x |0x%x(r%d,0,%d)",
insn->addr, biv->insn->addr,
biv->regName,biv->stride);
}
return 1;
}
//(1):biv is redefined by this insn
else if (bivAddr != insn->addr
&& (biv->flag & BIV_SAVED)==0
&& insn->addr > bivAddr
&& regRedefined(biv->regName, insn)) {
if (dbg) {
fprintf(dbgExec,"\nRedefined: insn 0x%x |0x%x(r%d,0,%d)",
insn->addr,bivAddr,biv->regName,biv->stride);
fflush(dbgExec);
}
return 1;
#if 0
if (prvNode) prvNode->next = bivNode->next;
else biv_list = bivNode->next;
freeBIV(&biv); free(bivNode);
if (prvNode) bivNode = prvNode->next;
else bivNode = biv_list;
#endif
}
}
return 0;
}
/*** Loop induction variable detection ***/
static void detectBIV() {
int dbg = 0; /*dbg flag*/
int i,j,k,h;
unsigned bivAddr;
biv_p biv;
int str;
worklist_p biv_list, bivNode, prvNode;
de_inst_t *insn;
inf_node_t *cur;
loop_t *curLp;
proc_t *p;
int lpHeadId, lpTailId, lpId;
reg_t *regList;
for (i=num_tcfg_loops-1; i>0; i--) {
curLp = loops[i];
if (curLp==NULL) continue;
biv_list = NULL;
p = curLp->head->bb->proc;
if (curLp->head) lpHeadId = curLp->head->bb->id;
else lpHeadId = 0;
if (curLp->tail) lpTailId = curLp->tail->bb->id;
else lpTailId = p->num_bb-1;
if (dbg) {
fprintf(dbgExec,"\nLoop %d head (%d:%d) tail (%d:%d)",
curLp->id, p->id, lpHeadId, p->id, lpTailId);
fflush(dbgExec);
}
//detect possible biv within the loop
for (j=curLp->first_bb_id; j<=curLp->last_bb_id; j++) {
/*scan through inst, detect basic induction var*/
cur = &(inf_procs[p->id].inf_cfg[j]);
regList = (reg_t*)(cur->regListIn);
for (k=0; k<cur->num_insn; k++) {
insn = cur->insnlist[k];
if (insn->flag==BIV_INST) continue;//induction inst of outer lp
str = checkBivStride(regList,insn);
if (str != INFINITY) {
if (dbg) {
fprintf(dbgExec,"\nBIV: insn: 0x%x (r%d,_,%d)",
insn->addr,insn->out[0],str);fflush(dbgExec);
}
//insn->flag = BIV_INST;
biv = createBIV(regList,insn);
//check whether a biv is saved before it is redefined
for (h=j; h<= lpTailId; h++) {
if (saved2Mem(inf_procs[p->id].inf_cfg+h,biv)) break;
}
if (0) {
fprintf(dbgExec,"\nSaved BIV: insn: 0x%x - ",insn->addr);
printBIV(dbgExec,biv);
fflush(dbgExec);
}
//biv->lp = curLp;
addToWorkList(&biv_list, biv);
}
}//end insn[k]
}//end bb[j]
for (j=curLp->first_bb_id; j<=curLp->last_bb_id; j++) {
cur = &(inf_procs[p->id].inf_cfg[j]);
regList = (reg_t*)(cur->regListIn);
for (k=0; k<cur->num_insn; k++) {
insn = cur->insnlist[k];
bivNode = biv_list; prvNode = NULL;
while (bivNode) {
biv = bivNode->data;
bivAddr = biv->insn->addr;
if (biv==NULL) {bivNode=bivNode->next; continue;}
//check whether a possible biv is not a real biv because it is redefined (before it is saved to memory)
if (bivAddr != insn->addr
&& (biv->flag & BIV_SAVED)==0
&& regRedefined(biv->regName, insn)) {
if (dbg) {
fprintf(dbgExec,"\nRedefined: insn 0x%x |0x%x(r%d,0,%d)",
insn->addr,bivAddr,biv->regName,biv->stride);
fflush(dbgExec);
}
if (prvNode) prvNode->next = bivNode->next;
else biv_list = bivNode->next;
freeBIV(&biv); free(bivNode);
if (prvNode) bivNode = prvNode->next;
else bivNode = biv_list;
}
else {//not redefined by this insn
prvNode = bivNode;
bivNode = bivNode->next;
}
}//end bivNode
}//end insn[k]
}//end bb[j]
#if 0
//check whether a possible biv is not a real biv because it is redefined
for (j=lpHeadId; j<=lpTailId; j++) {
cur = &(inf_procs[p->id].inf_cfg[j]);
regList = (reg_t*)(cur->regListIn);
for (k=0; k<cur->num_insn; k++) {
insn = &(cur->insnlist[k]);
bivNode = biv_list; prvNode = NULL;
while (bivNode) {
biv = bivNode->data;
bivAddr = ((insn_t*)(biv->insn))->addr;
if (biv==NULL) {bivNode=bivNode->next; continue;}
//(1):redefined by this insn
if (strcmp(bivAddr,insn->addr)!=0
&& (biv->flag & BIV_SAVED)==0
&& regRedefined(biv->regName, insn)) {
if (dbg) {
fprintf(dbgExec,"\nRedefined: insn %s |%s(%s,0,%d)",
insn->addr,bivAddr,biv->regName,biv->stride);
fflush(dbgExec);
}
if (prvNode) prvNode->next = bivNode->next;
else biv_list = bivNode->next;
freeBIV(&biv); free(bivNode);
if (prvNode) bivNode = prvNode->next;
else bivNode = biv_list;
}
else {//not redefined by this insn
prvNode = bivNode;
bivNode = bivNode->next;
}
}//end bivNode
}//end insn[k]
}//end bb[j]
#endif
//record real biv
curLp->biv_list = biv_list;
for (bivNode = biv_list; bivNode; bivNode=bivNode->next) {
biv = bivNode->data;
if (biv) biv->insn->flag |= BIV_INST;
}
if (dbg) {
fprintf(dbgExec,"\n BIV list of L%d ",curLp->id);
for (bivNode = biv_list; bivNode; bivNode = bivNode->next) {
biv = (biv_p) bivNode->data;
bivAddr = biv->insn->addr;
lpId = curLp->id;
//lpId = ((loop_t*)(biv->lp))->id;
fprintf(dbgExec,"\n\t 0x%x r%d L%d",bivAddr,biv->regName,lpId);
printBIV(dbgExec,biv);
}
}
}//end loop[i]
}
/*** Functions for conflicting pair detection ***/
#if 0 /*HBK: this should belong to conflict.c or infeasible.c, not support now*/
int addAssign( char deritree[], cfg_node_t *bb, int lineno, int rhs, char rhs_var ) {
int dbg = 0;
int i;
assign_t *assg;
inf_node_t *ib;
if (conflictDetectFlag==0) return;/*not do conflicting pair detection yet*/
ib = &(inf_procs[bb->proc->id].inf_cfg[bb->id]);
// check if there is previous assignment to the same memory address in the same block
for( i = 0; i < ib->num_assign; i++ ) {
assg = ib->assignlist[i];
if( streq( assg->deritree, deritree )) {
// overwrite this assignment
assg->lineno = lineno;
assg->rhs = rhs;
assg->rhs_var = rhs_var;
if( dbg & 0 ) { printf( "OVR " ); printAssign( assg, 0 ); }
return 1;
}
}
// else add new
assg = (assign_t*) malloc( sizeof(assign_t) );
strcpy( assg->deritree, deritree );
assg->rhs = rhs;
assg->rhs_var = rhs_var;
assg->bb = bb;
assg->lineno = lineno;
ib->num_assign++;
i = ib->num_assign;
ib->assignlist = (assign_t**) realloc( ib->assignlist, i * sizeof(assign_t*) );
ib->assignlist[i-1] = assg;
if( dbg & 0 ) { printf( "NEW " ); printAssign( assg, 0 ); }
return 0;
}
int addBranch( char deritree[], cfg_node_t *bb, int rhs, char rhs_var, char jump_cond ) {
int dbg = 0;
int i;
branch_t *br;
int numbb = prog.procs[bb->proc->id].num_bb;
if (conflictDetectFlag==0) return;/*not do conflicting pair detection yet*/
br = (branch_t*) malloc( sizeof(branch_t) );
strcpy( br->deritree, deritree );
br->rhs = rhs;
br->rhs_var = rhs_var;
br->jump_cond = jump_cond;
br->bb = bb;
br->num_BA_conflicts = 0;
br->BA_conflict_list = NULL;
br->num_BB_conflicts = 0;
br->BB_conflict_list = NULL;
inf_procs[bb->proc->id].inf_cfg[bb->id].branch = br;
if( dbg & 0 ) { printBranch( br, 0 ); }
return 0;
}
#endif
/*** MEMORY MODELING FRAMEWORK ***/
mem_p createMem(addr_t instAddr, reg_t writeAddr, reg_t regValue) {
mem_p memBlk;
memBlk = calloc(1,sizeof(mem_s));
memBlk->instAddr = instAddr;
initReg( &(memBlk->writeAddr) );
initReg( &(memBlk->regValue) );
cpyReg( &(memBlk->writeAddr),writeAddr);
cpyReg( &(memBlk->regValue),regValue);
return memBlk;
}
static
void freeMemBlk(mem_p *memBlk) {
clrReg( &( (*memBlk)->writeAddr) );
clrReg( &( (*memBlk)->regValue) );
*memBlk=NULL;
}
static
void freeMemList(worklist_p *memList) {
mem_p memBlk;
worklist_p curNode, nextNode;
curNode = *memList;
while (curNode) {
nextNode = curNode->next;
memBlk = curNode->data;
freeMemBlk( &memBlk );
curNode->data = NULL;
curNode->next = NULL;
free(curNode);
curNode = nextNode;
}
*memList = NULL;
}
int copyMem(mem_p dst, mem_p src) {
int changed = 0;
if (dst->instAddr != src->instAddr) {
changed = 1;
dst->instAddr = src->instAddr;
}
changed |= cpyReg( &(dst->writeAddr), src->writeAddr );
changed |= cpyReg( &(dst->regValue), src->regValue );
return changed;
}
void printMemList(FILE *fp,worklist_p memList) {
worklist_p memNode;
mem_p memBlk;
fprintf(fp,"[ ");
for (memNode = memList; memNode; memNode=memNode->next) {
memBlk = memNode->data;
if (memBlk->regValue.t==VALUE_UNPRED)continue;//dont print unpredictable
fprintf(fp," (%lx ",memBlk->instAddr);
printReg(fp,memBlk->writeAddr);
fprintf(fp," ");
printReg(fp,memBlk->regValue); fprintf(fp,")");
}
fprintf(fp," ]");
fflush(fp);
}
/* dst = src, old dst data will be removed */
int copyMemList(worklist_p *dstList, worklist_p srcList) {
int dbg = 0;
worklist_p srcNode, dstNode, prvNode;
mem_p dstBlk;
int changed,flag;
srcNode = srcList; dstNode= *dstList; prvNode = NULL;
changed = 0;
if (dbg) {
fprintf(dbgExec,"\n CopyMem: SRC ");
printMemList(dbgExec,srcList);
}
while (srcNode) {
if (dstNode) {
flag = copyMem(dstNode->data, srcNode->data);
if (flag) changed = 1;
prvNode = dstNode;
dstNode = dstNode->next;
}
else {
dstBlk = calloc(1,sizeof(mem_s));
copyMem(dstBlk, srcNode->data);
addAfterNode(dstBlk, &prvNode, dstList);
changed = 1;
}
srcNode = srcNode->next;
}
if (prvNode) {//remove remaining nodes of dst after prvNode
prvNode->next = NULL;
freeMemList( &dstNode);
changed = 1;
}
else if (*dstList!=NULL) {//prvNode==NULL -> dstList=NULL
freeMemList(dstList);
changed = 1;
}//dstList==NULL -> do nothing
if (dbg) {
fprintf(dbgExec," ->DST ");
printMemList(dbgExec,*dstList);
}
return changed;
}
/*save deriValue to writeAddr to memList, for st instruction at addr instAddr*/
int storeMem (worklist_p *memList, addr_t instAddr,
reg_t writeAddr, reg_t regValue) {
int dbg=0;
mem_p memBlk;
worklist_p memNode, prvNode;
int updated, predictable;
FILE *dbgExec = stdout;
//ERR: not handle unpredictable, assume it won't interfere with pred.mem
if (writeAddr.t==VALUE_UNPRED || writeAddr.t==VALUE_UNDEF) return 0;
if (regValue.t==VALUE_UNDEF || regValue.t==VALUE_UNPRED) predictable = 0;
else predictable = 1;//type=CONST / EXPR / INDUCT
if (dbg && predictable) {
fprintf(dbgExec,"\nStore: 0x%x ",instAddr);printReg(dbgExec, writeAddr);
fprintf(dbgExec," ");printReg(dbgExec, regValue);
}
if (dbg && predictable) {
fprintf(dbgExec,"\nBefore ");printMemList(dbgExec, *memList);
}
updated = 0;
prvNode = NULL;
for (memNode = *memList; memNode; memNode=memNode->next) {
memBlk = memNode->data;
prvNode = memNode;
if (regEq(memBlk->writeAddr, writeAddr)==1) break;
}
if (memNode) {//found memBlk->writeAddr == writeAddr
if (!regEq(memBlk->regValue, regValue)) {
if (memBlk->instAddr==instAddr) {
//same inst, same writeAddr, diff. regValue -> merge value
//mergeReg( &(memBlk->regValue), regValue, 0);
cpyReg( &(memBlk->regValue), regValue);
//regUnknown( &(memBlk->regValue) );
}
else {//set new regValue to memBlk->writeAddr
memBlk->instAddr = instAddr;
if (predictable) cpyReg( &(memBlk->regValue), regValue);
else regUnknown( &(memBlk->regValue) );
}
}//else memBlk->regValue == regValue: do nothing
}
else {//cannot find writeAddr in memList
if (predictable) {
if (dbg) {
fprintf(dbgExec,"\nAdd new mem entry");
fprintf(dbgExec,"\nStore: 0x%x ",instAddr);
printReg(dbgExec, writeAddr);
}
memBlk=createMem(instAddr,writeAddr,regValue);
addAfterNode(memBlk,&prvNode,memList);
}
}
if (dbg && predictable) {
fprintf(dbgExec,"\nAfter: ");printMemList(dbgExec, *memList);}
return updated;
}
/*load deriValue from writeAddr in memList, for ld instruction*/
void loadMem (worklist_p memList, reg_t writeAddr, reg_t *regValue) {
int dbg=0;
FILE *dbgExec = stdout;
mem_p memBlk;
worklist_p memNode;
if (dbg) printMemList(dbgExec, memList);
regUnknown(regValue);
for (memNode=memList; memNode; memNode=memNode->next) {
memBlk = memNode->data;
if (regEq(writeAddr,memBlk->writeAddr)) {
cpyReg(regValue, memBlk->regValue);
break;
}
}
if (dbg && regValue->t!=VALUE_UNPRED) {
fprintf(dbgExec,"\nLoad from i:%lx",memBlk->instAddr);
fprintf(dbgExec," a:");printReg(dbgExec,memBlk->writeAddr);
fprintf(dbgExec," v:");printReg(dbgExec,*regValue);
}
if (regValue->t != VALUE_CONST && writeAddr.t == VALUE_CONST) {
long value;
int find = global_memory_query(writeAddr.val, &value);
if (find)
setInt(regValue, value);
}
}
int memListEq(worklist_p dstList, worklist_p srcList) {
worklist_p srcNode, dstNode;
mem_p srcBlk, dstBlk;
//not really correct, need to ensure certain order for the list
//hopefully it can work, for now
srcNode = srcList; dstNode = dstList;
while (srcNode && dstNode) {
srcBlk = srcNode->data; dstBlk=dstNode->data;
if (!regEq(srcBlk->writeAddr,dstBlk->writeAddr)
|| !regEq(srcBlk->regValue,dstBlk->regValue))
return 0;
srcNode = srcNode->next;
dstNode = dstNode->next;
}
if (srcNode || dstNode) return 0;
return 1;
}
int mergeMemList(worklist_p *dstList, worklist_p srcList) {
int dbg = 0;
worklist_p srcNode, dstNode, dstTail, newList;
mem_p memBlk, srcBlk, dstBlk;
int dstChanged;
int flag;
if (dbg) {
fprintf(dbgExec,"\nMerge mem.list:");
fprintf(dbgExec,"\nSrc: "); printMemList(dbgExec,srcList);
fprintf(dbgExec,"\nDst: "); printMemList(dbgExec,*dstList);
}
dstChanged = 0;
if (dbg && 0) fprintf(dbgExec,"\nMerging: ");
dstTail = *dstList;
while (dstTail && dstTail->next) dstTail = dstTail->next;
newList = NULL;
//a very simple but slow implementation of mem.search
srcNode = srcList;
while (srcNode) {
srcBlk = srcNode->data;
dstNode = *dstList;
while (dstNode!=NULL) {
dstBlk = dstNode->data;
if (regEq(srcBlk->writeAddr,dstBlk->writeAddr)) {
flag = mergeReg( &(dstBlk->regValue), srcBlk->regValue, 0);
if (flag) dstChanged = 1;
break;
}
dstNode = dstNode->next;
}
if (dstNode==NULL) {
memBlk = createMem(srcBlk->instAddr,
srcBlk->writeAddr,srcBlk->regValue);
addToWorkList(&newList,memBlk);
}
srcNode = srcNode->next;
}
if (dstTail) dstTail->next = newList;
else *dstList = newList;
if (dbg) {fprintf(dbgExec,"\nMERGED c:%d ",dstChanged);
printMemList(dbgExec,*dstList);}
return dstChanged;
}
// Note: for commutative operations on mixed-type operands
// (one is a variable and the other is a constant value),
// the derivation string is stored in the format "<var>+<const>"
#define PROCESS_STORE \
if (traceMemFlag) {\
/*HBK: sw -> save to mem model*/ \
if (insn->has_imm) {\
setInt(&tmpReg,insn->imm);\
regOpr(OPR_ADD, &writeAddr,regList[r2],tmpReg);\
}\
else if (insn->num_in > 1)\
regOpr(OPR_ADD, &writeAddr,regList[r2],regList[r3]);\
else\
cpyReg(&writeAddr, regList[r2]);\
storeMem(memList,instAddr,writeAddr,regList[r1]);\
if (dbg) {\
fprintf(dbgF,"\nStore (%x ",instAddr); \
fprintf(dbgF," ");printReg(dbgF,writeAddr);\
fprintf(dbgF," -> ");printReg(dbgF,regList[r1]);\
}\
}
#define PROCESS_LOAD \
regUnknown(regList+r1);\
if (traceMemFlag) {\
/*HBK: ld -> load from mem model*/ \
if (insn->has_imm) {\
setInt(&tmpReg,insn->imm);\
regOpr(OPR_ADD, &writeAddr,regList[r2],tmpReg);\
}\
else if (insn->num_in > 1)\
regOpr(OPR_ADD, &writeAddr,regList[r2],regList[r3]);\
else\
cpyReg(&writeAddr, regList[r2]);\
loadMem(*memList,writeAddr,regList+r1);\
if (dbg) {\
fprintf(dbgF,"\nLoad (%x ",instAddr); \
fprintf(dbgF," ");printReg(dbgF,writeAddr);\
fprintf(dbgF," -> ");printReg(dbgF,regList[r1]);\
}\
}
#define PROCESS_SLTI \
/* set r1 to 1 if r2 < atoi(r3) */ \
if (regList[r2].t == VALUE_CONST) {\
if (regList[r2].val<atoi(insn->r3)) \
setInt(regList+r1,1);\
else setInt(regList+r1,0);\
}\
else regUnknown(regList+r1);
#define PROCESS_SLT \
/* set r1 to 1 if r2 < r3 */ \
if (regList[r2].t == VALUE_CONST && regList[r2].t==regList[r3].t) {\
if ( regList[r2].val < regList[r3].val ) \
setInt(regList[r1],1);\
else setInt(regList[r1],0);\
}\
else regUnknown(regList[r1]);
#define ADD_ASSIGN
/*add assignments for AB/BB conflict detection, ignore for now*/
static void update_cond_flags(int cond_flags, reg_t *reg_list) {
if (cond_flags == UNKNOWN_COND_FLAGS)
regUnknown(reg_list + ARM_COND_FLAGS_REG);
else
setInt(reg_list + ARM_COND_FLAGS_REG, cond_flags);
}
#define IS_N_SET(f) ((f & 0x8) == 0x8)
#define IS_N_CLEAR(f) ((f & 0x8) == 0x0)
#define IS_Z_SET(f) ((f & 0x4) == 0x4)
#define IS_Z_CLEAR(f) ((f & 0x4) == 0x0)
#define IS_C_SET(f) ((f & 0x2) == 0x2)
#define IS_C_CLEAR(f) ((f & 0x2) == 0x0)
#define IS_V_SET(f) ((f & 0x1) == 0x1)
#define IS_V_CLEAR(f) ((f & 0x1) == 0x0)
static int merge_cond_flags(int flag1, int flag2) {
if (flag1 == UNKNOWN_COND_FLAGS || flag2 == UNKNOWN_COND_FLAGS)
return UNKNOWN_COND_FLAGS;
return (flag2 & 0xc) | (flag1 & flag2 & 0x3);
}
static int regDerive(inf_node_t *ib, de_inst_t *insn,
int ignore, char *jal, int dbg) {
FILE *dbgF = stdout;
int r1, r2, r3, last_in_reg;
addr_t instAddr;
de_inst_t *insnTmp;
biv_p biv, bivInit;
int i;
worklist_p *memList;
reg_t *regList;
reg_t writeAddr, writeValue, tmpReg, tmpReg1; //for load/store
if (insn->in == NULL && insn->out == NULL)
return 0;
// test the condition
int cond = insn->condition;
//reg_t *inRegs = (reg_t*)(ib->regListIn);
regList = (reg_t*)(ib->regListOut);
for (i = 0; i < NO_REG; ++i)
cpyReg(((reg_t*)(ib->regListLastSecondOut)) + i, regList[i]);
setInt(regList + ARM_PC_REG, insn->addr + 8);
r1 = insn->out?insn->out[0]:-1;
r2 = insn->in?insn->in[0]:-1;
r3 = (insn->in && insn->num_in>1)?insn->in[1]:-1;
last_in_reg = insn->in?insn->in[insn->num_in-1]:-1;
// if there's condition
if (cond >= COND_EQ && cond <= COND_AL) {
if (regList[ARM_COND_FLAGS_REG].t != VALUE_CONST) {
if (r1 != ARM_MEM_REG)
regUnknown(regList + r1);
if (insn->s_bit)
regUnknown(regList + ARM_COND_FLAGS_REG);
return 1;
}
// Then, regList[ARM_COND_FLAGS_REG).t == VALUE_CONST
int flag = regList[ARM_COND_FLAGS_REG].val;
switch (cond) {
case COND_EQ:
if (!IS_Z_SET(flag))
return 1;
break;
case COND_NE:
if (!IS_Z_CLEAR(flag))
return 1;
break;
case COND_CS:
case COND_HS:
if (!IS_C_SET(flag))
return 1;
break;
case COND_CC:
case COND_LO:
if (!IS_C_CLEAR(flag))
return 1;
break;
case COND_MI:
if (!IS_N_SET(flag))
return 1;
break;
case COND_PL:
if (!IS_N_CLEAR(flag))
return 1;
break;
case COND_VS:
if (!IS_V_SET(flag))
return 1;
break;
case COND_VC:
if (!IS_V_CLEAR(flag))
return 1;
break;
case COND_HI:
if (!(IS_C_SET(flag) && IS_Z_CLEAR(flag)))
return 1;
break;
case COND_LS:
if (!(IS_C_CLEAR(flag) || IS_Z_SET(flag)))
return 1;
break;
case COND_GE:
if (IS_N_SET(flag) ^ IS_V_SET(flag))
return 1;
break;
case COND_LT:
if (!(IS_N_SET(flag) ^ IS_V_SET(flag)))
return 1;
break;
case COND_GT:
if (!(IS_Z_CLEAR(flag) && ((IS_N_SET(flag) ^ IS_V_SET(flag)) == 0)))
return 1;
break;
case COND_LE:
if (!(IS_Z_SET(flag) || ((IS_N_SET(flag) ^ IS_V_SET(flag)) == 1)))
return 1;
break;
case COND_AL:
break;
}
}
initReg(&writeAddr);
initReg(&writeValue);
initReg(&tmpReg);
initReg(&tmpReg1);
ignore = 1; //no AB - BB detection supported, for now
memList = &(ib->memListOut);
//op = insn->op;
//sscanf(insn->addr,"%x",&instAddr);
instAddr = insn->addr;
//if (dbg) printRegList(dbgF, (reg_t*)(ib->regListOut) );
/*if( dbg ) {
fprintf(dbgF,"\n%s ",insn->r1);
if (r1>=0) printReg(dbgF,regList[r1]);
fprintf(dbgF," %s ",insn->r2);
if (r2>=0) printReg(dbgF,regList[r2]);
fprintf(dbgF," %s ",insn->r3);
if (r3>=0) printReg(dbgF,regList[r3]);
fprintf(dbgF," | ");
} */
#if 0
if (deriveUnknown(regList,insn)) {
if (dbg) { printf( "\n--> unpred. " ); printReg(stdout,regList[r1]);}
return 1;
}
#endif
if (insn->flag==BIV_INST) {
/*Derivation of inductive instruction*/
if (dbg) {printf("\nInduction: ");printReg(stdout,regList[r1]);}
if (regList[r1].t!=VALUE_BIV) {
biv = createBIV(regList, insn);
if (regList[r1].t!=VALUE_UNDEF) {
updateInitVal(biv,regList[r1]);
}
regList[r1].t = VALUE_BIV;
regList[r1].biv = biv;
}
else {
bivInit = regList[r1].biv;
insnTmp = bivInit->insn;
if (insnTmp->addr != insn->addr) {
//different biv of different instruction
biv = createBIV(regList, insn);
updateInitVal(biv,regList[r1]);
regList[r1].t = VALUE_BIV;
regList[r1].biv = biv;
}
//else do nothing, induction value remains the same for loop
}
if (dbg) { printf( "\n--> biv: " ); printReg(stdout,regList[r1]);}
return 1;
}
if (insn->op_enum == NA)
return 1;
// don't process these instructions
if (insn->op_enum == SWI || insn->op_enum == SWI)
return 1;
unsigned cond_flags, flag1, flag2;
if (insn->last_shift != NO_SHIFT) {
cpyReg(&tmpReg, regList[last_in_reg]);
if (insn->last_shift == SHIFT_BY_IMM)
setInt(&tmpReg1, insn->shift_val);
else if (insn->last_shift == SHIFT_BY_REG)
cpyReg(&tmpReg1, regList[insn->shift_val]);
if (insn->shift_mode == SHIFT_MODE_LSL)
regOpr(OPR_LSF, regList + last_in_reg, tmpReg, tmpReg1);
else if (insn->shift_mode == SHIFT_MODE_LSR)
regOpr(OPR_RSF, regList + last_in_reg, tmpReg, tmpReg1);
}
{
switch (insn->op_enum) {
case LDR_L:
case LDR_H:
case LDR_BL:
if (traceMemFlag) {
if (insn->offset_addr_mode == POST_INDEXED)
cpyReg(&writeAddr, regList[r2]);
else {
if (insn->has_imm) {
setInt(&tmpReg,insn->imm);
regOpr(OPR_ADD, &writeAddr,regList[r2],tmpReg);
}
else
cpyReg(&writeAddr, regList[r2]);
}
loadMem(*memList, writeAddr, regList + r1);
if (insn->offset_addr_mode == POST_INDEXED) {
assert(insn->has_imm);
setInt(&tmpReg,insn->imm);