diff --git a/.github/workflows/rogue_ci.yml b/.github/workflows/rogue_ci.yml index 8815eb110..9049d5583 100644 --- a/.github/workflows/rogue_ci.yml +++ b/.github/workflows/rogue_ci.yml @@ -21,7 +21,7 @@ on: [push] jobs: full_build_test: name: Full Build Test - runs-on: ubuntu-latest + runs-on: ubuntu-20.04 steps: # This step checks out a copy of your repository. @@ -90,31 +90,9 @@ jobs: python -m compileall -f ./python/ #flake8 --count ./python/ - # Code Coverage - - name: Code Coverage - run: | - source setup_rogue.sh - codecov - coverage report -m - - # Generate Documentation - - name: Generate Documentation - if: github.ref == 'refs/heads/documentation' - run: | - source setup_rogue.sh - cd docs - make html - - - name: Deploy Documentation - if: github.ref == 'refs/heads/documentation' - uses: peaceiris/actions-gh-pages@v3 - with: - github_token: ${{ secrets.GH_TOKEN }} - publish_dir: docs/build/html - small_build_test: name: Small Build Test - runs-on: ubuntu-latest + runs-on: ubuntu-20.04 steps: # This step checks out a copy of your repository. @@ -136,7 +114,7 @@ jobs: gen_release: name: Generate Release - runs-on: ubuntu-latest + runs-on: ubuntu-20.04 needs: [full_build_test, small_build_test] if: startsWith(github.ref, 'refs/tags/') steps: @@ -168,132 +146,3 @@ jobs: run: | python ruckus/scripts/releaseGen.py - conda_build: - name: Anaconda Build - needs: [full_build_test, small_build_test] - if: startsWith(github.ref, 'refs/tags/') || github.ref == 'refs/heads/pre-release' - strategy: - matrix: - os: - - ubuntu-latest - - macos-10.15 - runs-on: ${{ matrix.os }} - steps: - - # This step checks out a copy of your repository. - - uses: actions/checkout@v2 - with: - fetch-depth: 0 - - - uses: actions/setup-python@v2 - with: - python-version: 3.8 - - - name: Setup anaconda - env: - OS_NAME: ${{ matrix.os }} - run: | - cd ${HOME} - if [ $OS_NAME == "macos-10.15" ] - then - wget -O miniconda.sh https://repo.continuum.io/miniconda/Miniconda3-latest-MacOSX-x86_64.sh - else - wget -O miniconda.sh https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh - fi - bash miniconda.sh -b -p ${HOME}/miniconda - export PATH="${HOME}/miniconda/bin:$PATH" - source ${HOME}/miniconda/etc/profile.d/conda.sh - conda config --set always_yes yes - conda install conda-build anaconda-client conda-verify - if [ $OS_NAME == "macos-10.15" ] - then - conda install libiconv libarchive -c conda-forge - fi - conda update -q conda conda-build - conda update --all - - - name: Setup MacOS - if: matrix.os == 'macos-10.15' - run: | - cd ${HOME} - wget https://github.com/phracker/MacOSX-SDKs/releases/download/10.15/MacOSX10.15.sdk.tar.xz - tar xzf MacOSX10.15.sdk.tar.xz - sudo mkdir -p /opt/ - sudo mv MacOSX10.15.sdk /opt/ - CONDA_BUILD_SYSROOT=/opt/MacOSX10.15.sdk - CONDA_BUILD=1 - echo "CONDA_BUILD_SYSROOT=$CONDA_BUILD_SYSROOT" >> $GITHUB_ENV - echo "CONDA_BUILD=$CONDA_BUILD" >> $GITHUB_ENV - - - name: Get Image Information - id: get_image_info - env: - CONDA_UPLOAD_TOKEN_DEV: ${{ secrets.CONDA_UPLOAD_TOKEN_DEV }} - CONDA_UPLOAD_TOKEN_TAG: ${{ secrets.CONDA_UPLOAD_TOKEN_TAG }} - OS_NAME: ${{ matrix.os }} - run: | - if [ ${GITHUB_REF} == "refs/heads/pre-release" ] - then - echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_DEV - else - echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_TAG - fi - if [ ${OS_NAME} == "macos-10.15" ] - then - echo ::set-output name=os::osx-64 - else - echo ::set-output name=os::linux-64 - fi - - - name: Build And Upload - run: | - export PATH="${HOME}/miniconda/bin:$PATH" - source ${HOME}/miniconda/etc/profile.d/conda.sh - conda build conda-recipe --debug --output-folder bld-dir -c tidair-packages -c conda-forge - anaconda -t ${{ steps.get_image_info.outputs.token }} upload --force bld-dir/${{ steps.get_image_info.outputs.os }}/*.tar.bz2 - - docker_build: - name: Docker Build - runs-on: ubuntu-latest - needs: [full_build_test, small_build_test] - if: startsWith(github.ref, 'refs/tags/') || github.ref == 'refs/heads/pre-release' - steps: - - # This step checks out a copy of your repository. - - uses: actions/checkout@v2 - with: - fetch-depth: 0 - - - name: Get Image Information - id: get_image_info - run: | - echo ::set-output name=tag::`git describe --tags` - echo ::set-output name=branch::`echo ${GITHUB_REF} | awk 'BEGIN { FS = "/" } ; { print $3 }'` - if [ ${GITHUB_REF} == "refs/heads/pre-release" ] - then - echo ::set-output name=name::"rogue-dev" - else - echo ::set-output name=name::"rogue" - fi - - # Setup docker build environment - - name: Set up Docker Buildx - uses: docker/setup-buildx-action@v1 - - # Login to Dockerhub - - name: Login to Dockerhub - uses: docker/login-action@v1 - with: - username: tidair - password: ${{ secrets.DOCKERHUB_TOKEN }} - - # Build and push the docker image - - name: Build and push image to Dockerhub - uses: docker/build-push-action@v2 - with: - context: . - file: ./Dockerfile - push: true - tags: tidair/${{ steps.get_image_info.outputs.name }}:${{ steps.get_image_info.outputs.tag }} - build-args: branch=${{ steps.get_image_info.outputs.branch }} - diff --git a/include/rogue/hardware/drivers/AxisDriver.h b/include/rogue/hardware/drivers/AxisDriver.h index e0fedd272..cefe829b0 100755 --- a/include/rogue/hardware/drivers/AxisDriver.h +++ b/include/rogue/hardware/drivers/AxisDriver.h @@ -5,15 +5,15 @@ * Description: * Definitions and inline functions for interacting with AXIS driver. * ---------------------------------------------------------------------------- - * This file is part of the aes_stream_drivers package. It is subject to - * the license terms in the LICENSE.txt file found in the top-level directory - * of this distribution and at: - * https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. - * No part of the aes_stream_drivers package, including this file, may be - * copied, modified, propagated, or distributed except according to the terms + * This file is part of the aes_stream_drivers package. It is subject to + * the license terms in the LICENSE.txt file found in the top-level directory + * of this distribution and at: + * https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. + * No part of the aes_stream_drivers package, including this file, may be + * copied, modified, propagated, or distributed except according to the terms * contained in the LICENSE.txt file. * ---------------------------------------------------------------------------- -**/ + **/ #ifndef __ASIS_DRIVER_H__ #define __ASIS_DRIVER_H__ #include "DmaDriver.h" @@ -25,36 +25,35 @@ #ifndef DMA_IN_KERNEL // Set flags -//static constexpr inline uint32_t axisSetFlags(uint32_t fuser, uint32_t luser, uint32_t cont) { +// static constexpr inline uint32_t axisSetFlags(uint32_t fuser, uint32_t luser, uint32_t cont) { // return ( ((cont & 0x1) << 16) | ((luser & 0xFF) << 8) | ((fuser & 0xFF) << 0) ); //} static inline uint32_t axisSetFlags(uint32_t fuser, uint32_t luser, uint32_t cont) { - uint32_t flags; + uint32_t flags; - flags = fuser & 0xFF; - flags += (luser << 8) & 0xFF00; - flags += (cont << 16) & 0x10000; - return(flags); + flags = fuser & 0xFF; + flags += (luser << 8) & 0xFF00; + flags += (cont << 16) & 0x10000; + return (flags); } static inline uint32_t axisGetFuser(uint32_t flags) { - return(flags & 0xFF); + return (flags & 0xFF); } static inline uint32_t axisGetLuser(uint32_t flags) { - return((flags >> 8) & 0xFF); + return ((flags >> 8) & 0xFF); } static inline uint32_t axisGetCont(uint32_t flags) { - return((flags >> 16) & 0x1); + return ((flags >> 16) & 0x1); } // Read ACK -static inline void axisReadAck (int32_t fd) { - ioctl(fd,AXIS_Read_Ack,0); +static inline void axisReadAck(int32_t fd) { + ioctl(fd, AXIS_Read_Ack, 0); } #endif #endif - diff --git a/include/rogue/hardware/drivers/DmaDriver.h b/include/rogue/hardware/drivers/DmaDriver.h index 32bee9c42..b16bdeba6 100755 --- a/include/rogue/hardware/drivers/DmaDriver.h +++ b/include/rogue/hardware/drivers/DmaDriver.h @@ -6,17 +6,17 @@ * Created : 2016-08-08 * ---------------------------------------------------------------------------- * Description: - * Definitions and inline functions for interacting drivers. + * Defintions and inline functions for interacting drivers. * ---------------------------------------------------------------------------- - * This file is part of the aes_stream_drivers package. It is subject to - * the license terms in the LICENSE.txt file found in the top-level directory - * of this distribution and at: - * https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. - * No part of the aes_stream_drivers package, including this file, may be - * copied, modified, propagated, or distributed except according to the terms + * This file is part of the aes_stream_drivers package. It is subject to + * the license terms in the LICENSE.txt file found in the top-level directory + * of this distribution and at: + * https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. + * No part of the aes_stream_drivers package, including this file, may be + * copied, modified, propagated, or distributed except according to the terms * contained in the LICENSE.txt file. * ---------------------------------------------------------------------------- -**/ + **/ #ifndef __DMA_DRIVER_H__ #define __DMA_DRIVER_H__ @@ -27,7 +27,7 @@ #endif // API Version -#define DMA_VERSION 0x05 +#define DMA_VERSION 0x06 // Error values #define DMA_ERR_FIFO 0x01 @@ -36,19 +36,24 @@ #define DMA_ERR_BUS 0x08 // Commands -#define DMA_Get_Buff_Count 0x1001 -#define DMA_Get_Buff_Size 0x1002 -#define DMA_Set_Debug 0x1003 -#define DMA_Set_Mask 0x1004 -#define DMA_Ret_Index 0x1005 -#define DMA_Get_Index 0x1006 -#define DMA_Read_Ready 0x1007 -#define DMA_Set_MaskBytes 0x1008 -#define DMA_Get_Version 0x1009 -#define DMA_Write_Register 0x100A -#define DMA_Read_Register 0x100B -#define DMA_Get_RxBuff_Count 0x100C -#define DMA_Get_TxBuff_Count 0x100D +#define DMA_Get_Buff_Count 0x1001 +#define DMA_Get_Buff_Size 0x1002 +#define DMA_Set_Debug 0x1003 +#define DMA_Set_Mask 0x1004 +#define DMA_Ret_Index 0x1005 +#define DMA_Get_Index 0x1006 +#define DMA_Read_Ready 0x1007 +#define DMA_Set_MaskBytes 0x1008 +#define DMA_Get_Version 0x1009 +#define DMA_Write_Register 0x100A +#define DMA_Read_Register 0x100B +#define DMA_Get_RxBuff_Count 0x100C +#define DMA_Get_TxBuff_Count 0x100D +#define DMA_Get_TxBuffinUser_Count 0x100F +#define DMA_Get_TxBuffinHW_Count 0x1010 +#define DMA_Get_TxBuffinPreHWQ_Count 0x1011 +#define DMA_Get_TxBuffinSWQ_Count 0x1012 +#define DMA_Get_TxBuffMiss_Count 0x1013 // Mask size #define DMA_MASK_SIZE 512 @@ -56,384 +61,404 @@ // TX Structure // Size = 0 for return index struct DmaWriteData { - uint64_t data; - uint32_t dest; - uint32_t flags; - uint32_t index; - uint32_t size; - uint32_t is32; - uint32_t pad; + uint64_t data; + uint32_t dest; + uint32_t flags; + uint32_t index; + uint32_t size; + uint32_t is32; + uint32_t pad; }; // RX Structure // Data = 0 for read index struct DmaReadData { - uint64_t data; - uint32_t dest; - uint32_t flags; - uint32_t index; - uint32_t error; - uint32_t size; - uint32_t is32; - int32_t ret; + uint64_t data; + uint32_t dest; + uint32_t flags; + uint32_t index; + uint32_t error; + uint32_t size; + uint32_t is32; + int32_t ret; }; // Register data struct DmaRegisterData { - uint32_t address; - uint32_t data; + uint64_t address; + uint32_t data; }; // Everything below is hidden during kernel module compile #ifndef DMA_IN_KERNEL +#include +#include #include #include -#include -#include -#include -#include +#include #include +#include #include -#include #include +#include // Write Frame -static inline ssize_t dmaWrite(int32_t fd, const void * buf, size_t size, uint32_t flags, uint32_t dest) { - struct DmaWriteData w; +static inline ssize_t dmaWrite(int32_t fd, const void* buf, size_t size, uint32_t flags, uint32_t dest) { + struct DmaWriteData w; - memset(&w,0,sizeof(struct DmaWriteData)); - w.dest = dest; - w.flags = flags; - w.size = size; - w.is32 = (sizeof(void *)==4); - w.data = (uint64_t)buf; + memset(&w, 0, sizeof(struct DmaWriteData)); + w.dest = dest; + w.flags = flags; + w.size = size; + w.is32 = (sizeof(void*) == 4); + w.data = (uint64_t)buf; - return(write(fd,&w,sizeof(struct DmaWriteData))); + return (write(fd, &w, sizeof(struct DmaWriteData))); } // Write Frame, memory mapped static inline ssize_t dmaWriteIndex(int32_t fd, uint32_t index, size_t size, uint32_t flags, uint32_t dest) { - struct DmaWriteData w; + struct DmaWriteData w; - memset(&w,0,sizeof(struct DmaWriteData)); - w.dest = dest; - w.flags = flags; - w.size = size; - w.is32 = (sizeof(void *)==4); - w.index = index; + memset(&w, 0, sizeof(struct DmaWriteData)); + w.dest = dest; + w.flags = flags; + w.size = size; + w.is32 = (sizeof(void*) == 4); + w.index = index; - return(write(fd,&w,sizeof(struct DmaWriteData))); + return (write(fd, &w, sizeof(struct DmaWriteData))); } // Write frame from iovector -static inline ssize_t dmaWriteVector(int32_t fd, struct iovec *iov, size_t iovlen, - uint32_t begFlags, uint32_t midFlags, uint32_t endFlags, uint32_t dest) { - uint32_t x; - ssize_t ret; - ssize_t res; - struct DmaWriteData w; - - ret = 0; - - for (x=0; x < iovlen; x++) { - memset(&w,0,sizeof(struct DmaWriteData)); - w.dest = dest; - w.flags = (x==0)?begFlags:((x==(iovlen-1))?endFlags:midFlags); - w.size = iov[x].iov_len; - w.is32 = (sizeof(void *)==4); - w.data = (uint64_t)iov[x].iov_base; - - do { - res = write(fd,&w,sizeof(struct DmaWriteData)); - - if ( res < 0 ) return(res); - else if ( res == 0 ) usleep(10); - else ret += res; - } while (res == 0); - } - return(ret); +static inline ssize_t dmaWriteVector(int32_t fd, + struct iovec* iov, + size_t iovlen, + uint32_t begFlags, + uint32_t midFlags, + uint32_t endFlags, + uint32_t dest) { + uint32_t x; + ssize_t ret; + ssize_t res; + struct DmaWriteData w; + + ret = 0; + + for (x = 0; x < iovlen; x++) { + memset(&w, 0, sizeof(struct DmaWriteData)); + w.dest = dest; + w.flags = (x == 0) ? begFlags : ((x == (iovlen - 1)) ? endFlags : midFlags); + w.size = iov[x].iov_len; + w.is32 = (sizeof(void*) == 4); + w.data = (uint64_t)iov[x].iov_base; + + do { + res = write(fd, &w, sizeof(struct DmaWriteData)); + + if (res < 0) + return (res); + else if (res == 0) + usleep(10); + else + ret += res; + } while (res == 0); + } + return (ret); } // Write Frame, memory mapped from iovector -static inline ssize_t dmaWriteIndexVector(int32_t fd, struct iovec *iov, size_t iovlen, - uint32_t begFlags, uint32_t midFlags, uint32_t endFlags, uint32_t dest) { - uint32_t x; - ssize_t ret; - ssize_t res; - struct DmaWriteData w; - - ret = 0; - - for (x=0; x < iovlen; x++) { - memset(&w,0,sizeof(struct DmaWriteData)); - w.dest = dest; - w.flags = (x==0)?begFlags:((x==(iovlen-1))?endFlags:midFlags); - w.size = iov[x].iov_len; - w.is32 = (sizeof(void *)==4); - w.index = (uint32_t)(((uint64_t)iov[x].iov_base) & 0xFFFFFFFF); - - do { - res = write(fd,&w,sizeof(struct DmaWriteData)); - - if ( res < 0 ) return(res); - else if ( res == 0 ) usleep(10); - else ret += res; - } while (res == 0); - } - return(ret); +static inline ssize_t dmaWriteIndexVector(int32_t fd, + struct iovec* iov, + size_t iovlen, + uint32_t begFlags, + uint32_t midFlags, + uint32_t endFlags, + uint32_t dest) { + uint32_t x; + ssize_t ret; + ssize_t res; + struct DmaWriteData w; + + ret = 0; + + for (x = 0; x < iovlen; x++) { + memset(&w, 0, sizeof(struct DmaWriteData)); + w.dest = dest; + w.flags = (x == 0) ? begFlags : ((x == (iovlen - 1)) ? endFlags : midFlags); + w.size = iov[x].iov_len; + w.is32 = (sizeof(void*) == 4); + w.index = (uint32_t)(((uint64_t)iov[x].iov_base) & 0xFFFFFFFF); + + do { + res = write(fd, &w, sizeof(struct DmaWriteData)); + + if (res < 0) + return (res); + else if (res == 0) + usleep(10); + else + ret += res; + } while (res == 0); + } + return (ret); } // Receive Frame -static inline ssize_t dmaRead(int32_t fd, void * buf, size_t maxSize, uint32_t * flags, uint32_t *error, uint32_t * dest) { - struct DmaReadData r; - ssize_t ret; +static inline ssize_t dmaRead(int32_t fd, void* buf, size_t maxSize, uint32_t* flags, uint32_t* error, uint32_t* dest) { + struct DmaReadData r; + ssize_t ret; - memset(&r,0,sizeof(struct DmaReadData)); - r.size = maxSize; - r.is32 = (sizeof(void *)==4); - r.data = (uint64_t)buf; + memset(&r, 0, sizeof(struct DmaReadData)); + r.size = maxSize; + r.is32 = (sizeof(void*) == 4); + r.data = (uint64_t)buf; - ret = read(fd,&r,sizeof(struct DmaReadData)); + ret = read(fd, &r, sizeof(struct DmaReadData)); - if ( ret <= 0 ) return(ret); + if (ret <= 0) return (ret); - if ( dest != NULL ) *dest = r.dest; - if ( flags != NULL ) *flags = r.flags; - if ( error != NULL ) *error = r.error; + if (dest != NULL) *dest = r.dest; + if (flags != NULL) *flags = r.flags; + if (error != NULL) *error = r.error; - return(r.ret); + return (r.ret); } // Receive Frame, access memory mapped buffer // Returns receive size -static inline ssize_t dmaReadIndex(int32_t fd, uint32_t * index, uint32_t * flags, uint32_t *error, uint32_t * dest) { - struct DmaReadData r; - size_t ret; +static inline ssize_t dmaReadIndex(int32_t fd, uint32_t* index, uint32_t* flags, uint32_t* error, uint32_t* dest) { + struct DmaReadData r; + size_t ret; - memset(&r,0,sizeof(struct DmaReadData)); + memset(&r, 0, sizeof(struct DmaReadData)); - ret = read(fd,&r,sizeof(struct DmaReadData)); + ret = read(fd, &r, sizeof(struct DmaReadData)); - if ( ret <= 0 ) return(ret); + if (ret <= 0) return (ret); - if ( dest != NULL ) *dest = r.dest; - if ( flags != NULL ) *flags = r.flags; - if ( error != NULL ) *error = r.error; + if (dest != NULL) *dest = r.dest; + if (flags != NULL) *flags = r.flags; + if (error != NULL) *error = r.error; - *index = r.index; - return(r.ret); + *index = r.index; + return (r.ret); } // Receive Frame, access memory mapped buffer // Returns receive size -static inline ssize_t dmaReadBulkIndex(int32_t fd, uint32_t count, int32_t *ret, uint32_t * index, uint32_t * flags, uint32_t *error, uint32_t * dest) { - struct DmaReadData r[count]; - size_t res; - size_t x; - - memset(r,0,count * sizeof(struct DmaReadData)); - - res = read(fd,r,count * sizeof(struct DmaReadData)); - - for (x = 0; x < res; ++x) { - if ( dest != NULL ) dest[x] = r[x].dest; - if ( flags != NULL ) flags[x] = r[x].flags; - if ( error != NULL ) error[x] = r[x].error; - - index[x] = r[x].index; - ret[x] = r[x].ret; - } - return(res); +static inline ssize_t dmaReadBulkIndex(int32_t fd, + uint32_t count, + int32_t* ret, + uint32_t* index, + uint32_t* flags, + uint32_t* error, + uint32_t* dest) { + struct DmaReadData r[count]; + size_t res; + size_t x; + + memset(r, 0, count * sizeof(struct DmaReadData)); + + res = read(fd, r, count * sizeof(struct DmaReadData)); + + for (x = 0; x < res; ++x) { + if (dest != NULL) dest[x] = r[x].dest; + if (flags != NULL) flags[x] = r[x].flags; + if (error != NULL) error[x] = r[x].error; + + index[x] = r[x].index; + ret[x] = r[x].ret; + } + return (res); } - // Post Index static inline ssize_t dmaRetIndex(int32_t fd, uint32_t index) { - uint32_t cmd = DMA_Ret_Index | 0x10000; + uint32_t cmd = DMA_Ret_Index | 0x10000; - return(ioctl(fd,cmd,&index)); + return (ioctl(fd, cmd, &index)); } // Post Index List -static inline ssize_t dmaRetIndexes(int32_t fd, uint32_t count, uint32_t *indexes) { - uint32_t cmd = DMA_Ret_Index | ((count << 16) & 0xFFFF0000); +static inline ssize_t dmaRetIndexes(int32_t fd, uint32_t count, uint32_t* indexes) { + uint32_t cmd = DMA_Ret_Index | ((count << 16) & 0xFFFF0000); - return(ioctl(fd,cmd,indexes)); + return (ioctl(fd, cmd, indexes)); } // Get write buffer index static inline uint32_t dmaGetIndex(int32_t fd) { - return(ioctl(fd,DMA_Get_Index,0)); + return (ioctl(fd, DMA_Get_Index, 0)); } // Get read ready status static inline ssize_t dmaReadReady(int32_t fd) { - return(ioctl(fd,DMA_Read_Ready,0)); + return (ioctl(fd, DMA_Read_Ready, 0)); } // get rx buffer count static inline ssize_t dmaGetRxBuffCount(int32_t fd) { - return(ioctl(fd,DMA_Get_RxBuff_Count,0)); + return (ioctl(fd, DMA_Get_RxBuff_Count, 0)); } // get tx buffer count static inline ssize_t dmaGetTxBuffCount(int32_t fd) { - return(ioctl(fd,DMA_Get_TxBuff_Count,0)); + return (ioctl(fd, DMA_Get_TxBuff_Count, 0)); } // get buffer size static inline ssize_t dmaGetBuffSize(int32_t fd) { - return(ioctl(fd,DMA_Get_Buff_Size,0)); + return (ioctl(fd, DMA_Get_Buff_Size, 0)); } // Return user space mapping to dma buffers -static inline void ** dmaMapDma(int32_t fd, uint32_t *count, uint32_t *size) { - void * temp; - void ** ret; - uint32_t bCount; - uint32_t gCount; - uint32_t bSize; - off_t offset; - - bSize = ioctl(fd,DMA_Get_Buff_Size,0); - bCount = ioctl(fd,DMA_Get_Buff_Count,0); - - if ( count != NULL ) *count = bCount; - if ( size != NULL ) *size = bSize; - - if ( (ret = (void **)malloc(sizeof(void *) * bCount)) == 0 ) return(NULL); - - // Attempt to map - gCount = 0; - while ( gCount < bCount ) { - offset = (off_t)bSize * (off_t)gCount; - - if ( (temp = mmap (0, bSize, PROT_READ | PROT_WRITE, MAP_SHARED, fd, offset)) == MAP_FAILED) break; - ret[gCount++] = temp; - } - - // Map failed - if ( gCount != bCount ) { - while ( gCount != 0 ) munmap(ret[--gCount],bSize); - free(ret); - ret = NULL; - } - return(ret); +static inline void** dmaMapDma(int32_t fd, uint32_t* count, uint32_t* size) { + void* temp; + void** ret; + uint32_t bCount; + uint32_t gCount; + uint32_t bSize; + off_t offset; + + bSize = ioctl(fd, DMA_Get_Buff_Size, 0); + bCount = ioctl(fd, DMA_Get_Buff_Count, 0); + + if (count != NULL) *count = bCount; + if (size != NULL) *size = bSize; + + if ((ret = (void**)malloc(sizeof(void*) * bCount)) == 0) return (NULL); + + // Attempt to map + gCount = 0; + while (gCount < bCount) { + offset = (off_t)bSize * (off_t)gCount; + + if ((temp = mmap(0, bSize, PROT_READ | PROT_WRITE, MAP_SHARED, fd, offset)) == MAP_FAILED) break; + ret[gCount++] = temp; + } + + // Map failed + if (gCount != bCount) { + while (gCount != 0) munmap(ret[--gCount], bSize); + free(ret); + ret = NULL; + } + return (ret); } // Free space mapping to dma buffers -static inline ssize_t dmaUnMapDma(int32_t fd, void ** buffer) { - uint32_t bCount; - uint32_t bSize; - uint32_t x; +static inline ssize_t dmaUnMapDma(int32_t fd, void** buffer) { + uint32_t bCount; + uint32_t bSize; + uint32_t x; - bCount = ioctl(fd,DMA_Get_Buff_Count,0); - bSize = ioctl(fd,DMA_Get_Buff_Size,0); + bCount = ioctl(fd, DMA_Get_Buff_Count, 0); + bSize = ioctl(fd, DMA_Get_Buff_Size, 0); - for (x=0; x < bCount; x++) munmap (buffer[x], bSize); + for (x = 0; x < bCount; x++) munmap(buffer[x], bSize); - free(buffer); - return(0); + free(buffer); + return (0); } // Set debug static inline ssize_t dmaSetDebug(int32_t fd, uint32_t level) { - return(ioctl(fd,DMA_Set_Debug,level)); + return (ioctl(fd, DMA_Set_Debug, level)); } // Assign interrupt handler -static inline void dmaAssignHandler (int32_t fd, void (*handler)(int32_t)) { - struct sigaction act; - int32_t oflags; - - act.sa_handler = handler; - sigemptyset(&act.sa_mask); - act.sa_flags = 0; - - sigaction(SIGIO, &act, NULL); - fcntl(fd, F_SETOWN, getpid()); - oflags = fcntl(fd, F_GETFL); - fcntl(fd, F_SETFL, oflags | FASYNC); +static inline void dmaAssignHandler(int32_t fd, void (*handler)(int32_t)) { + struct sigaction act; + int32_t oflags; + + act.sa_handler = handler; + sigemptyset(&act.sa_mask); + act.sa_flags = 0; + + sigaction(SIGIO, &act, NULL); + fcntl(fd, F_SETOWN, getpid()); + oflags = fcntl(fd, F_GETFL); + fcntl(fd, F_SETFL, oflags | FASYNC); } // set mask static inline ssize_t dmaSetMask(int32_t fd, uint32_t mask) { - return(ioctl(fd,DMA_Set_Mask,mask)); + return (ioctl(fd, DMA_Set_Mask, mask)); } // Init mask byte array -static inline void dmaInitMaskBytes(uint8_t * mask) { - memset(mask,0,DMA_MASK_SIZE); +static inline void dmaInitMaskBytes(uint8_t* mask) { + memset(mask, 0, DMA_MASK_SIZE); } // Add destination to mask byte array -static inline void dmaAddMaskBytes(uint8_t * mask, uint32_t dest) { - uint32_t byte; - uint32_t bit; - - if ( dest < 8*(DMA_MASK_SIZE)) { - byte = dest / 8; - bit = dest % 8; - mask[byte] += (1 << bit); - } +static inline void dmaAddMaskBytes(uint8_t* mask, uint32_t dest) { + uint32_t byte; + uint32_t bit; + + if (dest < 8 * (DMA_MASK_SIZE)) { + byte = dest / 8; + bit = dest % 8; + mask[byte] += (1 << bit); + } } // set mask byte array to driver -static inline ssize_t dmaSetMaskBytes(int32_t fd, uint8_t * mask) { - return(ioctl(fd,DMA_Set_MaskBytes,mask)); +static inline ssize_t dmaSetMaskBytes(int32_t fd, uint8_t* mask) { + return (ioctl(fd, DMA_Set_MaskBytes, mask)); } // Check API version, return negative on error static inline ssize_t dmaCheckVersion(int32_t fd) { - int32_t version; - version = ioctl(fd,DMA_Get_Version); - return((version == DMA_VERSION)?-0:-1); + int32_t version; + version = ioctl(fd, DMA_Get_Version); + return ((version == DMA_VERSION) ? -0 : -1); } // Write Register -static inline ssize_t dmaWriteRegister(int32_t fd, uint32_t address, uint32_t data) { - struct DmaRegisterData reg; +static inline ssize_t dmaWriteRegister(int32_t fd, uint64_t address, uint32_t data) { + struct DmaRegisterData reg; - reg.address = address; - reg.data = data; - return(ioctl(fd,DMA_Write_Register,®)); + reg.address = address; + reg.data = data; + return (ioctl(fd, DMA_Write_Register, ®)); } // Read Register -static inline ssize_t dmaReadRegister(int32_t fd, uint32_t address, uint32_t *data) { - struct DmaRegisterData reg; - ssize_t res; +static inline ssize_t dmaReadRegister(int32_t fd, uint64_t address, uint32_t* data) { + struct DmaRegisterData reg; + ssize_t res; - reg.address = address; - reg.data = 0; - res = ioctl(fd,DMA_Read_Register,®); + reg.address = address; + reg.data = 0; + res = ioctl(fd, DMA_Read_Register, ®); - if ( data != NULL ) *data = reg.data; + if (data != NULL) *data = reg.data; - return(res); + return (res); } -// Return user space mapping to a relative register space -static inline void * dmaMapRegister(int32_t fd, off_t offset, uint32_t size) { - uint32_t bCount; - uint32_t bSize; - off_t intOffset; +// Return user space mapping to a relative register space +static inline void* dmaMapRegister(int32_t fd, off_t offset, uint32_t size) { + uint32_t bCount; + uint32_t bSize; + off_t intOffset; - bSize = ioctl(fd,DMA_Get_Buff_Size,0); - bCount = ioctl(fd,DMA_Get_Buff_Count,0); + bSize = ioctl(fd, DMA_Get_Buff_Size, 0); + bCount = ioctl(fd, DMA_Get_Buff_Count, 0); - intOffset = (bSize * bCount) + offset; + intOffset = (bSize * bCount) + offset; - // Attempt to map - return(mmap (0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, intOffset)); + // Attempt to map + return (mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, intOffset)); } // Free space mapping to dma buffers -static inline ssize_t dmaUnMapRegister(int32_t fd, void *ptr, uint32_t size) { - munmap (ptr, size); - return(0); +static inline ssize_t dmaUnMapRegister(int32_t fd, void* ptr, uint32_t size) { + munmap(ptr, size); + return (0); } #endif #endif - diff --git a/include/rogue/hardware/drivers/PgpDriver.h b/include/rogue/hardware/drivers/PgpDriver.h index b5ac557c5..575d48b27 100755 --- a/include/rogue/hardware/drivers/PgpDriver.h +++ b/include/rogue/hardware/drivers/PgpDriver.h @@ -5,199 +5,194 @@ * Description: * Definitions and inline functions for interacting with PGP driver. * ---------------------------------------------------------------------------- - * This file is part of the aes_stream_drivers package. It is subject to - * the license terms in the LICENSE.txt file found in the top-level directory - * of this distribution and at: - * https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. - * No part of the aes_stream_drivers package, including this file, may be - * copied, modified, propagated, or distributed except according to the terms + * This file is part of the aes_stream_drivers package. It is subject to + * the license terms in the LICENSE.txt file found in the top-level directory + * of this distribution and at: + * https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. + * No part of the aes_stream_drivers package, including this file, may be + * copied, modified, propagated, or distributed except according to the terms * contained in the LICENSE.txt file. * ---------------------------------------------------------------------------- -**/ + **/ #ifndef __PGP_DRIVER_H__ #define __PGP_DRIVER_H__ #include "DmaDriver.h" //! PGP Card Info struct PgpInfo { + //! PGP Card Serial # + uint64_t serial; - //! PGP Card Serial # - uint64_t serial; + //! PGP Card Type + uint32_t type; - //! PGP Card Type - uint32_t type; + //! PGP Card Version + uint32_t version; - //! PGP Card Version - uint32_t version; + //! PGP Card Lane Mask + uint32_t laneMask; - //! PGP Card Lane Mask - uint32_t laneMask; + //! PGP Card VCs per Lane Mask + uint32_t vcPerMask; - //! PGP Card VCs per Lane Mask - uint32_t vcPerMask; + //! PGP Card Line Rate + uint32_t pgpRate; - //! PGP Card Line Rate - uint32_t pgpRate; + //! PGP Card Prom Programming Support Flag + uint32_t promPrgEn; - //! PGP Card Prom Programming Support Flag - uint32_t promPrgEn; + //! PGP Card EVR Support Flag + uint32_t evrSupport; - //! PGP Card EVR Support Flag - uint32_t evrSupport; + uint32_t pad; - uint32_t pad; - - char buildStamp[256]; + char buildStamp[256]; }; //! PCI Status struct PciStatus { + //! PCI Express Command Field + uint32_t pciCommand; - //! PCI Express Command Field - uint32_t pciCommand; - - //! PCI Express Status Field - uint32_t pciStatus; + //! PCI Express Status Field + uint32_t pciStatus; - //! PCI Express D Command Field - uint32_t pciDCommand; + //! PCI Express D Command Field + uint32_t pciDCommand; - //! PCI Express D Status Field - uint32_t pciDStatus; + //! PCI Express D Status Field + uint32_t pciDStatus; - //! PCI Express L Command Field - uint32_t pciLCommand; + //! PCI Express L Command Field + uint32_t pciLCommand; - //! PCI Express L Status Field - uint32_t pciLStatus; + //! PCI Express L Status Field + uint32_t pciLStatus; - //! PCI Express Link State - uint32_t pciLinkState; + //! PCI Express Link State + uint32_t pciLinkState; - //! PCI Express Function Number - uint32_t pciFunction; + //! PCI Express Function Number + uint32_t pciFunction; - //! PCI Express Device Number - uint32_t pciDevice; + //! PCI Express Device Number + uint32_t pciDevice; - //! PCI Express Bus Number - uint32_t pciBus; + //! PCI Express Bus Number + uint32_t pciBus; - //! Number Of PCI Lanes - uint32_t pciLanes; + //! Number Of PCI Lanes + uint32_t pciLanes; - uint32_t pad; + uint32_t pad; }; //! PGP Lane Status struct PgpStatus { + //! Lane number associated with this record + uint32_t lane; - //! Lane number associated with this record - uint32_t lane; - - //! Lane loopback status - uint32_t loopBack; + //! Lane loopback status + uint32_t loopBack; - //! Lane local link ready status - uint32_t locLinkReady; + //! Lane local link ready status + uint32_t locLinkReady; - //! Lane remote link ready status - uint32_t remLinkReady; + //! Lane remote link ready status + uint32_t remLinkReady; - //! Lane receive PLL ready status - uint32_t rxReady; + //! Lane receive PLL ready status + uint32_t rxReady; - //! Lane transmit PLL ready status - uint32_t txReady; + //! Lane transmit PLL ready status + uint32_t txReady; - //! Lane receive frame counter - uint32_t rxCount; + //! Lane receive frame counter + uint32_t rxCount; - //! Lane cell error counter - uint32_t cellErrCnt; + //! Lane cell error counter + uint32_t cellErrCnt; - //! Lane link lost transition counter - uint32_t linkDownCnt; + //! Lane link lost transition counter + uint32_t linkDownCnt; - //! Lane link error counter - uint32_t linkErrCnt; + //! Lane link error counter + uint32_t linkErrCnt; - //! Lane FIFO error counter - uint32_t fifoErr; + //! Lane FIFO error counter + uint32_t fifoErr; - //! Lane current received remote sideband data - uint32_t remData; + //! Lane current received remote sideband data + uint32_t remData; - //! Lane remote buffer status - uint32_t remBuffStatus; + //! Lane remote buffer status + uint32_t remBuffStatus; - uint32_t pad; + uint32_t pad; }; //! EVR Control, one per lane struct PgpEvrControl { + //! Lane number associated with this record + uint32_t lane; - //! Lane number associated with this record - uint32_t lane; + //! Global EVR enable for all lanes, 1 = enable, 0 = disabled + uint32_t evrEnable; // Global flag - //! Global EVR enable for all lanes, 1 = enable, 0 = disabled - uint32_t evrEnable; // Global flag + //! Run trigger enable for this lane, 1 = enable, 0 = disable + uint32_t laneRunMask; // 1 = Run trigger enable - //! Run trigger enable for this lane, 1 = enable, 0 = disable - uint32_t laneRunMask; // 1 = Run trigger enable + //! EVR Sync enable, 1 = start, 0 = stop + uint32_t evrSyncEn; // 1 = Start, 0 = Stop - //! EVR Sync enable, 1 = start, 0 = stop - uint32_t evrSyncEn; // 1 = Start, 0 = Stop + //! Sync select, 0 = async, 1 = sync for start/stop + uint32_t evrSyncSel; // 0 = async, 1 = sync for start/stop - //! Sync select, 0 = async, 1 = sync for start/stop - uint32_t evrSyncSel; // 0 = async, 1 = sync for start/stop + //! Header checking mask, 1 enable bit for each of 4 virtual channels. + uint32_t headerMask; // 1 = Enable header data checking, one bit per VC (4 bits) - //! Header checking mask, 1 enable bit for each of 4 virtual channels. - uint32_t headerMask; // 1 = Enable header data checking, one bit per VC (4 bits) + //! EVR Sync word, 32-bit timing fidicial to transition start/stop on + uint32_t evrSyncWord; // fiducial to transition start stop - //! EVR Sync word, 32-bit timing fidicial to transition start/stop on - uint32_t evrSyncWord; // fiducial to transition start stop + //! 8-bit timing code to assert run trigger + uint32_t runCode; // Run code - //! 8-bit timing code to assert run trigger - uint32_t runCode; // Run code + //! Delay between timing code reception and assertion of run trigger + uint32_t runDelay; // Run delay - //! Delay between timing code reception and assertion of run trigger - uint32_t runDelay; // Run delay + //! 8-bit timing code to assert accept trigger + uint32_t acceptCode; // Accept code - //! 8-bit timing code to assert accept trigger - uint32_t acceptCode; // Accept code + //! Delay between timing code reception and assertion of accept trigger + uint32_t acceptDelay; // Accept delay - //! Delay between timing code reception and assertion of accept trigger - uint32_t acceptDelay; // Accept delay - - uint32_t pad; + uint32_t pad; }; //! EVR Status, one per lane struct PgpEvrStatus { + //! Lane number associated with this record + uint32_t lane; - //! Lane number associated with this record - uint32_t lane; - - //! EVR link error counter - uint32_t linkErrors; + //! EVR link error counter + uint32_t linkErrors; - //! EVR link up state, 0 = down, 1 = up - uint32_t linkUp; + //! EVR link up state, 0 = down, 1 = up + uint32_t linkUp; - //! EVR running status, 0 = stopped, 1 = running - uint32_t runStatus; // 1 = Running, 0 = Stopped + //! EVR running status, 0 = stopped, 1 = running + uint32_t runStatus; // 1 = Running, 0 = Stopped - //! Current distributed timing seconds value - uint32_t evrSeconds; + //! Current distributed timing seconds value + uint32_t evrSeconds; - //! Number of run triggers received - uint32_t runCounter; + //! Number of run triggers received + uint32_t runCounter; - //! Number of accepts triggers received - uint32_t acceptCounter; + //! Number of accepts triggers received + uint32_t acceptCounter; - uint32_t pad; + uint32_t pad; }; // Card Types @@ -228,108 +223,107 @@ struct PgpEvrStatus { #ifndef DMA_IN_KERNEL static inline uint32_t pgpSetDest(uint32_t lane, uint32_t vc) { - uint32_t dest; + uint32_t dest; - dest = lane * 4; - dest += vc; - return(dest); + dest = lane * 4; + dest += vc; + return (dest); } -static inline uint32_t pgpSetFlags(uint32_t cont){ - return(cont & 0x1); +static inline uint32_t pgpSetFlags(uint32_t cont) { + return (cont & 0x1); } static inline uint32_t pgpGetLane(uint32_t dest) { - return(dest / 4); + return (dest / 4); } static inline uint32_t pgpGetVc(uint32_t dest) { - return(dest % 4); + return (dest % 4); } static inline uint32_t pgpGetCont(uint32_t flags) { - return(flags & 0x1); + return (flags & 0x1); } // Read Card Info -static inline ssize_t pgpGetInfo(int32_t fd, struct PgpInfo * info) { - return(ioctl(fd,PGP_Read_Info,info)); +static inline ssize_t pgpGetInfo(int32_t fd, struct PgpInfo* info) { + return (ioctl(fd, PGP_Read_Info, info)); } // Read PCI Status -static inline ssize_t pgpGetPci(int32_t fd, struct PciStatus * status) { - return(ioctl(fd,PGP_Read_Pci,status)); +static inline ssize_t pgpGetPci(int32_t fd, struct PciStatus* status) { + return (ioctl(fd, PGP_Read_Pci, status)); } // Read Lane Status -static inline ssize_t pgpGetStatus(int32_t fd, uint32_t lane, struct PgpStatus * status) { - status->lane = lane; - return(ioctl(fd,PGP_Read_Status,status)); +static inline ssize_t pgpGetStatus(int32_t fd, uint32_t lane, struct PgpStatus* status) { + status->lane = lane; + return (ioctl(fd, PGP_Read_Status, status)); } // Set Loopback State For Lane static inline ssize_t pgpSetLoop(int32_t fd, uint32_t lane, uint32_t state) { - uint32_t temp; + uint32_t temp; - temp = lane & 0xFF; - temp |= ((state << 8) & 0x100); + temp = lane & 0xFF; + temp |= ((state << 8) & 0x100); - return(ioctl(fd,PGP_Set_Loop,temp)); + return (ioctl(fd, PGP_Set_Loop, temp)); } // Reset counters static inline ssize_t pgpCountReset(int32_t fd) { - return(ioctl(fd,PGP_Count_Reset,0)); + return (ioctl(fd, PGP_Count_Reset, 0)); } // Set Sideband Data static inline ssize_t pgpSetData(int32_t fd, uint32_t lane, uint32_t data) { - uint32_t temp; + uint32_t temp; - temp = lane & 0xFF; - temp |= ((data << 8) & 0xFF00); + temp = lane & 0xFF; + temp |= ((data << 8) & 0xFF00); - return(ioctl(fd,PGP_Set_Data,temp)); + return (ioctl(fd, PGP_Set_Data, temp)); } // Send OpCode static inline ssize_t pgpSendOpCode(int32_t fd, uint32_t code) { - return(ioctl(fd,PGP_Send_OpCode,code)); + return (ioctl(fd, PGP_Send_OpCode, code)); } // Set EVR Control -static inline ssize_t pgpSetEvrControl(int32_t fd, uint32_t lane, struct PgpEvrControl * control) { - control->lane = lane; - return(ioctl(fd,PGP_Set_Evr_Cntrl,control)); +static inline ssize_t pgpSetEvrControl(int32_t fd, uint32_t lane, struct PgpEvrControl* control) { + control->lane = lane; + return (ioctl(fd, PGP_Set_Evr_Cntrl, control)); } // Get EVR Control -static inline ssize_t pgpGetEvrControl(int32_t fd, uint32_t lane, struct PgpEvrControl * control) { - control->lane = lane; - return(ioctl(fd,PGP_Get_Evr_Cntrl,control)); +static inline ssize_t pgpGetEvrControl(int32_t fd, uint32_t lane, struct PgpEvrControl* control) { + control->lane = lane; + return (ioctl(fd, PGP_Get_Evr_Cntrl, control)); } // Get EVR Status -static inline ssize_t pgpGetEvrStatus(int32_t fd, uint32_t lane, struct PgpEvrStatus * status) { - status->lane = lane; - return(ioctl(fd,PGP_Get_Evr_Status,status)); +static inline ssize_t pgpGetEvrStatus(int32_t fd, uint32_t lane, struct PgpEvrStatus* status) { + status->lane = lane; + return (ioctl(fd, PGP_Get_Evr_Status, status)); } // Reset EVR Counters static inline ssize_t pgpResetEvrCount(int32_t fd, uint32_t lane) { - return(ioctl(fd,PGP_Rst_Evr_Count,lane)); + return (ioctl(fd, PGP_Rst_Evr_Count, lane)); } // Add destination to mask byte array -static inline void pgpAddMaskBytes(uint8_t * mask, uint32_t lane, uint32_t vc) { - dmaAddMaskBytes(mask,lane*4+vc); +static inline void pgpAddMaskBytes(uint8_t* mask, uint32_t lane, uint32_t vc) { + dmaAddMaskBytes(mask, lane * 4 + vc); } // set lane/vc rx mask, one bit per vc static inline ssize_t pgpSetMask(int32_t fd, uint32_t lane, uint32_t vc) { - return(dmaSetMask(fd, lane*4+vc)); + return (dmaSetMask(fd, lane * 4 + vc)); } #endif #endif - diff --git a/src/rogue/hardware/pgp/Info.cpp b/src/rogue/hardware/pgp/Info.cpp index d86b2195f..ad6075e4c 100755 --- a/src/rogue/hardware/pgp/Info.cpp +++ b/src/rogue/hardware/pgp/Info.cpp @@ -10,16 +10,17 @@ * Description: * Wrapper for PgpInfo structure * ---------------------------------------------------------------------------- - * This file is part of the rogue software platform. It is subject to - * the license terms in the LICENSE.txt file found in the top-level directory - * of this distribution and at: - * https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. - * No part of the rogue software platform, including this file, may be - * copied, modified, propagated, or distributed except according to the terms + * This file is part of the rogue software platform. It is subject to + * the license terms in the LICENSE.txt file found in the top-level directory + * of this distribution and at: + * https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. + * No part of the rogue software platform, including this file, may be + * copied, modified, propagated, or distributed except according to the terms * contained in the LICENSE.txt file. * ---------------------------------------------------------------------------- **/ +#include #include #include @@ -54,7 +55,7 @@ void rhp::Info::setup_python() { .def_readonly("promPrgEn", &rhp::Info::promPrgEn) .def_readonly("evrSupport", &rhp::Info::evrSupport) .def("buildString", &rhp::Info::buildString) - ; + ; #endif }