diff --git a/src/rogue/interfaces/memory/Variable.cpp b/src/rogue/interfaces/memory/Variable.cpp
index eaa025e3f..b70630829 100755
--- a/src/rogue/interfaces/memory/Variable.cpp
+++ b/src/rogue/interfaces/memory/Variable.cpp
@@ -343,6 +343,9 @@ void rim::Variable::shiftOffsetDown(uint32_t shift, uint32_t minSize) {
 
    // Compute the highest byte, aligned to min access
    highTranByte_ = varBytes_ - 1;
+
+   // Adjust fast copy location
+   if ( fastCopy_ ) fastByte_ = bitOffset_[0] / 8;
 }
 
 void rim::Variable::updatePath(std::string path) {
diff --git a/tests/test_memory.py b/tests/test_memory.py
index 969955c44..e8fd7b7a1 100644
--- a/tests/test_memory.py
+++ b/tests/test_memory.py
@@ -17,11 +17,71 @@
 import rogue.interfaces.memory
 import time
 
-#rogue.Logging.setLevel(rogue.Logging.Warning)
+#rogue.Logging.setLevel(rogue.Logging.Debug)
 #import logging
 #logger = logging.getLogger('pyrogue')
 #logger.setLevel(logging.DEBUG)
 
+class SimpleDev(pr.Device):
+
+    def __init__(self,**kwargs):
+
+        super().__init__(**kwargs)
+
+        self.add(pr.RemoteVariable(
+            name         = "SimpleTestAA",
+            offset       =  0x1c,
+            bitSize      =  16,
+            bitOffset    =  0x00,
+            base         = pr.UInt,
+            mode         = "RW",
+        ))
+
+        self.add(pr.RemoteVariable(
+            name         = "SimpleTestAB",
+            offset       =  0x1e,
+            bitSize      =  16,
+            bitOffset    =  0x00,
+            base         = pr.UInt,
+            mode         = "RW",
+        ))
+
+        self.add(pr.RemoteVariable(
+            name         = "SimpleTestBA",
+            offset       =  0x20,
+            bitSize      =  8,
+            bitOffset    =  0x00,
+            base         = pr.UInt,
+            mode         = "RW",
+        ))
+
+        self.add(pr.RemoteVariable(
+            name         = "SimpleTestBB",
+            offset       =  0x21,
+            bitSize      =  8,
+            bitOffset    =  0x00,
+            base         = pr.UInt,
+            mode         = "RW",
+        ))
+
+        self.add(pr.RemoteVariable(
+            name         = "SimpleTestBC",
+            offset       =  0x22,
+            bitSize      =  8,
+            bitOffset    =  0x00,
+            base         = pr.UInt,
+            mode         = "RW",
+        ))
+
+        self.add(pr.RemoteVariable(
+            name         = "SimpleTestBD",
+            offset       =  0x23,
+            bitSize      =  8,
+            bitOffset    =  0x00,
+            base         = pr.UInt,
+            mode         = "RW",
+        ))
+
 class MemDev(pr.Device):
 
     def __init__(self,modeConfig='RW',**kwargs):
@@ -89,6 +149,12 @@ def __init__(self):
                 memBase    = mc,
             ))
 
+        self.add(SimpleDev(
+                name       = 'SimpleDev',
+                offset     = 0x80000,
+                memBase    = mc,
+            ))
+
 def test_memory():
 
     with DummyTree() as root:
@@ -100,6 +166,13 @@ def test_memory():
                 root.MemDev[dev].TestBlockBytes[i].set(value=i,write=writeVar)
                 root.MemDev[dev].TestBlockBits[i].set(value=i,write=writeVar)
 
+        root.SimpleDev.SimpleTestAA.set(0x40)
+        root.SimpleDev.SimpleTestAB.set(0x80)
+        root.SimpleDev.SimpleTestBA.set(0x41)
+        root.SimpleDev.SimpleTestBB.set(0x42)
+        root.SimpleDev.SimpleTestBC.set(0x43)
+        root.SimpleDev.SimpleTestBD.set(0x44)
+
         # Bulk Write Device
         root.MemDev[1].WriteDevice()
 
@@ -118,5 +191,16 @@ def test_memory():
                 if (retByte != i) or (retBit != i):
                     raise AssertionError(f'{root.MemDev[dev].path}: Verification Failure: i={i}, TestBlockBytes={retByte}, TestBlockBits={retBit}')
 
+        retAA = root.SimpleDev.SimpleTestAA.get()
+        retAB = root.SimpleDev.SimpleTestAB.get()
+        retBA = root.SimpleDev.SimpleTestBA.get()
+        retBB = root.SimpleDev.SimpleTestBB.get()
+        retBC = root.SimpleDev.SimpleTestBC.get()
+        retBD = root.SimpleDev.SimpleTestBD.get()
+
+        if (retAA != 0x40) or (retAB != 0x80) or (retBA != 0x41) or (retBB != 0x42) or (retBC != 0x43) or (retBD != 0x44):
+            raise AssertionError(f'Verification Failure: retAA={retAA}, retAB={retAB}, retBA={retBA}, retBB={retBB}, retBC={retBC}, retBD={retBD}')
+
+
 if __name__ == "__main__":
     test_memory()