From 2932d797c0b5c085adf489e0023860372d2bbe3d Mon Sep 17 00:00:00 2001 From: FilMarini Date: Fri, 7 Jun 2024 14:28:35 +0200 Subject: [PATCH 1/5] working on questa script generator --- vivado/msim.tcl | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/vivado/msim.tcl b/vivado/msim.tcl index 233b6feb..558dbf56 100644 --- a/vivado/msim.tcl +++ b/vivado/msim.tcl @@ -190,28 +190,20 @@ foreach filePntr ${fileList} { } } -##################################################################################################### -## Run Questa simulation -##################################################################################################### -set errMsg "\n\n*********************************************************\n" -set errMsg "${errMsg}Error in ${Simulator}. Check the errors in the console\n" - set errMsg "${errMsg}*********************************************************\n\n" +# Export command export_simulation -lib_map_path "/home/fmarini/git/BlueSurf/build/BlueSurf/BlueSurf_project.cache/compile_simlib/questa" -absolute_path -directory "/home/fmarini/git/BlueSurf/build/BlueSurf" -simulator questa -use_ip_compiled_libs -set sim_rc [catch { +# with vcs: export_simulation -lib_map_path "/home/fmarini/git/BlueSurf/build/BlueSurf/BlueSurf_project.cache/compile_simlib/vcs" -absolute_path -directory "/home/fmarini/git/BlueSurf/build/BlueSurf" -simulator vcs -use_ip_compiled_libs - # Set sim properties - set_property top ${VIVADO_PROJECT_SIM} [get_filesets sim_1] - set_property top_lib xil_defaultlib [get_filesets sim_1] +##################################################################################################### +## Export the Simulation +##################################################################################################### - # Launch the msim - launch_simulation -install_path ${MSIM_PATH} +# Export Xilinx & User IP Cores +generate_target -force {simulation} [get_ips] +export_ip_user_files -force -no_script -} _SIM_RESULT] +# Launch the scripts generator +set include [get_property include_dirs [get_filesets sim_1]]; # Verilog only +set define [get_property verilog_define [get_filesets sim_1]]; # Verilog only +export_simulation -force -absolute_path -simulator questa -include ${include} -define ${define} -lib_map_path ${simLibOutDir} -directory ${simTbOutDir}/ -######################################################## -# Check for error return code during the process -######################################################## -if { ${sim_rc} } { - puts ${errMsg} - exit -1 -} From d268a2ef5a680b609db18ea088dd55f0996076a0 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 11 Jun 2024 09:50:14 +0200 Subject: [PATCH 2/5] chnged msim script to generate sim files --- vivado/msim.tcl | 185 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 175 insertions(+), 10 deletions(-) diff --git a/vivado/msim.tcl b/vivado/msim.tcl index 558dbf56..fb7eed0c 100644 --- a/vivado/msim.tcl +++ b/vivado/msim.tcl @@ -75,7 +75,7 @@ proc Modelsim-QuestaVersionCheck { } { set retVar -1 # List of supported ModelSim/QuestaSim versions - set supported "2019.2 2021.1_2" + set supported "2019.2 2019.3_2 2021.1_2" # Get Version Name set SimInfo [GetModelsim-QuestaName] @@ -116,7 +116,6 @@ if { [VersionCheck 2016.4] < 0 } { # Check for supported ModelSim/Questa version if { [Modelsim-QuestaVersionCheck] < 0 } { - #exit -1 puts -nonewline "Sim version not supported, do you want to continue? (y/n): " flush stdout set Cont [gets stdin] @@ -141,12 +140,36 @@ SourceTclFile ${VIVADO_DIR}/pre_msim.tcl ##################################################################################################### # Setup variables - set SimInfo [GetModelsim-QuestaName] set Simulator [lindex $SimInfo 0] set VersionNumber [lindex $SimInfo 1] set MSIM_PATH [lindex $SimInfo 2] -set simLibOutDir ${VIVADO_INSTALL}/msim-${VersionNumber} +if { [info exists ::env(MSIM_LIB_PATH)] } { + set simLibOutDir $::env(MSIM_LIB_PATH) +} else { + set simLibOutDir ${VIVADO_INSTALL}/msim-${VersionNumber} +} +set simTbOutDir ${OUT_DIR}/${PROJECT}_project.sim/sim_1/behav +set simTbFileName [get_property top [get_filesets sim_1]] + +# Set the compile/elaborate options +if { [info exists ::env(MSIM_CARGS_VERILOG)] } { + set vlogOpt $::env(MSIM_CARGS_VERILOG) +} else { + set vlogOpt "" +} +if { [info exists ::env(MSIM_CARGS_VHDL)] } { + set vcomOpt $::env(MSIM_CARGS_VHDL) +} else { + set vcomOpt "" +} +if { [info exists ::env(MSIM_ELAB_FLAGS)] } { + set elabOpt $::env(MSIM_ELAB_FLAGS) +} else { + set elabOpt "" +} +puts ${vlogOpt} +puts ${vcomOpt} ##################################################################################################### ## Compile the Questa Simulation Library @@ -175,6 +198,9 @@ set_property compxlib.[string tolower ${Simulator}]_compiled_library_dir ${simLi # Configure ModelSim/Questa settings set VIVADO_PROJECT_SIM_TIME "set_property -name {[string tolower ${Simulator}].simulate.runtime} -value {$::env(VIVADO_PROJECT_SIM_TIME)} -objects \[\get_filesets \sim_1\]" eval ${VIVADO_PROJECT_SIM_TIME} +set_property -name {[string tolower ${Simulator}].compile.vcom.more_options} -value ${vcomOpt} -objects [get_filesets sim_1] +set_property -name {[string tolower ${Simulator}].compile.vlog.more_options} -value ${vlogOpt} -objects [get_filesets sim_1] +set_property -name {[string tolower ${Simulator}].elaborate.vopt.more_options} -value ${elabOpt} -objects [get_filesets sim_1] set_property nl.process_corner fast [get_filesets sim_1] set_property unifast true [get_filesets sim_1] @@ -190,14 +216,9 @@ foreach filePntr ${fileList} { } } -# Export command export_simulation -lib_map_path "/home/fmarini/git/BlueSurf/build/BlueSurf/BlueSurf_project.cache/compile_simlib/questa" -absolute_path -directory "/home/fmarini/git/BlueSurf/build/BlueSurf" -simulator questa -use_ip_compiled_libs - -# with vcs: export_simulation -lib_map_path "/home/fmarini/git/BlueSurf/build/BlueSurf/BlueSurf_project.cache/compile_simlib/vcs" -absolute_path -directory "/home/fmarini/git/BlueSurf/build/BlueSurf" -simulator vcs -use_ip_compiled_libs - ##################################################################################################### ## Export the Simulation ##################################################################################################### - # Export Xilinx & User IP Cores generate_target -force {simulation} [get_ips] export_ip_user_files -force -no_script @@ -205,5 +226,149 @@ export_ip_user_files -force -no_script # Launch the scripts generator set include [get_property include_dirs [get_filesets sim_1]]; # Verilog only set define [get_property verilog_define [get_filesets sim_1]]; # Verilog only -export_simulation -force -absolute_path -simulator questa -include ${include} -define ${define} -lib_map_path ${simLibOutDir} -directory ${simTbOutDir}/ +export_simulation -force -absolute_path -simulator [string tolower ${Simulator}] -include ${include} -define ${define} -lib_map_path ${simLibOutDir} -directory ${simTbOutDir}/ + +##################################################################################################### +## Customization of the executable bash (.sh) script +##################################################################################################### + +set err_ret [catch {get_files -compile_order sources -used_in simulation {*.v}} vList] +set err_ret [catch {get_files -compile_order sources -used_in simulation {*.vh}} vhList] +set err_ret [catch {get_files -compile_order sources -used_in simulation {*.sv}} svList] + +# Copy of all the Xilinx IP core datafile +set list "" +set list_rc [catch { + set list [glob -directory ${simTbOutDir}/[string tolower ${Simulator}]/ *.dat *.coe *.mem *.edif *.mif] +} _RESULT] +if { ${list} != "" } { + foreach pntr ${list} { + exec cp -f ${pntr} ${simTbOutDir}/. + } +} + +# open the main file +set in [open ${simTbOutDir}/[string tolower ${Simulator}]/${simTbFileName}.sh r] +set out [open ${simTbOutDir}/sim_vcs_mx.sh w] + +# Find and replace the AFS path +while { [eof ${in}] != 1 } { + + gets ${in} line + + # Do not execute the simulation in sim_vcs_mx.sh build script + if { [string match "*simulate.do*" ${line}] } { + set line " echo \"Ready to simulate\"" + + } + + # Replace ${simTbFileName}_simv with the simv + set replaceString "${simTbFileName}_simv simv" + set line [string map ${replaceString} ${line}] + + # Change the glbl.v path (Vivado 2017.2 fix) + set replaceString "behav/vcs/glbl.v glbl.v" + set line [string map ${replaceString} ${line}] + + # Write to file + puts ${out} ${line} +} + +# Close the files +close ${in} +close ${out} + +# Update the permissions +exec chmod 0755 ${simTbOutDir}/sim_vcs_mx.sh + +# Update the compile options (fix bug in export_simulation not including more_options properties) +if { [VersionCompare 2022.1] <= 0 } { + # open the compile file + set in [open ${simTbOutDir}/[string tolower ${Simulator}]/compile.do r] + set out [open ${simTbOutDir}/compile.do w] + + # Set substitutions + set vcom_new_sub "-64 -93 ${vcomOpt} " + set vcom_old_sub "-64 -93 " + + set vlog_new_sub "-incr -mfcu ${vlogOpt} " + set vlog_old_sub "-incr -mfcu " + + # Find and replace the AFS path + while { [eof ${in}] != 1 } { + gets ${in} line + + set line [regsub -- ${vcom_old_sub} $line ${vcom_new_sub}] + set line [regsub -- ${vlog_old_sub} $line ${vlog_new_sub}] + + puts ${out} ${line} + } + + # Close the files + close ${in} + close ${out} + + # open the elaborate file + set in [open ${simTbOutDir}/[string tolower ${Simulator}]/elaborate.do r] + set out [open ${simTbOutDir}/elaborate.do w] + + # Set substitutions + set velab_new_sub "-64 ${elabOpt} " + set velab_old_sub "-64 " + + # Find and replace the AFS path + while { [eof ${in}] != 1 } { + gets ${in} line + + set line [regsub -- ${velab_old_sub} $line ${velab_new_sub}] + set line [regsub -- ${velab_old_sub} $line ${velab_new_sub}] + + # Check if only a VHDL simulation + if { ${vList} == "" && + ${vhList} == "" && + ${svList} == "" } { + # Remove xil_defaultlib.glbl (bug fix for Vivado compiling VCS script) + set line [string map { "xil_defaultlib.glbl" "" } ${line}] + } + + puts ${out} ${line} + } + + # Close the files + close ${in} + close ${out} + +} else { + # Copy the compile.do file + if { [file exists ${simTbOutDir}/[string tolower ${Simulator}]/compile.do] == 1 } { + exec cp -f ${simTbOutDir}/[string tolower ${Simulator}]/compile.do ${simTbOutDir}/compile.do + } + + # Copy the elaborate.do file + if { [file exists ${simTbOutDir}/[string tolower ${Simulator}]/elaborate.do] == 1 } { + exec cp -f ${simTbOutDir}/[string tolower ${Simulator}]/elaborate.do ${simTbOutDir}/elaborate.do + } +} + +##################################################################################################### +##################################################################################################### +##################################################################################################### + +# Copy the glbl.v file +if { [file exists ${simTbOutDir}/[string tolower ${Simulator}]/glbl.v] == 1 } { + # Change the glbl.v path (Vivado 2017.2 fix) + exec cp -f ${simTbOutDir}/[string tolower ${Simulator}]/glbl.v ${simTbOutDir}/../glbl.v + exec cp -f ${simTbOutDir}/[string tolower ${Simulator}]/glbl.v ${simTbOutDir}/glbl.v +} + +# Target specific VCS script +SourceTclFile ${VIVADO_DIR}/post_vcs.tcl + +# Close the project (required for cd function) +close_project + +# Set rogue Sim +set rogueSimEn false +# VCS Complete Message +VcsCompleteMessage ${simTbOutDir} ${rogueSimEn} From 3c792c3eb1a0019aff552450d8e9e149a661931a Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 11 Jun 2024 17:57:44 +0200 Subject: [PATCH 3/5] finalized script, to check for oversights --- vivado/msim.tcl | 85 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 77 insertions(+), 8 deletions(-) diff --git a/vivado/msim.tcl b/vivado/msim.tcl index fb7eed0c..248b39ad 100644 --- a/vivado/msim.tcl +++ b/vivado/msim.tcl @@ -151,6 +151,8 @@ if { [info exists ::env(MSIM_LIB_PATH)] } { } set simTbOutDir ${OUT_DIR}/${PROJECT}_project.sim/sim_1/behav set simTbFileName [get_property top [get_filesets sim_1]] +set hopeTopFile [lindex [find_top -fileset [get_filesets sim_1] -return_file_paths] 1] +set simTbLibName [get_property -quiet LIBRARY [get_files -quiet $hopeTopFile]] # Set the compile/elaborate options if { [info exists ::env(MSIM_CARGS_VERILOG)] } { @@ -168,8 +170,17 @@ if { [info exists ::env(MSIM_ELAB_FLAGS)] } { } else { set elabOpt "" } -puts ${vlogOpt} -puts ${vcomOpt} +if { [info exists ::env(MSIM_RUN_FLAGS)] } { + set runOpt $::env(MSIM_RUN_FLAGS) +} else { + set runOpt "" +} +# Run vsim with GUI +if { [info exists ::env(MSIM_RUN_GUI)] } { + set msimGui $::env(MSIM_RUN_GUI) +} else { + set msimGui false +} ##################################################################################################### ## Compile the Questa Simulation Library @@ -249,17 +260,24 @@ if { ${list} != "" } { # open the main file set in [open ${simTbOutDir}/[string tolower ${Simulator}]/${simTbFileName}.sh r] -set out [open ${simTbOutDir}/sim_vcs_mx.sh w] +set out [open ${simTbOutDir}/sim_msim.sh w] # Find and replace the AFS path while { [eof ${in}] != 1 } { gets ${in} line - # Do not execute the simulation in sim_vcs_mx.sh build script + # Do not execute the simulation in sim_msim.sh build script if { [string match "*simulate.do*" ${line}] } { - set line " echo \"Ready to simulate\"" - + if { ${msimGui} } { + set line "echo \"\vsim -64 ${runOpt} -do \\\"do \{simulate.do\}\\\" -lib xil_defaultlib ${simTbFileName}_opt\" >> vsim\n" + append line "chmod 0755 ${simTbOutDir}/simv\n" + append line echo \"Ready to simulate\"" + } else { + set line "echo \"vsim -64 -c ${runOpt} -do \\\"do \{simulate.do\}\\\" -lib ${simTbLibName} ${simTbFileName}_opt\" >> simv\n" + append line "chmod 0755 ${simTbOutDir}/simv\n" + append line "echo \"Ready to simulate\"" + } } # Replace ${simTbFileName}_simv with the simv @@ -279,7 +297,7 @@ close ${in} close ${out} # Update the permissions -exec chmod 0755 ${simTbOutDir}/sim_vcs_mx.sh +exec chmod 0755 ${simTbOutDir}/sim_msim.sh # Update the compile options (fix bug in export_simulation not including more_options properties) if { [VersionCompare 2022.1] <= 0 } { @@ -328,7 +346,7 @@ if { [VersionCompare 2022.1] <= 0 } { ${vhList} == "" && ${svList} == "" } { # Remove xil_defaultlib.glbl (bug fix for Vivado compiling VCS script) - set line [string map { "xil_defaultlib.glbl" "" } ${line}] + set line [string map { "xil_defaultlib.glbl" "" } ${line}] } puts ${out} ${line} @@ -350,6 +368,57 @@ if { [VersionCompare 2022.1] <= 0 } { } } +# Copy the simulation file +set in [open ${simTbOutDir}/[string tolower ${Simulator}]/simulate.do r] +set out [open ${simTbOutDir}/simulate.do w] + +# Find and replace the AFS path +while { [eof ${in}] != 1 } { + gets ${in} line + # Delete vsim command + if { [string match "*vsim*" ${line}] } { + set line "" + } + # Delete need for .udo files + if { [string match "*.udo\}" ${line}] } { + set line "# Insert custom action here" + } + puts ${out} ${line} +} + +# Close the files +close ${in} +close ${out} + +# Copy the wave.do file +if { [info exists ::env(MSIM_DUMP_VCD)] } { + set msimVcdDump $::env(MSIM_DUMP_VCD) +} else { + set msimVcdDump false +} + +if { ${msimVcdDump} } { + set in [open ${simTbOutDir}/[string tolower ${Simulator}]/wave.do r] + set out [open ${simTbOutDir}/wave.do w] + + # Find and replace the AFS path + while { [eof ${in}] != 1 } { + # copy files + gets ${in} line + puts ${out} ${line} + } + puts ${out} "vcd file sim.vcd" + puts ${out} "vcd add -r *" + + # Close the files + close ${in} + close ${out} +} else { + if { [file exists ${simTbOutDir}/[string tolower ${Simulator}]/wave.do] == 1 } { + exec cp -f ${simTbOutDir}/[string tolower ${Simulator}]/wave.do ${simTbOutDir}/wave.do + } +} + ##################################################################################################### ##################################################################################################### ##################################################################################################### From 058c40b5c99fe700e5ea6369295f9c8e42f456a9 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Wed, 12 Jun 2024 09:54:50 +0200 Subject: [PATCH 4/5] added msim script generation --- vivado/msim.tcl | 14 +++++++------- vivado/proc/sim_management.tcl | 17 +++++++++++++++++ 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/vivado/msim.tcl b/vivado/msim.tcl index 248b39ad..3b1899e5 100644 --- a/vivado/msim.tcl +++ b/vivado/msim.tcl @@ -285,7 +285,7 @@ while { [eof ${in}] != 1 } { set line [string map ${replaceString} ${line}] # Change the glbl.v path (Vivado 2017.2 fix) - set replaceString "behav/vcs/glbl.v glbl.v" + set replaceString "behav/[string tolower ${Simulator}]/glbl.v glbl.v" set line [string map ${replaceString} ${line}] # Write to file @@ -345,7 +345,7 @@ if { [VersionCompare 2022.1] <= 0 } { if { ${vList} == "" && ${vhList} == "" && ${svList} == "" } { - # Remove xil_defaultlib.glbl (bug fix for Vivado compiling VCS script) + # Remove xil_defaultlib.glbl (bug fix for Vivado compiling Msim script) set line [string map { "xil_defaultlib.glbl" "" } ${line}] } @@ -407,7 +407,7 @@ if { ${msimVcdDump} } { gets ${in} line puts ${out} ${line} } - puts ${out} "vcd file sim.vcd" + puts ${out} "vcd file ${simTbFileName}.vcd" puts ${out} "vcd add -r *" # Close the files @@ -430,8 +430,8 @@ if { [file exists ${simTbOutDir}/[string tolower ${Simulator}]/glbl.v] == 1 } { exec cp -f ${simTbOutDir}/[string tolower ${Simulator}]/glbl.v ${simTbOutDir}/glbl.v } -# Target specific VCS script -SourceTclFile ${VIVADO_DIR}/post_vcs.tcl +# Target specific MSIM script +SourceTclFile ${VIVADO_DIR}/post_msim.tcl # Close the project (required for cd function) close_project @@ -439,5 +439,5 @@ close_project # Set rogue Sim set rogueSimEn false -# VCS Complete Message -VcsCompleteMessage ${simTbOutDir} ${rogueSimEn} +# MSIM Complete Message +MsimCompleteMessage ${simTbOutDir} ${rogueSimEn} diff --git a/vivado/proc/sim_management.tcl b/vivado/proc/sim_management.tcl index e6c867ad..4a999921 100644 --- a/vivado/proc/sim_management.tcl +++ b/vivado/proc/sim_management.tcl @@ -78,3 +78,20 @@ proc VcsCompleteMessage {dirPath rogueSim} { puts "\t\$ ./simv -verdi &" puts "********************************************************\n\n" } + +## Print the MSIM build complete message +proc MsimCompleteMessage {dirPath rogueSim} { + puts "\n\n********************************************************" + puts "The Modelsim/Questa simulation script has been generated." + puts "To compile and run the simulation:" + puts "\t\$ cd ${dirPath}/" + if { ${rogueSim} == true } { + if { $::env(SHELL) != "/bin/bash" } { + puts "\t\$ source setup_env.csh" + } else { + puts "\t\$ source setup_env.sh" + } + } + puts "\t\$ ./sim_msim.sh" + puts "********************************************************\n\n" +} From 812b34d5d9a0b3b4d79c4067a65736c7440b9e14 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Wed, 12 Jun 2024 10:18:57 +0200 Subject: [PATCH 5/5] fixed oversight --- vivado/msim.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vivado/msim.tcl b/vivado/msim.tcl index 3b1899e5..446fd554 100644 --- a/vivado/msim.tcl +++ b/vivado/msim.tcl @@ -270,11 +270,11 @@ while { [eof ${in}] != 1 } { # Do not execute the simulation in sim_msim.sh build script if { [string match "*simulate.do*" ${line}] } { if { ${msimGui} } { - set line "echo \"\vsim -64 ${runOpt} -do \\\"do \{simulate.do\}\\\" -lib xil_defaultlib ${simTbFileName}_opt\" >> vsim\n" + set line "echo \"\vsim -64 ${runOpt} -do \\\"do \{simulate.do\}\\\" -lib xil_defaultlib ${simTbFileName}_opt\" > vsim\n" append line "chmod 0755 ${simTbOutDir}/simv\n" append line echo \"Ready to simulate\"" } else { - set line "echo \"vsim -64 -c ${runOpt} -do \\\"do \{simulate.do\}\\\" -lib ${simTbLibName} ${simTbFileName}_opt\" >> simv\n" + set line "echo \"vsim -64 -c ${runOpt} -do \\\"do \{simulate.do\}\\\" -lib ${simTbLibName} ${simTbFileName}_opt\" > simv\n" append line "chmod 0755 ${simTbOutDir}/simv\n" append line "echo \"Ready to simulate\"" }