control-unit

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Here are 23 public repositories matching this topic...

mck-sbs / PyConSys

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Python Control System : Create control loops and let the AI set the PID parameters

python ai pid evolutionary-algorithms control-systems control-unit control-loops pygad

Updated Nov 15, 2023
Python

mck-sbs / Pendulum

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Inverted Pendulum in python with pybox2d. Fuzzy and PID simulation included.

control pid fuzzy control-systems control-loop inverted-pendulum pybox2d control-unit

Updated Jan 24, 2021
Python

Karan-nevage / RISC-V-Single-Cycle-Core-Verilog-

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This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.

verilog alu vlsi risc-v control-unit verilog-project cpu-design

Updated Oct 11, 2024
JavaScript

arasgungore / NandGame

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Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

Updated Nov 4, 2023

gabrielganzer / VHDL-DesignSynthesis

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Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

polito vhdl scripts tcl rtl verilog synthesis digital-design control-unit subtractor physical-design booth-multiplier register-file windowed-register-file adder-subtractor

Updated Jan 24, 2021
Verilog

EmreKumas / Processor_Design

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This is an implementation of a simple CPU in Logisim and Verilog.

cpu instructions assembler alu logisim modelsim control-unit cpu-design cpu-simulation register-file data-memory address-memory

Updated Jan 11, 2019
Verilog

ryanvickr / Taillight-Control-Unit

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An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.

vhdl altera cyclone-v control-unit taillight

Updated Feb 8, 2021
VHDL

keonhee-han / Control-Unit-Design-VHDL-

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fpga vhdl control-unit

Updated Aug 31, 2018

ErfanXH / Computer-Architecture-IUST

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My Solutions to Computer Architecture Course Practical Assignments

cache processor vhdl computer-architecture alu fifo fifo-queue multiplier control-unit direct-mapped-cache

Updated Sep 2, 2024
VHDL

claudiomarpda / control_unit

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Implementation of a microprogrammed control unit for didactic purpose

cpu register memory cache computer-architecture control-unit

Updated Dec 5, 2017
C

IshanMK / 8-bit-single-cycle-cpu

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simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL.

Updated Jun 5, 2023
Verilog

EslamAsHhraf / Pipelined-Processor

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🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

python state-machine memory processor instrumentation verilog buffers computer-architecture registers program-counter control-unit pipline pipline-operators cufe-2024 execution-unit pipelined-processor

Updated Oct 16, 2023
Verilog

0marAmr / Single_Cycle_RISC-V_processor

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fpga memory processor verilog vivado datapath alu verilog-hdl risc-v digital-design control-unit fpga-programming

Updated Mar 12, 2023
Verilog

ksajan / Control_Unit_Simulation

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Using Python creating simulation of Control unit

python3 control-unit microprogrammed-control-unit computer-organisation-architechure

Updated Apr 15, 2019
Python

NajimAlfutini / Design-A-Full-SRC-Processor

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The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.

cpu pipeline memory isa alu control-unit

Updated Apr 9, 2024
HTML

mehmetakifkoz / MARS-Web-App

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This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.