From 29f8c6c9169bef17f2f294bd97e9931b809face3 Mon Sep 17 00:00:00 2001 From: seveibar Date: Wed, 24 Jul 2024 13:31:01 -0700 Subject: [PATCH 1/3] add hack allowing missing start_pcb_port_ids and end_pcb_port_ids to not break overlap testing when a trace only contains two ports --- lib/add-start-and-end-port-ids-if-missing.ts | 60 +- lib/check-each-pcb-trace-non-overlapping.ts | 55 +- tests/assets/traces1.solution.json | 1883 +++++++++++++++++ .../overlapping-bug-traces1.test.ts | 12 + 4 files changed, 1980 insertions(+), 30 deletions(-) create mode 100644 tests/assets/traces1.solution.json create mode 100644 tests/lib/check-each-pcb-trace-non-overlapping/overlapping-bug-traces1.test.ts diff --git a/lib/add-start-and-end-port-ids-if-missing.ts b/lib/add-start-and-end-port-ids-if-missing.ts index b82638a..b7009ed 100644 --- a/lib/add-start-and-end-port-ids-if-missing.ts +++ b/lib/add-start-and-end-port-ids-if-missing.ts @@ -4,37 +4,77 @@ import type { SourceTrace, AnySoupElement, PCBTraceError, + PCBSMTPad, } from "@tscircuit/soup" function distance(x1: number, y1: number, x2: number, y2: number): number { return Math.sqrt((x2 - x1) ** 2 + (y2 - y1) ** 2) } +/** + * HACK: this whole method and all usage of it is a hack because of this issue: + * https://github.com/tscircuit/tscircuit/issues/291 + */ export const addStartAndEndPortIdsIfMissing = ( soup: AnySoupElement[], ): void => { const pcbPorts: PCBPort[] = soup.filter((item) => item.type === "pcb_port") + const pcbSmtPads: PCBSMTPad[] = soup.filter( + (item) => item.type === "pcb_smtpad", + ) const pcbTraces: PCBTrace[] = soup.filter((item) => item.type === "pcb_trace") + function findPortIdOverlappingPoint( + point: { + x: number + y: number + }, + options: { isFirstOrLastPoint?: boolean } = {}, + ): string | null { + const directPort = pcbPorts.find( + (port) => distance(port.x, port.y, point.x, point.y) < 0.01, + ) + if (directPort) return directPort.pcb_port_id + + // If it starts or ends inside an smtpad, we'll connect it to the por + if (options.isFirstOrLastPoint) { + const smtPad = pcbSmtPads.find((pad) => { + if (pad.shape === "rect") { + return ( + Math.abs(point.x - pad.x) < pad.width / 2 && + Math.abs(point.y - pad.y) < pad.height / 2 + ) + // biome-ignore lint/style/noUselessElse: + } else if (pad.shape === "circle") { + return distance(point.x, point.y, pad.x, pad.y) < pad.radius + } + }) + if (smtPad) return smtPad.pcb_port_id ?? null + } + + return null + } + // Add start_pcb_port_id and end_pcb_port_id if not present for (const trace of pcbTraces) { for (let index = 0; index < trace.route.length; index++) { const segment = trace.route[index] + const isFirstOrLastPoint = index === 0 || index === trace.route.length - 1 if (segment.route_type === "wire") { if (!segment.start_pcb_port_id && index === 0) { - const startPort = pcbPorts.find( - (port) => distance(port.x, port.y, segment.x, segment.y) < 0.001, - ) - if (startPort) { - segment.start_pcb_port_id = startPort.pcb_port_id + const startPortId = findPortIdOverlappingPoint(segment, { + isFirstOrLastPoint, + }) + if (startPortId) { + segment.start_pcb_port_id = startPortId } } if (!segment.end_pcb_port_id && index === trace.route.length - 1) { - const endPort = pcbPorts.find( - (port) => distance(port.x, port.y, segment.x, segment.y) < 0.001, - ) - if (endPort) { - segment.end_pcb_port_id = endPort.pcb_port_id + const endPortId = findPortIdOverlappingPoint(segment, { + isFirstOrLastPoint, + }) + if (endPortId) { + segment.end_pcb_port_id = endPortId } } } diff --git a/lib/check-each-pcb-trace-non-overlapping.ts b/lib/check-each-pcb-trace-non-overlapping.ts index bdbf12d..7475ecf 100644 --- a/lib/check-each-pcb-trace-non-overlapping.ts +++ b/lib/check-each-pcb-trace-non-overlapping.ts @@ -7,6 +7,7 @@ import type { import { NetManager } from "./net-manager" import { addStartAndEndPortIdsIfMissing } from "./add-start-and-end-port-ids-if-missing" import Debug from "debug" +import { su } from "@tscircuit/soup-util" const debug = Debug("tscircuit:checks:check-each-pcb-trace-non-overlapping") @@ -58,7 +59,7 @@ function tracesOverlap(trace1: PCBTrace, trace2: PCBTrace): boolean { seg4.x, seg4.y, ) - return areLinesIntersecting + if (areLinesIntersecting) return true } } } @@ -130,22 +131,24 @@ function traceOverlapsWithPad(trace: PCBTrace, pad: PCBSMTPad): boolean { return false } -function getPortIdsConnectedToTrace(trace: PCBTrace) { - const connectedPorts = new Set() +function getPcbPortIdsConnectedToTrace(trace: PCBTrace) { + const connectedPcbPorts = new Set() for (const segment of trace.route) { if (segment.route_type === "wire") { if (segment.start_pcb_port_id) - connectedPorts.add(segment.start_pcb_port_id) - if (segment.end_pcb_port_id) connectedPorts.add(segment.end_pcb_port_id) + connectedPcbPorts.add(segment.start_pcb_port_id) + if (segment.end_pcb_port_id) + connectedPcbPorts.add(segment.end_pcb_port_id) } } - return Array.from(connectedPorts) + + return Array.from(connectedPcbPorts) } -function getPortIdsConnectedToTraces(...traces: PCBTrace[]) { +function getPcbPortIdsConnectedToTraces(traces: PCBTrace[]) { const connectedPorts = new Set() for (const trace of traces) { - for (const portId of getPortIdsConnectedToTrace(trace)) { + for (const portId of getPcbPortIdsConnectedToTrace(trace)) { connectedPorts.add(portId) } } @@ -167,7 +170,7 @@ function checkEachPcbTraceNonOverlapping( // TODO use source port ids instead of port ids, parse source ports for connections for (const trace of pcbTraces) { - netManager.setConnected(getPortIdsConnectedToTrace(trace)) + netManager.setConnected(getPcbPortIdsConnectedToTrace(trace)) } for (let i = 0; i < pcbTraces.length; i++) { @@ -175,14 +178,23 @@ function checkEachPcbTraceNonOverlapping( debug( `Checking overlap for ${pcbTraces[i].pcb_trace_id} and ${pcbTraces[j].pcb_trace_id}`, ) - debug( - `Connected ports: ${getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j])}`, - ) - if ( - netManager.isConnected( - getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j]), - ) - ) { + const connectedPorts = getPcbPortIdsConnectedToTraces([ + pcbTraces[i], + pcbTraces[j], + ]) + debug(`Connected ports: ${connectedPorts.join(",")}`) + + if (connectedPorts.length === 0) { + debug("No ports connected to trace, skipping") + continue + } + + if (connectedPorts.length === 1) { + debug("Only one port connected, skipping") + continue + } + + if (netManager.isConnected(connectedPorts)) { continue } if (tracesOverlap(pcbTraces[i], pcbTraces[j])) { @@ -194,7 +206,10 @@ function checkEachPcbTraceNonOverlapping( source_trace_id: "", pcb_error_id: `overlap_${pcbTraces[i].pcb_trace_id}_${pcbTraces[j].pcb_trace_id}`, pcb_component_ids: [], - pcb_port_ids: getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j]), + pcb_port_ids: getPcbPortIdsConnectedToTraces([ + pcbTraces[i], + pcbTraces[j], + ]), }) } } @@ -203,7 +218,7 @@ function checkEachPcbTraceNonOverlapping( if ( pad.pcb_port_id && netManager.isConnected( - getPortIdsConnectedToTrace(pcbTraces[i]).concat([pad.pcb_port_id]), + getPcbPortIdsConnectedToTrace(pcbTraces[i]).concat([pad.pcb_port_id]), ) ) { continue @@ -217,7 +232,7 @@ function checkEachPcbTraceNonOverlapping( source_trace_id: "", pcb_error_id: `overlap_${pcbTraces[i].pcb_trace_id}_${pad.pcb_smtpad_id}`, pcb_component_ids: [], - pcb_port_ids: getPortIdsConnectedToTrace(pcbTraces[i]), + pcb_port_ids: getPcbPortIdsConnectedToTrace(pcbTraces[i]), }) } } diff --git a/tests/assets/traces1.solution.json b/tests/assets/traces1.solution.json new file mode 100644 index 0000000..12ab1ed --- /dev/null +++ b/tests/assets/traces1.solution.json @@ -0,0 +1,1883 @@ +[ + { + "type": "source_component", + "source_component_id": "simple_bug_0", + "name": "A", + "supplier_part_numbers": {}, + "ftype": "simple_bug", + "pcbX": 0, + "pcbY": 0 + }, + { + "type": "schematic_component", + "source_component_id": "simple_bug_0", + "schematic_component_id": "schematic_component_simple_bug_0", + "rotation": 0, + "size": { + "width": 1, + "height": 2.5 + }, + "center": { + "x": 0, + "y": 0 + } + }, + { + "type": "source_port", + "name": "1", + "source_port_id": "source_port_0", + "source_component_id": "simple_bug_0", + "pin_number": 1, + "port_hints": [ + "1", + "1" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_0", + "source_port_id": "source_port_0", + "center": { + "x": -0.75, + "y": 1 + }, + "facing_direction": "left", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_0", + "schematic_text_id": "schematic_text_10", + "text": "1", + "anchor": "center", + "rotation": 0, + "position": { + "x": -0.6262563132923542, + "y": 0.8762563132923542 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_0", + "source_port_id": "source_port_0", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": -2.125, + "y": 0.375, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "2", + "source_port_id": "source_port_1", + "source_component_id": "simple_bug_0", + "pin_number": 2, + "port_hints": [ + "2", + "2" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_1", + "source_port_id": "source_port_1", + "center": { + "x": -0.75, + "y": 0.5 + }, + "facing_direction": "left", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_1", + "schematic_text_id": "schematic_text_11", + "text": "2", + "anchor": "center", + "rotation": 0, + "position": { + "x": -0.6262563132923542, + "y": 0.3762563132923542 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_1", + "source_port_id": "source_port_1", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": -2.125, + "y": -0.125, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "3", + "source_port_id": "source_port_2", + "source_component_id": "simple_bug_0", + "pin_number": 3, + "port_hints": [ + "3", + "3" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_2", + "source_port_id": "source_port_2", + "center": { + "x": -0.75, + "y": 0 + }, + "facing_direction": "left", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_2", + "schematic_text_id": "schematic_text_12", + "text": "3", + "anchor": "center", + "rotation": 0, + "position": { + "x": -0.6262563132923542, + "y": -0.12374368670764582 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_2", + "source_port_id": "source_port_2", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": -2.125, + "y": -0.625, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "4", + "source_port_id": "source_port_3", + "source_component_id": "simple_bug_0", + "pin_number": 4, + "port_hints": [ + "4", + "4" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_3", + "source_port_id": "source_port_3", + "center": { + "x": -0.75, + "y": -0.5 + }, + "facing_direction": "left", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_3", + "schematic_text_id": "schematic_text_13", + "text": "4", + "anchor": "center", + "rotation": 0, + "position": { + "x": -0.6262563132923542, + "y": -0.6237436867076458 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_3", + "source_port_id": "source_port_3", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": -0.125, + "y": -2.125, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "5", + "source_port_id": "source_port_4", + "source_component_id": "simple_bug_0", + "pin_number": 5, + "port_hints": [ + "5", + "5" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_4", + "source_port_id": "source_port_4", + "center": { + "x": -0.75, + "y": -1 + }, + "facing_direction": "left", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_4", + "schematic_text_id": "schematic_text_14", + "text": "5", + "anchor": "center", + "rotation": 0, + "position": { + "x": -0.6262563132923542, + "y": -1.1237436867076458 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_4", + "source_port_id": "source_port_4", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": 0.375, + "y": -2.125, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "6", + "source_port_id": "source_port_5", + "source_component_id": "simple_bug_0", + "pin_number": 6, + "port_hints": [ + "6", + "6" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_5", + "source_port_id": "source_port_5", + "center": { + "x": 0.75, + "y": -1 + }, + "facing_direction": "right", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_5", + "schematic_text_id": "schematic_text_15", + "text": "6", + "anchor": "center", + "rotation": 0, + "position": { + "x": 0.6262563132923542, + "y": -1.1237436867076458 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_5", + "source_port_id": "source_port_5", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": 2.125, + "y": -0.375, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "7", + "source_port_id": "source_port_6", + "source_component_id": "simple_bug_0", + "pin_number": 7, + "port_hints": [ + "7", + "7" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_6", + "source_port_id": "source_port_6", + "center": { + "x": 0.75, + "y": -0.5 + }, + "facing_direction": "right", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_6", + "schematic_text_id": "schematic_text_16", + "text": "7", + "anchor": "center", + "rotation": 0, + "position": { + "x": 0.6262563132923542, + "y": -0.6237436867076458 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_6", + "source_port_id": "source_port_6", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": 2.125, + "y": 0.125, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "8", + "source_port_id": "source_port_7", + "source_component_id": "simple_bug_0", + "pin_number": 8, + "port_hints": [ + "8", + "8" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_7", + "source_port_id": "source_port_7", + "center": { + "x": 0.75, + "y": 0 + }, + "facing_direction": "right", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_7", + "schematic_text_id": "schematic_text_17", + "text": "8", + "anchor": "center", + "rotation": 0, + "position": { + "x": 0.6262563132923542, + "y": -0.12374368670764582 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_7", + "source_port_id": "source_port_7", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": 2.125, + "y": 0.625, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "9", + "source_port_id": "source_port_8", + "source_component_id": "simple_bug_0", + "pin_number": 9, + "port_hints": [ + "9", + "9" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_8", + "source_port_id": "source_port_8", + "center": { + "x": 0.75, + "y": 0.5 + }, + "facing_direction": "right", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_8", + "schematic_text_id": "schematic_text_18", + "text": "9", + "anchor": "center", + "rotation": 0, + "position": { + "x": 0.6262563132923542, + "y": 0.3762563132923542 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_8", + "source_port_id": "source_port_8", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": 0.125, + "y": 2.125, + "layers": [ + "top" + ] + }, + { + "type": "source_port", + "name": "10", + "source_port_id": "source_port_9", + "source_component_id": "simple_bug_0", + "pin_number": 10, + "port_hints": [ + "10", + "10" + ] + }, + { + "type": "schematic_port", + "schematic_port_id": "schematic_port_9", + "source_port_id": "source_port_9", + "center": { + "x": 0.75, + "y": 1 + }, + "facing_direction": "right", + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "schematic_text", + "schematic_port_id": "schematic_port_9", + "schematic_text_id": "schematic_text_19", + "text": "10", + "anchor": "center", + "rotation": 0, + "position": { + "x": 0.6262563132923542, + "y": 0.8762563132923542 + }, + "schematic_component_id": "schematic_component_simple_bug_0" + }, + { + "type": "pcb_port", + "pcb_port_id": "pcb_port_9", + "source_port_id": "source_port_9", + "pcb_component_id": "pcb_component_simple_bug_0", + "x": -0.375, + "y": 2.125, + "layers": [ + "top" + ] + }, + { + "type": "schematic_text", + "schematic_text_id": "schematic_text_0", + "schematic_component_id": "schematic_component_simple_bug_0", + "text": "1", + "anchor": "left", + "rotation": 0, + "position": { + "x": -0.35, + "y": 1 + } + }, + { + "type": "schematic_text", + "schematic_text_id": "schematic_text_1", + "schematic_component_id": "schematic_component_simple_bug_0", + "text": "2", + "anchor": "left", + "rotation": 0, + "position": { + "x": -0.35, + "y": 0.5 + } + }, + { + "type": "schematic_text", + "schematic_text_id": "schematic_text_2", + "schematic_component_id": "schematic_component_simple_bug_0", + "text": "3", + "anchor": "left", + "rotation": 0, + "position": { + "x": -0.35, + "y": 0 + } + }, + { + "type": "schematic_text", + "schematic_text_id": "schematic_text_3", + "schematic_component_id": "schematic_component_simple_bug_0", + "text": "4", + "anchor": "left", + "rotation": 0, + "position": { + "x": -0.35, + "y": -0.5 + } + }, + { + "type": "schematic_text", + "schematic_text_id": "schematic_text_4", + "schematic_component_id": "schematic_component_simple_bug_0", + "text": "5", + "anchor": "left", + "rotation": 0, + "position": { + "x": -0.35, + "y": -1 + } + }, + { + "type": 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"pcb_component_id": "pcb_component_simple_bug_1", + "pcb_silkscreen_path_id": "pcb_silkscreen_path_0", + "route": [ + { + "x": 6.007719371572277, + "y": 4.780964200959524 + }, + { + "x": 6.007719371572277, + "y": 7.330964200959524 + }, + { + "x": 7.3077193715722775, + "y": 7.330964200959524 + }, + { + "x": 7.357197675439941, + "y": 7.082219969922216 + }, + { + "x": 7.498099963801021, + "y": 6.8713447931882685 + }, + { + "x": 7.708975140534968, + "y": 6.730442504827188 + }, + { + "x": 7.957719371572277, + "y": 6.680964200959524 + }, + { + "x": 8.206463602609585, + "y": 6.730442504827188 + }, + { + "x": 8.417338779343533, + "y": 6.8713447931882685 + }, + { + "x": 8.558241067704614, + "y": 7.082219969922216 + }, + { + "x": 8.607719371572276, + "y": 7.330964200959524 + }, + { + "x": 9.907719371572277, + "y": 7.330964200959524 + }, + { + "x": 9.907719371572277, + "y": 4.780964200959524 + }, + { + "x": 6.007719371572277, + "y": 4.780964200959524 + } + ], + "stroke_width": 0.1 + }, + { + "type": "source_trace", + "source_trace_id": "source_trace_0", + "connected_source_port_ids": [ + "source_port_2", + "source_port_14" + ], + "connected_source_net_ids": [] + }, + { + "type": "schematic_trace", + "source_trace_id": "source_trace_0", + "schematic_trace_id": "schematic_trace_0", + "edges": [ + { + "from": { + "x": -1.1, + "y": 0.10000000000000009 + }, + "to": { + "x": -1.1, + "y": -1.3 + } + }, + { + "from": { + "x": -1.1, + "y": -1.3 + }, + "to": { + "x": 1, + "y": -1.3 + } + }, + { + "from": { + "x": 1, + "y": -1.3 + }, + "to": { + "x": 1, + "y": -0.8 + } + }, + { + "from": { + "x": -0.75, + "y": 0, + "ti": 0 + }, + "to": { + "x": -1.1, + "y": 0.10000000000000009 + } + }, + { + "from": { + "x": 0.75, + "y": -0.75, + "ti": 1 + }, + "to": { + "x": 1, + "y": -0.8 + } + } + ] + }, + { + "type": "pcb_trace", + "pcb_trace_id": "pcb_trace_0", + "source_trace_id": "source_trace_0", + "route": [ + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": -2.1000000000000005, + "y": -0.6000000000000001 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": -1.6000000000000005, + "y": -0.6000000000000001 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": -1.5000000000000004, + "y": -0.5 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": -1.5, + "y": -0.5 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": -0.5, + "y": 0.5 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 0.5, + "y": 0.5 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 1, + "y": 1 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 4.5, + "y": 1 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 7.5, + "y": 4 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 8.5, + "y": 4 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 9.5, + "y": 5 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 9.5, + "y": 5 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 10.2, + "y": 5 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 10.3, + "y": 5.1 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 10.5, + "y": 5.1 + } + ] + }, + { + "type": "source_trace", + "source_trace_id": "source_trace_1", + "connected_source_port_ids": [ + "source_port_5", + "source_port_15" + ], + "connected_source_net_ids": [] + }, + { + "type": "schematic_trace", + "source_trace_id": "source_trace_1", + "schematic_trace_id": "schematic_trace_1", + "edges": [ + { + "from": { + "x": 1.1, + "y": -0.2999999999999998 + }, + "to": { + "x": 1.1, + "y": -1 + } + }, + { + "from": { + "x": 0.75, + "y": -1, + "ti": 0 + }, + "to": { + "x": 1.1, + "y": -1 + } + }, + { + "from": { + "x": 0.75, + "y": -0.25, + "ti": 1 + }, + "to": { + "x": 1.1, + "y": -0.2999999999999998 + } + } + ] + }, + { + "type": "pcb_trace", + "pcb_trace_id": "pcb_trace_1", + "source_trace_id": "source_trace_1", + "route": [ + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 2.1, + "y": -0.40000000000000036 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 2.8000000000000003, + "y": -0.40000000000000036 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 2.8000000000000003, + "y": -0.40000000000000036 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 5.4, + "y": 2.2 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 5.6000000000000005, + "y": 2.2 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 6.4, + "y": 3 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 7.000000000000001, + "y": 3 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 9.6, + "y": 5.6 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 10.4, + "y": 5.6 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 10.4, + "y": 5.6 + }, + { + "route_type": "wire", + "layer": "top", + "width": 0.05, + "x": 10.5, + "y": 5.7 + } + ] + }, + { + "type": "pcb_board", + "center": { + "x": 0, + "y": 0 + }, + "width": 10, + "height": 10 + } +] \ No newline at end of file diff --git a/tests/lib/check-each-pcb-trace-non-overlapping/overlapping-bug-traces1.test.ts b/tests/lib/check-each-pcb-trace-non-overlapping/overlapping-bug-traces1.test.ts new file mode 100644 index 0000000..975c8ba --- /dev/null +++ b/tests/lib/check-each-pcb-trace-non-overlapping/overlapping-bug-traces1.test.ts @@ -0,0 +1,12 @@ +import { expect, test, describe } from "bun:test" +import { checkEachPcbTraceNonOverlapping } from "lib/check-each-pcb-trace-non-overlapping" +import type { AnySoupElement, PCBTrace, PCBSMTPad } from "@tscircuit/soup" +import traces1 from "tests/assets/traces1.solution.json" + +describe("checkEachPcbTraceNonOverlapping", () => { + test("should return no errors when traces don't overlap", () => { + const soup: AnySoupElement[] = traces1 as any + + expect(checkEachPcbTraceNonOverlapping(soup)).toHaveLength(1) + }) +}) From 110ea26900ddec83d44613656b1f24b2bcb0771a Mon Sep 17 00:00:00 2001 From: tscircuitbot Date: Wed, 24 Jul 2024 20:34:00 +0000 Subject: [PATCH 2/3] formatbot: Automatically format code --- package-lock.json | 31 +++- package.json | 4 +- tests/assets/traces1.solution.json | 246 +++++++---------------------- 3 files changed, 84 insertions(+), 197 deletions(-) diff --git a/package-lock.json b/package-lock.json index 4e1621d..2d66602 100644 --- a/package-lock.json +++ b/package-lock.json @@ -1,21 +1,25 @@ { "name": "@tscircuit/checks", - "version": "0.0.1", + "version": "0.0.10", "lockfileVersion": 3, "requires": true, "packages": { "": { "name": "@tscircuit/checks", - "version": "0.0.1", + "version": "0.0.10", "devDependencies": { "@biomejs/biome": "^1.8.3", "@tscircuit/log-soup": "^1.0.2", "@tscircuit/soup": "^0.0.40", "@tscircuit/soup-util": "^0.0.13", "@types/bun": "latest", - "tsup": "^8.2.1" + "@types/debug": "^4.1.12", + "debug": "^4.3.5", + "tsup": "^8.2.3" }, "peerDependencies": { + "@tscircuit/soup": "*", + "@tscircuit/soup-util": "*", "typescript": "^5.5.3" } }, @@ -918,12 +922,27 @@ "bun-types": "1.1.17" } }, + "node_modules/@types/debug": { + "version": "4.1.12", + "resolved": "https://registry.npmjs.org/@types/debug/-/debug-4.1.12.tgz", + "integrity": "sha512-vIChWdVG3LG1SMxEvI/AK+FWJthlrqlTu7fbrlywTkkaONwk/UAGaULXRlf8vkzFBLVm0zkMdCquhL5aOjhXPQ==", + "dev": true, + "dependencies": { + "@types/ms": "*" + } + }, "node_modules/@types/estree": { "version": "1.0.5", "resolved": "https://registry.npmjs.org/@types/estree/-/estree-1.0.5.tgz", "integrity": "sha512-/kYRxGDLWzHOB7q+wtSUQlFrtcdUccpfy+X+9iMBpHK8QLLhx2wIPYuS5DYtR9Wa/YlZAbIovy7qVdB1Aq6Lyw==", "dev": true }, + "node_modules/@types/ms": { + "version": "0.7.34", + "resolved": "https://registry.npmjs.org/@types/ms/-/ms-0.7.34.tgz", + "integrity": "sha512-nG96G3Wp6acyAgJqGasjODb+acrI7KltPiRxzHPXnP3NgI28bpQDRv53olbqGXbfcgF5aiiHmO3xpwEpS5Ld9g==", + "dev": true + }, "node_modules/@types/node": { "version": "20.12.14", "resolved": "https://registry.npmjs.org/@types/node/-/node-20.12.14.tgz", @@ -2325,9 +2344,9 @@ "dev": true }, "node_modules/tsup": { - "version": "8.2.2", - "resolved": "https://registry.npmjs.org/tsup/-/tsup-8.2.2.tgz", - "integrity": "sha512-MufIuzdSt6HYPOeOtjUXLR4rqRJySi6XsRNZdwvjC2XR+xghsu2L3vSmYmX+k4S1mO6j0OlUEyVQ3Fc0H66XcA==", + "version": "8.2.3", + "resolved": "https://registry.npmjs.org/tsup/-/tsup-8.2.3.tgz", + "integrity": "sha512-6YNT44oUfXRbZuSMNmN36GzwPPIlD2wBccY7looM2fkTcxkf2NEmwr3OZuDZoySklnrIG4hoEtzy8yUXYOqNcg==", "dev": true, "dependencies": { "bundle-require": "^5.0.0", diff --git a/package.json b/package.json index 7a99f36..f22b44e 100644 --- a/package.json +++ b/package.json @@ -23,8 +23,8 @@ "tsup": "^8.2.3" }, "peerDependencies": { - "typescript": "^5.5.3", "@tscircuit/soup": "*", - "@tscircuit/soup-util": "*" + "@tscircuit/soup-util": "*", + "typescript": "^5.5.3" } } diff --git a/tests/assets/traces1.solution.json b/tests/assets/traces1.solution.json index 12ab1ed..23316c0 100644 --- a/tests/assets/traces1.solution.json +++ b/tests/assets/traces1.solution.json @@ -28,10 +28,7 @@ "source_port_id": "source_port_0", "source_component_id": "simple_bug_0", "pin_number": 1, - "port_hints": [ - "1", - "1" - ] + "port_hints": ["1", "1"] }, { "type": "schematic_port", @@ -64,9 +61,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": -2.125, "y": 0.375, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -74,10 +69,7 @@ "source_port_id": "source_port_1", "source_component_id": "simple_bug_0", "pin_number": 2, - "port_hints": [ - "2", - "2" - ] + "port_hints": ["2", "2"] }, { "type": "schematic_port", @@ -110,9 +102,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": -2.125, "y": -0.125, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -120,10 +110,7 @@ "source_port_id": "source_port_2", "source_component_id": "simple_bug_0", "pin_number": 3, - "port_hints": [ - "3", - "3" - ] + "port_hints": ["3", "3"] }, { "type": "schematic_port", @@ -156,9 +143,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": -2.125, "y": -0.625, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -166,10 +151,7 @@ "source_port_id": "source_port_3", "source_component_id": "simple_bug_0", "pin_number": 4, - "port_hints": [ - "4", - "4" - ] + "port_hints": ["4", "4"] }, { "type": "schematic_port", @@ -202,9 +184,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": -0.125, "y": -2.125, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -212,10 +192,7 @@ "source_port_id": "source_port_4", "source_component_id": "simple_bug_0", "pin_number": 5, - "port_hints": [ - "5", - "5" - ] + "port_hints": ["5", "5"] }, { "type": "schematic_port", @@ -248,9 +225,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": 0.375, "y": -2.125, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -258,10 +233,7 @@ "source_port_id": "source_port_5", "source_component_id": "simple_bug_0", "pin_number": 6, - "port_hints": [ - "6", - "6" - ] + "port_hints": ["6", "6"] }, { "type": "schematic_port", @@ -294,9 +266,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": 2.125, "y": -0.375, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -304,10 +274,7 @@ "source_port_id": "source_port_6", "source_component_id": "simple_bug_0", "pin_number": 7, - "port_hints": [ - "7", - "7" - ] + "port_hints": ["7", "7"] }, { "type": "schematic_port", @@ -340,9 +307,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": 2.125, "y": 0.125, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -350,10 +315,7 @@ "source_port_id": "source_port_7", "source_component_id": "simple_bug_0", "pin_number": 8, - "port_hints": [ - "8", - "8" - ] + "port_hints": ["8", "8"] }, { "type": "schematic_port", @@ -386,9 +348,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": 2.125, "y": 0.625, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -396,10 +356,7 @@ "source_port_id": "source_port_8", "source_component_id": "simple_bug_0", "pin_number": 9, - "port_hints": [ - "9", - "9" - ] + "port_hints": ["9", "9"] }, { "type": "schematic_port", @@ -432,9 +389,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": 0.125, "y": 2.125, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -442,10 +397,7 @@ "source_port_id": "source_port_9", "source_component_id": "simple_bug_0", "pin_number": 10, - "port_hints": [ - "10", - "10" - ] + "port_hints": ["10", "10"] }, { "type": "schematic_port", @@ -478,9 +430,7 @@ "pcb_component_id": "pcb_component_simple_bug_0", "x": -0.375, "y": 2.125, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "schematic_text", @@ -625,9 +575,7 @@ "height": 0.25, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "1" - ], + "port_hints": ["1"], "pcb_port_id": "pcb_port_0" }, { @@ -640,9 +588,7 @@ "height": 0.25, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "2" - ], + "port_hints": ["2"], "pcb_port_id": "pcb_port_1" }, { @@ -655,9 +601,7 @@ "height": 0.25, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "3" - ], + "port_hints": ["3"], "pcb_port_id": "pcb_port_2" }, { @@ -670,9 +614,7 @@ "height": 1, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "4" - ], + "port_hints": ["4"], "pcb_port_id": "pcb_port_3" }, { @@ -685,9 +627,7 @@ "height": 1, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "5" - ], + "port_hints": ["5"], "pcb_port_id": "pcb_port_4" }, { @@ -700,9 +640,7 @@ "height": 0.25, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "6" - ], + "port_hints": ["6"], "pcb_port_id": "pcb_port_5" }, { @@ -715,9 +653,7 @@ "height": 0.25, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "7" - ], + "port_hints": ["7"], "pcb_port_id": "pcb_port_6" }, { @@ -730,9 +666,7 @@ "height": 0.25, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "8" - ], + "port_hints": ["8"], "pcb_port_id": "pcb_port_7" }, { @@ -745,9 +679,7 @@ "height": 1, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "9" - ], + "port_hints": ["9"], "pcb_port_id": "pcb_port_8" }, { @@ -760,9 +692,7 @@ "height": 1, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_0", - "port_hints": [ - "10" - ], + "port_hints": ["10"], "pcb_port_id": "pcb_port_9" }, { @@ -903,10 +833,7 @@ "source_port_id": "source_port_10", "source_component_id": "simple_bug_1", "pin_number": 1, - "port_hints": [ - "1", - "1" - ] + "port_hints": ["1", "1"] }, { "type": "schematic_port", @@ -939,9 +866,7 @@ "pcb_component_id": "pcb_component_simple_bug_1", "x": 5.407719371572277, "y": 7.030964200959524, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -949,10 +874,7 @@ "source_port_id": "source_port_11", "source_component_id": "simple_bug_1", "pin_number": 2, - "port_hints": [ - "2", - "2" - ] + "port_hints": ["2", "2"] }, { "type": "schematic_port", @@ -985,9 +907,7 @@ "pcb_component_id": "pcb_component_simple_bug_1", "x": 5.407719371572277, "y": 6.380964200959524, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -995,10 +915,7 @@ "source_port_id": "source_port_12", "source_component_id": "simple_bug_1", "pin_number": 3, - "port_hints": [ - "3", - "3" - ] + "port_hints": ["3", "3"] }, { "type": "schematic_port", @@ -1031,9 +948,7 @@ "pcb_component_id": "pcb_component_simple_bug_1", "x": 5.407719371572277, "y": 5.730964200959524, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -1041,10 +956,7 @@ "source_port_id": "source_port_13", "source_component_id": "simple_bug_1", "pin_number": 4, - "port_hints": [ - "4", - "4" - ] + "port_hints": ["4", "4"] }, { "type": "schematic_port", @@ -1077,9 +989,7 @@ "pcb_component_id": "pcb_component_simple_bug_1", "x": 5.407719371572277, "y": 5.080964200959524, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -1087,10 +997,7 @@ "source_port_id": "source_port_14", "source_component_id": "simple_bug_1", "pin_number": 5, - "port_hints": [ - "5", - "5" - ] + "port_hints": ["5", "5"] }, { "type": "schematic_port", @@ -1123,9 +1030,7 @@ "pcb_component_id": "pcb_component_simple_bug_1", "x": 10.507719371572277, "y": 5.080964200959524, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -1133,10 +1038,7 @@ "source_port_id": "source_port_15", "source_component_id": "simple_bug_1", "pin_number": 6, - "port_hints": [ - "6", - "6" - ] + "port_hints": ["6", "6"] }, { "type": "schematic_port", @@ -1169,9 +1071,7 @@ "pcb_component_id": "pcb_component_simple_bug_1", "x": 10.507719371572277, "y": 5.730964200959524, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -1179,10 +1079,7 @@ "source_port_id": "source_port_16", "source_component_id": "simple_bug_1", "pin_number": 7, - "port_hints": [ - "7", - "7" - ] + "port_hints": ["7", "7"] }, { "type": "schematic_port", @@ -1215,9 +1112,7 @@ "pcb_component_id": "pcb_component_simple_bug_1", "x": 10.507719371572277, "y": 6.380964200959524, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "source_port", @@ -1225,10 +1120,7 @@ "source_port_id": "source_port_17", "source_component_id": "simple_bug_1", "pin_number": 8, - "port_hints": [ - "8", - "8" - ] + "port_hints": ["8", "8"] }, { "type": "schematic_port", @@ -1261,9 +1153,7 @@ "pcb_component_id": "pcb_component_simple_bug_1", "x": 10.507719371572277, "y": 7.030964200959524, - "layers": [ - "top" - ] + "layers": ["top"] }, { "type": "schematic_text", @@ -1384,9 +1274,7 @@ "height": 0.6, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_1", - "port_hints": [ - "1" - ], + "port_hints": ["1"], "pcb_port_id": "pcb_port_10" }, { @@ -1399,9 +1287,7 @@ "height": 0.6, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_1", - "port_hints": [ - "2" - ], + "port_hints": ["2"], "pcb_port_id": "pcb_port_11" }, { @@ -1414,9 +1300,7 @@ "height": 0.6, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_1", - "port_hints": [ - "3" - ], + "port_hints": ["3"], "pcb_port_id": "pcb_port_12" }, { @@ -1429,9 +1313,7 @@ "height": 0.6, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_1", - "port_hints": [ - "4" - ], + "port_hints": ["4"], "pcb_port_id": "pcb_port_13" }, { @@ -1444,9 +1326,7 @@ "height": 0.6, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_1", - "port_hints": [ - "5" - ], + "port_hints": ["5"], "pcb_port_id": "pcb_port_14" }, { @@ -1459,9 +1339,7 @@ "height": 0.6, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_1", - "port_hints": [ - "6" - ], + "port_hints": ["6"], "pcb_port_id": "pcb_port_15" }, { @@ -1474,9 +1352,7 @@ "height": 0.6, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_1", - "port_hints": [ - "7" - ], + "port_hints": ["7"], "pcb_port_id": "pcb_port_16" }, { @@ -1489,9 +1365,7 @@ "height": 0.6, "layer": "top", "pcb_component_id": "pcb_component_simple_bug_1", - "port_hints": [ - "8" - ], + "port_hints": ["8"], "pcb_port_id": "pcb_port_17" }, { @@ -1562,10 +1436,7 @@ { "type": "source_trace", "source_trace_id": "source_trace_0", - "connected_source_port_ids": [ - "source_port_2", - "source_port_14" - ], + "connected_source_port_ids": ["source_port_2", "source_port_14"], "connected_source_net_ids": [] }, { @@ -1742,10 +1613,7 @@ { "type": "source_trace", "source_trace_id": "source_trace_1", - "connected_source_port_ids": [ - "source_port_5", - "source_port_15" - ], + "connected_source_port_ids": ["source_port_5", "source_port_15"], "connected_source_net_ids": [] }, { @@ -1880,4 +1748,4 @@ "width": 10, "height": 10 } -] \ No newline at end of file +] From 97f16648189e6c3be6be0051fe6b02c32ae9c281 Mon Sep 17 00:00:00 2001 From: seveibar Date: Wed, 24 Jul 2024 13:36:26 -0700 Subject: [PATCH 3/3] update traces2 test --- .../overlapping-bug-traces2.test.ts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/lib/check-each-pcb-trace-non-overlapping/overlapping-bug-traces2.test.ts b/tests/lib/check-each-pcb-trace-non-overlapping/overlapping-bug-traces2.test.ts index 6fecaa7..3fb5ddb 100644 --- a/tests/lib/check-each-pcb-trace-non-overlapping/overlapping-bug-traces2.test.ts +++ b/tests/lib/check-each-pcb-trace-non-overlapping/overlapping-bug-traces2.test.ts @@ -7,6 +7,6 @@ describe("checkEachPcbTraceNonOverlapping", () => { test("should return no errors when traces don't overlap", () => { const soup: AnySoupElement[] = traces2 as any - expect(checkEachPcbTraceNonOverlapping(soup)).toHaveLength(4) + expect(checkEachPcbTraceNonOverlapping(soup)).toHaveLength(1) }) })