From 3ef2dd48fe995cadce53016350b3d59861afbdf5 Mon Sep 17 00:00:00 2001
From: seveibar <seveibar@gmail.com>
Date: Mon, 30 Sep 2024 20:27:40 -0700
Subject: [PATCH] add errors when there's a missing footprint

---
 lib/components/primitive-components/Port.ts   |  4 ++
 lib/components/primitive-components/Trace.ts  | 22 +++++++
 tests/examples/example4-kicad.test.tsx        | 51 +++++++++++++++
 .../repros/repro2-capacitor-pin-bug.test.tsx  | 64 +++++++++++++++++++
 4 files changed, 141 insertions(+)
 create mode 100644 tests/examples/example4-kicad.test.tsx
 create mode 100644 tests/repros/repro2-capacitor-pin-bug.test.tsx

diff --git a/lib/components/primitive-components/Port.ts b/lib/components/primitive-components/Port.ts
index f2e1997..6e39daa 100644
--- a/lib/components/primitive-components/Port.ts
+++ b/lib/components/primitive-components/Port.ts
@@ -249,4 +249,8 @@ export class Port extends PrimitiveComponent<typeof portProps> {
       y: newCenter.y,
     })
   }
+
+  _hasMatchedPcbPrimitive() {
+    return this.matchedComponents.some((c) => c.isPcbPrimitive)
+  }
 }
diff --git a/lib/components/primitive-components/Trace.ts b/lib/components/primitive-components/Trace.ts
index c37eded..9d0ecec 100644
--- a/lib/components/primitive-components/Trace.ts
+++ b/lib/components/primitive-components/Trace.ts
@@ -41,6 +41,7 @@ import {
 } from "lib/utils/selector-matching"
 import { tryNow } from "lib/utils/try-now"
 import { getFullConnectivityMapFromCircuitJson } from "circuit-json-to-connectivity-map"
+import type { Renderable } from "../base-components/Renderable"
 
 type PcbRouteObjective =
   | RouteHintPoint
@@ -270,6 +271,27 @@ export class Trace extends PrimitiveComponent<typeof traceProps> {
 
     if (!allPortsFound) return
 
+    const portsWithoutMatchedPcbPrimitive: Port[] = []
+    for (const port of ports) {
+      if (!port._hasMatchedPcbPrimitive()) {
+        portsWithoutMatchedPcbPrimitive.push(port)
+      }
+    }
+
+    if (portsWithoutMatchedPcbPrimitive.length > 0) {
+      db.pcb_trace_error.insert({
+        error_type: "pcb_trace_error",
+        source_trace_id: this.source_trace_id!,
+        message: `Some ports did not have a matching PCB primitive (e.g. a pad or plated hole), this can happen if a footprint is missing. As a result, ${this} wasn't routed. Missing ports: ${portsWithoutMatchedPcbPrimitive.map((p) => p.getString()).join(", ")}`,
+        pcb_trace_id: this.pcb_trace_id!,
+        pcb_component_ids: [],
+        pcb_port_ids: portsWithoutMatchedPcbPrimitive
+          .map((p) => p.pcb_port_id!)
+          .filter(Boolean),
+      })
+      return
+    }
+
     const nets = this._findConnectedNets().netsWithSelectors
 
     if (ports.length === 0 && nets.length === 2) {
diff --git a/tests/examples/example4-kicad.test.tsx b/tests/examples/example4-kicad.test.tsx
new file mode 100644
index 0000000..3af19f8
--- /dev/null
+++ b/tests/examples/example4-kicad.test.tsx
@@ -0,0 +1,51 @@
+import { it, expect } from "bun:test"
+import { getTestFixture } from "tests/fixtures/get-test-fixture"
+
+it("example 4: kicad theme demo", async () => {
+  const { project, logSoup } = getTestFixture()
+
+  project.add(
+    <board width="10mm" height="10mm">
+      <resistor
+        name="R1"
+        resistance="10k"
+        footprint="0402"
+        pcbX={-2}
+        schX={-2}
+      />
+      <capacitor
+        capacitance={"10"}
+        name="LED1"
+        footprint="0402"
+        pcbX={2}
+        schX={2}
+      />
+      <trace from=".R1 > .pin2" to=".LED1 > .anode" />
+
+      <chip
+        name="U2"
+        manufacturerPartNumber="ATmega8-16A"
+        schX={5}
+        schPinStyle={{
+          pin29: { bottomMargin: 0.5 },
+        }}
+        schPortArrangement={{
+          leftSide: {
+            pins: [29, 7, 8, 20, 19, 22],
+            direction: "top-to-bottom",
+          },
+          topSide: {
+            direction: "left-to-right",
+            pins: [4, 18],
+          },
+          rightSide: {
+            direction: "bottom-to-top",
+            pins: [12, 13, 14, 15, 16, 17, 23],
+          },
+        }}
+      />
+    </board>,
+  )
+
+  project.render()
+})
diff --git a/tests/repros/repro2-capacitor-pin-bug.test.tsx b/tests/repros/repro2-capacitor-pin-bug.test.tsx
new file mode 100644
index 0000000..5a425bc
--- /dev/null
+++ b/tests/repros/repro2-capacitor-pin-bug.test.tsx
@@ -0,0 +1,64 @@
+import { expect, test } from "bun:test"
+import { getTestFixture } from "tests/fixtures/get-test-fixture"
+
+test("capacitor connection not working", async () => {
+  const { circuit } = getTestFixture()
+
+  const BlinkingLedWith555Timer = () => (
+    <board width="40mm" height="30mm">
+      <chip
+        name="U1"
+        footprint="dip8_p1.27mm"
+        pcbX="-10mm"
+        pcbY="0mm"
+        pinLabels={{
+          1: "GND",
+          2: "TRIG",
+          3: "OUT",
+          4: "RESET",
+          5: "CTRL",
+          6: "THRES",
+          7: "DISCH",
+          8: "VCC",
+        }}
+      />
+      <led name="LED1" pcbX="10mm" pcbY="5mm" footprint="0603" />
+      <resistor
+        name="R1"
+        pcbX="-5mm"
+        pcbY="-5mm"
+        resistance="1k"
+        footprint="0603"
+      />
+      <resistor
+        name="R2"
+        pcbX="5mm"
+        pcbY="-5mm"
+        resistance="470"
+        footprint="0603"
+      />
+      <capacitor name="C1" pcbX="10mm" pcbY="-5mm" capacitance="100nF" />
+
+      <trace from=".U1 .VCC" to="net.VCC" />
+      <trace from=".U1 .GND" to="net.GND" />
+      <trace from="net.VCC" to=".R1 .pin1" />
+      <trace from=".R1 .pin2" to=".U1 .DISCH" />
+      <trace from=".U1 .DISCH" to=".R2 .pin1" />
+      <trace from=".R2 .pin2" to=".LED1 .pin1" />
+      <trace from=".LED1 .pin2" to="net.GND" />
+      <trace from=".U1 .OUT" to=".C1 .pin1" />
+      <trace from=".C1 .pin2" to=".U1 .CTRL" />
+      <trace from=".U1 .THRES" to=".U1 .CTRL" />
+    </board>
+  )
+
+  circuit.add(<BlinkingLedWith555Timer />)
+
+  circuit.render()
+
+  const errors = circuit.db.pcb_trace_error.list()
+
+  expect(errors.map((e) => e.message).join("\n\n")).toContain(
+    "Some ports did not have a matching PCB primitive",
+  )
+})