diff --git a/.gitattributes b/.gitattributes index ed4e0201e..cff0700cc 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1,8 +1,18 @@ text=auto +# Image files *.png filter=lfs diff=lfs merge=lfs -text +# Model files *.dae filter=lfs diff=lfs merge=lfs -text -*.blend filter=lfs diff=lfs merge=lfs -text *.stl filter=lfs diff=lfs merge=lfs -text +*.blend filter=lfs diff=lfs merge=lfs -text +# Neural network files +*.pt filter=lfs diff=lfs merge=lfs -text +*.onnx filter=lfs diff=lfs merge=lfs -text +*.engine filter=lfs diff=lfs merge=lfs -text +# Model files *.glb filter=lfs diff=lfs merge=lfs -text *.fbx filter=lfs diff=lfs merge=lfs -text +# Packages +*.deb filter=lfs diff=lfs merge=lfs -text +# Program files ansible/roles/esw/files/bin/fdcanusb_daemon filter=lfs diff=lfs merge=lfs -text diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 53cadecc9..fe8490c2e 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -3,6 +3,7 @@ on: pull_request: branches: - master + - integration push: branches: - master @@ -22,7 +23,7 @@ jobs: # This makes sure that $GITHUB_WORKSPACE is the catkin workspace path path: "src/mrover" - name: Ensure Python Requirements - run: . /home/mrover/catkin_ws/src/mrover/venv/bin/activate && pip install -e "$GITHUB_WORKSPACE/src/mrover[dev]" + run: . /home/mrover/catkin_ws/src/mrover/venv/bin/activate && pip install --no-cache-dir -e "$GITHUB_WORKSPACE/src/mrover[dev]" - name: Style Check run: . /home/mrover/catkin_ws/src/mrover/venv/bin/activate && cd $GITHUB_WORKSPACE/src/mrover/ && ./style.sh - name: Update ROS APT @@ -37,9 +38,12 @@ jobs: - name: Initialize if: github.event.pull_request.draft == false run: . /opt/ros/noetic/setup.sh && catkin init && catkin profile set ci - - name: Build - if: github.event.pull_request.draft == false + - name: Build Without Clang Tidy + if: github.event.pull_request.draft == false && github.event.pull_request.base.ref != 'refs/heads/master' run: . /opt/ros/noetic/setup.sh && . /home/mrover/catkin_ws/src/mrover/venv/bin/activate && catkin build + - name: Build With Clang Tidy + if : github.event_name == 'push' && github.event.pull_request.base.ref == 'refs/heads/master' + run: . /opt/ros/noetic/setup.sh && . /home/mrover/catkin_ws/src/mrover/venv/bin/activate && catkin build -DCMAKE_CXX_CLANG_TIDY=clang-tidy-16 - name: Test if: github.event.pull_request.draft == false - run: . /opt/ros/noetic/setup.sh && . /home/mrover/catkin_ws/src/mrover/venv/bin/activate && . $GITHUB_WORKSPACE/devel/setup.sh && catkin test -j1 + run: . /opt/ros/noetic/setup.sh && . /home/mrover/catkin_ws/src/mrover/venv/bin/activate && . $GITHUB_WORKSPACE/devel/setup.sh && catkin test && rostest mrover integration.test --text diff --git a/.gitignore b/.gitignore index 6ace9c35d..6e0165744 100644 --- a/.gitignore +++ b/.gitignore @@ -21,6 +21,7 @@ yarn.lock* yarn-error.log* bun.lock* package-lock.json* +db.sqlite3 # Bag Files /bags/ diff --git a/.gitmodules b/.gitmodules index cbd3669a1..4416faa01 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,20 @@ [submodule "deps/libde265"] path = deps/libde265 - url = git@github.com:strukturag/libde265.git + url = https://github.com/strukturag/libde265.git shallow = true + branch = v1.0.15 [submodule "deps/dawn"] path = deps/dawn url = https://dawn.googlesource.com/dawn shallow = true branch = chromium/6108 +[submodule "deps/emsdk"] + path = deps/emsdk + url = git@github.com:emscripten-core/emsdk.git + shallow = true + branch = 3.1.53 +[submodule "deps/manif"] + path = deps/manif + url = https://github.com/artivis/manif.git + shallow = true + branch = devel diff --git a/.vscode/settings.json b/.vscode/settings.json index 38c24f766..d452b4721 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -33,7 +33,6 @@ "python.analysis.typeCheckingMode": "off", //// Miscellaneous "redhat.telemetry.enabled": false, - "editor.formatOnSave": true, "git.ignoreSubmodules": true, "git.detectSubmodules": false, "cSpell.words": [ @@ -41,4 +40,14 @@ "GLFW", "wgpu" ], + "search.exclude": { + "**/node_modules": true, + "**/bower_components": true, + "**/*.code-search": true, + "deps/dawn": true, + }, + "python.autoComplete.extraPaths": [ + "/home/eric/catkin_ws/devel/lib/python3/dist-packages", + "/opt/ros/noetic/lib/python3/dist-packages" + ] } \ No newline at end of file diff --git a/CMakeLists.txt b/CMakeLists.txt index f73623bf0..ac179ac15 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,6 +1,18 @@ cmake_minimum_required(VERSION 3.16) project(mrover VERSION 2024.0.0 LANGUAGES CXX) +option(MROVER_IS_CI "Build for CI" OFF) +option(MROVER_RUN_CLANG_TIDY "Run clang-tidy" OFF) +option(MROVER_IS_JETSON "Build for the Jetson" OFF) + +set(CMAKE_CXX_STANDARD 23) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) # Generate compile_commands.json for clangd + +### ============= ### +### OS & Compiler ### +### ============= ### + if (APPLE) # Ensures that homebrew packages are never used over miniforge packages set(CMAKE_IGNORE_PATH /opt/homebrew) @@ -15,24 +27,29 @@ if (APPLE) link_libraries(fmt::fmt) else () # TODO(quintin): Fix this - find_package(TBB REQUIRED) - link_libraries(TBB::tbb) + find_package(TBB QUIET) + if (TBB_FOUND) + link_libraries(TBB::tbb) + endif () endif () -include_directories(BEFORE SYSTEM src/preload) +if (NOT APPLE AND CMAKE_CXX_COMPILER_ID STREQUAL "Clang") # Link with LLVM lld instead of GNU ld when using Clang on Linux, it is faster + add_link_options(-fuse-ld=lld) +endif () -set(CMAKE_CXX_STANDARD 23) -set(CMAKE_CXX_STANDARD_REQUIRED ON) -set(CMAKE_EXPORT_COMPILE_COMMANDS ON) # Generate compile_commands.json for clangd -if (NOT APPLE AND CMAKE_CXX_COMPILER_ID STREQUAL "Clang") - add_link_options(-fuse-ld=lld) # LLVM lld is faster than GNU ld +if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU" OR CMAKE_CXX_COMPILER_ID STREQUAL "Clang") + set(MROVER_CPP_COMPILE_OPTIONS -Wall -Wextra -pedantic -Wno-missing-field-initializers) + if (MROVER_IS_CI) # Make warnings errors in CI + list(APPEND MROVER_CPP_COMPILE_OPTIONS -Werror) + endif () endif () -set(MROVER_CPP_COMPILE_OPTIONS -Wall -Wextra -pedantic) -if (MROVER_CI) - list(APPEND MROVER_CPP_COMPILE_OPTIONS -Werror) + +if (MROVER_IS_JETSON) + add_definitions(-DMROVER_IS_JETSON) endif () -option(MROVER_BUILD_SIM "Build the simulator" ON) +# Inject header files that get included before anything else, including system headers +include_directories(BEFORE SYSTEM src/preload) include(cmake/macros.cmake) @@ -63,6 +80,7 @@ set(MROVER_MESSAGE_DEPENDENCIES set(MROVER_PARAMETERS config/DetectorParams.cfg + config/ObjectDetectorParams.cfg ) set(MROVER_CMAKE_INCLUDES @@ -73,29 +91,8 @@ set(MROVER_CMAKE_INCLUDES ### Dependencies ### ### ============ ### -if (MROVER_BUILD_SIM) - # Apparently Assimp has different names on different systems - # find_package is case-sensitive so try both - find_package(Assimp QUIET) - find_package(assimp QUIET) - if (NOT Assimp_FOUND AND NOT assimp_FOUND) - message(FATAL_ERROR "Assimp not found") - endif () - - find_package(Bullet REQUIRED) - - find_package(glfw3 REQUIRED) - - include(cmake/webgpu.cmake) +include(cmake/deps.cmake) - add_subdirectory(deps/glfw3webgpu) -endif () -find_package(OpenCV REQUIRED) -find_package(ZED QUIET) -find_package(Eigen3 REQUIRED) -find_package(PkgConfig REQUIRED) -pkg_search_module(NetLink libnl-3.0) -pkg_search_module(NetLinkRoute libnl-route-3.0) if (ZED_FOUND) # Anything newer than C++17 combined with libstdc++13 is not supported just yet by NVCC (the CUDA compiler) set(CMAKE_CUDA_STANDARD 17) @@ -142,20 +139,21 @@ catkin_package() ## Libraries mrover_add_library(lie src/util/lie/*.cpp src/util/lie) +target_link_libraries(lie PUBLIC MANIF::manif) ## ESW if (NOT APPLE) - mrover_add_vendor_header_only_library(moteus src/esw/mjbots) + mrover_add_vendor_header_only_library(moteus deps/mjbots) mrover_add_header_only_library(can_device src/esw/can_device) mrover_add_library(motor_library src/esw/motor_library/*.cpp src/esw/motor_library) target_link_libraries(motor_library PUBLIC can_device moteus) - mrover_add_nodelet(can_driver src/esw/can_driver/*.cpp src/esw/can_driver src/esw/can_driver/pch.hpp) - mrover_nodelet_link_libraries(can_driver nl-3 nl-route-3) - # TODO(quintin): Fix this CMake hard coding - #mrover_nodelet_link_libraries(can ${NetLink_LIBRARIES} ${NetLinkRoute_LIBRARIES}}) - mrover_nodelet_include_directories(can_driver /usr/include/libnl3) + if (NetLink_FOUND AND NetLinkRoute_FOUND) + mrover_add_nodelet(can_driver src/esw/can_driver/*.cpp src/esw/can_driver src/esw/can_driver/pch.hpp) + mrover_nodelet_link_libraries(can_driver ${NetLink_LIBRARIES} ${NetLinkRoute_LIBRARIES}) + mrover_nodelet_include_directories(can_driver ${NetLink_INCLUDE_DIRS} ${NetLinkRoute_INCLUDE_DIRS}) + endif () macro(mrover_add_esw_bridge_node name sources) mrover_add_node(${name} ${sources}) @@ -167,29 +165,55 @@ if (NOT APPLE) mrover_add_esw_bridge_node(cache_bridge src/esw/cache_bridge/*.cpp) mrover_add_esw_bridge_node(drive_bridge src/esw/drive_bridge/*.cpp) mrover_add_esw_bridge_node(led_hw_bridge src/esw/led_hw_bridge/*.cpp) + mrover_add_esw_bridge_node(led src/esw/led/*.cpp) mrover_add_esw_bridge_node(mast_gimbal_bridge src/esw/mast_gimbal_bridge/*.cpp) mrover_add_esw_bridge_node(pdb_bridge src/esw/pdb_bridge/*.cpp) - mrover_add_esw_bridge_node(sa_bridge src/esw/sa_bridge/*.cpp) + mrover_add_esw_bridge_node(sa_hw_bridge src/esw/sa_hw_bridge/*.cpp) + mrover_add_esw_bridge_node(sa_translator_bridge src/esw/sa_translator_bridge/*.cpp) mrover_add_esw_bridge_node(science_bridge src/esw/science_bridge/*.cpp) mrover_add_esw_bridge_node(brushless_test_bridge src/esw/brushless_test_bridge/*.cpp motor_library) mrover_add_esw_bridge_node(brushed_test_bridge src/esw/brushed_test_bridge/*.cpp) mrover_add_esw_bridge_node(test_arm_bridge src/esw/test_arm_bridge/*.cpp) + mrover_add_esw_bridge_node(pdb_test_bridge src/esw/pdb_test_bridge/*.cpp) + mrover_add_esw_bridge_node(arm_position_test_bridge src/esw/arm_position_test_bridge/*.cpp) + # mrover_add_esw_bridge_node(sa_sensor src/esw/fw/dirt_sensor/dirt_sensor_ros/dirt_sensor_ros.ino) endif () ## Perception -mrover_add_nodelet(tag_detector src/perception/tag_detector/*.cpp src/perception/tag_detector src/perception/tag_detector/pch.hpp) -mrover_nodelet_link_libraries(tag_detector opencv_core opencv_objdetect opencv_aruco opencv_imgproc opencv_highgui lie) +mrover_add_library(websocket_server src/esw/websocket_server/*.cpp src/esw/websocket_server) +target_compile_definitions(websocket_server PUBLIC BOOST_ASIO_NO_DEPRECATED) + +mrover_add_nodelet(zed_tag_detector src/perception/tag_detector/zed/*.cpp src/perception/tag_detector/zed src/perception/tag_detector/zed/pch.hpp) +mrover_nodelet_link_libraries(zed_tag_detector opencv_core opencv_objdetect opencv_aruco opencv_imgproc lie) + +mrover_add_nodelet(long_range_tag_detector src/perception/tag_detector/long_range_cam/*.cpp src/perception/tag_detector/long_range_cam src/perception/tag_detector/long_range_cam/pch.hpp) +mrover_nodelet_link_libraries(long_range_tag_detector opencv_core opencv_objdetect opencv_aruco opencv_imgproc lie) -# if (CUDA_FOUND) -# mrover_add_library(streaming src/esw/streaming/*.c* src/esw/streaming) -# # target_link_libraries(streaming PUBLIC opencv_core opencv_cudacodec) -# target_link_libraries(streaming PUBLIC cuda nvidia-encode opencv_core) -# target_include_directories(streaming SYSTEM PUBLIC deps/nvenc) -# target_compile_definitions(streaming PUBLIC BOOST_ASIO_NO_DEPRECATED) -# endif () +mrover_add_nodelet(usb_camera src/perception/usb_camera/*.cpp src/perception/usb_camera src/perception/usb_camera/pch.hpp) +mrover_nodelet_link_libraries(usb_camera opencv_core opencv_objdetect opencv_aruco opencv_imgproc opencv_highgui) + +if (CUDA_FOUND) + # mrover_add_node(nv_vid_codec_h265_enc src/esw/nv_vid_codec_h265_enc/*.c*) + # target_link_libraries(nv_vid_codec_h265_enc PUBLIC cuda nvidia-encode opencv_core opencv_imgproc streaming) + # target_include_directories(nv_vid_codec_h265_enc SYSTEM PUBLIC deps/nvenc) +endif () + +mrover_add_nodelet(gst_websocket_streamer src/esw/gst_websocket_streamer/*.c* src/esw/gst_websocket_streamer src/esw/gst_websocket_streamer/pch.hpp) +mrover_nodelet_link_libraries(gst_websocket_streamer PRIVATE websocket_server ${Gst_LIBRARIES} ${GstApp_LIBRARIES}) +mrover_nodelet_include_directories(gst_websocket_streamer ${Gst_INCLUDE_DIRS} ${GstApp_INCLUDE_DIRS}) if (ZED_FOUND) + mrover_add_nodelet(object_detector src/perception/object_detector/*.c* src/perception/object_detector src/perception/object_detector/pch.hpp) + mrover_nodelet_link_libraries(object_detector PRIVATE opencv_core opencv_dnn opencv_imgproc lie nvinfer nvonnxparser tbb) + mrover_nodelet_defines(object_detector + __CUDA_INCLUDE_COMPILER_INTERNAL_HEADERS__ # Eigen includes some files it should not, ignore + ) + # TODO(john): Update object detector to use new API + target_compile_options(object_detector_nodelet PRIVATE -Wno-deprecated-declarations) + # Temporary + mrover_nodelet_link_libraries(object_detector PRIVATE opencv_imgcodecs opencv_highgui) + mrover_add_nodelet(zed src/perception/zed_wrapper/*.c* src/perception/zed_wrapper src/perception/zed_wrapper/pch.hpp) mrover_nodelet_include_directories(zed ${ZED_INCLUDE_DIRS} ${CUDA_INCLUDE_DIRS}) mrover_nodelet_link_libraries(zed ${ZED_LIBRARIES} ${SPECIAL_OS_LIBS} lie) @@ -202,18 +226,17 @@ endif () ## Teleoperation mrover_add_node(arm_controller src/teleoperation/arm_controller/*.cpp) +target_link_libraries(arm_controller PRIVATE lie) ## Simulator if (MROVER_BUILD_SIM) mrover_add_nodelet(simulator src/simulator/*.cpp src/simulator src/simulator/pch.hpp) - mrover_nodelet_include_directories(simulator ${ASSIMP_INCLUDE_DIRS} ${BULLET_INCLUDE_DIRS} ${OPENCV_INCLUDE_DIRS} src/simulator/imgui) - mrover_nodelet_link_libraries(simulator ${ASSIMP_LIBRARIES} ${BULLET_LIBRARIES} glfw3webgpu webgpu glfw opencv_core opencv_imgcodecs opencv_imgproc lie) + mrover_nodelet_include_directories(simulator ${ASSIMP_INCLUDE_DIRS} ${BULLET_INCLUDE_DIRS} ${OPENCV_INCLUDE_DIRS}) + mrover_nodelet_link_libraries(simulator ${ASSIMP_LIBRARIES} ${BULLET_LIBRARIES} glfw3webgpu webgpu glfw opencv_core opencv_imgcodecs opencv_imgproc webgpu_hpp imgui lie) mrover_nodelet_defines(simulator BOOST_THREAD_PROVIDES_FUTURE) endif () -# TODO - ### ======= ### ### Testing ### ### ======= ### @@ -223,15 +246,16 @@ catkin_add_gtest(example-cpp-test test/example/cpp_test.cpp) # Python unit tests catkin_add_nosetests(test/navigation/drive_test.py) -catkin_add_nosetests(test/teleop/teleop_test.py) catkin_add_nosetests(test/util/SE3_test.py) catkin_add_nosetests(test/util/SO3_test.py) # Integration tests (python and c++) -find_package(rostest REQUIRED) -add_rostest(test/example/basic_integration_test.test) -add_rostest(test/integration/integration.test) -add_rostest(test/util/SE3_tf_test.test) +# Note(quintin): Commented these out because they ignore the Python virtual environment +# Most of our code relies on newer Python features so they fail to initialize +#find_package(rostest REQUIRED) +#add_rostest(test/example/basic_integration_test.test) +#add_rostest(test/integration/integration.test) +#add_rostest(test/util/SE3_tf_test.test) ## Install diff --git a/Dockerfile b/Dockerfile index cd65b024e..a3c4474ae 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,12 +1,11 @@ -FROM ros:noetic +FROM ubuntu:focal -# DEBIAN_FRONTEND=noninteractive and keyboard-configuration are needed to prevent stdin prompting later on -# This was super annoying to figure out because otherwise the build would hang +# DEBIAN_FRONTEND=noninteractive prevents apt from asking for user input # software-properties-common is needed for apt-add-repository -RUN apt-get update -y && apt-get upgrade -y && DEBIAN_FRONTEND=noninteractive apt-get install software-properties-common keyboard-configuration -y -RUN apt-add-repository ppa:ansible/ansible -y -RUN apt-add-repository ppa:git-core/ppa -y -RUN apt-get install -y ansible git git-lfs +# sudo is needed for ansible since it escalates from a normal user to root +ENV DEBIAN_FRONTEND=noninteractive +RUN apt-get update -y && apt-get install software-properties-common sudo -y +RUN apt-add-repository ppa:ansible/ansible -y && apt-get install -y git git-lfs ansible RUN useradd --create-home --groups sudo --shell /bin/zsh mrover # Give mrover user sudo access with no password @@ -17,18 +16,22 @@ RUN mkdir -p /home/mrover/catkin_ws/src/mrover WORKDIR /home/mrover/catkin_ws/src/mrover # Defines the APT packages that need to be installed # rosdep is called from Ansible to install them -ADD ./package.xml . +ADD --chown=mrover:mrover ./package.xml . # Defines the Python packages that need to be installed # pip is called from Ansible to install them -ADD ./pyproject.toml . +ADD --chown=mrover:mrover ./pyproject.toml . +# Define the NPM packages that need to be installed by Bun +ADD --chown=mrover:mrover ./src/teleoperation/frontend/package.json ./src/teleoperation/frontend/bun.lockb ./src/teleoperation/frontend/ # Copy over all Ansible files -ADD ./ansible ./ansible -ADD ./ansible.sh . -RUN ./ansible.sh build.yml +ADD --chown=mrover:mrover ./ansible ./ansible +ADD --chown=mrover:mrover ./ansible.sh . +ADD --chown=mrover:mrover ./pkg ./pkg +RUN ./ansible.sh ci.yml USER root +RUN apt-get purge ansible -y && apt-get autoremove -y # Remove apt cache to free up space in the image RUN apt-get clean && rm -rf /var/lib/apt/lists/* USER mrover -ENTRYPOINT [ "/bin/zsh" ] +ENTRYPOINT [ "/bin/bash" ] diff --git a/README.md b/README.md index dd255c8fc..2e9328c67 100644 --- a/README.md +++ b/README.md @@ -2,4 +2,4 @@ Check out our [Wiki](../../wiki/) for more information -![image](https://user-images.githubusercontent.com/20666629/183543916-a7fee846-31db-44d0-8845-c6a95af1110c.png) +![Picture of Rover in the Custom Simulator atop an Orange Mallet](https://github.com/umrover/mrover-ros/assets/20666629/55fbaf74-bc1b-407a-b8ed-407f276f2803) diff --git a/ansible.sh b/ansible.sh index f37d0b3cc..d5e0b120b 100755 --- a/ansible.sh +++ b/ansible.sh @@ -2,8 +2,8 @@ # Helper script to run Ansible playbooks -if [ "$#" -ne 1 ]; then - echo "Usage: $0 " +if [ "$#" -le 0 ]; then + echo "Usage: $0 " exit 1 fi @@ -11,4 +11,4 @@ sudo -v # Ensure Ansible has sudo permission readonly MROVER_PATH=$(dirname "$0") readonly CATKIN_WORKSPACE_PATH=$(realpath "${MROVER_PATH}"/../..) -ansible-playbook -i "localhost," -c local "${MROVER_PATH}"/ansible/"$1" --extra-vars "catkin_workspace=${CATKIN_WORKSPACE_PATH}" +ansible-playbook -i "localhost," -c local "${MROVER_PATH}"/ansible/"$1" --extra-vars "catkin_workspace=${CATKIN_WORKSPACE_PATH} $2" diff --git a/ansible/ci.yml b/ansible/ci.yml new file mode 100644 index 000000000..1a6dc4c5f --- /dev/null +++ b/ansible/ci.yml @@ -0,0 +1,7 @@ +--- +- hosts: all + vars: + ros_distro: noetic + ubuntu_release: focal + roles: + - ci diff --git a/ansible/roles/basestation_networks/files/networking_setup_basestation.sh b/ansible/roles/basestation_networks/files/networking_setup_basestation.sh old mode 100644 new mode 100755 index 2f64797da..3c44e42d7 --- a/ansible/roles/basestation_networks/files/networking_setup_basestation.sh +++ b/ansible/roles/basestation_networks/files/networking_setup_basestation.sh @@ -1,4 +1,4 @@ #!/usr/bin/env sh -export ROS_MASTER_URI=http://10.0.0.10:11311 -export ROS_IP=10.0.0.2 +export ROS_MASTER_URI=http://10.1.0.10:11311 +export ROS_IP=10.1.0.2 diff --git a/ansible/roles/basestation_networks/tasks/main.yml b/ansible/roles/basestation_networks/tasks/main.yml index a0cfc70b6..0445a34b3 100644 --- a/ansible/roles/basestation_networks/tasks/main.yml +++ b/ansible/roles/basestation_networks/tasks/main.yml @@ -4,9 +4,9 @@ conn_name: MRover state: present type: ethernet - ifname: enx207bd284f29c + ifname: "{{ ifname }}" autoconnect: yes - ip4: 10.0.0.2/8 + ip4: 10.1.0.2/8 # Share connection to the Internet method4: shared method6: disabled @@ -15,5 +15,5 @@ community.general.ssh_config: user: "{{ ansible_user_id }}" host: jetson - hostname: 10.0.0.10 + hostname: 10.1.0.10 remote_user: mrover diff --git a/ansible/roles/build/files/profiles/ci/config.yaml b/ansible/roles/build/files/profiles/ci/config.yaml index ca0dfcf70..d14216f40 100644 --- a/ansible/roles/build/files/profiles/ci/config.yaml +++ b/ansible/roles/build/files/profiles/ci/config.yaml @@ -7,9 +7,8 @@ cmake_args: - -DCMAKE_C_COMPILER=clang-16 - -DCMAKE_CXX_FLAGS=-pipe - -DCMAKE_CXX_COMPILER=clang++-16 - - -DCMAKE_CXX_CLANG_TIDY=clang-tidy-16 - -DCMAKE_CUDA_HOST_COMPILER=clang++-16 - - -DMROVER_CI=ON + - -DMROVER_IS_CI=ON - -Wno-dev devel_layout: linked devel_space: devel diff --git a/ansible/roles/build/tasks/main.yml b/ansible/roles/build/tasks/main.yml index c32199bcc..bc8d866b6 100644 --- a/ansible/roles/build/tasks/main.yml +++ b/ansible/roles/build/tasks/main.yml @@ -89,8 +89,22 @@ - ros-{{ ros_distro }}-rosbash - libbullet-dev - libglfw3-dev - - xorg-dev - libx11-xcb-dev + - libnl-3-dev + - libnl-route-3-dev + - libtbb-dev + - libopencv-dev + - libgstreamer1.0-dev + - libgstreamer-plugins-base1.0-dev + +- name: Install Local APT Packages + become: True + apt: + state: present + deb: "{{ catkin_workspace }}/src/mrover/pkg/{{ item }}" + with_items: + - libmanif-dev.deb + - libdawn-dev.deb - name: Initialize rosdep become: True @@ -176,6 +190,14 @@ link: /usr/bin/lld priority: 160 +- name: Set clang-tidy 16 as Default + become: True + alternatives: + name: clang-tidy + path: /usr/bin/clang-tidy-16 + link: /usr/bin/clang-tidy + priority: 160 + - name: Setup Python Virtual Environment pip: name: diff --git a/ansible/roles/ci/tasks/main.yml b/ansible/roles/ci/tasks/main.yml new file mode 100644 index 000000000..81d80a3b2 --- /dev/null +++ b/ansible/roles/ci/tasks/main.yml @@ -0,0 +1,192 @@ +# Allows us to install Python versions newer than 3.8 +- name: Add Python PPA + become: True + apt_repository: + repo: ppa:deadsnakes/ppa + +# Allows us to install G++13, so we can use an updated libstdc++ which provides more standard library features (C++20) +- name: Add GCC PPA + become: True + apt_repository: + repo: ppa:ubuntu-toolchain-r/test + +- name: Add LLVM APT Key + become: True + apt_key: + url: https://apt.llvm.org/llvm-snapshot.gpg.key + +# Allows us to install Clang 16 and other LLVM tools +- name: Add LLVM APT List + become: True + apt_repository: + repo: deb http://apt.llvm.org/{{ ubuntu_release }}/ llvm-toolchain-{{ ubuntu_release }}-16 main + filename: llvm + +- name: Add CMake APT Key + become: True + apt_key: + url: https://apt.kitware.com/keys/kitware-archive-latest.asc + keyring: /usr/share/keyrings/kitware-archive-keyring.gpg + +# Allows us to install CMake versions newer than 3.16 +- name: Add CMake APT List + become: True + apt_repository: + repo: deb [signed-by=/usr/share/keyrings/kitware-archive-keyring.gpg] https://apt.kitware.com/ubuntu/ {{ ubuntu_release }} main + filename: kitware + +- name: Add ROS APT Key + become: True + apt_key: + url: https://raw.githubusercontent.com/ros/rosdistro/master/ros.asc + +- name: Add ROS APT List + become: True + apt_repository: + repo: deb http://packages.ros.org/ros/ubuntu {{ ubuntu_release }} main + filename: ros + +- name: Upgrade APT Packages + become: True + apt: + cache_valid_time: 604800 + state: latest + upgrade: yes + +- name: Install APT Packages + become: True + apt: + cache_valid_time: 604800 + state: latest + name: + - cmake + - rsync + - python3-rosdep + - python3-catkin-tools + - clang-16 + - clang-tidy-16 + - clang-format-16 + - lld-16 + - gcc-13 + - g++-13 + - python3.10 + - python3.10-dev + - python3.10-venv + - libbullet-dev + - libglfw3-dev + - libx11-xcb-dev + - libnl-3-dev + - libnl-route-3-dev + - libtbb-dev + - libopencv-dev + - libgstreamer1.0-dev + - libgstreamer-plugins-base1.0-dev + +- name: Install Local APT Packages + become: True + apt: + state: present + deb: "{{ catkin_workspace }}/src/mrover/pkg/{{ item }}" + with_items: + - libmanif-dev.deb + - libdawn-dev.deb + +- name: Initialize rosdep + become: True + command: rosdep init + args: + # This command will be skipped if this file already exists + creates: /etc/ros/rosdep/sources.list.d/20-default.list + +- name: Update rosdep + command: rosdep update + +- name: Install ROS Packages + command: rosdep install --from-paths {{ catkin_workspace }}/src --ignore-src -y --rosdistro={{ ros_distro }} + +#- name: Download Bun Installer +# get_url: +# url: https://bun.sh/install +# dest: /tmp/bun_installer.sh +# mode: 0755 +# +#- name: Run Bun Installer +# command: /tmp/bun_installer.sh +# args: +# creates: ~/.bun/bin/bun +# +#- name: Upgrade Bun +# command: ~/.bun/bin/bun upgrade +# +#- name: Install Bun Packages +# command: ~/.bun/bin/bun install --cwd {{ catkin_workspace }}/src/mrover/src/teleoperation/frontend + +#- name: Install Catkin Profiles +# synchronize: +# src: files/profiles +# dest: "{{ catkin_workspace }}/.catkin_tools" +# recursive: true + +- name: Set G++ 13 as Default + become: True + alternatives: + name: g++ + path: /usr/bin/g++-13 + link: /usr/bin/g++ + priority: 130 + +- name: Set GCC 13 as Default + become: True + alternatives: + name: gcc + path: /usr/bin/gcc-13 + link: /usr/bin/gcc + priority: 130 + +- name: Set Clang++ 16 as Default + become: True + alternatives: + name: clang++ + path: /usr/bin/clang++-16 + link: /usr/bin/clang++ + priority: 160 + +- name: Set Clang 16 as Default + become: True + alternatives: + name: clang + path: /usr/bin/clang-16 + link: /usr/bin/clang + priority: 160 + +#- name: Set clangd 16 as Default +# become: True +# alternatives: +# name: clangd +# path: /usr/bin/clangd-16 +# link: /usr/bin/clangd +# priority: 160 + +- name: Set LLD 16 as Default + become: True + alternatives: + name: lld + path: /usr/bin/lld-16 + link: /usr/bin/lld + priority: 160 + +- name: Set clang-tidy 16 as Default + become: True + alternatives: + name: clang-tidy + path: /usr/bin/clang-tidy-16 + link: /usr/bin/clang-tidy + priority: 160 + +- name: Setup Python Virtual Environment + pip: + name: + # Installs from pyproject.toml + - "{{ catkin_workspace }}/src/mrover[dev]" + virtualenv: "{{ catkin_workspace }}/src/mrover/venv" + virtualenv_command: /usr/bin/python3.10 -m venv diff --git a/ansible/roles/jetson_networks/files/networking_setup_jetson.sh b/ansible/roles/jetson_networks/files/networking_setup_jetson.sh index 3d1bcec67..6e52f2473 100644 --- a/ansible/roles/jetson_networks/files/networking_setup_jetson.sh +++ b/ansible/roles/jetson_networks/files/networking_setup_jetson.sh @@ -1,3 +1,3 @@ #!/usr/bin/env bash -export ROS_IP=10.0.0.2 +export ROS_IP=10.1.0.10 diff --git a/ansible/roles/jetson_networks/tasks/main.yml b/ansible/roles/jetson_networks/tasks/main.yml index bef0a6aee..8a7df762f 100644 --- a/ansible/roles/jetson_networks/tasks/main.yml +++ b/ansible/roles/jetson_networks/tasks/main.yml @@ -6,7 +6,7 @@ type: ethernet ifname: eth0 autoconnect: yes - ip4: 10.0.0.10/8 - gw4: 10.0.0.2 - dns4: [10.0.0.2] + ip4: 10.1.0.10/8 + gw4: 10.1.0.2 + dns4: [10.1.0.2] method6: disabled diff --git a/cmake/deps.cmake b/cmake/deps.cmake new file mode 100644 index 000000000..89bf0dd88 --- /dev/null +++ b/cmake/deps.cmake @@ -0,0 +1,62 @@ +find_package(dawn QUIET) +if (dawn_FOUND) + message(STATUS "Using Dawn system install") +else () + message(STATUS "Using Dawn from source") + add_library(webgpu SHARED IMPORTED) + + set(WEBGPU_BUILD_DIR ${CMAKE_CURRENT_LIST_DIR}/../deps/dawn/out/Release) + if (APPLE) + set(WEBGPU_SHARED_LIB ${WEBGPU_BUILD_DIR}/src/dawn/native/libwebgpu_dawn.dylib) + else () + set(WEBGPU_SHARED_LIB ${WEBGPU_BUILD_DIR}/src/dawn/native/libwebgpu_dawn.so) + endif () + if (EXISTS ${WEBGPU_SHARED_LIB}) + target_include_directories(webgpu INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../deps/dawn/include ${WEBGPU_BUILD_DIR}/gen/include) + set_property(TARGET webgpu PROPERTY IMPORTED_LOCATION ${WEBGPU_SHARED_LIB}) + + set(dawn_FOUND TRUE) + else () + message(WARNING "Dawn not found. If on Ubuntu install with 'sudo apt install -f ./pkg/libdawn-dev.deb'. Or build from source with ./scripts/build_dawn.sh") + endif () +endif () + +option(MROVER_BUILD_SIM "Build the simulator" ${dawn_FOUND}) + +if (MROVER_BUILD_SIM) + # Apparently Assimp has different names on different systems + # find_package is case-sensitive so try both + find_package(Assimp NAMES Assimp assimp QUIET) + if (NOT Assimp_FOUND) + message(FATAL_ERROR "Assimp not found") + endif () + + find_package(Bullet REQUIRED) + find_package(glfw3 REQUIRED) + + add_subdirectory(deps/glfw3webgpu SYSTEM EXCLUDE_FROM_ALL) + add_subdirectory(deps/imgui SYSTEM EXCLUDE_FROM_ALL) + add_subdirectory(deps/webgpuhpp SYSTEM EXCLUDE_FROM_ALL) +endif () + +find_package(OpenCV REQUIRED) +find_package(ZED QUIET) +find_package(Eigen3 REQUIRED) + +find_package(manif QUIET) +if (NOT manif_FOUND) + if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/../deps/manif/include/manif) + add_subdirectory(deps/manif SYSTEM) + add_library(MANIF::manif ALIAS manif) + + set(manif_FOUND TRUE) + else () + message(FATAL_ERROR "Manif not found. If on Ubuntu install with 'sudo apt install -f ./pkg/libmanif-dev.deb'. Or build from source with 'submodule update --init deps/manif' and make sure it is non-empty") + endif () +endif () + +find_package(PkgConfig REQUIRED) +pkg_search_module(NetLink libnl-3.0 QUIET) +pkg_search_module(NetLinkRoute libnl-route-3.0 QUIET) +pkg_search_module(Gst gstreamer-1.0 QUIET) +pkg_search_module(GstApp gstreamer-app-1.0 QUIET) diff --git a/cmake/macros.cmake b/cmake/macros.cmake index 5b8aaafc0..41674a8cb 100644 --- a/cmake/macros.cmake +++ b/cmake/macros.cmake @@ -11,6 +11,10 @@ macro(target_rosify target) LIBRARY DESTINATION ${CATKIN_PACKAGE_LIB_DESTINATION} RUNTIME DESTINATION ${CATKIN_PACKAGE_BIN_DESTINATION} ) + + if (MROVER_RUN_CLANG_TIDY) + set_target_properties(${target} PROPERTIES CXX_CLANG_TIDY clang-tidy) + endif () endmacro() macro(mrover_add_library name sources includes) diff --git a/cmake/webgpu.cmake b/cmake/webgpu.cmake deleted file mode 100644 index d3a3dc946..000000000 --- a/cmake/webgpu.cmake +++ /dev/null @@ -1,170 +0,0 @@ -add_library(webgpu SHARED IMPORTED) -if (APPLE) - set(WEBGPU_SHARED_LIB_NAME "libwebgpu_dawn.dylib") -else() - set(WEBGPU_SHARED_LIB_NAME "libwebgpu_dawn.so") -endif() -set(WEBGPU_BUILD_DIR ${CMAKE_CURRENT_LIST_DIR}/../deps/dawn/out/Release) -set_property(TARGET webgpu PROPERTY IMPORTED_LOCATION ${WEBGPU_BUILD_DIR}/src/dawn/native/${WEBGPU_SHARED_LIB_NAME}) -target_include_directories(webgpu INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../deps/dawn/include ${WEBGPU_BUILD_DIR}/gen/include) - -#add_library(webgpu INTERFACE) -# -#target_link_libraries(webgpu INTERFACE webgpu_dawn) -# target_include_directories(webgpu INTERFACE -# "${CMAKE_CURRENT_SOURCE_DIR}/deps/dawn/include" -# ) -# -# # This is used to advertise the flavor of WebGPU that this zip provides -# target_compile_definitions(webgpu INTERFACE WEBGPU_BACKEND_DAWN) -# -#include(FetchContent) -# -#FetchContent_Declare( -# dawn -# SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/deps/dawn -# DOWNLOAD_COMMAND -# cd ${CMAKE_CURRENT_SOURCE_DIR}/deps/dawn && -# git init && -# git fetch --depth=1 https://dawn.googlesource.com/dawn chromium/6108 && -# git reset --hard FETCH_HEAD -#) -# -#FetchContent_GetProperties(dawn) -#if (NOT dawn_POPULATED) -# FetchContent_Populate(dawn) -# -# # This option replaces depot_tools -# set(DAWN_FETCH_DEPENDENCIES ON) -# -# # A more minimalistic choice of backand than Dawn's default -# if (APPLE) -# set(USE_VULKAN OFF) -# set(USE_METAL ON) -# else() -# set(USE_VULKAN ON) -# set(USE_METAL OFF) -# endif() -# set(DAWN_ENABLE_D3D11 OFF) -# set(DAWN_ENABLE_D3D12 OFF) -# set(DAWN_ENABLE_METAL ${USE_METAL}) -# set(DAWN_ENABLE_NULL OFF) -# set(DAWN_ENABLE_DESKTOP_GL OFF) -# set(DAWN_ENABLE_OPENGLES OFF) -# set(DAWN_ENABLE_VULKAN ${USE_VULKAN}) -# set(TINT_BUILD_SPV_READER OFF) -# -# # Disable unneeded parts -# set(DAWN_BUILD_SAMPLES OFF) -# set(TINT_BUILD_TINT OFF) -# set(TINT_BUILD_SAMPLES OFF) -# set(TINT_BUILD_DOCS OFF) -# set(TINT_BUILD_TESTS OFF) -# set(TINT_BUILD_FUZZERS OFF) -# set(TINT_BUILD_SPIRV_TOOLS_FUZZER OFF) -# set(TINT_BUILD_AST_FUZZER OFF) -# set(TINT_BUILD_REGEX_FUZZER OFF) -# set(TINT_BUILD_BENCHMARKS OFF) -# set(TINT_BUILD_TESTS OFF) -# set(TINT_BUILD_AS_OTHER_OS OFF) -# set(TINT_BUILD_REMOTE_COMPILE OFF) -# -# add_subdirectory(${dawn_SOURCE_DIR} ${dawn_BINARY_DIR} SYSTEM EXCLUDE_FROM_ALL) -#endif () -# -#set(AllDawnTargets -# core_tables -# dawn_common -# dawn_glfw -# dawn_headers -# dawn_native -# dawn_platform -# dawn_proc -# dawn_utils -# dawn_wire -# dawncpp -# dawncpp_headers -# emscripten_bits_gen -# enum_string_mapping -# extinst_tables -# webgpu_dawn -# webgpu_headers_gen -# -# tint_api -# tint_api_common -# tint_api_options -# tint_cmd_common -# tint_cmd_info_cmd -# tint_cmd_loopy_cmd -# tint_cmd_remote_compile_cmd -# tint_cmd_tint_cmd -# tint_lang_core -# tint_lang_core_constant -# tint_lang_core_intrinsic -# tint_lang_core_ir -# tint_lang_core_ir_transform -# tint_lang_core_type -# tint_lang_glsl_validate -# tint_lang_glsl_writer_raise -# tint_lang_hlsl_writer_common -# tint_lang_msl_writer_raise -# tint_lang_spirv -# tint_lang_spirv_intrinsic -# tint_lang_spirv_ir -# tint_lang_spirv_reader_common -# tint_lang_spirv_type -# tint_lang_spirv_writer -# tint_lang_spirv_writer_ast_printer -# tint_lang_spirv_writer_ast_raise -# tint_lang_spirv_writer_common -# tint_lang_spirv_writer_helpers -# tint_lang_spirv_writer_printer -# tint_lang_spirv_writer_raise -# tint_lang_wgsl -# tint_lang_wgsl_ast -# tint_lang_wgsl_ast_transform -# tint_lang_wgsl_helpers -# tint_lang_wgsl_inspector -# tint_lang_wgsl_intrinsic -# tint_lang_wgsl_ir -# tint_lang_wgsl_program -# tint_lang_wgsl_reader -# tint_lang_wgsl_reader_lower -# tint_lang_wgsl_reader_parser -# tint_lang_wgsl_reader_program_to_ir -# tint_lang_wgsl_resolver -# tint_lang_wgsl_sem -# tint_lang_wgsl_writer -# tint_lang_wgsl_writer_ast_printer -# tint_lang_wgsl_writer_ir_to_program -# tint_lang_wgsl_writer_raise -# tint_lang_wgsl_writer_syntax_tree_printer -# tint_utils_cli -# tint_utils_command -# tint_utils_containers -# tint_utils_debug -# tint_utils_diagnostic -# tint_utils_file -# tint_utils_generator -# tint_utils_ice -# tint_utils_id -# tint_utils_macros -# tint_utils_math -# tint_utils_memory -# tint_utils_reflection -# tint_utils_result -# tint_utils_rtti -# tint_utils_socket -# tint_utils_strconv -# tint_utils_symbol -# tint_utils_text -# tint_utils_traits -# tint-format -# tint-lint -#) -# -#foreach (Target ${AllDawnTargets}) -# if (TARGET ${Target}) -# set_property(TARGET ${Target} PROPERTY FOLDER "Dawn") -# endif() -#endforeach() diff --git a/config/ObjectDetectorParams.cfg b/config/ObjectDetectorParams.cfg new file mode 100755 index 000000000..1ef932be5 --- /dev/null +++ b/config/ObjectDetectorParams.cfg @@ -0,0 +1,10 @@ +#!/usr/bin/env python3 +PACKAGE = "mrover" + +from dynamic_reconfigure.parameter_generator_catkin import * + +gen = ParameterGenerator() + +# TODO(percep/obj-detector): add parameters + +exit(gen.generate(PACKAGE, "object_detector", "ObjectDetectorParams")) diff --git a/config/ekf.yaml b/config/ekf.yaml index 5552cb87b..147f17e24 100644 --- a/config/ekf.yaml +++ b/config/ekf.yaml @@ -35,17 +35,17 @@ global_ekf: publish_tf: true # odom frame off - # map_frame: none - # odom_frame: map - # base_link_frame: base_link - # world_frame: map - - # odom frame on - map_frame: map - odom_frame: odom + map_frame: none + odom_frame: map base_link_frame: base_link world_frame: map + # odom frame on + # map_frame: map + # odom_frame: odom + # base_link_frame: base_link + # world_frame: map + # IMU accel and gyro # imu0: imu/imu_only diff --git a/config/esw.yaml b/config/esw.yaml index b03084763..ab80e6d2c 100644 --- a/config/esw.yaml +++ b/config/esw.yaml @@ -1,122 +1,173 @@ -gps_driver: - port: "/dev/gps" - baud: 115200 - useRMC: false # get covariance instead of velocity, see wiki for more info - frame_id: "base_link" - imu_driver: port: "/dev/tty.usbmodem101" baud: 115200 frame_id: "imu_link" +gps: + port: "/dev/gps" + baud: 115200 + useRMC: false # get covariance instead of velocity, see wiki for more info + frame_id: "base_link" + can: devices: - name: "jetson" - bus: 0 + bus: 2 + id: 0x10 + - name: "jetson" + bus: 3 id: 0x10 - name: "front_left" - bus: 0 - id: 0x11 - - name: "front_right" - bus: 0 + bus: 2 id: 0x12 + - name: "front_right" + bus: 2 + id: 0x11 - name: "middle_left" - bus: 0 - id: 0x13 - - name: "middle_right" - bus: 0 + bus: 2 id: 0x14 + - name: "middle_right" + bus: 2 + id: 0x13 - name: "back_left" - bus: 0 - id: 0x15 - - name: "back_right" - bus: 0 + bus: 2 id: 0x16 + - name: "back_right" + bus: 3 + id: 0x15 - name: "joint_a" - bus: 0 - id: 0x17 + bus: 3 + id: 0x20 - name: "joint_b" - bus: 0 - id: 0x18 + bus: 3 + id: 0x21 - name: "joint_c" - bus: 0 - id: 0x19 + bus: 3 + id: 0x22 - name: "joint_de_0" - bus: 0 - id: 0x20 + bus: 3 + id: 0x23 - name: "joint_de_1" - bus: 0 - id: 0x21 + bus: 3 + id: 0x24 - name: "allen_key" - bus: 0 - id: 0x22 + bus: 3 + id: 0x25 - name: "gripper" - bus: 0 - id: 0x23 - - name: "mast_gimbal_x" - bus: 0 - id: 0x24 + bus: 3 + id: 0x26 - name: "mast_gimbal_y" - bus: 0 - id: 0x25 + bus: 3 + id: 0x28 + - name: "mast_gimbal_z" + bus: 3 + id: 0x27 - name: "sa_x" - bus: 0 - id: 0x26 + bus: 3 + id: 0x29 - name: "sa_y" - bus: 0 - id: 0x27 + bus: 3 + id: 0x30 - name: "sa_z" - bus: 0 - id: 0x28 - - name: "scoop" - bus: 0 - id: 0x29 + bus: 3 + id: 0x31 + - name: "sampler" + bus: 3 + id: 0x32 - name: "sensor_actuator" - bus: 0 - id: 0x30 + bus: 3 + id: 0x33 - name: "cache" - bus: 0 - id: 0x31 + bus: 3 + id: 0x34 - name: "pdlb" - bus: 0 - id: 0x32 + bus: 3 + id: 0x50 - name: "science" - bus: 0 - id: 0x33 + bus: 2 + id: 0x51 brushless_motors: controllers: front_left: + velocity_multiplier: -1.0 min_velocity: -70.0 max_velocity: 70.0 front_right: + velocity_multiplier: 1.0 min_velocity: -70.0 max_velocity: 70.0 middle_left: + velocity_multiplier: -1.0 min_velocity: -70.0 max_velocity: 70.0 middle_right: + velocity_multiplier: 1.0 min_velocity: -70.0 max_velocity: 70.0 back_left: + velocity_multiplier: -1.0 min_velocity: -70.0 max_velocity: 70.0 back_right: + velocity_multiplier: 1.0 min_velocity: -70.0 max_velocity: 70.0 joint_a: - min_velocity: -70.0 - max_velocity: 70.0 + velocity_multiplier: 1.0 + min_velocity: -100.0 + max_velocity: 100.0 + is_linear: true + rad_to_meters_ratio: 1236.8475 # 5.0 = 5 motor radians -> 1 meter + limit_0_present: true + limit_1_present: true + limit_0_enabled: true + limit_1_enabled: true + limit_0_limits_fwd: true + limit_1_limits_fwd: false + limit_0_is_active_high: false + limit_1_is_active_high: false + limit_0_used_for_readjustment: true + limit_1_used_for_readjustment: true + limit_0_readjust_position: 0.0 # radians TODO + limit_1_readjust_position: 494.739 # radians + limit_max_forward_pos: true + limit_max_backward_pos: true + max_forward_pos: 0.4 + max_backward_pos: 0.0 joint_c: - min_velocity: -70.0 - max_velocity: 70.0 + velocity_multiplier: -1.0 + min_velocity: -3.0 # gear ratio: 484:1 + max_velocity: 3.0 + min_position: 0.0 + max_position: 3.8 # 220 degrees of motion joint_de_0: - min_velocity: -70.0 - max_velocity: 70.0 + velocity_multiplier: 1.0 + min_velocity: -67.0 + max_velocity: 67.0 joint_de_1: - min_velocity: -70.0 - max_velocity: 70.0 - + velocity_multiplier: 1.0 + min_velocity: -67.0 + max_velocity: 67.0 + sa_z: + velocity_multiplier: 1.0 + min_velocity: -100.0 + max_velocity: 100.0 + is_linear: true + rad_to_meters_ratio: 157.48 #rad/m + limit_0_present: false + limit_1_present: false + limit_0_enabled: true + limit_1_enabled: true + limit_0_limits_fwd: true + limit_1_limits_fwd: false + limit_0_is_active_high: false + limit_1_is_active_high: false + limit_0_used_for_readjustment: true + limit_1_used_for_readjustment: true + limit_0_readjust_position: 0.0 # radians TODO + limit_1_readjust_position: 0.0 # radians TODO + max_torque: 0.5 joint_de: pitch_offset: 0.0 roll_offset: 0.0 @@ -129,10 +180,10 @@ brushed_motors: # limit_1_present: false # limit_2_present: false # limit_3_present: false - # limit_0_default_enabled: false - # limit_1_default_enabled: false - # limit_2_default_enabled: false - # limit_3_default_enabled: false + # limit_0_enabled: false + # limit_1_enabled: false + # limit_2_enabled: false + # limit_3_enabled: false # limit_0_is_active_high: true # limit_1_is_active_high: true # limit_2_is_active_high: true @@ -155,37 +206,44 @@ brushed_motors: # limit_3_readjust_position: 0.0 # radians # quad_ratio: 1.0 # encoder ratio compared to motor # abs_ratio: 1.0 # encoder ratio compared to motor - # abs_encoder_offset: 0.0 # 0 for joint position corresponds to this radians reading by absolute encoder - # driver_voltage: 24.0 # used to calculate max pwm + # abs_offset: 0.0 # 0 for joint position corresponds to this radians reading by absolute encoder + # driver_voltage: 12.0 # used to calculate max pwm # motor_max_voltage: 12.0 # used to calculate max pwm # limit_max_forward_pos: false # limit_max_backward_pos: false # max_forward_pos: 1.0 # max_backward_pos: 0.0 + # calibration_throttle: 5.0 joint_b: + velocity_multiplier: 1.0 gear_ratio: 1.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint limit_0_present: true - limit_0_default_enabled: true - limit_0_is_active_high: true + limit_0_enabled: true + limit_0_is_active_high: false limit_0_limits_fwd: false limit_0_used_for_readjustment: true abs_present: true abs_is_fwd_polarity: true - limit_0_readjust_position: 0.0 # radians + limit_0_readjust_position: -0.7853981633974483 # radians abs_ratio: 1.0 # encoder ratio compared to motor - abs_encoder_offset: 0.0 # 0 for joint position corresponds to this radians reading by absolute encoder - driver_voltage: 24.0 # used to calculate max pwm + abs_offset: 0.0 # 0 for joint position corresponds to this radians reading by absolute encoder + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 12.0 # used to calculate max pwm limit_max_forward_pos: true - max_forward_pos: 1.0 + min_position: -0.7853981633974483 + max_position: 0.0 + min_velocity: -1.0 + max_velocity: 1.0 + calibration_throttle: 0.5 # throttle during calibration allen_key: + velocity_multiplier: 1.0 gear_ratio: 30.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint limit_0_present: true limit_1_present: true - limit_0_default_enabled: true - limit_1_default_enabled: true - limit_0_is_active_high: true - limit_1_is_active_high: true + limit_0_enabled: true + limit_1_enabled: true + limit_0_is_active_high: false + limit_1_is_active_high: false limit_0_limits_fwd: true limit_1_limits_fwd: true limit_0_used_for_readjustment: true @@ -195,51 +253,44 @@ brushed_motors: limit_0_readjust_position: 0.0 # radians limit_1_readjust_position: 0.0 # radians quad_ratio: 1.0 # encoder ratio compared to motor - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 12.0 # used to calculate max pwm + calibration_throttle: 0.5 # throttle during calibration gripper: + velocity_multiplier: 1.0 gear_ratio: 47.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint quad_present: false quad_is_fwd_polarity: true abs_present: false abs_is_fwd_polarity: true quad_ratio: 1.0 # encoder ratio compared to motor - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 12.0 # used to calculate max pwm - mast_gimbal_x: + calibration_throttle: 0.5 # throttle during calibration + mast_gimbal_y: + velocity_multiplier: 1.0 gear_ratio: 1000.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - limit_0_present: true - limit_1_present: true - limit_0_default_enabled: true - limit_1_default_enabled: true - limit_0_is_active_high: true - limit_1_is_active_high: true - limit_0_limits_fwd: true - limit_1_limits_fwd: false - limit_0_used_for_readjustment: true - limit_1_used_for_readjustment: true - quad_present: true - quad_is_fwd_polarity: true - limit_0_readjust_position: 0.0 # radians - limit_1_readjust_position: 6.28 # radians - quad_ratio: 1.0 # encoder ratio compared to motor - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 12.0 # used to calculate max pwm - mast_gimbal_y: + mast_gimbal_z: + velocity_multiplier: 1.0 gear_ratio: 1000.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 12.0 # used to calculate max pwm sa_x: + velocity_multiplier: 1.0 gear_ratio: 75.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - limit_0_present: true - limit_1_present: true - limit_2_present: true - limit_0_default_enabled: true - limit_1_default_enabled: true - limit_2_default_enabled: true - limit_0_is_active_high: true - limit_1_is_active_high: true - limit_2_is_active_high: true + is_linear: true + rad_to_meters_ratio: 1.0 #TODO 5.0 = 5 motor radians -> 1 meter + limit_0_present: false + limit_1_present: false + limit_2_present: false + limit_0_enabled: true + limit_1_enabled: true + limit_2_enabled: true + limit_0_is_active_high: false + limit_1_is_active_high: false + limit_2_is_active_high: false limit_0_limits_fwd: true limit_1_limits_fwd: false limit_2_limits_fwd: true @@ -251,16 +302,22 @@ brushed_motors: limit_0_readjust_position: 0.0 # radians limit_1_readjust_position: 0.0 # radians quad_ratio: 48.0 # encoder ratio compared to motor - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 6.0 # used to calculate max pwm + min_velocity: -1.0 + max_velocity: 1.0 + calibration_throttle: 0.5 # throttle during calibration sa_y: + velocity_multiplier: -1.0 gear_ratio: 75.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - limit_0_present: true - limit_1_present: true - limit_0_default_enabled: true - limit_1_default_enabled: true - limit_0_is_active_high: true - limit_1_is_active_high: true + is_linear: true + rad_to_meters_ratio: 1.0 #TODO 5.0 = 5 motor radians -> 1 meter + limit_0_present: false + limit_1_present: false + limit_0_enabled: true + limit_1_enabled: true + limit_0_is_active_high: false + limit_1_is_active_high: false limit_0_limits_fwd: true limit_1_limits_fwd: false limit_0_used_for_readjustment: true @@ -270,16 +327,21 @@ brushed_motors: limit_0_readjust_position: 0.0 # radians limit_1_readjust_position: 0.0 # radians quad_ratio: 48.0 # encoder ratio compared to motor - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 6.0 # used to calculate max pwm - sa_z: + min_velocity: -1.0 + max_velocity: 1.0 + calibration_throttle: 0.5 # throttle during calibration + sampler: gear_ratio: 75.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - limit_0_present: true - limit_1_present: true - limit_0_default_enabled: true - limit_1_default_enabled: true - limit_0_is_active_high: true - limit_1_is_active_high: true + is_linear: true + rad_to_meters_ratio: 1.0 #TODO 5.0 = 5 motor radians -> 1 meter + limit_0_present: false + limit_1_present: false + limit_0_enabled: true + limit_1_enabled: true + limit_0_is_active_high: false + limit_1_is_active_high: false limit_0_limits_fwd: true limit_1_limits_fwd: false limit_0_used_for_readjustment: true @@ -289,59 +351,44 @@ brushed_motors: limit_0_readjust_position: 0.0 # radians limit_1_readjust_position: 0.0 # radians quad_ratio: 48.0 # encoder ratio compared to motor - driver_voltage: 24.0 # used to calculate max pwm - motor_max_voltage: 6.0 # used to calculate max pwm - scoop: - gear_ratio: 75.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - limit_0_present: true - limit_1_present: true - limit_0_default_enabled: true - limit_1_default_enabled: true - limit_0_is_active_high: true - limit_1_is_active_high: true - limit_0_limits_fwd: true - limit_1_limits_fwd: false - limit_0_used_for_readjustment: true - limit_1_used_for_readjustment: true - quad_present: true - quad_is_fwd_polarity: true - limit_0_readjust_position: 0.0 # radians - limit_1_readjust_position: 0.0 # radians - quad_ratio: 48.0 # encoder ratio compared to motor - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 6.0 # used to calculate max pwm + calibration_throttle: 0.5 # throttle during calibration sensor_actuator: + velocity_multiplier: 1.0 gear_ratio: 1.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - limit_0_present: true - limit_1_present: true - limit_0_default_enabled: true - limit_1_default_enabled: true - limit_0_is_active_high: true - limit_1_is_active_high: true + limit_0_present: false + limit_1_present: false + limit_0_enabled: true + limit_1_enabled: true + limit_0_is_active_high: false + limit_1_is_active_high: false limit_0_limits_fwd: true limit_1_limits_fwd: false limit_0_used_for_readjustment: true limit_1_used_for_readjustment: true limit_0_readjust_position: 0.0 # radians limit_1_readjust_position: 0.0 # radians - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 6.0 # used to calculate max pwm cache: + velocity_multiplier: 1.0 gear_ratio: 1.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - limit_0_present: true - limit_1_present: true - limit_0_default_enabled: true - limit_1_default_enabled: true - limit_0_is_active_high: true - limit_1_is_active_high: true + limit_0_present: false + limit_1_present: false + limit_0_enabled: true + limit_1_enabled: true + limit_0_is_active_high: false + limit_1_is_active_high: false limit_0_limits_fwd: true limit_1_limits_fwd: false limit_0_used_for_readjustment: true limit_1_used_for_readjustment: true limit_0_readjust_position: 0.0 # radians limit_1_readjust_position: 0.0 # radians - driver_voltage: 24.0 # used to calculate max pwm + driver_voltage: 12.0 # used to calculate max pwm motor_max_voltage: 6.0 # used to calculate max pwm + cameras: camera_type_info: # vendor_id and vendor is obtained by running `udevadm info --query=all /dev/video0` @@ -473,38 +520,6 @@ wheel: gear_ratio: 50.0 radius: 0.13 -arm: - controllers: - joint_a: - multiplier: 1.0 - joint_b: - multiplier: 1.0 - joint_c: - multiplier: 1.0 - joint_de_0: - multiplier: 1.0 - joint_de_1: - multiplier: 1.0 - allen_key: - multiplier: 1.0 - gripper: - multiplier: 1.0 - -drive: - controllers: - front_left: - multiplier: -1.0 - front_right: - multiplier: 1.0 - middle_left: - multiplier: -1.0 - middle_right: - multiplier: 1.0 - back_left: - multiplier: -1.0 - back_right: - multiplier: 1.0 - motors_group: arm_hw: - "joint_a" @@ -515,15 +530,15 @@ motors_group: - "allen_key" - "gripper" mast_gimbal: - - "mast_gimbal_x" - "mast_gimbal_y" + - "mast_gimbal_z" cache: - "cache_motor" - sa: + sa_hw: - "sa_x" - "sa_y" - "sa_z" - - "scoop" + - "sampler" - "sensor_actuator" drive: - "front_left" @@ -561,17 +576,17 @@ motors: type: "brushless" back_right: type: "brushless" - mast_gimbal_x: - type: "brushed" mast_gimbal_y: type: "brushed" + mast_gimbal_z: + type: "brushed" sa_x: type: "brushed" sa_y: type: "brushed" sa_z: - type: "brushed" - scoop: + type: "brushless" + sampler: type: "brushed" sensor_actuator: type: "brushed" @@ -579,3 +594,7 @@ motors: type: "brushed" default_network_iface: "enp0s31f6" + +auton_led_driver: + port: "/dev/ttyACM0" + baud: 115200 diff --git a/config/esw_devboard.yaml b/config/esw_devboard.yaml index 66e383018..ffea715e7 100644 --- a/config/esw_devboard.yaml +++ b/config/esw_devboard.yaml @@ -10,6 +10,14 @@ can: brushless_motors: controllers: devboard: + limit_0_present: true + limit_1_present: true + limit_0_enabled: true + limit_1_enabled: true + limit_0_is_active_high: true + limit_1_is_active_high: true + limit_0_limits_fwd: true + limit_1_limits_fwd: false min_velocity: -5.0 max_velocity: 5.0 min_position: -100.0 @@ -18,33 +26,37 @@ brushless_motors: brushed_motors: controllers: devboard: + min_velocity: -5.0 + max_velocity: 5.0 + min_position: -100.0 + max_position: 100.0 gear_ratio: 1.0 # motor ratio compared to joint, e.g. if 5, then 5 rotations of motor = 1 rotation of joint - limit_0_present: false - limit_1_present: false + limit_0_present: true + limit_1_present: true limit_2_present: false limit_3_present: false - limit_0_default_enabled: false - limit_1_default_enabled: false - limit_2_default_enabled: false - limit_3_default_enabled: false + limit_0_enabled: true + limit_1_enabled: true + limit_2_enabled: false + limit_3_enabled: false limit_0_is_active_high: true limit_1_is_active_high: true limit_2_is_active_high: true limit_3_is_active_high: true - limit_0_limits_fwd: true + limit_0_limits_fwd: false limit_1_limits_fwd: true limit_2_limits_fwd: true limit_3_limits_fwd: true - limit_0_used_for_readjustment: false - limit_1_used_for_readjustment: false - limit_2_used_for_readjustment: false - limit_3_used_for_readjustment: false - quad_present: false + limit_0_used_for_readjustment: true + limit_1_used_for_readjustment: true + limit_2_used_for_readjustment: true + limit_3_used_for_readjustment: true + quad_present: true quad_is_fwd_polarity: true abs_present: false abs_is_fwd_polarity: true - limit_0_readjust_position: 0.0 # radians - limit_1_readjust_position: 0.0 # radians + limit_0_readjust_position: -20.0 # radians + limit_1_readjust_position: 20.0 # radians limit_2_readjust_position: 0.0 # radians limit_3_readjust_position: 0.0 # radians quad_ratio: 1.0 # encoder ratio compared to motor @@ -56,3 +68,6 @@ brushed_motors: limit_max_backward_pos: false max_forward_pos: 1.0 max_backward_pos: 0.0 + position_p: 1.2 + velocity_p: 1.4 + velocity_ff: 0.9 diff --git a/config/navigation.yaml b/config/navigation.yaml index fe5a6adfb..4483d8c56 100644 --- a/config/navigation.yaml +++ b/config/navigation.yaml @@ -22,6 +22,10 @@ search: segments_per_rotation: 8 distance_between_spirals: 3 +object_search: + coverage_radius: 10 + distance_between_spirals: 3 + single_fiducial: stop_thresh: 1.0 fiducial_stop_threshold: 1.75 @@ -46,5 +50,13 @@ failure_identification: watchdog: window_size: 100 #size of window we are looking at for being stuck - angular_threshold: 0.1 + angular_threshold: 0.1 linear_threshold: 0.2 + +long_range: + distance_ahead: 20 + time_threshold: 5 + increment_weight: 5 + decrement_weight: 1 + min_hits: 3 + max_hits: 10 diff --git a/config/rviz/auton_sim.rviz b/config/rviz/auton_sim.rviz index 8ed1993dc..d16b7139a 100644 --- a/config/rviz/auton_sim.rviz +++ b/config/rviz/auton_sim.rviz @@ -82,7 +82,7 @@ Visualization Manager: Value: true right_camera_link: Value: true - zed2i_left_camera_frame: + zed_left_camera_frame: Value: true Marker Alpha: 1 Marker Scale: 1 @@ -112,7 +112,7 @@ Visualization Manager: {} right_camera_link: {} - zed2i_left_camera_frame: + zed_left_camera_frame: {} Update Interval: 0 Value: true diff --git a/config/sim_ekf.yaml b/config/sim_ekf.yaml index 3d16bb477..9d2b75e3c 100644 --- a/config/sim_ekf.yaml +++ b/config/sim_ekf.yaml @@ -5,28 +5,28 @@ global_ekf: # This option controls whether to use that DoP covariance matrix, or to # replace it with the configured gps_covariane matrix below use_gps_dop_covariance: false - gps_covariance: [[2, 0, 0], - [0, 2, 0], - [0, 0, 2]] + gps_covariance: [ [ 0.02, 0, 0 ], + [ 0, 0.02, 0 ], + [ 0, 0, 0.02 ] ] - imu_orientation_covariance: [[0.1, 0, 0], - [0, 0.1, 0], - [0, 0, 0.1]] + imu_orientation_covariance: [ [ 0.01, 0, 0 ], + [ 0, 0.01, 0 ], + [ 0, 0, 0.01 ] ] - imu_accel_covariance: [[0.1, 0, 0], - [0, 0.1, 0], - [0, 0, 0.1]] + imu_accel_covariance: [ [ 0.01, 0, 0 ], + [ 0, 0.01, 0 ], + [ 0, 0, 0.01 ] ] - imu_gyro_covariance: [[0.1, 0, 0], - [0, 0.1, 0], - [0, 0, 0.1]] + imu_gyro_covariance: [ [ 0.01, 0, 0 ], + [ 0, 0.01, 0 ], + [ 0, 0, 0.01 ] ] - imu_mag_pose_covariance: [[0, 0, 0, 0, 0, 0], - [0, 0, 0, 0, 0, 0], - [0, 0, 0, 0, 0, 0], - [0, 0, 0, 0, 0, 0], - [0, 0, 0, 0, 0, 0], - [0, 0, 0, 0, 0, 0.1]] + imu_mag_pose_covariance: [ [ 0, 0, 0, 0, 0, 0 ], + [ 0, 0, 0, 0, 0, 0 ], + [ 0, 0, 0, 0, 0, 0 ], + [ 0, 0, 0, 0, 0, 0 ], + [ 0, 0, 0, 0, 0, 0 ], + [ 0, 0, 0, 0, 0, 0.1 ] ] # Hz frequency: 30 @@ -69,11 +69,11 @@ global_ekf: # true, true, true, # false, true, true] - pose0_config: [true, true, true, - true, true, true, - false, false, false, - false, false, false, - false, false, false] + pose0_config: [ true, true, true, + true, true, true, + false, false, false, + false, false, false, + false, false, false ] # pose1_config: [false, false, false, # false, false, true, @@ -95,40 +95,40 @@ global_ekf: use_control: true # Which velocities are being controlled. Order is vx, vy, vz, vroll, vpitch, vyaw. - control_config: [true, false, false, false, false, true] - acceleration_limits: [1.3, 0.0, 0.0, 0.0, 0.0, 3.4] - deceleration_limits: [1.3, 0.0, 0.0, 0.0, 0.0, 4.5] + control_config: [ true, false, false, false, false, true ] + acceleration_limits: [ 1.3, 0.0, 0.0, 0.0, 0.0, 3.4 ] + deceleration_limits: [ 1.3, 0.0, 0.0, 0.0, 0.0, 4.5 ] # x, y, z, roll, pitch, yaw, vx, vy, vz, vroll, vpitch, vyaw, ax, ay, az - process_noise_covariance: [0.05, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0.05, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0.06, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0.03, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0.03, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0.06, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0.025, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0.025, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0.04, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.01, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.01, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.02, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.01, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.01, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.015] - - initial_estimate_covariance: [0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9] + process_noise_covariance: [ 0.05, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0.05, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0.06, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0.03, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0.03, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0.06, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0.025, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0.025, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0.04, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.01, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.01, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.02, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.01, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.01, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.015 ] + + initial_estimate_covariance: [ 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1e-9 ] diff --git a/config/simulator/simulator.yaml b/config/simulator/simulator.yaml index acd6866b2..5df26b848 100644 --- a/config/simulator/simulator.yaml +++ b/config/simulator/simulator.yaml @@ -2,39 +2,39 @@ objects: - type: urdf name: rover uri: package://mrover/urdf/rover/rover.urdf.xacro - translation: [ 0, 0, 0.5 ] + translation: [0, 0, 0.5] - type: urdf name: world uri: package://mrover/urdf/world/world.urdf.xacro - type: urdf name: tag_0 uri: package://mrover/urdf/world/tag_0.urdf.xacro - translation: [ -3, -3, 0.7 ] + translation: [ -2, -2, 0.7 ] - type: urdf name: tag_1 uri: package://mrover/urdf/world/tag_1.urdf.xacro - translation: [ 15, -14, 2.4 ] + translation: [15, -14, 2.4] - type: urdf name: hammer uri: package://mrover/urdf/world/hammer.urdf.xacro - translation: [ 8, 7, 0.6 ] + translation: [5, 2, 0.7] - type: urdf name: bottle uri: package://mrover/urdf/world/bottle.urdf.xacro - translation: [ -6.25, 10.5, 0.3 ] + translation: [-6.25, 10.5, 0.3] - type: urdf name: rock1 uri: package://mrover/urdf/world/rock.urdf.xacro - translation: [ 2, -2, 0.1 ] + translation: [2, -2, 0.1] - type: urdf name: rock2 uri: package://mrover/urdf/world/rock.urdf.xacro - translation: [ 7, -6, 0.2 ] + translation: [7, -6, 0.2] - type: urdf name: rock3 uri: package://mrover/urdf/world/rock.urdf.xacro - translation: [ 8, -10, 1 ] + translation: [8, -10, 1] - type: urdf name: rock4 uri: package://mrover/urdf/world/rock.urdf.xacro - translation: [ 9, -2, 0.2 ] \ No newline at end of file + translation: [9, -2, 0.2] diff --git a/config/teleop.yaml b/config/teleop.yaml index b57cdb37d..2158f1ef4 100644 --- a/config/teleop.yaml +++ b/config/teleop.yaml @@ -1,59 +1,70 @@ # You will need to restart basestation.launch for # Any changes to take effect teleop: - ra_joints: ["joint_a", "joint_b", "joint_c", "joint_d", "joint_e"] - + ra_names: ["joint_a", "joint_b", "joint_c", "joint_de_pitch", "joint_de_roll", "allen_key", "gripper"] ra_controls: joint_a: multiplier: 1 slow_mode_multiplier: 0.5 invert: False + xbox_index: 0 joint_b: multiplier: -1 slow_mode_multiplier: 1 - invert: False + invert: True + xbox_index: 1 joint_c: - multiplier: 1 + multiplier: -1 slow_mode_multiplier: 0.6 invert: True - joint_d: - multiplier: 1 + xbox_index: 3 + joint_de_pitch: + multiplier: 0.5 slow_mode_multiplier: 1 invert: False - joint_e: - multiplier: 1 + xbox_index_left: 4 + xbox_index_right: 5 + joint_de_roll: + multiplier: 0.5 slow_mode_multiplier: 1 invert: False - joint_f: - multiplier: 1 - slow_mode_multiplier: 1 - invert: False - finger: + xbox_index_left: 4 + xbox_index_right: 5 + allen_key: multiplier: 1 slow_mode_multiplier: 1 invert: False + # xbox_index: 7 gripper: multiplier: 1 slow_mode_multiplier: 1 invert: False - + # xbox_index: 7 + sa_controls: - sa_joint_1: + sa_x: multiplier: 1 slow_mode_multiplier: 0.5 - sa_joint_2: + xbox_index: 1 + sa_y: multiplier: -1 slow_mode_multiplier: 0.5 - sa_joint_3: + xbox_index: 0 + sa_z: multiplier: -1 slow_mode_multiplier: 0.5 - scoop: + xbox_index: 4 + sampler: multiplier: 1 slow_mode_multiplier: 1.0 - microscope: + xbox_index: 5 + sensor_actuator: multiplier: 1 slow_mode_multiplier: 0.5 - + cache: + multiplier: 1 + xbox_index: 4 + drive_controls: forward_back: multiplier: 1 @@ -63,24 +74,23 @@ teleop: multiplier: 1 twist: multiplier: 0.7 - xbox_mappings: left_js_x: 0 left_js_y: 1 - left_trigger: 2 + right_js_x: 2 + right_js_y: 3 + left_trigger: 4 right_trigger: 5 - right_js_x: 3 - right_js_y: 4 - right_bumper: 5 + a: 0 + b: 1 + x: 3 + y: 2 left_bumper: 4 + right_bumper: 5 d_pad_x: 6 d_pad_y: 7 - a: 0 - b: 1 - x: 2 - y: 3 - + joystick_mappings: left_right: 1 forward_back: 0 @@ -115,3 +125,8 @@ teleop: blah: ["/tf", "/tf_static", "/rosout"] foo: ["/rosout", "/tf"] bar: ["/tf_static", "/rosout", "/tf"] + + ik_multipliers: + x: 1 + y: 1 + z: 1 \ No newline at end of file diff --git a/config/zed/common.yaml b/config/zed/common.yaml index 9ab7c2640..a3a07841e 100644 --- a/config/zed/common.yaml +++ b/config/zed/common.yaml @@ -37,7 +37,7 @@ video: extrinsic_in_camera_frame: true # if `false` extrinsic parameter in `camera_info` will use ROS native frame (X FORWARD, Z UP) instead of the camera frame (Z FORWARD, Y DOWN) [`true` use old behavior as for version < v3.1] depth: - quality: 2 # '0': NONE, '1': PERFORMANCE, '2': QUALITY, '3': ULTRA, '4': NEURAL + quality: 4 # '0': NONE, '1': PERFORMANCE, '2': QUALITY, '3': ULTRA, '4': NEURAL sensing_mode: 0 # '0': STANDARD, '1': FILL (not use FILL for robotic applications) depth_stabilization: 1 # `0`: disabled, `1`: enabled openni_depth_mode: false # 'false': 32bit float meters, 'true': 16bit uchar millimeters diff --git a/data/.gitignore b/data/.gitignore new file mode 100644 index 000000000..d0598ddeb --- /dev/null +++ b/data/.gitignore @@ -0,0 +1,3 @@ +# Compiled ONXX networks +# They are specific to the device they were built on, so they should not be checked in +*.engine diff --git a/data/yolov8n_mallet_bottle_better.onnx b/data/yolov8n_mallet_bottle_better.onnx new file mode 100644 index 000000000..35335cc1c --- /dev/null +++ b/data/yolov8n_mallet_bottle_better.onnx @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:01b717f4c1aebdc31f23cf9f53a5dceb6cb6666745b8ba34056df688a44b263d +size 44720296 diff --git a/deps/imgui/CMakeLists.txt b/deps/imgui/CMakeLists.txt new file mode 100644 index 000000000..ab074f5d9 --- /dev/null +++ b/deps/imgui/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.16) +project(imgui VERSION 1.90 LANGUAGES CXX) + +set(CMAKE_POSITION_INDEPENDENT_CODE ON) + +file(GLOB_RECURSE IMGUI_SOURCES CONFIGURE_DEPENDS ${CMAKE_CURRENT_LIST_DIR}/*.cpp) +add_library(imgui ${IMGUI_SOURCES}) +target_include_directories(imgui PUBLIC ${CMAKE_CURRENT_LIST_DIR}) +target_link_libraries(imgui PUBLIC glfw webgpu) diff --git a/src/simulator/imgui/LICENSE.txt b/deps/imgui/LICENSE.txt similarity index 100% rename from src/simulator/imgui/LICENSE.txt rename to deps/imgui/LICENSE.txt diff --git a/src/simulator/imgui/README.md b/deps/imgui/README.md similarity index 100% rename from src/simulator/imgui/README.md rename to deps/imgui/README.md diff --git a/src/simulator/imgui/backends/imgui_impl_glfw.cpp b/deps/imgui/backends/imgui_impl_glfw.cpp similarity index 100% rename from src/simulator/imgui/backends/imgui_impl_glfw.cpp rename to deps/imgui/backends/imgui_impl_glfw.cpp diff --git a/src/simulator/imgui/backends/imgui_impl_glfw.h b/deps/imgui/backends/imgui_impl_glfw.h similarity index 100% rename from src/simulator/imgui/backends/imgui_impl_glfw.h rename to deps/imgui/backends/imgui_impl_glfw.h diff --git a/src/simulator/imgui/backends/imgui_impl_wgpu.cpp b/deps/imgui/backends/imgui_impl_wgpu.cpp similarity index 100% rename from src/simulator/imgui/backends/imgui_impl_wgpu.cpp rename to deps/imgui/backends/imgui_impl_wgpu.cpp diff --git a/src/simulator/imgui/backends/imgui_impl_wgpu.h b/deps/imgui/backends/imgui_impl_wgpu.h similarity index 100% rename from src/simulator/imgui/backends/imgui_impl_wgpu.h rename to deps/imgui/backends/imgui_impl_wgpu.h diff --git a/src/simulator/imgui/imconfig.h b/deps/imgui/imconfig.h similarity index 100% rename from src/simulator/imgui/imconfig.h rename to deps/imgui/imconfig.h diff --git a/src/simulator/imgui/imgui.cpp b/deps/imgui/imgui.cpp similarity index 100% rename from src/simulator/imgui/imgui.cpp rename to deps/imgui/imgui.cpp diff --git a/src/simulator/imgui/imgui.h b/deps/imgui/imgui.h similarity index 100% rename from src/simulator/imgui/imgui.h rename to deps/imgui/imgui.h diff --git a/src/simulator/imgui/imgui_draw.cpp b/deps/imgui/imgui_draw.cpp similarity index 100% rename from src/simulator/imgui/imgui_draw.cpp rename to deps/imgui/imgui_draw.cpp diff --git a/src/simulator/imgui/imgui_internal.h b/deps/imgui/imgui_internal.h similarity index 100% rename from src/simulator/imgui/imgui_internal.h rename to deps/imgui/imgui_internal.h diff --git a/src/simulator/imgui/imgui_tables.cpp b/deps/imgui/imgui_tables.cpp similarity index 100% rename from src/simulator/imgui/imgui_tables.cpp rename to deps/imgui/imgui_tables.cpp diff --git a/src/simulator/imgui/imgui_widgets.cpp b/deps/imgui/imgui_widgets.cpp similarity index 100% rename from src/simulator/imgui/imgui_widgets.cpp rename to deps/imgui/imgui_widgets.cpp diff --git a/src/simulator/imgui/imstb_rectpack.h b/deps/imgui/imstb_rectpack.h similarity index 100% rename from src/simulator/imgui/imstb_rectpack.h rename to deps/imgui/imstb_rectpack.h diff --git a/src/simulator/imgui/imstb_textedit.h b/deps/imgui/imstb_textedit.h similarity index 100% rename from src/simulator/imgui/imstb_textedit.h rename to deps/imgui/imstb_textedit.h diff --git a/src/simulator/imgui/imstb_truetype.h b/deps/imgui/imstb_truetype.h similarity index 100% rename from src/simulator/imgui/imstb_truetype.h rename to deps/imgui/imstb_truetype.h diff --git a/deps/manif b/deps/manif new file mode 160000 index 000000000..03c497df3 --- /dev/null +++ b/deps/manif @@ -0,0 +1 @@ +Subproject commit 03c497df3364e999cec46fe4f974eae1959a34e1 diff --git a/src/esw/mjbots/README.md b/deps/mjbots/README.md similarity index 100% rename from src/esw/mjbots/README.md rename to deps/mjbots/README.md diff --git a/src/esw/mjbots/moteus/moteus.h b/deps/mjbots/moteus/moteus.h similarity index 96% rename from src/esw/mjbots/moteus/moteus.h rename to deps/mjbots/moteus/moteus.h index b2df3b77d..b1f3d7db1 100644 --- a/src/esw/mjbots/moteus/moteus.h +++ b/deps/mjbots/moteus/moteus.h @@ -424,6 +424,38 @@ class Controller { } + ///////////////////////////////////////// + // RecapturePositionVelocity + + CanFdFrame MakeRecapturePositionVelocity( + const RecapturePositionVelocity::Command& cmd = {}, + const RecapturePositionVelocity::Format* command_override = nullptr, + const Query::Format* query_override = nullptr) { + return MakeFrame(RecapturePositionVelocity(), cmd, + (command_override == nullptr ? + RecapturePositionVelocity::Format() : *command_override), + query_override); + } + + Optional SetRecapturePositionVelocity( + const RecapturePositionVelocity::Command& cmd, + const RecapturePositionVelocity::Format* command_override = nullptr, + const Query::Format* query_override = nullptr) { + return ExecuteSingleCommand( + MakeRecapturePositionVelocity(cmd, command_override, query_override)); + } + + void AsyncRecapturePositionVelocity( + const RecapturePositionVelocity::Command& cmd, + Result* result, CompletionCallback callback, + const RecapturePositionVelocity::Format* command_override = nullptr, + const Query::Format* query_override = nullptr) { + AsyncStartSingleCommand( + MakeRecapturePositionVelocity(cmd, command_override, query_override), + result, callback); + } + + ///////////////////////////////////////// // ClockTrim diff --git a/src/esw/mjbots/moteus/moteus_multiplex.h b/deps/mjbots/moteus/moteus_multiplex.h similarity index 100% rename from src/esw/mjbots/moteus/moteus_multiplex.h rename to deps/mjbots/moteus/moteus_multiplex.h diff --git a/src/esw/mjbots/moteus/moteus_optional.h b/deps/mjbots/moteus/moteus_optional.h similarity index 100% rename from src/esw/mjbots/moteus/moteus_optional.h rename to deps/mjbots/moteus/moteus_optional.h diff --git a/src/esw/mjbots/moteus/moteus_protocol.h b/deps/mjbots/moteus/moteus_protocol.h similarity index 98% rename from src/esw/mjbots/moteus/moteus_protocol.h rename to deps/mjbots/moteus/moteus_protocol.h index 0e0595c4b..dc0cb7920 100644 --- a/src/esw/mjbots/moteus/moteus_protocol.h +++ b/deps/mjbots/moteus/moteus_protocol.h @@ -26,6 +26,7 @@ #ifndef ARDUINO #include +#include #define NaN std::numeric_limits::quiet_NaN(); #else @@ -197,6 +198,7 @@ enum Register : uint16_t { kSetOutputNearest = 0x130, kSetOutputExact = 0x131, kRequireReindex = 0x132, + kRecapturePositionVelocity = 0x133, kDriverFault1 = 0x140, kDriverFault2 = 0x141, @@ -399,7 +401,7 @@ struct Query { // below. if (required_registers > 512) { ::abort(); } - Resolution resolutions[required_registers]; + std::vector resolutions(required_registers); ::memset(&resolutions[0], 0, sizeof(Resolution) * required_registers); for (int16_t this_register = min_register_number, index = 0; @@ -415,7 +417,7 @@ struct Query { } WriteCombiner combiner( frame, 0x10, min_register_number, - resolutions, required_registers); + &resolutions[0], required_registers); for (uint16_t i = 0; i < required_registers; i++) { combiner.MaybeWrite(); } @@ -640,6 +642,7 @@ struct Query { { R::kSetOutputNearest, 3, MP::kInt, }, // { R::kSetOutputExact, 1, MP::kInt, }, // { R::kRequireReindex, 1, MP::kInt, }, + // { R::kRecapturePositionVelocity, 1, MP::kInt, } { R::kDriverFault1, 2, MP::kInt, }, // { R::kDriverFault2, 1, MP::kInt, }, @@ -721,7 +724,7 @@ struct GenericQuery { // below. if (required_registers > 512) { ::abort(); } - Resolution resolutions[required_registers]; + std::vector resolutions(required_registers); ::memset(&resolutions[0], 0, sizeof(Resolution) * required_registers); for (int16_t this_register = min_register_number, index = 0; @@ -737,7 +740,7 @@ struct GenericQuery { } WriteCombiner combiner( frame, 0x10, min_register_number, - resolutions, required_registers); + &resolutions[0], required_registers); for (uint16_t i = 0; i < required_registers; i++) { combiner.MaybeWrite(); } @@ -1150,6 +1153,18 @@ struct RequireReindex { } }; +struct RecapturePositionVelocity { + struct Command {}; + struct Format {}; + + static uint8_t Make(WriteCanData* frame, const Command&, const Format&) { + frame->Write(Multiplex::kWriteInt8 | 0x01); + frame->WriteVaruint(Register::kRecapturePositionVelocity); + frame->Write(1); + return 0; + } +}; + struct DiagnosticWrite { struct Command { int8_t channel = 1; diff --git a/src/esw/mjbots/moteus/moteus_tokenizer.h b/deps/mjbots/moteus/moteus_tokenizer.h similarity index 100% rename from src/esw/mjbots/moteus/moteus_tokenizer.h rename to deps/mjbots/moteus/moteus_tokenizer.h diff --git a/src/esw/mjbots/moteus/moteus_transport.h b/deps/mjbots/moteus/moteus_transport.h similarity index 98% rename from src/esw/mjbots/moteus/moteus_transport.h rename to deps/mjbots/moteus/moteus_transport.h index 976a9fc14..822c3c9d3 100644 --- a/src/esw/mjbots/moteus/moteus_transport.h +++ b/deps/mjbots/moteus/moteus_transport.h @@ -45,6 +45,10 @@ #include "moteus_protocol.h" #include "moteus_tokenizer.h" +#ifdef CANFD_FDF +#define MJBOTS_MOTEUS_ENABLE_SOCKETCAN 1 +#endif + namespace mjbots { namespace moteus { @@ -313,7 +317,8 @@ class TimeoutTransport : public Transport { expected_ok_count++; CHILD_SendCanFdFrame(frames[i]); if (frames[i].reply_required) { - if ((frames[i].destination + 1) > expected_reply_count_.size()) { + if ((frames[i].destination + 1) > + static_cast(expected_reply_count_.size())) { expected_reply_count_.resize(frames[i].destination + 1); } expected_reply_count_[frames[i].destination]++; @@ -528,7 +533,7 @@ class Fdcanusb : public details::TimeoutTransport { virtual ConsumeCount CHILD_ConsumeData( std::vector* replies, - int expected_ok_count, + int /* expected_ok_count */, std::vector* expected_reply_count) override { // Read into our line buffer. const int to_read = sizeof(line_buffer_) - line_buffer_pos_; @@ -620,7 +625,8 @@ class Fdcanusb : public details::TimeoutTransport { } if (expected_reply_count) { - if (this_frame.source < expected_reply_count->size()) { + if (this_frame.source < + static_cast(expected_reply_count->size())) { (*expected_reply_count)[this_frame.source] = std::max( (*expected_reply_count)[this_frame.source] - 1, 0); } @@ -754,6 +760,7 @@ class Fdcanusb : public details::TimeoutTransport { }; +#ifdef MJBOTS_MOTEUS_ENABLE_SOCKETCAN class Socketcan : public details::TimeoutTransport { public: struct Options : details::TimeoutTransport::Options { @@ -836,7 +843,7 @@ class Socketcan : public details::TimeoutTransport { virtual ConsumeCount CHILD_ConsumeData( std::vector* replies, - int expected_ok_count, + int /* expected_ok_count */, std::vector* expected_reply_count) override { struct canfd_frame recv_frame = {}; FailIf(::read(socket_, &recv_frame, sizeof(recv_frame)) < 0, @@ -857,7 +864,8 @@ class Socketcan : public details::TimeoutTransport { this_frame.size = recv_frame.len; if (expected_reply_count) { - if (this_frame.source < expected_reply_count->size()) { + if (this_frame.source < + static_cast(expected_reply_count->size())) { (*expected_reply_count)[this_frame.source] = std::max( (*expected_reply_count)[this_frame.source] - 1, 0); } @@ -878,7 +886,7 @@ class Socketcan : public details::TimeoutTransport { const Options options_; details::FileDescriptor socket_; }; - +#endif // MJBOTS_MOTEUS_ENABLE_SOCKETCAN /// A factory which can create transports given an optional set of /// commandline arguments. @@ -968,6 +976,7 @@ class FdcanusbFactory : public TransportFactory { } }; +#ifdef MJBOTS_MOTEUS_ENABLE_SOCKETCAN class SocketcanFactory : public TransportFactory { public: virtual ~SocketcanFactory() {} @@ -1019,6 +1028,7 @@ class SocketcanFactory : public TransportFactory { return false; } }; +#endif // MJBOTS_MOTEUS_ENABLE_SOCKETCAN class TransportRegistry { public: @@ -1106,7 +1116,9 @@ class TransportRegistry { private: TransportRegistry() { Register(); +#ifdef MJBOTS_MOTEUS_ENABLE_SOCKETCAN Register(); +#endif } std::vector> items_; diff --git a/deps/webgpuhpp/CMakeLists.txt b/deps/webgpuhpp/CMakeLists.txt new file mode 100644 index 000000000..fe9703ece --- /dev/null +++ b/deps/webgpuhpp/CMakeLists.txt @@ -0,0 +1,5 @@ +cmake_minimum_required(VERSION 3.16) +project(webgpu_hpp VERSION 6108 LANGUAGES CXX) + +add_library(webgpu_hpp INTERFACE webgpu.hpp) +target_include_directories(imgui PUBLIC ${CMAKE_CURRENT_LIST_DIR}) diff --git a/src/simulator/webgpu/webgpu.hpp b/deps/webgpuhpp/webgpu.hpp similarity index 100% rename from src/simulator/webgpu/webgpu.hpp rename to deps/webgpuhpp/webgpu.hpp diff --git a/launch/autonomy.launch b/launch/autonomy.launch index 411a9e202..2312591c3 100644 --- a/launch/autonomy.launch +++ b/launch/autonomy.launch @@ -1,5 +1,6 @@ + @@ -7,6 +8,7 @@ + diff --git a/launch/basestation.launch b/launch/basestation.launch index 9a6a18a4d..fc32e47fa 100644 --- a/launch/basestation.launch +++ b/launch/basestation.launch @@ -7,6 +7,7 @@ + @@ -20,4 +21,4 @@ - \ No newline at end of file + diff --git a/launch/brushless_test.launch b/launch/brushless_test.launch new file mode 100644 index 000000000..264915076 --- /dev/null +++ b/launch/brushless_test.launch @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/launch/esw_arm.launch b/launch/esw_arm.launch index 47aefc6ab..734c2f598 100644 --- a/launch/esw_arm.launch +++ b/launch/esw_arm.launch @@ -1,6 +1,6 @@ - + - - - \ No newline at end of file + + + diff --git a/launch/esw_autonomy.launch b/launch/esw_autonomy.launch index 07e0e24e2..69efefdfd 100644 --- a/launch/esw_autonomy.launch +++ b/launch/esw_autonomy.launch @@ -1,6 +1,3 @@ - - - - \ No newline at end of file + diff --git a/launch/esw_base.launch b/launch/esw_base.launch index 3b9ad9bef..c5fb90cb5 100644 --- a/launch/esw_base.launch +++ b/launch/esw_base.launch @@ -1,8 +1,59 @@ - + - - - - + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/launch/esw_science.launch b/launch/esw_science.launch index 0d8635e7d..587d4add4 100644 --- a/launch/esw_science.launch +++ b/launch/esw_science.launch @@ -1,10 +1,14 @@ - - - + + + + + + + \ No newline at end of file diff --git a/launch/jetson_autonomy.launch b/launch/jetson_autonomy.launch index ac64503af..afe24bfde 100644 --- a/launch/jetson_autonomy.launch +++ b/launch/jetson_autonomy.launch @@ -1,6 +1,16 @@ - - - - - \ No newline at end of file + + + + + + + + + + + + + + + diff --git a/launch/jetson_base.launch b/launch/jetson_base.launch index ea71e408e..49a3c6912 100644 --- a/launch/jetson_base.launch +++ b/launch/jetson_base.launch @@ -1,3 +1,6 @@ + + \ No newline at end of file diff --git a/launch/jetson_es.launch b/launch/jetson_es.launch new file mode 100644 index 000000000..3dca9c2e3 --- /dev/null +++ b/launch/jetson_es.launch @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/launch/localization.launch b/launch/localization.launch index c6051a46f..2f14c13ae 100644 --- a/launch/localization.launch +++ b/launch/localization.launch @@ -15,19 +15,20 @@ - + - + - + diff --git a/launch/long_range_cam.launch b/launch/long_range_cam.launch new file mode 100644 index 000000000..aa399145e --- /dev/null +++ b/launch/long_range_cam.launch @@ -0,0 +1,12 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/launch/perception.launch b/launch/perception.launch index 0fcce3c20..b836a753e 100644 --- a/launch/perception.launch +++ b/launch/perception.launch @@ -1,8 +1,17 @@ + - \ No newline at end of file + pkg="nodelet" type="nodelet" name="zed_tag_detector" + args="load mrover/TagDetectorNodelet perception_nodelet_manager" output="screen" /> + + + + + diff --git a/launch/simulator.launch b/launch/simulator.launch index 78ecfbae8..23230736f 100644 --- a/launch/simulator.launch +++ b/launch/simulator.launch @@ -1,16 +1,26 @@ - + + - - - - + - + + + + - + - - \ No newline at end of file + + + + + + + + + + + diff --git a/launch/test_arm_bridge.launch b/launch/test_arm_bridge.launch new file mode 100644 index 000000000..096314afa --- /dev/null +++ b/launch/test_arm_bridge.launch @@ -0,0 +1,12 @@ + + + + + + + + diff --git a/launch/zed.launch b/launch/zed.launch index 20bf3b4a5..4c384eae7 100644 --- a/launch/zed.launch +++ b/launch/zed.launch @@ -6,8 +6,9 @@ + + args="load mrover/ZedNodelet perception_nodelet_manager" output="screen"> diff --git a/launch/zed_test.launch b/launch/zed_test.launch index 38dd234d1..247f1c107 100644 --- a/launch/zed_test.launch +++ b/launch/zed_test.launch @@ -1,16 +1,24 @@ + + + + + + + + @@ -18,14 +26,15 @@ - - + - - \ No newline at end of file + + diff --git a/msg/AutonCommand.msg b/msg/AutonCommand.msg new file mode 100644 index 000000000..7b2628c7d --- /dev/null +++ b/msg/AutonCommand.msg @@ -0,0 +1,2 @@ +bool is_enabled +GPSWaypoint[] waypoints \ No newline at end of file diff --git a/msg/CalibrationStatus.msg b/msg/CalibrationStatus.msg index 190e3d3ae..4a141eeda 100644 --- a/msg/CalibrationStatus.msg +++ b/msg/CalibrationStatus.msg @@ -1,5 +1,2 @@ std_msgs/Header header -uint8 system_calibration -uint8 gyroscope_calibration -uint8 accelerometer_calibration -uint8 magnetometer_calibration \ No newline at end of file +uint8 system_calibration \ No newline at end of file diff --git a/msg/DetectedObject.msg b/msg/DetectedObject.msg deleted file mode 100644 index fcc2d45ca..000000000 --- a/msg/DetectedObject.msg +++ /dev/null @@ -1,4 +0,0 @@ -DetectedObjectType type -float32 detection_confidence -float32 bearing -float32 distance \ No newline at end of file diff --git a/msg/DetectedObjectType.msg b/msg/DetectedObjectType.msg deleted file mode 100644 index 28c2319ff..000000000 --- a/msg/DetectedObjectType.msg +++ /dev/null @@ -1,3 +0,0 @@ -uint8 NO_OBJ=0 -uint8 MALLET=1 -uint8 WATER_BOTTLE=2 \ No newline at end of file diff --git a/msg/GPSWaypoint.msg b/msg/GPSWaypoint.msg index 184684c0d..4befc3c26 100644 --- a/msg/GPSWaypoint.msg +++ b/msg/GPSWaypoint.msg @@ -1,4 +1,4 @@ int8 tag_id float64 latitude_degrees float64 longitude_degrees -WaypointType type \ No newline at end of file +WaypointType type diff --git a/msg/H265Packet.msg b/msg/H265Packet.msg new file mode 100644 index 000000000..dd2331bbe --- /dev/null +++ b/msg/H265Packet.msg @@ -0,0 +1 @@ +uint8[] data diff --git a/msg/IK.msg b/msg/IK.msg index e6803ee8b..2dd6ec8a5 100644 --- a/msg/IK.msg +++ b/msg/IK.msg @@ -1 +1 @@ -geometry_msgs/Pose pose \ No newline at end of file +geometry_msgs/PoseStamped target \ No newline at end of file diff --git a/msg/LongRangeTag.msg b/msg/LongRangeTag.msg index 45790cb74..ae4d49ab8 100644 --- a/msg/LongRangeTag.msg +++ b/msg/LongRangeTag.msg @@ -1,3 +1,4 @@ -int32 id -int32 hitCount +# Message published by the LongRangeTagDetector nodelet. +# Bearing is in degrees from center of image +uint8 id float32 bearing \ No newline at end of file diff --git a/msg/LongRangeTags.msg b/msg/LongRangeTags.msg index 3f0d521b5..4a48ffb9b 100644 --- a/msg/LongRangeTags.msg +++ b/msg/LongRangeTags.msg @@ -1 +1 @@ -LongRangeTag[] tags \ No newline at end of file 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-{"dependencies":{"@tsconfig/node18":"^18.2.2","@vitejs/plugin-vue":"^4.4.0","bootstrap":"^4.6.2","bootstrap-vue":"^2.23.1","vite":"^4.4.11","vue":"^3.3.4","vue-router":"^4.2.5"},"devDependencies":{"sass":"^1.69.2"}} diff --git a/package.xml b/package.xml index 0839b8d8f..7208ccec5 100644 --- a/package.xml +++ b/package.xml @@ -18,7 +18,6 @@ - @@ -50,8 +49,6 @@ message_generation xacro robot_state_publisher - joint_state_publisher - joint_state_publisher_gui message_runtime @@ -80,9 +77,13 @@ - - - - + + + + + + + + - \ No newline at end of file + diff --git a/pkg/libdawn-dev.deb b/pkg/libdawn-dev.deb new file mode 100644 index 000000000..950699c32 --- /dev/null +++ b/pkg/libdawn-dev.deb @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:252984a13ad2dfa510c4414720044fc1f9148d27f27796fbdcbcbc37276bbe7e +size 5208066 diff --git a/pkg/libmanif-dev.deb b/pkg/libmanif-dev.deb new file mode 100644 index 000000000..fd4d93d9d --- /dev/null +++ b/pkg/libmanif-dev.deb @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0d2d9eb466099f021ac8e6291a254906949eadb44dc6796ec0c3e272218e1af5 +size 73452 diff --git a/plugins/gst_websocket_streamer.xml b/plugins/gst_websocket_streamer.xml new file mode 100644 index 000000000..89175d4b7 --- /dev/null +++ b/plugins/gst_websocket_streamer.xml @@ -0,0 +1,6 @@ + + + + \ No newline at end of file diff --git a/plugins/long_range_tag_detector_plugin.xml b/plugins/long_range_tag_detector_plugin.xml new file mode 100644 index 000000000..6a7d82109 --- /dev/null +++ b/plugins/long_range_tag_detector_plugin.xml @@ -0,0 +1,6 @@ + + + + \ No newline at end of file diff --git a/plugins/object_detector_plugin.xml b/plugins/object_detector_plugin.xml new file mode 100644 index 000000000..36ddebcde --- /dev/null +++ b/plugins/object_detector_plugin.xml @@ -0,0 +1,6 @@ + + + + diff --git a/plugins/tag_detector_plugin.xml b/plugins/tag_detector_plugin.xml index 7f9242490..babad0bed 100644 --- a/plugins/tag_detector_plugin.xml +++ b/plugins/tag_detector_plugin.xml @@ -1,6 +1,6 @@ - + + type="mrover::TagDetectorNodelet" + base_class_type="nodelet::Nodelet"> - + \ No newline at end of file diff --git a/plugins/usb_camera_plugin.xml b/plugins/usb_camera_plugin.xml new file mode 100644 index 000000000..bda6b0d86 --- /dev/null +++ b/plugins/usb_camera_plugin.xml @@ -0,0 +1,6 @@ + + + + \ No newline at end of file diff --git a/pyproject.toml b/pyproject.toml index e84b7448c..bc40a70bd 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -14,10 +14,11 @@ dependencies = [ "netifaces==0.11.0", "defusedxml==0.7.1", # MRover dependencies - "Django==4.2.7", + "Django==4.2.11", "empy==3.3.4", - "numpy==1.26.0", + "numpy==1.26.4", "pandas==2.2.0", + "pyarrow==15.0.0", "shapely==2.0.1", "pyserial==3.5", "moteus==0.3.59", @@ -25,6 +26,7 @@ dependencies = [ "aenum==3.1.15", "daphne==4.0.0", "channels==4.0.0", + "opencv-python==4.9.0.80", ] [project.optional-dependencies] diff --git a/science-spectral/.settings/language.settings.xml b/science-spectral/.settings/language.settings.xml new file mode 100644 index 000000000..0f1b8f6fa --- /dev/null +++ b/science-spectral/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/science-spectral/Debug/Core/Src/main.cyclo b/science-spectral/Debug/Core/Src/main.cyclo new file mode 100644 index 000000000..14f4b372c --- /dev/null +++ b/science-spectral/Debug/Core/Src/main.cyclo @@ -0,0 +1,5 @@ +../Core/Src/main.c:71:5:main 3 +../Core/Src/main.c:135:6:SystemClock_Config 3 +../Core/Src/main.c:176:13:MX_I2C1_Init 4 +../Core/Src/main.c:224:13:MX_GPIO_Init 1 +../Core/Src/main.c:265:6:Error_Handler 1 diff --git a/science-spectral/Debug/Core/Src/main.d b/science-spectral/Debug/Core/Src/main.d new file mode 100644 index 000000000..3590bd365 --- /dev/null +++ b/science-spectral/Debug/Core/Src/main.d @@ -0,0 +1,63 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h \ + ../Core/Inc/spectral.h ../Core/Inc/smbus.h +../Core/Inc/main.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: +../Core/Inc/spectral.h: +../Core/Inc/smbus.h: diff --git a/science-spectral/Debug/Core/Src/main.o b/science-spectral/Debug/Core/Src/main.o new file mode 100644 index 000000000..80629176b Binary files /dev/null and b/science-spectral/Debug/Core/Src/main.o differ diff --git a/science-spectral/Debug/Core/Src/main.su b/science-spectral/Debug/Core/Src/main.su new file mode 100644 index 000000000..3162a4a04 --- /dev/null +++ b/science-spectral/Debug/Core/Src/main.su @@ -0,0 +1,5 @@ +../Core/Src/main.c:71:5:main 16 static +../Core/Src/main.c:135:6:SystemClock_Config 96 static +../Core/Src/main.c:176:13:MX_I2C1_Init 8 static +../Core/Src/main.c:224:13:MX_GPIO_Init 48 static +../Core/Src/main.c:265:6:Error_Handler 8 static,ignoring_inline_asm diff --git a/science-spectral/Debug/Core/Src/smbus.cyclo b/science-spectral/Debug/Core/Src/smbus.cyclo new file mode 100644 index 000000000..9155658eb --- /dev/null +++ b/science-spectral/Debug/Core/Src/smbus.cyclo @@ -0,0 +1,7 @@ +../Core/Src/smbus.c:8:8:new_smbus 1 +../Core/Src/smbus.c:25:5:smbus_check_error 2 +../Core/Src/smbus.c:41:6:smbus_read_byte_data 2 +../Core/Src/smbus.c:86:6:smbus_read_word_data 2 +../Core/Src/smbus.c:130:6:smbus_reset 1 +../Core/Src/smbus.c:141:6:smbus_write_byte_data 2 +../Core/Src/smbus.c:176:6:smbus_write_word_data 2 diff --git a/science-spectral/Debug/Core/Src/smbus.d b/science-spectral/Debug/Core/Src/smbus.d new file mode 100644 index 000000000..b2d8ffbee --- /dev/null +++ b/science-spectral/Debug/Core/Src/smbus.d @@ -0,0 +1,60 @@ +Core/Src/smbus.o: ../Core/Src/smbus.c ../Core/Inc/smbus.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Core/Inc/smbus.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Core/Src/smbus.o b/science-spectral/Debug/Core/Src/smbus.o new file mode 100644 index 000000000..9885dc585 Binary files /dev/null and b/science-spectral/Debug/Core/Src/smbus.o differ diff --git a/science-spectral/Debug/Core/Src/smbus.su b/science-spectral/Debug/Core/Src/smbus.su new file mode 100644 index 000000000..a07140c58 --- /dev/null +++ b/science-spectral/Debug/Core/Src/smbus.su @@ -0,0 +1,7 @@ +../Core/Src/smbus.c:8:8:new_smbus 24 static +../Core/Src/smbus.c:25:5:smbus_check_error 16 static +../Core/Src/smbus.c:41:6:smbus_read_byte_data 24 static +../Core/Src/smbus.c:86:6:smbus_read_word_data 32 static +../Core/Src/smbus.c:130:6:smbus_reset 16 static +../Core/Src/smbus.c:141:6:smbus_write_byte_data 32 static +../Core/Src/smbus.c:176:6:smbus_write_word_data 32 static diff --git a/science-spectral/Debug/Core/Src/spectral.cyclo b/science-spectral/Debug/Core/Src/spectral.cyclo new file mode 100644 index 000000000..402e2d6c7 --- /dev/null +++ b/science-spectral/Debug/Core/Src/spectral.cyclo @@ -0,0 +1,7 @@ +../Core/Src/spectral.c:8:11:new_spectral 2 +../Core/Src/spectral.c:21:6:initialize_spectral 1 +../Core/Src/spectral.c:40:6:update_spectral_all_channel_data 2 +../Core/Src/spectral.c:51:6:update_spectral_channel_data 2 +../Core/Src/spectral.c:69:10:get_spectral_channel_data 1 +../Core/Src/spectral.c:82:6:virtual_write_spectral 3 +../Core/Src/spectral.c:109:9:virtual_read_spectral 6 diff --git a/science-spectral/Debug/Core/Src/spectral.d b/science-spectral/Debug/Core/Src/spectral.d new file mode 100644 index 000000000..54a195233 --- /dev/null +++ b/science-spectral/Debug/Core/Src/spectral.d @@ -0,0 +1,62 @@ +Core/Src/spectral.o: ../Core/Src/spectral.c ../Core/Inc/spectral.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h \ + ../Core/Inc/smbus.h +../Core/Inc/spectral.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: +../Core/Inc/smbus.h: diff --git a/science-spectral/Debug/Core/Src/spectral.o b/science-spectral/Debug/Core/Src/spectral.o new file mode 100644 index 000000000..4788b94dd Binary files /dev/null and b/science-spectral/Debug/Core/Src/spectral.o differ diff --git a/science-spectral/Debug/Core/Src/spectral.su b/science-spectral/Debug/Core/Src/spectral.su new file mode 100644 index 000000000..26498932b --- /dev/null +++ b/science-spectral/Debug/Core/Src/spectral.su @@ -0,0 +1,7 @@ +../Core/Src/spectral.c:8:11:new_spectral 24 static +../Core/Src/spectral.c:21:6:initialize_spectral 16 static +../Core/Src/spectral.c:40:6:update_spectral_all_channel_data 24 static +../Core/Src/spectral.c:51:6:update_spectral_channel_data 48 static +../Core/Src/spectral.c:69:10:get_spectral_channel_data 16 static +../Core/Src/spectral.c:82:6:virtual_write_spectral 24 static +../Core/Src/spectral.c:109:9:virtual_read_spectral 32 static diff --git a/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.cyclo b/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.cyclo new file mode 100644 index 000000000..18ee4dc2d --- /dev/null +++ b/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.cyclo @@ -0,0 +1,3 @@ +../Core/Src/stm32g0xx_hal_msp.c:64:6:HAL_MspInit 1 +../Core/Src/stm32g0xx_hal_msp.c:86:6:HAL_I2C_MspInit 3 +../Core/Src/stm32g0xx_hal_msp.c:132:6:HAL_I2C_MspDeInit 2 diff --git a/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.d b/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.d new file mode 100644 index 000000000..8b6f3f75a --- /dev/null +++ b/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.d @@ -0,0 +1,60 @@ +Core/Src/stm32g0xx_hal_msp.o: ../Core/Src/stm32g0xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Core/Inc/main.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.o b/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.o new file mode 100644 index 000000000..ab814a2c0 Binary files /dev/null and b/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.o differ diff --git a/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.su b/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.su new file mode 100644 index 000000000..6af4af91d --- /dev/null +++ b/science-spectral/Debug/Core/Src/stm32g0xx_hal_msp.su @@ -0,0 +1,3 @@ +../Core/Src/stm32g0xx_hal_msp.c:64:6:HAL_MspInit 16 static +../Core/Src/stm32g0xx_hal_msp.c:86:6:HAL_I2C_MspInit 128 static +../Core/Src/stm32g0xx_hal_msp.c:132:6:HAL_I2C_MspDeInit 16 static diff --git a/science-spectral/Debug/Core/Src/stm32g0xx_it.cyclo b/science-spectral/Debug/Core/Src/stm32g0xx_it.cyclo new file mode 100644 index 000000000..bcccd40ec --- /dev/null +++ b/science-spectral/Debug/Core/Src/stm32g0xx_it.cyclo @@ -0,0 +1,5 @@ +../Core/Src/stm32g0xx_it.c:69:6:NMI_Handler 1 +../Core/Src/stm32g0xx_it.c:84:6:HardFault_Handler 1 +../Core/Src/stm32g0xx_it.c:99:6:SVC_Handler 1 +../Core/Src/stm32g0xx_it.c:112:6:PendSV_Handler 1 +../Core/Src/stm32g0xx_it.c:125:6:SysTick_Handler 1 diff --git a/science-spectral/Debug/Core/Src/stm32g0xx_it.d b/science-spectral/Debug/Core/Src/stm32g0xx_it.d new file mode 100644 index 000000000..d8473b0dd --- /dev/null +++ b/science-spectral/Debug/Core/Src/stm32g0xx_it.d @@ -0,0 +1,62 @@ +Core/Src/stm32g0xx_it.o: ../Core/Src/stm32g0xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h \ + ../Core/Inc/stm32g0xx_it.h +../Core/Inc/main.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: +../Core/Inc/stm32g0xx_it.h: diff --git a/science-spectral/Debug/Core/Src/stm32g0xx_it.o b/science-spectral/Debug/Core/Src/stm32g0xx_it.o new file mode 100644 index 000000000..9e13e27f7 Binary files /dev/null and b/science-spectral/Debug/Core/Src/stm32g0xx_it.o differ diff --git a/science-spectral/Debug/Core/Src/stm32g0xx_it.su b/science-spectral/Debug/Core/Src/stm32g0xx_it.su new file mode 100644 index 000000000..8bc2acade --- /dev/null +++ b/science-spectral/Debug/Core/Src/stm32g0xx_it.su @@ -0,0 +1,5 @@ +../Core/Src/stm32g0xx_it.c:69:6:NMI_Handler 8 static +../Core/Src/stm32g0xx_it.c:84:6:HardFault_Handler 8 static +../Core/Src/stm32g0xx_it.c:99:6:SVC_Handler 8 static +../Core/Src/stm32g0xx_it.c:112:6:PendSV_Handler 8 static +../Core/Src/stm32g0xx_it.c:125:6:SysTick_Handler 8 static diff --git a/science-spectral/Debug/Core/Src/subdir.mk b/science-spectral/Debug/Core/Src/subdir.mk new file mode 100644 index 000000000..446f6cc27 --- /dev/null +++ b/science-spectral/Debug/Core/Src/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/main.c \ +../Core/Src/smbus.c \ +../Core/Src/spectral.c \ +../Core/Src/stm32g0xx_hal_msp.c \ +../Core/Src/stm32g0xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32g0xx.c + +C_DEPS += \ +./Core/Src/main.d \ +./Core/Src/smbus.d \ +./Core/Src/spectral.d \ +./Core/Src/stm32g0xx_hal_msp.d \ +./Core/Src/stm32g0xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32g0xx.d + +OBJS += \ +./Core/Src/main.o \ +./Core/Src/smbus.o \ +./Core/Src/spectral.o \ +./Core/Src/stm32g0xx_hal_msp.o \ +./Core/Src/stm32g0xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32g0xx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G0B1xx -c -I../Core/Inc -I../Drivers/STM32G0xx_HAL_Driver/Inc -I../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G0xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/smbus.cyclo ./Core/Src/smbus.d ./Core/Src/smbus.o ./Core/Src/smbus.su ./Core/Src/spectral.cyclo ./Core/Src/spectral.d ./Core/Src/spectral.o ./Core/Src/spectral.su ./Core/Src/stm32g0xx_hal_msp.cyclo ./Core/Src/stm32g0xx_hal_msp.d ./Core/Src/stm32g0xx_hal_msp.o ./Core/Src/stm32g0xx_hal_msp.su ./Core/Src/stm32g0xx_it.cyclo ./Core/Src/stm32g0xx_it.d ./Core/Src/stm32g0xx_it.o ./Core/Src/stm32g0xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32g0xx.cyclo ./Core/Src/system_stm32g0xx.d ./Core/Src/system_stm32g0xx.o ./Core/Src/system_stm32g0xx.su + +.PHONY: clean-Core-2f-Src + diff --git a/science-spectral/Debug/Core/Src/syscalls.cyclo b/science-spectral/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 000000000..d24fe5e87 --- /dev/null +++ b/science-spectral/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:48:5:_getpid 1 +../Core/Src/syscalls.c:53:5:_kill 1 +../Core/Src/syscalls.c:61:6:_exit 1 +../Core/Src/syscalls.c:67:27:_read 2 +../Core/Src/syscalls.c:80:27:_write 2 +../Core/Src/syscalls.c:92:5:_close 1 +../Core/Src/syscalls.c:99:5:_fstat 1 +../Core/Src/syscalls.c:106:5:_isatty 1 +../Core/Src/syscalls.c:112:5:_lseek 1 +../Core/Src/syscalls.c:120:5:_open 1 +../Core/Src/syscalls.c:128:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:142:5:_times 1 +../Core/Src/syscalls.c:148:5:_stat 1 +../Core/Src/syscalls.c:155:5:_link 1 +../Core/Src/syscalls.c:163:5:_fork 1 +../Core/Src/syscalls.c:169:5:_execve 1 diff --git a/science-spectral/Debug/Core/Src/syscalls.d b/science-spectral/Debug/Core/Src/syscalls.d new file mode 100644 index 000000000..e14669a92 --- /dev/null +++ b/science-spectral/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/science-spectral/Debug/Core/Src/syscalls.o b/science-spectral/Debug/Core/Src/syscalls.o new file mode 100644 index 000000000..1dd2564dc Binary files /dev/null and b/science-spectral/Debug/Core/Src/syscalls.o differ diff --git a/science-spectral/Debug/Core/Src/syscalls.su b/science-spectral/Debug/Core/Src/syscalls.su new file mode 100644 index 000000000..d761054fc --- /dev/null +++ b/science-spectral/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 8 static +../Core/Src/syscalls.c:48:5:_getpid 8 static +../Core/Src/syscalls.c:53:5:_kill 16 static +../Core/Src/syscalls.c:61:6:_exit 16 static +../Core/Src/syscalls.c:67:27:_read 32 static +../Core/Src/syscalls.c:80:27:_write 32 static +../Core/Src/syscalls.c:92:5:_close 16 static +../Core/Src/syscalls.c:99:5:_fstat 16 static +../Core/Src/syscalls.c:106:5:_isatty 16 static +../Core/Src/syscalls.c:112:5:_lseek 24 static +../Core/Src/syscalls.c:120:5:_open 20 static +../Core/Src/syscalls.c:128:5:_wait 16 static +../Core/Src/syscalls.c:135:5:_unlink 16 static +../Core/Src/syscalls.c:142:5:_times 16 static +../Core/Src/syscalls.c:148:5:_stat 16 static +../Core/Src/syscalls.c:155:5:_link 16 static +../Core/Src/syscalls.c:163:5:_fork 8 static +../Core/Src/syscalls.c:169:5:_execve 24 static diff --git a/science-spectral/Debug/Core/Src/sysmem.cyclo b/science-spectral/Debug/Core/Src/sysmem.cyclo new file mode 100644 index 000000000..b7286f772 --- /dev/null +++ b/science-spectral/Debug/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 3 diff --git a/science-spectral/Debug/Core/Src/sysmem.d b/science-spectral/Debug/Core/Src/sysmem.d new file mode 100644 index 000000000..9492cfb53 --- /dev/null +++ b/science-spectral/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/science-spectral/Debug/Core/Src/sysmem.o b/science-spectral/Debug/Core/Src/sysmem.o new file mode 100644 index 000000000..b10dbb50c Binary files /dev/null and b/science-spectral/Debug/Core/Src/sysmem.o differ diff --git a/science-spectral/Debug/Core/Src/sysmem.su b/science-spectral/Debug/Core/Src/sysmem.su new file mode 100644 index 000000000..f659b7c15 --- /dev/null +++ b/science-spectral/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 32 static diff --git a/science-spectral/Debug/Core/Src/system_stm32g0xx.cyclo b/science-spectral/Debug/Core/Src/system_stm32g0xx.cyclo new file mode 100644 index 000000000..8eac3bf9f --- /dev/null +++ b/science-spectral/Debug/Core/Src/system_stm32g0xx.cyclo @@ -0,0 +1,2 @@ +../Core/Src/system_stm32g0xx.c:185:6:SystemInit 1 +../Core/Src/system_stm32g0xx.c:233:6:SystemCoreClockUpdate 8 diff --git a/science-spectral/Debug/Core/Src/system_stm32g0xx.d b/science-spectral/Debug/Core/Src/system_stm32g0xx.d new file mode 100644 index 000000000..1bf6c64b6 --- /dev/null +++ b/science-spectral/Debug/Core/Src/system_stm32g0xx.d @@ -0,0 +1,59 @@ +Core/Src/system_stm32g0xx.o: ../Core/Src/system_stm32g0xx.c \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Core/Src/system_stm32g0xx.o b/science-spectral/Debug/Core/Src/system_stm32g0xx.o new file mode 100644 index 000000000..48ec7e7d1 Binary files /dev/null and b/science-spectral/Debug/Core/Src/system_stm32g0xx.o differ diff --git a/science-spectral/Debug/Core/Src/system_stm32g0xx.su b/science-spectral/Debug/Core/Src/system_stm32g0xx.su new file mode 100644 index 000000000..23b0831f8 --- /dev/null +++ b/science-spectral/Debug/Core/Src/system_stm32g0xx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32g0xx.c:185:6:SystemInit 8 static +../Core/Src/system_stm32g0xx.c:233:6:SystemCoreClockUpdate 32 static diff --git a/science-spectral/Debug/Core/Startup/startup_stm32g0b1retx.d b/science-spectral/Debug/Core/Startup/startup_stm32g0b1retx.d new file mode 100644 index 000000000..a33c3395b --- /dev/null +++ b/science-spectral/Debug/Core/Startup/startup_stm32g0b1retx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32g0b1retx.o: \ + ../Core/Startup/startup_stm32g0b1retx.s diff --git a/science-spectral/Debug/Core/Startup/startup_stm32g0b1retx.o b/science-spectral/Debug/Core/Startup/startup_stm32g0b1retx.o new file mode 100644 index 000000000..7f7fb1202 Binary files /dev/null and b/science-spectral/Debug/Core/Startup/startup_stm32g0b1retx.o differ diff --git a/science-spectral/Debug/Core/Startup/subdir.mk b/science-spectral/Debug/Core/Startup/subdir.mk new file mode 100644 index 000000000..185288a1f --- /dev/null +++ b/science-spectral/Debug/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32g0b1retx.s + +S_DEPS += \ +./Core/Startup/startup_stm32g0b1retx.d + +OBJS += \ +./Core/Startup/startup_stm32g0b1retx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m0plus -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32g0b1retx.d ./Core/Startup/startup_stm32g0b1retx.o + +.PHONY: clean-Core-2f-Startup + diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.cyclo new file mode 100644 index 000000000..e98bea305 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.cyclo @@ -0,0 +1,35 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:143:19:HAL_Init 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:180:19:HAL_DeInit 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:206:13:HAL_MspInit 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:217:13:HAL_MspDeInit 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:240:26:HAL_InitTick 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:308:13:HAL_IncTick 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:319:17:HAL_GetTick 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:328:10:HAL_GetTickPrio 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:337:19:HAL_SetTickFreq 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:368:21:HAL_GetTickFreq 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:384:13:HAL_Delay 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:410:13:HAL_SuspendTick 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:426:13:HAL_ResumeTick 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:436:10:HAL_GetHalVersion 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:445:10:HAL_GetREVID 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:454:10:HAL_GetDEVID 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:463:10:HAL_GetUIDw0 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:472:10:HAL_GetUIDw1 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:481:10:HAL_GetUIDw2 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:509:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:518:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:527:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:536:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:572:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:587:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:604:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:616:19:HAL_SYSCFG_EnableVREFBUF 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:642:6:HAL_SYSCFG_DisableVREFBUF 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:652:6:HAL_SYSCFG_EnableIOAnalogSwitchBooster 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:661:6:HAL_SYSCFG_DisableIOAnalogSwitchBooster 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:674:6:HAL_SYSCFG_EnableRemap 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:689:6:HAL_SYSCFG_DisableRemap 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:704:6:HAL_SYSCFG_EnableClampingDiode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:718:6:HAL_SYSCFG_DisableClampingDiode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:735:6:HAL_SYSCFG_StrobeDBattpinsConfig 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.d new file mode 100644 index 000000000..7d0713c2e --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.o new file mode 100644 index 000000000..233ad22bd Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.su new file mode 100644 index 000000000..f3f611c87 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.su @@ -0,0 +1,35 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:143:19:HAL_Init 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:180:19:HAL_DeInit 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:206:13:HAL_MspInit 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:217:13:HAL_MspDeInit 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:240:26:HAL_InitTick 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:308:13:HAL_IncTick 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:319:17:HAL_GetTick 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:328:10:HAL_GetTickPrio 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:337:19:HAL_SetTickFreq 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:368:21:HAL_GetTickFreq 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:384:13:HAL_Delay 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:410:13:HAL_SuspendTick 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:426:13:HAL_ResumeTick 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:436:10:HAL_GetHalVersion 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:445:10:HAL_GetREVID 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:454:10:HAL_GetDEVID 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:463:10:HAL_GetUIDw0 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:472:10:HAL_GetUIDw1 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:481:10:HAL_GetUIDw2 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:509:6:HAL_DBGMCU_EnableDBGStopMode 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:518:6:HAL_DBGMCU_DisableDBGStopMode 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:527:6:HAL_DBGMCU_EnableDBGStandbyMode 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:536:6:HAL_DBGMCU_DisableDBGStandbyMode 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:572:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:587:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:604:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:616:19:HAL_SYSCFG_EnableVREFBUF 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:642:6:HAL_SYSCFG_DisableVREFBUF 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:652:6:HAL_SYSCFG_EnableIOAnalogSwitchBooster 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:661:6:HAL_SYSCFG_DisableIOAnalogSwitchBooster 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:674:6:HAL_SYSCFG_EnableRemap 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:689:6:HAL_SYSCFG_DisableRemap 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:704:6:HAL_SYSCFG_EnableClampingDiode 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:718:6:HAL_SYSCFG_DisableClampingDiode 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c:735:6:HAL_SYSCFG_StrobeDBattpinsConfig 16 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.cyclo new file mode 100644 index 000000000..0f9f18c13 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.cyclo @@ -0,0 +1,26 @@ +../Drivers/CMSIS/Include/core_cm0plus.h:741:22:__NVIC_EnableIRQ 2 +../Drivers/CMSIS/Include/core_cm0plus.h:779:22:__NVIC_DisableIRQ 2 +../Drivers/CMSIS/Include/core_cm0plus.h:798:26:__NVIC_GetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm0plus.h:817:22:__NVIC_SetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm0plus.h:832:22:__NVIC_ClearPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm0plus.h:850:22:__NVIC_SetPriority 2 +../Drivers/CMSIS/Include/core_cm0plus.h:874:26:__NVIC_GetPriority 2 +../Drivers/CMSIS/Include/core_cm0plus.h:985:34:__NVIC_SystemReset 1 +../Drivers/CMSIS/Include/core_cm0plus.h:1056:26:SysTick_Config 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:131:6:HAL_NVIC_SetPriority 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:148:6:HAL_NVIC_EnableIRQ 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:164:6:HAL_NVIC_DisableIRQ 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:177:6:HAL_NVIC_SystemReset 0 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:190:10:HAL_SYSTICK_Config 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:221:10:HAL_NVIC_GetPriority 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:234:6:HAL_NVIC_SetPendingIRQ 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:252:10:HAL_NVIC_GetPendingIRQ 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:268:6:HAL_NVIC_ClearPendingIRQ 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:285:6:HAL_SYSTICK_CLKSourceConfig 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:303:6:HAL_SYSTICK_IRQHandler 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:312:13:HAL_SYSTICK_Callback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:331:6:HAL_MPU_Enable 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:346:6:HAL_MPU_Disable 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:359:6:HAL_MPU_EnableRegion 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:375:6:HAL_MPU_DisableRegion 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:393:6:HAL_MPU_ConfigRegion 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.d new file mode 100644 index 000000000..061c26cf8 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.o new file mode 100644 index 000000000..8ab53b9f9 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.su new file mode 100644 index 000000000..a7fa32c4a --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.su @@ -0,0 +1,26 @@ +../Drivers/CMSIS/Include/core_cm0plus.h:741:22:__NVIC_EnableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm0plus.h:779:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm0plus.h:798:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm0plus.h:817:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm0plus.h:832:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm0plus.h:850:22:__NVIC_SetPriority 24 static +../Drivers/CMSIS/Include/core_cm0plus.h:874:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm0plus.h:985:34:__NVIC_SystemReset 8 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm0plus.h:1056:26:SysTick_Config 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:131:6:HAL_NVIC_SetPriority 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:148:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:164:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:177:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:190:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:221:10:HAL_NVIC_GetPriority 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:234:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:252:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:268:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:285:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:303:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:312:13:HAL_SYSTICK_Callback 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:331:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:346:6:HAL_MPU_Disable 8 static,ignoring_inline_asm +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:359:6:HAL_MPU_EnableRegion 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:375:6:HAL_MPU_DisableRegion 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c:393:6:HAL_MPU_ConfigRegion 16 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.cyclo new file mode 100644 index 000000000..8c64db7f1 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.cyclo @@ -0,0 +1,15 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:152:19:HAL_DMA_Init 6 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:259:19:HAL_DMA_DeInit 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:382:19:HAL_DMA_Start 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:433:19:HAL_DMA_Start_IT 6 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:507:19:HAL_DMA_Abort 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:572:19:HAL_DMA_Abort_IT 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:637:19:HAL_DMA_PollForTransfer 13 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:797:6:HAL_DMA_IRQHandler 13 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:903:19:HAL_DMA_RegisterCallback 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:954:19:HAL_DMA_UnRegisterCallback 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1032:22:HAL_DMA_GetState 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1044:10:HAL_DMA_GetError 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1071:13:DMA_SetConfig 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1118:13:DMA_CalcDMAMUXChannelBaseAndMask 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1164:13:DMA_CalcDMAMUXRequestGenBaseAndMask 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.d new file mode 100644 index 000000000..b5e88887b --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.o new file mode 100644 index 000000000..eb47e7862 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.su new file mode 100644 index 000000000..5cff0b075 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.su @@ -0,0 +1,15 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:152:19:HAL_DMA_Init 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:259:19:HAL_DMA_DeInit 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:382:19:HAL_DMA_Start 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:433:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:507:19:HAL_DMA_Abort 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:572:19:HAL_DMA_Abort_IT 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:637:19:HAL_DMA_PollForTransfer 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:797:6:HAL_DMA_IRQHandler 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:903:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:954:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1032:22:HAL_DMA_GetState 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1044:10:HAL_DMA_GetError 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1071:13:DMA_SetConfig 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1118:13:DMA_CalcDMAMUXChannelBaseAndMask 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c:1164:13:DMA_CalcDMAMUXRequestGenBaseAndMask 24 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.cyclo new file mode 100644 index 000000000..ea79e94c4 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.cyclo @@ -0,0 +1,5 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:95:19:HAL_DMAEx_ConfigMuxSync 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:144:19:HAL_DMAEx_ConfigMuxRequestGenerator 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:203:19:HAL_DMAEx_EnableMuxRequestGenerator 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:231:19:HAL_DMAEx_DisableMuxRequestGenerator 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:259:6:HAL_DMAEx_MUX_IRQHandler 6 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.d new file mode 100644 index 000000000..7fc82db1c --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.o new file mode 100644 index 000000000..45a99c9e6 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.su new file mode 100644 index 000000000..78c4258b7 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.su @@ -0,0 +1,5 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:95:19:HAL_DMAEx_ConfigMuxSync 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:144:19:HAL_DMAEx_ConfigMuxRequestGenerator 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:203:19:HAL_DMAEx_EnableMuxRequestGenerator 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:231:19:HAL_DMAEx_DisableMuxRequestGenerator 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:259:6:HAL_DMAEx_MUX_IRQHandler 16 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.cyclo new file mode 100644 index 000000000..4f8e1a202 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:265:19:HAL_EXTI_GetConfigLine 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:359:19:HAL_EXTI_ClearConfigLine 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:425:19:HAL_EXTI_RegisterCallback 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:460:19:HAL_EXTI_GetHandle 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:501:6:HAL_EXTI_IRQHandler 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:555:10:HAL_EXTI_GetPending 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:599:6:HAL_EXTI_ClearPending 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:635:6:HAL_EXTI_GenerateSWI 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.d new file mode 100644 index 000000000..1700e34f6 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.o new file mode 100644 index 000000000..440b9c927 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.su new file mode 100644 index 000000000..fba6610a0 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:265:19:HAL_EXTI_GetConfigLine 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:359:19:HAL_EXTI_ClearConfigLine 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:425:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:460:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:501:6:HAL_EXTI_IRQHandler 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:555:10:HAL_EXTI_GetPending 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:599:6:HAL_EXTI_ClearPending 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c:635:6:HAL_EXTI_GenerateSWI 32 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.cyclo new file mode 100644 index 000000000..733605b00 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:164:19:HAL_FLASH_Program 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:226:19:HAL_FLASH_Program_IT 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:282:6:HAL_FLASH_IRQHandler 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:382:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:400:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:433:19:HAL_FLASH_Unlock 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:457:19:HAL_FLASH_Lock 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:480:19:HAL_FLASH_OB_Unlock 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:504:19:HAL_FLASH_OB_Lock 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:527:19:HAL_FLASH_OB_Launch 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:572:10:HAL_FLASH_GetError 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:596:19:FLASH_WaitForLastOperation 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:656:13:FLASH_Program_DoubleWord 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:678:24:FLASH_Program_Fast 3 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.d new file mode 100644 index 000000000..ae8f4ac3a --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.o new file mode 100644 index 000000000..aa287053a Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.su new file mode 100644 index 000000000..cb18abf93 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.su @@ -0,0 +1,14 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:164:19:HAL_FLASH_Program 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:226:19:HAL_FLASH_Program_IT 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:282:6:HAL_FLASH_IRQHandler 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:382:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:400:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:433:19:HAL_FLASH_Unlock 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:457:19:HAL_FLASH_Lock 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:480:19:HAL_FLASH_OB_Unlock 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:504:19:HAL_FLASH_OB_Lock 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:527:19:HAL_FLASH_OB_Launch 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:572:10:HAL_FLASH_GetError 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:596:19:FLASH_WaitForLastOperation 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:656:13:FLASH_Program_DoubleWord 32 static,ignoring_inline_asm +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c:678:24:FLASH_Program_Fast 40 static,ignoring_inline_asm diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.cyclo new file mode 100644 index 000000000..9cc58049f --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.cyclo @@ -0,0 +1,27 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:154:19:HAL_FLASHEx_Erase 6 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:226:19:HAL_FLASHEx_Erase_IT 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:297:19:HAL_FLASHEx_OBProgram 13 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:421:6:HAL_FLASHEx_OBGetConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:464:6:HAL_FLASHEx_EnableDebugger 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:476:6:HAL_FLASHEx_DisableDebugger 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:488:10:HAL_FLASHEx_FlashEmptyCheck 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:502:6:HAL_FLASHEx_ForceFlashEmpty 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:524:6:HAL_FLASHEx_EnableSecMemProtection 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:568:13:FLASH_MassErase 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:588:6:FLASH_PageErase 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:622:6:FLASH_FlushCaches 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:658:13:FLASH_OB_WRPConfig 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:701:13:FLASH_OB_GetWRP 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:764:13:FLASH_OB_OptrConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:787:17:FLASH_OB_GetRDP 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:823:17:FLASH_OB_GetUser 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:845:13:FLASH_OB_PCROP1AConfig 10 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:918:13:FLASH_OB_PCROP1BConfig 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:965:13:FLASH_OB_GetPCROP1A 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1004:13:FLASH_OB_GetPCROP1B 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1046:13:FLASH_OB_PCROP2AConfig 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1095:13:FLASH_OB_PCROP2BConfig 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1139:13:FLASH_OB_GetPCROP2A 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1173:13:FLASH_OB_GetPCROP2B 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1215:13:FLASH_OB_SecMemConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1242:13:FLASH_OB_GetSecMem 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.d new file mode 100644 index 000000000..f3cdcc0ae --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.o new file mode 100644 index 000000000..bba092be8 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.su new file mode 100644 index 000000000..885b1932a --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.su @@ -0,0 +1,27 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:154:19:HAL_FLASHEx_Erase 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:226:19:HAL_FLASHEx_Erase_IT 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:297:19:HAL_FLASHEx_OBProgram 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:421:6:HAL_FLASHEx_OBGetConfig 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:464:6:HAL_FLASHEx_EnableDebugger 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:476:6:HAL_FLASHEx_DisableDebugger 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:488:10:HAL_FLASHEx_FlashEmptyCheck 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:502:6:HAL_FLASHEx_ForceFlashEmpty 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:524:6:HAL_FLASHEx_EnableSecMemProtection 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:568:13:FLASH_MassErase 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:588:6:FLASH_PageErase 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:622:6:FLASH_FlushCaches 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:658:13:FLASH_OB_WRPConfig 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:701:13:FLASH_OB_GetWRP 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:764:13:FLASH_OB_OptrConfig 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:787:17:FLASH_OB_GetRDP 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:823:17:FLASH_OB_GetUser 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:845:13:FLASH_OB_PCROP1AConfig 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:918:13:FLASH_OB_PCROP1BConfig 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:965:13:FLASH_OB_GetPCROP1A 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1004:13:FLASH_OB_GetPCROP1B 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1046:13:FLASH_OB_PCROP2AConfig 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1095:13:FLASH_OB_PCROP2BConfig 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1139:13:FLASH_OB_GetPCROP2A 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1173:13:FLASH_OB_GetPCROP2B 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1215:13:FLASH_OB_SecMemConfig 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c:1242:13:FLASH_OB_GetSecMem 32 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.cyclo new file mode 100644 index 000000000..0ef182bc5 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:162:6:HAL_GPIO_Init 17 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:289:6:HAL_GPIO_DeInit 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:370:15:HAL_GPIO_ReadPin 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:404:6:HAL_GPIO_WritePin 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:427:6:HAL_GPIO_TogglePin 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:452:19:HAL_GPIO_LockPin 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:487:6:HAL_GPIO_EXTI_IRQHandler 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:508:13:HAL_GPIO_EXTI_Rising_Callback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:523:13:HAL_GPIO_EXTI_Falling_Callback 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.d new file mode 100644 index 000000000..b88fce34d --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.o new file mode 100644 index 000000000..6d44efd80 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.su new file mode 100644 index 000000000..c58dc74a9 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.su @@ -0,0 +1,9 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:162:6:HAL_GPIO_Init 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:289:6:HAL_GPIO_DeInit 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:370:15:HAL_GPIO_ReadPin 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:404:6:HAL_GPIO_WritePin 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:427:6:HAL_GPIO_TogglePin 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:452:19:HAL_GPIO_LockPin 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:487:6:HAL_GPIO_EXTI_IRQHandler 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:508:13:HAL_GPIO_EXTI_Rising_Callback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c:523:13:HAL_GPIO_EXTI_Falling_Callback 16 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.cyclo new file mode 100644 index 000000000..a7d49b988 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.cyclo @@ -0,0 +1,81 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:535:19:HAL_I2C_Init 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:650:19:HAL_I2C_DeInit 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:696:13:HAL_I2C_MspInit 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:712:13:HAL_I2C_MspDeInit 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1119:19:HAL_I2C_Master_Transmit 13 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1260:19:HAL_I2C_Master_Receive 12 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1378:19:HAL_I2C_Slave_Transmit 17 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1553:19:HAL_I2C_Slave_Receive 12 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1683:19:HAL_I2C_Master_Transmit_IT 6 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1773:19:HAL_I2C_Master_Receive_IT 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1842:19:HAL_I2C_Slave_Transmit_IT 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1906:19:HAL_I2C_Slave_Receive_IT 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1958:19:HAL_I2C_Master_Transmit_DMA 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2121:19:HAL_I2C_Master_Receive_DMA 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2266:19:HAL_I2C_Slave_Transmit_DMA 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2402:19:HAL_I2C_Slave_Receive_DMA 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2511:19:HAL_I2C_Mem_Write 15 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2648:19:HAL_I2C_Mem_Read 15 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2785:19:HAL_I2C_Mem_Write_IT 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2873:19:HAL_I2C_Mem_Read_IT 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2960:19:HAL_I2C_Mem_Write_DMA 10 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3106:19:HAL_I2C_Mem_Read_DMA 10 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3251:19:HAL_I2C_IsDeviceReady 14 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3377:19:HAL_I2C_Master_Seq_Transmit_IT 14 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3491:19:HAL_I2C_Master_Seq_Transmit_DMA 19 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3688:19:HAL_I2C_Master_Seq_Receive_IT 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3775:19:HAL_I2C_Master_Seq_Receive_DMA 12 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3941:19:HAL_I2C_Slave_Seq_Transmit_IT 11 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4041:19:HAL_I2C_Slave_Seq_Transmit_DMA 17 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4225:19:HAL_I2C_Slave_Seq_Receive_IT 11 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4325:19:HAL_I2C_Slave_Seq_Receive_DMA 17 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4505:19:HAL_I2C_EnableListen_IT 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4529:19:HAL_I2C_DisableListen_IT 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4562:19:HAL_I2C_Master_Abort_IT 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4624:6:HAL_I2C_EV_IRQHandler 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4643:6:HAL_I2C_ER_IRQHandler 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4695:13:HAL_I2C_MasterTxCpltCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4711:13:HAL_I2C_MasterRxCpltCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4726:13:HAL_I2C_SlaveTxCpltCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4742:13:HAL_I2C_SlaveRxCpltCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4760:13:HAL_I2C_AddrCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4778:13:HAL_I2C_ListenCpltCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4794:13:HAL_I2C_MemTxCpltCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4810:13:HAL_I2C_MemRxCpltCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4826:13:HAL_I2C_ErrorCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4842:13:HAL_I2C_AbortCpltCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4877:22:HAL_I2C_GetState 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4889:21:HAL_I2C_GetMode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4900:10:HAL_I2C_GetError 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4925:26:I2C_Master_ISR_IT 24 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5076:26:I2C_Mem_ISR_IT 20 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5219:26:I2C_Slave_ISR_IT 25 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5359:26:I2C_Master_ISR_DMA 18 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5499:26:I2C_Mem_ISR_DMA 18 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5647:26:I2C_Slave_ISR_DMA 27 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5791:26:I2C_RequestMemoryWrite 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5846:26:I2C_RequestMemoryRead 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5895:13:I2C_ITAddrCplt 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5990:13:I2C_ITMasterSeqCplt 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6043:13:I2C_ITSlaveSeqCplt 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6117:13:I2C_ITMasterCplt 12 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6260:13:I2C_ITSlaveCplt 26 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6476:13:I2C_ITListenCplt 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6527:13:I2C_ITError 19 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6658:13:I2C_TreatErrorCallback 2 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6696:13:I2C_Flush_TXDR 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6717:13:I2C_DMAMasterTransmitCplt 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6768:13:I2C_DMASlaveTransmitCplt 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6797:13:I2C_DMAMasterReceiveCplt 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6848:13:I2C_DMASlaveReceiveCplt 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6877:13:I2C_DMAError 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6896:13:I2C_DMAAbort 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6926:26:I2C_WaitOnFlagUntilTimeout 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6966:26:I2C_WaitOnTXISFlagUntilTimeout 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7007:26:I2C_WaitOnSTOPFlagUntilTimeout 6 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7045:26:I2C_WaitOnRXNEFlagUntilTimeout 13 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7122:26:I2C_IsErrorOccurred 17 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7263:13:I2C_TransferConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7290:13:I2C_Enable_IRQ 15 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7381:13:I2C_Disable_IRQ 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7444:13:I2C_ConvertOtherXferOptions 3 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.d new file mode 100644 index 000000000..f74ba7e5a --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.o new file mode 100644 index 000000000..c0e230254 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.su new file mode 100644 index 000000000..2a7534fa8 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.su @@ -0,0 +1,81 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:535:19:HAL_I2C_Init 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:650:19:HAL_I2C_DeInit 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:696:13:HAL_I2C_MspInit 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:712:13:HAL_I2C_MspDeInit 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1119:19:HAL_I2C_Master_Transmit 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1260:19:HAL_I2C_Master_Receive 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1378:19:HAL_I2C_Slave_Transmit 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1553:19:HAL_I2C_Slave_Receive 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1683:19:HAL_I2C_Master_Transmit_IT 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1773:19:HAL_I2C_Master_Receive_IT 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1842:19:HAL_I2C_Slave_Transmit_IT 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1906:19:HAL_I2C_Slave_Receive_IT 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:1958:19:HAL_I2C_Master_Transmit_DMA 56 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2121:19:HAL_I2C_Master_Receive_DMA 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2266:19:HAL_I2C_Slave_Transmit_DMA 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2402:19:HAL_I2C_Slave_Receive_DMA 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2511:19:HAL_I2C_Mem_Write 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2648:19:HAL_I2C_Mem_Read 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2785:19:HAL_I2C_Mem_Write_IT 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2873:19:HAL_I2C_Mem_Read_IT 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:2960:19:HAL_I2C_Mem_Write_DMA 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3106:19:HAL_I2C_Mem_Read_DMA 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3251:19:HAL_I2C_IsDeviceReady 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3377:19:HAL_I2C_Master_Seq_Transmit_IT 56 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3491:19:HAL_I2C_Master_Seq_Transmit_DMA 56 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3688:19:HAL_I2C_Master_Seq_Receive_IT 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3775:19:HAL_I2C_Master_Seq_Receive_DMA 56 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:3941:19:HAL_I2C_Slave_Seq_Transmit_IT 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4041:19:HAL_I2C_Slave_Seq_Transmit_DMA 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4225:19:HAL_I2C_Slave_Seq_Receive_IT 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4325:19:HAL_I2C_Slave_Seq_Receive_DMA 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4505:19:HAL_I2C_EnableListen_IT 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4529:19:HAL_I2C_DisableListen_IT 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4562:19:HAL_I2C_Master_Abort_IT 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4624:6:HAL_I2C_EV_IRQHandler 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4643:6:HAL_I2C_ER_IRQHandler 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4695:13:HAL_I2C_MasterTxCpltCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4711:13:HAL_I2C_MasterRxCpltCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4726:13:HAL_I2C_SlaveTxCpltCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4742:13:HAL_I2C_SlaveRxCpltCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4760:13:HAL_I2C_AddrCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4778:13:HAL_I2C_ListenCpltCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4794:13:HAL_I2C_MemTxCpltCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4810:13:HAL_I2C_MemRxCpltCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4826:13:HAL_I2C_ErrorCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4842:13:HAL_I2C_AbortCpltCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4877:22:HAL_I2C_GetState 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4889:21:HAL_I2C_GetMode 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4900:10:HAL_I2C_GetError 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:4925:26:I2C_Master_ISR_IT 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5076:26:I2C_Mem_ISR_IT 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5219:26:I2C_Slave_ISR_IT 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5359:26:I2C_Master_ISR_DMA 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5499:26:I2C_Mem_ISR_DMA 48 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5647:26:I2C_Slave_ISR_DMA 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5791:26:I2C_RequestMemoryWrite 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5846:26:I2C_RequestMemoryRead 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5895:13:I2C_ITAddrCplt 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:5990:13:I2C_ITMasterSeqCplt 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6043:13:I2C_ITSlaveSeqCplt 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6117:13:I2C_ITMasterCplt 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6260:13:I2C_ITSlaveCplt 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6476:13:I2C_ITListenCplt 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6527:13:I2C_ITError 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6658:13:I2C_TreatErrorCallback 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6696:13:I2C_Flush_TXDR 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6717:13:I2C_DMAMasterTransmitCplt 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6768:13:I2C_DMASlaveTransmitCplt 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6797:13:I2C_DMAMasterReceiveCplt 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6848:13:I2C_DMASlaveReceiveCplt 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6877:13:I2C_DMAError 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6896:13:I2C_DMAAbort 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6926:26:I2C_WaitOnFlagUntilTimeout 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:6966:26:I2C_WaitOnTXISFlagUntilTimeout 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7007:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7045:26:I2C_WaitOnRXNEFlagUntilTimeout 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7122:26:I2C_IsErrorOccurred 56 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7263:13:I2C_TransferConfig 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7290:13:I2C_Enable_IRQ 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7381:13:I2C_Disable_IRQ 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c:7444:13:I2C_ConvertOtherXferOptions 16 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.cyclo new file mode 100644 index 000000000..ee116cbdf --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:96:19:HAL_I2CEx_ConfigAnalogFilter 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:140:19:HAL_I2CEx_ConfigDigitalFilter 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:208:19:HAL_I2CEx_EnableWakeUp 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:247:19:HAL_I2CEx_DisableWakeUp 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:312:6:HAL_I2CEx_EnableFastModePlus 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:339:6:HAL_I2CEx_DisableFastModePlus 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.d new file mode 100644 index 000000000..2eebd1db7 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.o new file mode 100644 index 000000000..ae098979c Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.su new file mode 100644 index 000000000..8f7d56482 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.su @@ -0,0 +1,6 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:96:19:HAL_I2CEx_ConfigAnalogFilter 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:140:19:HAL_I2CEx_ConfigDigitalFilter 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:208:19:HAL_I2CEx_EnableWakeUp 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:247:19:HAL_I2CEx_DisableWakeUp 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:312:6:HAL_I2CEx_EnableFastModePlus 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c:339:6:HAL_I2CEx_DisableFastModePlus 24 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.cyclo new file mode 100644 index 000000000..c75e949e5 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.cyclo @@ -0,0 +1,12 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:73:6:HAL_PWR_DeInit 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:228:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:238:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:262:6:HAL_PWR_EnableWakeUpPin 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:284:6:HAL_PWR_DisableWakeUpPin 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:318:6:HAL_PWR_EnterSLEEPMode 6 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:398:6:HAL_PWR_EnterSTOPMode 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:453:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:480:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:494:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:508:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:521:6:HAL_PWR_DisableSEVOnPend 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.d new file mode 100644 index 000000000..df09da27f --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.o new file mode 100644 index 000000000..6efc53dc3 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.su new file mode 100644 index 000000000..fb4170396 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.su @@ -0,0 +1,12 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:73:6:HAL_PWR_DeInit 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:228:6:HAL_PWR_EnableBkUpAccess 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:238:6:HAL_PWR_DisableBkUpAccess 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:262:6:HAL_PWR_EnableWakeUpPin 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:284:6:HAL_PWR_DisableWakeUpPin 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:318:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:398:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:453:6:HAL_PWR_EnterSTANDBYMode 8 static,ignoring_inline_asm +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:480:6:HAL_PWR_EnableSleepOnExit 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:494:6:HAL_PWR_DisableSleepOnExit 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:508:6:HAL_PWR_EnableSEVOnPend 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c:521:6:HAL_PWR_DisableSEVOnPend 8 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.cyclo new file mode 100644 index 000000000..3afd9edbe --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.cyclo @@ -0,0 +1,34 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:131:6:HAL_PWREx_EnableBatteryCharging 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:146:6:HAL_PWREx_DisableBatteryCharging 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:159:6:HAL_PWREx_EnablePORMonitorSampling 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:169:6:HAL_PWREx_DisablePORMonitorSampling 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:187:19:HAL_PWREx_ConfigPVD 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:233:6:HAL_PWREx_EnablePVD 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:243:6:HAL_PWREx_DisablePVD 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:255:6:HAL_PWREx_EnableVddUSB 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:264:6:HAL_PWREx_DisableVddUSB 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:276:6:HAL_PWREx_EnableVddIO2 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:286:6:HAL_PWREx_DisableVddIO2 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:297:6:HAL_PWREx_EnablePVMUSB 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:306:6:HAL_PWREx_DisablePVMUSB 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:325:19:HAL_PWREx_ConfigPVM 6 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:381:6:HAL_PWREx_EnableInternalWakeUpLine 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:390:6:HAL_PWREx_DisableInternalWakeUpLine 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:414:19:HAL_PWREx_EnableGPIOPullUp 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:476:19:HAL_PWREx_DisableGPIOPullUp 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:538:19:HAL_PWREx_EnableGPIOPullDown 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:600:19:HAL_PWREx_DisableGPIOPullDown 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:653:6:HAL_PWREx_EnablePullUpPullDownConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:664:6:HAL_PWREx_DisablePullUpPullDownConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:676:6:HAL_PWREx_EnableSRAMRetention 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:688:6:HAL_PWREx_DisableSRAMRetention 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:704:6:HAL_PWREx_EnableFlashPowerDown 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:722:6:HAL_PWREx_DisableFlashPowerDown 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:736:10:HAL_PWREx_GetVoltageRange 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:762:19:HAL_PWREx_ControlVoltageScaling 4 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:803:6:HAL_PWREx_EnableLowPowerRunMode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:818:19:HAL_PWREx_DisableLowPowerRunMode 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:860:6:HAL_PWREx_EnterSHUTDOWNMode 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:884:6:HAL_PWREx_PVD_PVM_IRQHandler 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:931:13:HAL_PWREx_PVD_PVM_Rising_Callback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:942:13:HAL_PWREx_PVD_PVM_Falling_Callback 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.d new file mode 100644 index 000000000..841e7f968 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.o new file mode 100644 index 000000000..c86806c05 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.su new file mode 100644 index 000000000..b42c9482d --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.su @@ -0,0 +1,34 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:131:6:HAL_PWREx_EnableBatteryCharging 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:146:6:HAL_PWREx_DisableBatteryCharging 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:159:6:HAL_PWREx_EnablePORMonitorSampling 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:169:6:HAL_PWREx_DisablePORMonitorSampling 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:187:19:HAL_PWREx_ConfigPVD 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:233:6:HAL_PWREx_EnablePVD 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:243:6:HAL_PWREx_DisablePVD 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:255:6:HAL_PWREx_EnableVddUSB 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:264:6:HAL_PWREx_DisableVddUSB 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:276:6:HAL_PWREx_EnableVddIO2 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:286:6:HAL_PWREx_DisableVddIO2 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:297:6:HAL_PWREx_EnablePVMUSB 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:306:6:HAL_PWREx_DisablePVMUSB 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:325:19:HAL_PWREx_ConfigPVM 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:381:6:HAL_PWREx_EnableInternalWakeUpLine 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:390:6:HAL_PWREx_DisableInternalWakeUpLine 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:414:19:HAL_PWREx_EnableGPIOPullUp 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:476:19:HAL_PWREx_DisableGPIOPullUp 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:538:19:HAL_PWREx_EnableGPIOPullDown 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:600:19:HAL_PWREx_DisableGPIOPullDown 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:653:6:HAL_PWREx_EnablePullUpPullDownConfig 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:664:6:HAL_PWREx_DisablePullUpPullDownConfig 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:676:6:HAL_PWREx_EnableSRAMRetention 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:688:6:HAL_PWREx_DisableSRAMRetention 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:704:6:HAL_PWREx_EnableFlashPowerDown 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:722:6:HAL_PWREx_DisableFlashPowerDown 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:736:10:HAL_PWREx_GetVoltageRange 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:762:19:HAL_PWREx_ControlVoltageScaling 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:803:6:HAL_PWREx_EnableLowPowerRunMode 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:818:19:HAL_PWREx_DisableLowPowerRunMode 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:860:6:HAL_PWREx_EnterSHUTDOWNMode 8 static,ignoring_inline_asm +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:884:6:HAL_PWREx_PVD_PVM_IRQHandler 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:931:13:HAL_PWREx_PVD_PVM_Rising_Callback 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c:942:13:HAL_PWREx_PVD_PVM_Falling_Callback 8 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.cyclo new file mode 100644 index 000000000..4b018463a --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h:1793:26:LL_RCC_GetAPB1Prescaler 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:217:19:HAL_RCC_DeInit 8 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:309:19:HAL_RCC_OscConfig 76 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:805:19:HAL_RCC_ClockConfig 23 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1040:6:HAL_RCC_MCOConfig 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1128:10:HAL_RCC_GetSysClockFreq 7 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1196:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1207:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1220:6:HAL_RCC_GetOscConfig 9 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1323:6:HAL_RCC_GetClockConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1356:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1372:6:HAL_RCC_EnableLSECSS 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1383:6:HAL_RCC_DisableLSECSS 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1393:6:HAL_RCC_NMI_IRQHandler 3 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1419:13:HAL_RCC_CSSCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1430:13:HAL_RCC_LSECSSCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1443:10:HAL_RCC_GetResetSource 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.d new file mode 100644 index 000000000..86f85c613 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.o new file mode 100644 index 000000000..2e957ec56 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.su new file mode 100644 index 000000000..4a04221cf --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.su @@ -0,0 +1,17 @@ +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h:1793:26:LL_RCC_GetAPB1Prescaler 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:217:19:HAL_RCC_DeInit 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:309:19:HAL_RCC_OscConfig 40 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:805:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1040:6:HAL_RCC_MCOConfig 56 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1128:10:HAL_RCC_GetSysClockFreq 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1196:10:HAL_RCC_GetHCLKFreq 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1207:10:HAL_RCC_GetPCLK1Freq 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1220:6:HAL_RCC_GetOscConfig 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1323:6:HAL_RCC_GetClockConfig 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1356:6:HAL_RCC_EnableCSS 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1372:6:HAL_RCC_EnableLSECSS 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1383:6:HAL_RCC_DisableLSECSS 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1393:6:HAL_RCC_NMI_IRQHandler 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1419:13:HAL_RCC_CSSCallback 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1430:13:HAL_RCC_LSECSSCallback 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c:1443:10:HAL_RCC_GetResetSource 16 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.cyclo b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.cyclo new file mode 100644 index 000000000..e7d1156fd --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:112:19:HAL_RCCEx_PeriphCLKConfig 37 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:469:6:HAL_RCCEx_GetPeriphCLKConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:610:10:HAL_RCCEx_GetPeriphCLKFreq 132 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1216:6:HAL_RCCEx_EnableLSCO 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1263:6:HAL_RCCEx_DisableLSCO 5 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1370:6:HAL_RCCEx_CRSConfig 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1412:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1422:6:HAL_RCCEx_CRSGetSynchronizationInfo 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1455:10:HAL_RCCEx_CRSWaitSynchronization 11 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1538:6:HAL_RCCEx_CRS_IRQHandler 12 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1603:13:HAL_RCCEx_CRS_SyncOkCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1614:13:HAL_RCCEx_CRS_SyncWarnCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1625:13:HAL_RCCEx_CRS_ExpectedSyncCallback 1 +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1641:13:HAL_RCCEx_CRS_ErrorCallback 1 diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.d new file mode 100644 index 000000000..fbb5aebfc --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.o new file mode 100644 index 000000000..d40b16c0c Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.su b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.su new file mode 100644 index 000000000..87eae1dca --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.su @@ -0,0 +1,14 @@ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:112:19:HAL_RCCEx_PeriphCLKConfig 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:469:6:HAL_RCCEx_GetPeriphCLKConfig 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:610:10:HAL_RCCEx_GetPeriphCLKFreq 32 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1216:6:HAL_RCCEx_EnableLSCO 56 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1263:6:HAL_RCCEx_DisableLSCO 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1370:6:HAL_RCCEx_CRSConfig 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1412:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1422:6:HAL_RCCEx_CRSGetSynchronizationInfo 16 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1455:10:HAL_RCCEx_CRSWaitSynchronization 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1538:6:HAL_RCCEx_CRS_IRQHandler 24 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1603:13:HAL_RCCEx_CRS_SyncOkCallback 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1614:13:HAL_RCCEx_CRS_SyncWarnCallback 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1625:13:HAL_RCCEx_CRS_ExpectedSyncCallback 8 static +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c:1641:13:HAL_RCCEx_CRS_ErrorCallback 16 static diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.d new file mode 100644 index 000000000..4dffcd6ef --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.o new file mode 100644 index 000000000..fe6c696e9 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.d new file mode 100644 index 000000000..2cce84cc9 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.d @@ -0,0 +1,60 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + ../Core/Inc/stm32g0xx_hal_conf.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + ../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +../Core/Inc/stm32g0xx_hal_conf.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h: +../Drivers/CMSIS/Include/core_cm0plus.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +../Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.o new file mode 100644 index 000000000..787db3b1e Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.d new file mode 100644 index 000000000..62fc38352 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.d @@ -0,0 +1,2 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.o new file mode 100644 index 000000000..730dad148 Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.d b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.d new file mode 100644 index 000000000..47784b674 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.d @@ -0,0 +1,2 @@ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.o: \ + ../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.o b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.o new file mode 100644 index 000000000..d2f260f9c Binary files /dev/null and b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.o differ diff --git a/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/subdir.mk b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 000000000..80fc40400 --- /dev/null +++ b/science-spectral/Debug/Drivers/STM32G0xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,78 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c \ +../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c + +C_DEPS += \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.d \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.d + +OBJS += \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.o \ +./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.o + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32G0xx_HAL_Driver/Src/%.o Drivers/STM32G0xx_HAL_Driver/Src/%.su Drivers/STM32G0xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32G0xx_HAL_Driver/Src/%.c Drivers/STM32G0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G0B1xx -c -I../Core/Inc -I../Drivers/STM32G0xx_HAL_Driver/Inc -I../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G0xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32G0xx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32G0xx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.su ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.cyclo ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.d ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.o ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.su + +.PHONY: clean-Drivers-2f-STM32G0xx_HAL_Driver-2f-Src + diff --git a/science-spectral/Debug/makefile b/science-spectral/Debug/makefile new file mode 100644 index 000000000..addb6b46c --- /dev/null +++ b/science-spectral/Debug/makefile @@ -0,0 +1,109 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Drivers/STM32G0xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := science-spectral +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +science-spectral.elf \ + +MAP_FILES += \ +science-spectral.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +science-spectral.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: science-spectral.elf secondary-outputs + +# Tool invocations +science-spectral.elf science-spectral.map: $(OBJS) $(USER_OBJS) C:\Users\isabe\Documents\rover\mrover-ros\science-spectral\STM32G0B1RETX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-g++ -o "science-spectral.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0plus -T"C:\Users\isabe\Documents\rover\mrover-ros\science-spectral\STM32G0B1RETX_FLASH.ld" --specs=nosys.specs -Wl,-Map="science-spectral.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +science-spectral.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "science-spectral.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) default.size.stdout science-spectral.elf science-spectral.list science-spectral.map + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/science-spectral/Debug/objects.list b/science-spectral/Debug/objects.list new file mode 100644 index 000000000..24b41d546 --- /dev/null +++ b/science-spectral/Debug/objects.list @@ -0,0 +1,27 @@ +"./Core/Src/main.o" +"./Core/Src/smbus.o" +"./Core/Src/spectral.o" +"./Core/Src/stm32g0xx_hal_msp.o" +"./Core/Src/stm32g0xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32g0xx.o" +"./Core/Startup/startup_stm32g0b1retx.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.o" +"./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.o" diff --git a/science-spectral/Debug/objects.mk b/science-spectral/Debug/objects.mk new file mode 100644 index 000000000..5e6c2bd19 --- /dev/null +++ b/science-spectral/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/science-spectral/Debug/science-spectral.elf b/science-spectral/Debug/science-spectral.elf new file mode 100644 index 000000000..0f52c4347 Binary files /dev/null and b/science-spectral/Debug/science-spectral.elf differ diff --git a/science-spectral/Debug/science-spectral.list b/science-spectral/Debug/science-spectral.list new file mode 100644 index 000000000..e3d244d15 --- /dev/null +++ b/science-spectral/Debug/science-spectral.list @@ -0,0 +1,15207 @@ + +science-spectral.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000000bc 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000050ac 080000bc 080000bc 000100bc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000040 08005168 08005168 00015168 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 080051a8 080051a8 0002005c 2**0 + CONTENTS + 4 .ARM 00000000 080051a8 080051a8 0002005c 2**0 + CONTENTS + 5 .preinit_array 00000000 080051a8 080051a8 0002005c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 080051a8 080051a8 000151a8 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 080051ac 080051ac 000151ac 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 0000005c 20000000 080051b0 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000001d4 2000005c 0800520c 0002005c 2**2 + ALLOC + 10 ._user_heap_stack 00000600 20000230 0800520c 00020230 2**0 + ALLOC + 11 .ARM.attributes 00000028 00000000 00000000 0002005c 2**0 + CONTENTS, READONLY + 12 .comment 00000043 00000000 00000000 00020084 2**0 + CONTENTS, READONLY + 13 .debug_info 0000a2fe 00000000 00000000 000200c7 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_abbrev 00001fad 00000000 00000000 0002a3c5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_aranges 00000a00 00000000 00000000 0002c378 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_rnglists 000007a2 00000000 00000000 0002cd78 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_macro 0001b87e 00000000 00000000 0002d51a 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_line 0000dd57 00000000 00000000 00048d98 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_str 000ad9b3 00000000 00000000 00056aef 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_frame 00002528 00000000 00000000 001044a4 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000069 00000000 00000000 001069cc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080000bc <__do_global_dtors_aux>: + 80000bc: b510 push {r4, lr} + 80000be: 4c06 ldr r4, [pc, #24] ; (80000d8 <__do_global_dtors_aux+0x1c>) + 80000c0: 7823 ldrb r3, [r4, #0] + 80000c2: 2b00 cmp r3, #0 + 80000c4: d107 bne.n 80000d6 <__do_global_dtors_aux+0x1a> + 80000c6: 4b05 ldr r3, [pc, #20] ; (80000dc <__do_global_dtors_aux+0x20>) + 80000c8: 2b00 cmp r3, #0 + 80000ca: d002 beq.n 80000d2 <__do_global_dtors_aux+0x16> + 80000cc: 4804 ldr r0, [pc, #16] ; (80000e0 <__do_global_dtors_aux+0x24>) + 80000ce: e000 b.n 80000d2 <__do_global_dtors_aux+0x16> + 80000d0: bf00 nop + 80000d2: 2301 movs r3, #1 + 80000d4: 7023 strb r3, [r4, #0] + 80000d6: bd10 pop {r4, pc} + 80000d8: 2000005c .word 0x2000005c + 80000dc: 00000000 .word 0x00000000 + 80000e0: 08005150 .word 0x08005150 + +080000e4 : + 80000e4: 4b04 ldr r3, [pc, #16] ; (80000f8 ) + 80000e6: b510 push {r4, lr} + 80000e8: 2b00 cmp r3, #0 + 80000ea: d003 beq.n 80000f4 + 80000ec: 4903 ldr r1, [pc, #12] ; (80000fc ) + 80000ee: 4804 ldr r0, [pc, #16] ; (8000100 ) + 80000f0: e000 b.n 80000f4 + 80000f2: bf00 nop + 80000f4: bd10 pop {r4, pc} + 80000f6: 46c0 nop ; (mov r8, r8) + 80000f8: 00000000 .word 0x00000000 + 80000fc: 20000060 .word 0x20000060 + 8000100: 08005150 .word 0x08005150 + +08000104 <__udivsi3>: + 8000104: 2200 movs r2, #0 + 8000106: 0843 lsrs r3, r0, #1 + 8000108: 428b cmp r3, r1 + 800010a: d374 bcc.n 80001f6 <__udivsi3+0xf2> + 800010c: 0903 lsrs r3, r0, #4 + 800010e: 428b cmp r3, r1 + 8000110: d35f bcc.n 80001d2 <__udivsi3+0xce> + 8000112: 0a03 lsrs r3, r0, #8 + 8000114: 428b cmp r3, r1 + 8000116: d344 bcc.n 80001a2 <__udivsi3+0x9e> + 8000118: 0b03 lsrs r3, r0, #12 + 800011a: 428b cmp r3, r1 + 800011c: d328 bcc.n 8000170 <__udivsi3+0x6c> + 800011e: 0c03 lsrs r3, r0, #16 + 8000120: 428b cmp r3, r1 + 8000122: d30d bcc.n 8000140 <__udivsi3+0x3c> + 8000124: 22ff movs r2, #255 ; 0xff + 8000126: 0209 lsls r1, r1, #8 + 8000128: ba12 rev r2, r2 + 800012a: 0c03 lsrs r3, r0, #16 + 800012c: 428b cmp r3, r1 + 800012e: d302 bcc.n 8000136 <__udivsi3+0x32> + 8000130: 1212 asrs r2, r2, #8 + 8000132: 0209 lsls r1, r1, #8 + 8000134: d065 beq.n 8000202 <__udivsi3+0xfe> + 8000136: 0b03 lsrs r3, r0, #12 + 8000138: 428b cmp r3, r1 + 800013a: d319 bcc.n 8000170 <__udivsi3+0x6c> + 800013c: e000 b.n 8000140 <__udivsi3+0x3c> + 800013e: 0a09 lsrs r1, r1, #8 + 8000140: 0bc3 lsrs r3, r0, #15 + 8000142: 428b cmp r3, r1 + 8000144: d301 bcc.n 800014a <__udivsi3+0x46> + 8000146: 03cb lsls r3, r1, #15 + 8000148: 1ac0 subs r0, r0, r3 + 800014a: 4152 adcs r2, r2 + 800014c: 0b83 lsrs r3, r0, #14 + 800014e: 428b cmp r3, r1 + 8000150: d301 bcc.n 8000156 <__udivsi3+0x52> + 8000152: 038b lsls r3, r1, #14 + 8000154: 1ac0 subs r0, r0, r3 + 8000156: 4152 adcs r2, r2 + 8000158: 0b43 lsrs r3, r0, #13 + 800015a: 428b cmp r3, r1 + 800015c: d301 bcc.n 8000162 <__udivsi3+0x5e> + 800015e: 034b lsls r3, r1, #13 + 8000160: 1ac0 subs r0, r0, r3 + 8000162: 4152 adcs r2, r2 + 8000164: 0b03 lsrs r3, r0, #12 + 8000166: 428b cmp r3, r1 + 8000168: d301 bcc.n 800016e <__udivsi3+0x6a> + 800016a: 030b lsls r3, r1, #12 + 800016c: 1ac0 subs r0, r0, r3 + 800016e: 4152 adcs r2, r2 + 8000170: 0ac3 lsrs r3, r0, #11 + 8000172: 428b cmp r3, r1 + 8000174: d301 bcc.n 800017a <__udivsi3+0x76> + 8000176: 02cb lsls r3, r1, #11 + 8000178: 1ac0 subs r0, r0, r3 + 800017a: 4152 adcs r2, r2 + 800017c: 0a83 lsrs r3, r0, #10 + 800017e: 428b cmp r3, r1 + 8000180: d301 bcc.n 8000186 <__udivsi3+0x82> + 8000182: 028b lsls r3, r1, #10 + 8000184: 1ac0 subs r0, r0, r3 + 8000186: 4152 adcs r2, r2 + 8000188: 0a43 lsrs r3, r0, #9 + 800018a: 428b cmp r3, r1 + 800018c: d301 bcc.n 8000192 <__udivsi3+0x8e> + 800018e: 024b lsls r3, r1, #9 + 8000190: 1ac0 subs r0, r0, r3 + 8000192: 4152 adcs r2, r2 + 8000194: 0a03 lsrs r3, r0, #8 + 8000196: 428b cmp r3, r1 + 8000198: d301 bcc.n 800019e <__udivsi3+0x9a> + 800019a: 020b lsls r3, r1, #8 + 800019c: 1ac0 subs r0, r0, r3 + 800019e: 4152 adcs r2, r2 + 80001a0: d2cd bcs.n 800013e <__udivsi3+0x3a> + 80001a2: 09c3 lsrs r3, r0, #7 + 80001a4: 428b cmp r3, r1 + 80001a6: d301 bcc.n 80001ac <__udivsi3+0xa8> + 80001a8: 01cb lsls r3, r1, #7 + 80001aa: 1ac0 subs r0, r0, r3 + 80001ac: 4152 adcs r2, r2 + 80001ae: 0983 lsrs r3, r0, #6 + 80001b0: 428b cmp r3, r1 + 80001b2: d301 bcc.n 80001b8 <__udivsi3+0xb4> + 80001b4: 018b lsls r3, r1, #6 + 80001b6: 1ac0 subs r0, r0, r3 + 80001b8: 4152 adcs r2, r2 + 80001ba: 0943 lsrs r3, r0, #5 + 80001bc: 428b cmp r3, r1 + 80001be: d301 bcc.n 80001c4 <__udivsi3+0xc0> + 80001c0: 014b lsls r3, r1, #5 + 80001c2: 1ac0 subs r0, r0, r3 + 80001c4: 4152 adcs r2, r2 + 80001c6: 0903 lsrs r3, r0, #4 + 80001c8: 428b cmp r3, r1 + 80001ca: d301 bcc.n 80001d0 <__udivsi3+0xcc> + 80001cc: 010b lsls r3, r1, #4 + 80001ce: 1ac0 subs r0, r0, r3 + 80001d0: 4152 adcs r2, r2 + 80001d2: 08c3 lsrs r3, r0, #3 + 80001d4: 428b cmp r3, r1 + 80001d6: d301 bcc.n 80001dc <__udivsi3+0xd8> + 80001d8: 00cb lsls r3, r1, #3 + 80001da: 1ac0 subs r0, r0, r3 + 80001dc: 4152 adcs r2, r2 + 80001de: 0883 lsrs r3, r0, #2 + 80001e0: 428b cmp r3, r1 + 80001e2: d301 bcc.n 80001e8 <__udivsi3+0xe4> + 80001e4: 008b lsls r3, r1, #2 + 80001e6: 1ac0 subs r0, r0, r3 + 80001e8: 4152 adcs r2, r2 + 80001ea: 0843 lsrs r3, r0, #1 + 80001ec: 428b cmp r3, r1 + 80001ee: d301 bcc.n 80001f4 <__udivsi3+0xf0> + 80001f0: 004b lsls r3, r1, #1 + 80001f2: 1ac0 subs r0, r0, r3 + 80001f4: 4152 adcs r2, r2 + 80001f6: 1a41 subs r1, r0, r1 + 80001f8: d200 bcs.n 80001fc <__udivsi3+0xf8> + 80001fa: 4601 mov r1, r0 + 80001fc: 4152 adcs r2, r2 + 80001fe: 4610 mov r0, r2 + 8000200: 4770 bx lr + 8000202: e7ff b.n 8000204 <__udivsi3+0x100> + 8000204: b501 push {r0, lr} + 8000206: 2000 movs r0, #0 + 8000208: f000 f806 bl 8000218 <__aeabi_idiv0> + 800020c: bd02 pop {r1, pc} + 800020e: 46c0 nop ; (mov r8, r8) + +08000210 <__aeabi_uidivmod>: + 8000210: 2900 cmp r1, #0 + 8000212: d0f7 beq.n 8000204 <__udivsi3+0x100> + 8000214: e776 b.n 8000104 <__udivsi3> + 8000216: 4770 bx lr + +08000218 <__aeabi_idiv0>: + 8000218: 4770 bx lr + 800021a: 46c0 nop ; (mov r8, r8) + +0800021c
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 800021c: b580 push {r7, lr} + 800021e: b082 sub sp, #8 + 8000220: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000222: f000 fd03 bl 8000c2c + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000226: f000 f84b bl 80002c0 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 800022a: f000 f8d1 bl 80003d0 + MX_I2C1_Init(); + 800022e: f000 f88f bl 8000350 + /* USER CODE BEGIN 2 */ + smbus = new_smbus(&hi2c1, false); + 8000232: 4b1f ldr r3, [pc, #124] ; (80002b0 ) + 8000234: 2100 movs r1, #0 + 8000236: 0018 movs r0, r3 + 8000238: f000 f935 bl 80004a6 + 800023c: 0002 movs r2, r0 + 800023e: 4b1d ldr r3, [pc, #116] ; (80002b4 ) + 8000240: 601a str r2, [r3, #0] + spectral = new_spectral(smbus); + 8000242: 4b1c ldr r3, [pc, #112] ; (80002b4 ) + 8000244: 681b ldr r3, [r3, #0] + 8000246: 0018 movs r0, r3 + 8000248: f000 fa3e bl 80006c8 + 800024c: 0002 movs r2, r0 + 800024e: 4b1a ldr r3, [pc, #104] ; (80002b8 ) + 8000250: 601a str r2, [r3, #0] + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + // Initialize spectral (in case it disconnected before and needs to reconnect) + initialize_spectral(spectral); + 8000252: 4b19 ldr r3, [pc, #100] ; (80002b8 ) + 8000254: 681b ldr r3, [r3, #0] + 8000256: 0018 movs r0, r3 + 8000258: f000 fa5f bl 800071a + + for (size_t i = 0; i < SPECTRAL_CHANNELS; ++i) { + 800025c: 2300 movs r3, #0 + 800025e: 607b str r3, [r7, #4] + 8000260: e01f b.n 80002a2 + uint8_t error_flag = 0; + 8000262: 1cfb adds r3, r7, #3 + 8000264: 2200 movs r2, #0 + 8000266: 701a strb r2, [r3, #0] + update_spectral_channel_data(spectral, i, &error_flag); + 8000268: 4b13 ldr r3, [pc, #76] ; (80002b8 ) + 800026a: 681b ldr r3, [r3, #0] + 800026c: 687a ldr r2, [r7, #4] + 800026e: b2d1 uxtb r1, r2 + 8000270: 1cfa adds r2, r7, #3 + 8000272: 0018 movs r0, r3 + 8000274: f000 fa71 bl 800075a + + // If spectral I2C NAKs, leave early + if(error_flag) { + 8000278: 1cfb adds r3, r7, #3 + 800027a: 781b ldrb r3, [r3, #0] + 800027c: 2b00 cmp r3, #0 + 800027e: d114 bne.n 80002aa + break; + } + + spectral_data[i] = get_spectral_channel_data(spectral, i); + 8000280: 4b0d ldr r3, [pc, #52] ; (80002b8 ) + 8000282: 681b ldr r3, [r3, #0] + 8000284: 687a ldr r2, [r7, #4] + 8000286: b2d2 uxtb r2, r2 + 8000288: 0011 movs r1, r2 + 800028a: 0018 movs r0, r3 + 800028c: f000 fab2 bl 80007f4 + 8000290: 0003 movs r3, r0 + 8000292: 0019 movs r1, r3 + 8000294: 4b09 ldr r3, [pc, #36] ; (80002bc ) + 8000296: 687a ldr r2, [r7, #4] + 8000298: 0052 lsls r2, r2, #1 + 800029a: 52d1 strh r1, [r2, r3] + for (size_t i = 0; i < SPECTRAL_CHANNELS; ++i) { + 800029c: 687b ldr r3, [r7, #4] + 800029e: 3301 adds r3, #1 + 80002a0: 607b str r3, [r7, #4] + 80002a2: 687b ldr r3, [r7, #4] + 80002a4: 2b05 cmp r3, #5 + 80002a6: d9dc bls.n 8000262 + 80002a8: e7d3 b.n 8000252 + break; + 80002aa: 46c0 nop ; (mov r8, r8) + initialize_spectral(spectral); + 80002ac: e7d1 b.n 8000252 + 80002ae: 46c0 nop ; (mov r8, r8) + 80002b0: 20000078 .word 0x20000078 + 80002b4: 200000d0 .word 0x200000d0 + 80002b8: 200000cc .word 0x200000cc + 80002bc: 200000d4 .word 0x200000d4 + +080002c0 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 80002c0: b590 push {r4, r7, lr} + 80002c2: b095 sub sp, #84 ; 0x54 + 80002c4: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 80002c6: 2414 movs r4, #20 + 80002c8: 193b adds r3, r7, r4 + 80002ca: 0018 movs r0, r3 + 80002cc: 233c movs r3, #60 ; 0x3c + 80002ce: 001a movs r2, r3 + 80002d0: 2100 movs r1, #0 + 80002d2: f004 fef7 bl 80050c4 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 80002d6: 1d3b adds r3, r7, #4 + 80002d8: 0018 movs r0, r3 + 80002da: 2310 movs r3, #16 + 80002dc: 001a movs r2, r3 + 80002de: 2100 movs r1, #0 + 80002e0: f004 fef0 bl 80050c4 + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + 80002e4: 2380 movs r3, #128 ; 0x80 + 80002e6: 009b lsls r3, r3, #2 + 80002e8: 0018 movs r0, r3 + 80002ea: f003 fec7 bl 800407c + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 80002ee: 193b adds r3, r7, r4 + 80002f0: 2202 movs r2, #2 + 80002f2: 601a str r2, [r3, #0] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 80002f4: 193b adds r3, r7, r4 + 80002f6: 2280 movs r2, #128 ; 0x80 + 80002f8: 0052 lsls r2, r2, #1 + 80002fa: 60da str r2, [r3, #12] + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + 80002fc: 193b adds r3, r7, r4 + 80002fe: 2200 movs r2, #0 + 8000300: 611a str r2, [r3, #16] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000302: 193b adds r3, r7, r4 + 8000304: 2240 movs r2, #64 ; 0x40 + 8000306: 615a str r2, [r3, #20] + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000308: 193b adds r3, r7, r4 + 800030a: 2200 movs r2, #0 + 800030c: 621a str r2, [r3, #32] + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 800030e: 193b adds r3, r7, r4 + 8000310: 0018 movs r0, r3 + 8000312: f003 fef3 bl 80040fc + 8000316: 1e03 subs r3, r0, #0 + 8000318: d001 beq.n 800031e + { + Error_Handler(); + 800031a: f000 f8bf bl 800049c + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 800031e: 1d3b adds r3, r7, #4 + 8000320: 2207 movs r2, #7 + 8000322: 601a str r2, [r3, #0] + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 8000324: 1d3b adds r3, r7, #4 + 8000326: 2200 movs r2, #0 + 8000328: 605a str r2, [r3, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 800032a: 1d3b adds r3, r7, #4 + 800032c: 2200 movs r2, #0 + 800032e: 609a str r2, [r3, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000330: 1d3b adds r3, r7, #4 + 8000332: 2200 movs r2, #0 + 8000334: 60da str r2, [r3, #12] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 8000336: 1d3b adds r3, r7, #4 + 8000338: 2100 movs r1, #0 + 800033a: 0018 movs r0, r3 + 800033c: f004 fa3e bl 80047bc + 8000340: 1e03 subs r3, r0, #0 + 8000342: d001 beq.n 8000348 + { + Error_Handler(); + 8000344: f000 f8aa bl 800049c + } +} + 8000348: 46c0 nop ; (mov r8, r8) + 800034a: 46bd mov sp, r7 + 800034c: b015 add sp, #84 ; 0x54 + 800034e: bd90 pop {r4, r7, pc} + +08000350 : + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + 8000350: b580 push {r7, lr} + 8000352: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 8000354: 4b1b ldr r3, [pc, #108] ; (80003c4 ) + 8000356: 4a1c ldr r2, [pc, #112] ; (80003c8 ) + 8000358: 601a str r2, [r3, #0] + hi2c1.Init.Timing = 0x00303D5B; + 800035a: 4b1a ldr r3, [pc, #104] ; (80003c4 ) + 800035c: 4a1b ldr r2, [pc, #108] ; (80003cc ) + 800035e: 605a str r2, [r3, #4] + hi2c1.Init.OwnAddress1 = 0; + 8000360: 4b18 ldr r3, [pc, #96] ; (80003c4 ) + 8000362: 2200 movs r2, #0 + 8000364: 609a str r2, [r3, #8] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8000366: 4b17 ldr r3, [pc, #92] ; (80003c4 ) + 8000368: 2201 movs r2, #1 + 800036a: 60da str r2, [r3, #12] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 800036c: 4b15 ldr r3, [pc, #84] ; (80003c4 ) + 800036e: 2200 movs r2, #0 + 8000370: 611a str r2, [r3, #16] + hi2c1.Init.OwnAddress2 = 0; + 8000372: 4b14 ldr r3, [pc, #80] ; (80003c4 ) + 8000374: 2200 movs r2, #0 + 8000376: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 8000378: 4b12 ldr r3, [pc, #72] ; (80003c4 ) + 800037a: 2200 movs r2, #0 + 800037c: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 800037e: 4b11 ldr r3, [pc, #68] ; (80003c4 ) + 8000380: 2200 movs r2, #0 + 8000382: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8000384: 4b0f ldr r3, [pc, #60] ; (80003c4 ) + 8000386: 2200 movs r2, #0 + 8000388: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 800038a: 4b0e ldr r3, [pc, #56] ; (80003c4 ) + 800038c: 0018 movs r0, r3 + 800038e: f001 f943 bl 8001618 + 8000392: 1e03 subs r3, r0, #0 + 8000394: d001 beq.n 800039a + { + Error_Handler(); + 8000396: f000 f881 bl 800049c + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 800039a: 4b0a ldr r3, [pc, #40] ; (80003c4 ) + 800039c: 2100 movs r1, #0 + 800039e: 0018 movs r0, r3 + 80003a0: f003 fdd4 bl 8003f4c + 80003a4: 1e03 subs r3, r0, #0 + 80003a6: d001 beq.n 80003ac + { + Error_Handler(); + 80003a8: f000 f878 bl 800049c + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 80003ac: 4b05 ldr r3, [pc, #20] ; (80003c4 ) + 80003ae: 2100 movs r1, #0 + 80003b0: 0018 movs r0, r3 + 80003b2: f003 fe17 bl 8003fe4 + 80003b6: 1e03 subs r3, r0, #0 + 80003b8: d001 beq.n 80003be + { + Error_Handler(); + 80003ba: f000 f86f bl 800049c + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + 80003be: 46c0 nop ; (mov r8, r8) + 80003c0: 46bd mov sp, r7 + 80003c2: bd80 pop {r7, pc} + 80003c4: 20000078 .word 0x20000078 + 80003c8: 40005400 .word 0x40005400 + 80003cc: 00303d5b .word 0x00303d5b + +080003d0 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 80003d0: b590 push {r4, r7, lr} + 80003d2: b089 sub sp, #36 ; 0x24 + 80003d4: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80003d6: 240c movs r4, #12 + 80003d8: 193b adds r3, r7, r4 + 80003da: 0018 movs r0, r3 + 80003dc: 2314 movs r3, #20 + 80003de: 001a movs r2, r3 + 80003e0: 2100 movs r1, #0 + 80003e2: f004 fe6f bl 80050c4 +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 80003e6: 4b2c ldr r3, [pc, #176] ; (8000498 ) + 80003e8: 6b5a ldr r2, [r3, #52] ; 0x34 + 80003ea: 4b2b ldr r3, [pc, #172] ; (8000498 ) + 80003ec: 2104 movs r1, #4 + 80003ee: 430a orrs r2, r1 + 80003f0: 635a str r2, [r3, #52] ; 0x34 + 80003f2: 4b29 ldr r3, [pc, #164] ; (8000498 ) + 80003f4: 6b5b ldr r3, [r3, #52] ; 0x34 + 80003f6: 2204 movs r2, #4 + 80003f8: 4013 ands r3, r2 + 80003fa: 60bb str r3, [r7, #8] + 80003fc: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 80003fe: 4b26 ldr r3, [pc, #152] ; (8000498 ) + 8000400: 6b5a ldr r2, [r3, #52] ; 0x34 + 8000402: 4b25 ldr r3, [pc, #148] ; (8000498 ) + 8000404: 2120 movs r1, #32 + 8000406: 430a orrs r2, r1 + 8000408: 635a str r2, [r3, #52] ; 0x34 + 800040a: 4b23 ldr r3, [pc, #140] ; (8000498 ) + 800040c: 6b5b ldr r3, [r3, #52] ; 0x34 + 800040e: 2220 movs r2, #32 + 8000410: 4013 ands r3, r2 + 8000412: 607b str r3, [r7, #4] + 8000414: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000416: 4b20 ldr r3, [pc, #128] ; (8000498 ) + 8000418: 6b5a ldr r2, [r3, #52] ; 0x34 + 800041a: 4b1f ldr r3, [pc, #124] ; (8000498 ) + 800041c: 2101 movs r1, #1 + 800041e: 430a orrs r2, r1 + 8000420: 635a str r2, [r3, #52] ; 0x34 + 8000422: 4b1d ldr r3, [pc, #116] ; (8000498 ) + 8000424: 6b5b ldr r3, [r3, #52] ; 0x34 + 8000426: 2201 movs r2, #1 + 8000428: 4013 ands r3, r2 + 800042a: 603b str r3, [r7, #0] + 800042c: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin, GPIO_PIN_RESET); + 800042e: 23a0 movs r3, #160 ; 0xa0 + 8000430: 05db lsls r3, r3, #23 + 8000432: 2200 movs r2, #0 + 8000434: 2120 movs r1, #32 + 8000436: 0018 movs r0, r3 + 8000438: f001 f8d0 bl 80015dc + + /*Configure GPIO pins : USART2_TX_Pin USART2_RX_Pin */ + GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin; + 800043c: 193b adds r3, r7, r4 + 800043e: 220c movs r2, #12 + 8000440: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000442: 193b adds r3, r7, r4 + 8000444: 2202 movs r2, #2 + 8000446: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000448: 193b adds r3, r7, r4 + 800044a: 2200 movs r2, #0 + 800044c: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800044e: 193b adds r3, r7, r4 + 8000450: 2200 movs r2, #0 + 8000452: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF1_USART2; + 8000454: 193b adds r3, r7, r4 + 8000456: 2201 movs r2, #1 + 8000458: 611a str r2, [r3, #16] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800045a: 193a adds r2, r7, r4 + 800045c: 23a0 movs r3, #160 ; 0xa0 + 800045e: 05db lsls r3, r3, #23 + 8000460: 0011 movs r1, r2 + 8000462: 0018 movs r0, r3 + 8000464: f000 fe76 bl 8001154 + + /*Configure GPIO pin : LED_GREEN_Pin */ + GPIO_InitStruct.Pin = LED_GREEN_Pin; + 8000468: 0021 movs r1, r4 + 800046a: 187b adds r3, r7, r1 + 800046c: 2220 movs r2, #32 + 800046e: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000470: 187b adds r3, r7, r1 + 8000472: 2201 movs r2, #1 + 8000474: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000476: 187b adds r3, r7, r1 + 8000478: 2200 movs r2, #0 + 800047a: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 800047c: 187b adds r3, r7, r1 + 800047e: 2202 movs r2, #2 + 8000480: 60da str r2, [r3, #12] + HAL_GPIO_Init(LED_GREEN_GPIO_Port, &GPIO_InitStruct); + 8000482: 187a adds r2, r7, r1 + 8000484: 23a0 movs r3, #160 ; 0xa0 + 8000486: 05db lsls r3, r3, #23 + 8000488: 0011 movs r1, r2 + 800048a: 0018 movs r0, r3 + 800048c: f000 fe62 bl 8001154 + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + 8000490: 46c0 nop ; (mov r8, r8) + 8000492: 46bd mov sp, r7 + 8000494: b009 add sp, #36 ; 0x24 + 8000496: bd90 pop {r4, r7, pc} + 8000498: 40021000 .word 0x40021000 + +0800049c : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 800049c: b580 push {r7, lr} + 800049e: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 80004a0: b672 cpsid i +} + 80004a2: 46c0 nop ; (mov r8, r8) + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 80004a4: e7fe b.n 80004a4 + +080004a6 : +// MODIFIES: nothing +// EFFECTS: Returns a pointer to a created SMBus object +SMBus *new_smbus( + I2C_HandleTypeDef *hi2c, + bool _dma) +{ + 80004a6: b580 push {r7, lr} + 80004a8: b084 sub sp, #16 + 80004aa: af00 add r7, sp, #0 + 80004ac: 6078 str r0, [r7, #4] + 80004ae: 000a movs r2, r1 + 80004b0: 1cfb adds r3, r7, #3 + 80004b2: 701a strb r2, [r3, #0] + SMBus *smbus = malloc(sizeof(SMBus)); + 80004b4: 2024 movs r0, #36 ; 0x24 + 80004b6: f004 fd47 bl 8004f48 + 80004ba: 0003 movs r3, r0 + 80004bc: 60fb str r3, [r7, #12] + smbus->i2c = hi2c; + 80004be: 68fb ldr r3, [r7, #12] + 80004c0: 687a ldr r2, [r7, #4] + 80004c2: 601a str r2, [r3, #0] + smbus->ret = HAL_OK; + 80004c4: 68fb ldr r3, [r7, #12] + 80004c6: 2200 movs r2, #0 + 80004c8: 711a strb r2, [r3, #4] + memset(smbus->buf, 0, sizeof(smbus->buf)); + 80004ca: 68fb ldr r3, [r7, #12] + 80004cc: 3305 adds r3, #5 + 80004ce: 221e movs r2, #30 + 80004d0: 2100 movs r1, #0 + 80004d2: 0018 movs r0, r3 + 80004d4: f004 fdf6 bl 80050c4 + smbus->DMA = _dma; + 80004d8: 68fb ldr r3, [r7, #12] + 80004da: 1cfa adds r2, r7, #3 + 80004dc: 2123 movs r1, #35 ; 0x23 + 80004de: 7812 ldrb r2, [r2, #0] + 80004e0: 545a strb r2, [r3, r1] +} + 80004e2: 46c0 nop ; (mov r8, r8) + 80004e4: 0018 movs r0, r3 + 80004e6: 46bd mov sp, r7 + 80004e8: b004 add sp, #16 + 80004ea: bd80 pop {r7, pc} + +080004ec : +// EFFECTS: Checks if smbus->ret is HAL_OK. +// If not HAL_OK, then reset the I2C smbus +// and if smbus->uart is not NULL, then +// print out an error message. +int smbus_check_error(SMBus *smbus) +{ + 80004ec: b580 push {r7, lr} + 80004ee: b082 sub sp, #8 + 80004f0: af00 add r7, sp, #0 + 80004f2: 6078 str r0, [r7, #4] + if (smbus->ret == HAL_OK) + 80004f4: 687b ldr r3, [r7, #4] + 80004f6: 791b ldrb r3, [r3, #4] + 80004f8: 2b00 cmp r3, #0 + 80004fa: d101 bne.n 8000500 + { + return true; + 80004fc: 2301 movs r3, #1 + 80004fe: e007 b.n 8000510 + } + + smbus_reset(smbus); + 8000500: 687b ldr r3, [r7, #4] + 8000502: 0018 movs r0, r3 + 8000504: f000 f880 bl 8000608 + HAL_Delay(10); + 8000508: 200a movs r0, #10 + 800050a: f000 fc15 bl 8000d38 + return false; + 800050e: 2300 movs r3, #0 +} + 8000510: 0018 movs r0, r3 + 8000512: 46bd mov sp, r7 + 8000514: b002 add sp, #8 + 8000516: bd80 pop {r7, pc} + +08000518 : +// EFFECTS: Reads one byte from the register. +long smbus_read_byte_data( + SMBus *smbus, + char reg, + uint8_t device_address) +{ + 8000518: b580 push {r7, lr} + 800051a: b084 sub sp, #16 + 800051c: af02 add r7, sp, #8 + 800051e: 6078 str r0, [r7, #4] + 8000520: 0008 movs r0, r1 + 8000522: 0011 movs r1, r2 + 8000524: 1cfb adds r3, r7, #3 + 8000526: 1c02 adds r2, r0, #0 + 8000528: 701a strb r2, [r3, #0] + 800052a: 1cbb adds r3, r7, #2 + 800052c: 1c0a adds r2, r1, #0 + 800052e: 701a strb r2, [r3, #0] + smbus->buf[0] = reg; + 8000530: 687b ldr r3, [r7, #4] + 8000532: 1cfa adds r2, r7, #3 + 8000534: 7812 ldrb r2, [r2, #0] + 8000536: 715a strb r2, [r3, #5] + if (!smbus->DMA) + 8000538: 687b ldr r3, [r7, #4] + 800053a: 2223 movs r2, #35 ; 0x23 + 800053c: 5c9b ldrb r3, [r3, r2] + 800053e: 2201 movs r2, #1 + 8000540: 4053 eors r3, r2 + 8000542: b2db uxtb r3, r3 + 8000544: 2b00 cmp r3, #0 + 8000546: d02b beq.n 80005a0 + { + smbus->ret = HAL_I2C_Master_Transmit( + 8000548: 687b ldr r3, [r7, #4] + 800054a: 6818 ldr r0, [r3, #0] + 800054c: 1cbb adds r3, r7, #2 + 800054e: 781b ldrb r3, [r3, #0] + 8000550: b29b uxth r3, r3 + 8000552: 18db adds r3, r3, r3 + 8000554: b299 uxth r1, r3 + smbus->i2c, + device_address << 1, + smbus->buf, + 8000556: 687b ldr r3, [r7, #4] + 8000558: 1d5a adds r2, r3, #5 + smbus->ret = HAL_I2C_Master_Transmit( + 800055a: 2332 movs r3, #50 ; 0x32 + 800055c: 9300 str r3, [sp, #0] + 800055e: 2301 movs r3, #1 + 8000560: f001 f930 bl 80017c4 + 8000564: 0003 movs r3, r0 + 8000566: 001a movs r2, r3 + 8000568: 687b ldr r3, [r7, #4] + 800056a: 711a strb r2, [r3, #4] + 1, + 50); + smbus_check_error(smbus); + 800056c: 687b ldr r3, [r7, #4] + 800056e: 0018 movs r0, r3 + 8000570: f7ff ffbc bl 80004ec + smbus->ret = HAL_I2C_Master_Receive( + 8000574: 687b ldr r3, [r7, #4] + 8000576: 6818 ldr r0, [r3, #0] + smbus->i2c, + (device_address << 1) | 1, + 8000578: 1cbb adds r3, r7, #2 + 800057a: 781b ldrb r3, [r3, #0] + 800057c: 005b lsls r3, r3, #1 + 800057e: b21b sxth r3, r3 + 8000580: 2201 movs r2, #1 + 8000582: 4313 orrs r3, r2 + 8000584: b21b sxth r3, r3 + smbus->ret = HAL_I2C_Master_Receive( + 8000586: b299 uxth r1, r3 + smbus->buf, + 8000588: 687b ldr r3, [r7, #4] + 800058a: 1d5a adds r2, r3, #5 + smbus->ret = HAL_I2C_Master_Receive( + 800058c: 2332 movs r3, #50 ; 0x32 + 800058e: 9300 str r3, [sp, #0] + 8000590: 2301 movs r3, #1 + 8000592: f001 fa41 bl 8001a18 + 8000596: 0003 movs r3, r0 + 8000598: 001a movs r2, r3 + 800059a: 687b ldr r3, [r7, #4] + 800059c: 711a strb r2, [r3, #4] + 800059e: e026 b.n 80005ee + 1, + 50); + } + else + { + smbus->ret = HAL_I2C_Master_Transmit_DMA( + 80005a0: 687b ldr r3, [r7, #4] + 80005a2: 6818 ldr r0, [r3, #0] + 80005a4: 1cbb adds r3, r7, #2 + 80005a6: 781b ldrb r3, [r3, #0] + 80005a8: b29b uxth r3, r3 + 80005aa: 18db adds r3, r3, r3 + 80005ac: b299 uxth r1, r3 + smbus->i2c, + device_address << 1, + smbus->buf, + 80005ae: 687b ldr r3, [r7, #4] + 80005b0: 1d5a adds r2, r3, #5 + smbus->ret = HAL_I2C_Master_Transmit_DMA( + 80005b2: 2301 movs r3, #1 + 80005b4: f001 fb38 bl 8001c28 + 80005b8: 0003 movs r3, r0 + 80005ba: 001a movs r2, r3 + 80005bc: 687b ldr r3, [r7, #4] + 80005be: 711a strb r2, [r3, #4] + 1); + smbus_check_error(smbus); + 80005c0: 687b ldr r3, [r7, #4] + 80005c2: 0018 movs r0, r3 + 80005c4: f7ff ff92 bl 80004ec + smbus->ret = HAL_I2C_Master_Receive_DMA( + 80005c8: 687b ldr r3, [r7, #4] + 80005ca: 6818 ldr r0, [r3, #0] + smbus->i2c, + (device_address << 1) | 1, + 80005cc: 1cbb adds r3, r7, #2 + 80005ce: 781b ldrb r3, [r3, #0] + 80005d0: 005b lsls r3, r3, #1 + 80005d2: b21b sxth r3, r3 + 80005d4: 2201 movs r2, #1 + 80005d6: 4313 orrs r3, r2 + 80005d8: b21b sxth r3, r3 + smbus->ret = HAL_I2C_Master_Receive_DMA( + 80005da: b299 uxth r1, r3 + smbus->buf, + 80005dc: 687b ldr r3, [r7, #4] + 80005de: 1d5a adds r2, r3, #5 + smbus->ret = HAL_I2C_Master_Receive_DMA( + 80005e0: 2301 movs r3, #1 + 80005e2: f001 fc4b bl 8001e7c + 80005e6: 0003 movs r3, r0 + 80005e8: 001a movs r2, r3 + 80005ea: 687b ldr r3, [r7, #4] + 80005ec: 711a strb r2, [r3, #4] + 1); + } + HAL_Delay(10); + 80005ee: 200a movs r0, #10 + 80005f0: f000 fba2 bl 8000d38 + smbus_check_error(smbus); + 80005f4: 687b ldr r3, [r7, #4] + 80005f6: 0018 movs r0, r3 + 80005f8: f7ff ff78 bl 80004ec + return smbus->buf[0]; + 80005fc: 687b ldr r3, [r7, #4] + 80005fe: 795b ldrb r3, [r3, #5] +} + 8000600: 0018 movs r0, r3 + 8000602: 46bd mov sp, r7 + 8000604: b002 add sp, #8 + 8000606: bd80 pop {r7, pc} + +08000608 : + +// REQUIRES: smbus is an SMBus object +// MODIFIES: nothing +// EFFECTS: Deinitializes and initializes the I2C bus. +void smbus_reset(SMBus *smbus) +{ + 8000608: b580 push {r7, lr} + 800060a: b082 sub sp, #8 + 800060c: af00 add r7, sp, #0 + 800060e: 6078 str r0, [r7, #4] + HAL_I2C_DeInit(smbus->i2c); + 8000610: 687b ldr r3, [r7, #4] + 8000612: 681b ldr r3, [r3, #0] + 8000614: 0018 movs r0, r3 + 8000616: f001 f8a5 bl 8001764 + HAL_I2C_Init(smbus->i2c); + 800061a: 687b ldr r3, [r7, #4] + 800061c: 681b ldr r3, [r3, #0] + 800061e: 0018 movs r0, r3 + 8000620: f000 fffa bl 8001618 +} + 8000624: 46c0 nop ; (mov r8, r8) + 8000626: 46bd mov sp, r7 + 8000628: b002 add sp, #8 + 800062a: bd80 pop {r7, pc} + +0800062c : +void smbus_write_byte_data( + SMBus *smbus, + char reg, + uint8_t data, + uint8_t device_address) +{ + 800062c: b590 push {r4, r7, lr} + 800062e: b085 sub sp, #20 + 8000630: af02 add r7, sp, #8 + 8000632: 6078 str r0, [r7, #4] + 8000634: 000c movs r4, r1 + 8000636: 0010 movs r0, r2 + 8000638: 0019 movs r1, r3 + 800063a: 1cfb adds r3, r7, #3 + 800063c: 1c22 adds r2, r4, #0 + 800063e: 701a strb r2, [r3, #0] + 8000640: 1cbb adds r3, r7, #2 + 8000642: 1c02 adds r2, r0, #0 + 8000644: 701a strb r2, [r3, #0] + 8000646: 1c7b adds r3, r7, #1 + 8000648: 1c0a adds r2, r1, #0 + 800064a: 701a strb r2, [r3, #0] + smbus->buf[0] = reg; + 800064c: 687b ldr r3, [r7, #4] + 800064e: 1cfa adds r2, r7, #3 + 8000650: 7812 ldrb r2, [r2, #0] + 8000652: 715a strb r2, [r3, #5] + smbus->buf[1] = data; + 8000654: 687b ldr r3, [r7, #4] + 8000656: 1cba adds r2, r7, #2 + 8000658: 7812 ldrb r2, [r2, #0] + 800065a: 719a strb r2, [r3, #6] + + if (!smbus->DMA) + 800065c: 687b ldr r3, [r7, #4] + 800065e: 2223 movs r2, #35 ; 0x23 + 8000660: 5c9b ldrb r3, [r3, r2] + 8000662: 2201 movs r2, #1 + 8000664: 4053 eors r3, r2 + 8000666: b2db uxtb r3, r3 + 8000668: 2b00 cmp r3, #0 + 800066a: d012 beq.n 8000692 + { + smbus->ret = HAL_I2C_Master_Transmit( + 800066c: 687b ldr r3, [r7, #4] + 800066e: 6818 ldr r0, [r3, #0] + 8000670: 1c7b adds r3, r7, #1 + 8000672: 781b ldrb r3, [r3, #0] + 8000674: b29b uxth r3, r3 + 8000676: 18db adds r3, r3, r3 + 8000678: b299 uxth r1, r3 + smbus->i2c, + device_address << 1, + smbus->buf, + 800067a: 687b ldr r3, [r7, #4] + 800067c: 1d5a adds r2, r3, #5 + smbus->ret = HAL_I2C_Master_Transmit( + 800067e: 2332 movs r3, #50 ; 0x32 + 8000680: 9300 str r3, [sp, #0] + 8000682: 2302 movs r3, #2 + 8000684: f001 f89e bl 80017c4 + 8000688: 0003 movs r3, r0 + 800068a: 001a movs r2, r3 + 800068c: 687b ldr r3, [r7, #4] + 800068e: 711a strb r2, [r3, #4] + 8000690: e00f b.n 80006b2 + 2, + 50); + } + else + { + smbus->ret = HAL_I2C_Master_Transmit_DMA( + 8000692: 687b ldr r3, [r7, #4] + 8000694: 6818 ldr r0, [r3, #0] + 8000696: 1c7b adds r3, r7, #1 + 8000698: 781b ldrb r3, [r3, #0] + 800069a: b29b uxth r3, r3 + 800069c: 18db adds r3, r3, r3 + 800069e: b299 uxth r1, r3 + smbus->i2c, + device_address << 1, + smbus->buf, + 80006a0: 687b ldr r3, [r7, #4] + 80006a2: 1d5a adds r2, r3, #5 + smbus->ret = HAL_I2C_Master_Transmit_DMA( + 80006a4: 2302 movs r3, #2 + 80006a6: f001 fabf bl 8001c28 + 80006aa: 0003 movs r3, r0 + 80006ac: 001a movs r2, r3 + 80006ae: 687b ldr r3, [r7, #4] + 80006b0: 711a strb r2, [r3, #4] + 2); + } + HAL_Delay(10); + 80006b2: 200a movs r0, #10 + 80006b4: f000 fb40 bl 8000d38 + smbus_check_error(smbus); + 80006b8: 687b ldr r3, [r7, #4] + 80006ba: 0018 movs r0, r3 + 80006bc: f7ff ff16 bl 80004ec +} + 80006c0: 46c0 nop ; (mov r8, r8) + 80006c2: 46bd mov sp, r7 + 80006c4: b003 add sp, #12 + 80006c6: bd90 pop {r4, r7, pc} + +080006c8 : +// and uart is the debugging UART channel or NULL, +// and dma tells if DMA is enabled +// MODIFIES: nothing +// EFFECTS: Returns a pointer to a created Spectral object +Spectral *new_spectral(SMBus *smbus) +{ + 80006c8: b580 push {r7, lr} + 80006ca: b084 sub sp, #16 + 80006cc: af00 add r7, sp, #0 + 80006ce: 6078 str r0, [r7, #4] + Spectral *spectral = malloc(sizeof(Spectral)); + 80006d0: 2010 movs r0, #16 + 80006d2: f004 fc39 bl 8004f48 + 80006d6: 0003 movs r3, r0 + 80006d8: 60bb str r3, [r7, #8] + spectral->smbus = smbus; + 80006da: 68bb ldr r3, [r7, #8] + 80006dc: 687a ldr r2, [r7, #4] + 80006de: 601a str r2, [r3, #0] + for (uint8_t i = 0; i < SPECTRAL_CHANNELS; ++i) { + 80006e0: 230f movs r3, #15 + 80006e2: 18fb adds r3, r7, r3 + 80006e4: 2200 movs r2, #0 + 80006e6: 701a strb r2, [r3, #0] + 80006e8: e00d b.n 8000706 + spectral->channel_data[i] = 0; + 80006ea: 210f movs r1, #15 + 80006ec: 187b adds r3, r7, r1 + 80006ee: 781b ldrb r3, [r3, #0] + 80006f0: 68ba ldr r2, [r7, #8] + 80006f2: 005b lsls r3, r3, #1 + 80006f4: 18d3 adds r3, r2, r3 + 80006f6: 3304 adds r3, #4 + 80006f8: 2200 movs r2, #0 + 80006fa: 801a strh r2, [r3, #0] + for (uint8_t i = 0; i < SPECTRAL_CHANNELS; ++i) { + 80006fc: 187b adds r3, r7, r1 + 80006fe: 187a adds r2, r7, r1 + 8000700: 7812 ldrb r2, [r2, #0] + 8000702: 3201 adds r2, #1 + 8000704: 701a strb r2, [r3, #0] + 8000706: 230f movs r3, #15 + 8000708: 18fb adds r3, r7, r3 + 800070a: 781b ldrb r3, [r3, #0] + 800070c: 2b05 cmp r3, #5 + 800070e: d9ec bls.n 80006ea + } + return spectral; + 8000710: 68bb ldr r3, [r7, #8] +} + 8000712: 0018 movs r0, r3 + 8000714: 46bd mov sp, r7 + 8000716: b004 add sp, #16 + 8000718: bd80 pop {r7, pc} + +0800071a : + +// REQUIRES: spectral is a Spectral object +// MODIFIES: nothing +// EFFECTS: Initializes the spectral device +void initialize_spectral(Spectral *spectral) +{ + 800071a: b580 push {r7, lr} + 800071c: b082 sub sp, #8 + 800071e: af00 add r7, sp, #0 + 8000720: 6078 str r0, [r7, #4] + // RST is 0, so no reset is done + // INT Is 0, so no interrupt + // GAIN is 0b10, so it is 16x sensor channel gain + // BANK is 0b10, so data conversion is Mode 2 + // DATA_RDY is 0 and RSVD is 0 + virtual_write_spectral(spectral, CONTROL_SET_UP, 0x28); // runs twice to account for status miss + 8000722: 687b ldr r3, [r7, #4] + 8000724: 2228 movs r2, #40 ; 0x28 + 8000726: 2104 movs r1, #4 + 8000728: 0018 movs r0, r3 + 800072a: f000 f875 bl 8000818 + HAL_Delay(50); + 800072e: 2032 movs r0, #50 ; 0x32 + 8000730: f000 fb02 bl 8000d38 + virtual_write_spectral(spectral, CONTROL_SET_UP, 0x28); // converts data bank to 2 + 8000734: 687b ldr r3, [r7, #4] + 8000736: 2228 movs r2, #40 ; 0x28 + 8000738: 2104 movs r1, #4 + 800073a: 0018 movs r0, r3 + 800073c: f000 f86c bl 8000818 + // Integration time is 0xFF * 2.8ms + HAL_Delay(50); + 8000740: 2032 movs r0, #50 ; 0x32 + 8000742: f000 faf9 bl 8000d38 + virtual_write_spectral(spectral, INT_TIME, 0xFF); // increases integration time + 8000746: 687b ldr r3, [r7, #4] + 8000748: 22ff movs r2, #255 ; 0xff + 800074a: 2105 movs r1, #5 + 800074c: 0018 movs r0, r3 + 800074e: f000 f863 bl 8000818 +} + 8000752: 46c0 nop ; (mov r8, r8) + 8000754: 46bd mov sp, r7 + 8000756: b002 add sp, #8 + 8000758: bd80 pop {r7, pc} + +0800075a : +} + +// REQUIRES: spectral is an object and 0 <= channel < 6 +// MODIFIES: spectral.channels array +// EFFECTS: Updates values of spectral struct's channels array with data from spectral sensor +void update_spectral_channel_data(Spectral *spectral, uint8_t channel, uint8_t *error_flag) { + 800075a: b5f0 push {r4, r5, r6, r7, lr} + 800075c: b087 sub sp, #28 + 800075e: af00 add r7, sp, #0 + 8000760: 60f8 str r0, [r7, #12] + 8000762: 607a str r2, [r7, #4] + 8000764: 240b movs r4, #11 + 8000766: 193b adds r3, r7, r4 + 8000768: 1c0a adds r2, r1, #0 + 800076a: 701a strb r2, [r3, #0] + + + if (0 <= channel && channel < 6) { + 800076c: 193b adds r3, r7, r4 + 800076e: 781b ldrb r3, [r3, #0] + 8000770: 2b05 cmp r3, #5 + 8000772: d83b bhi.n 80007ec + uint8_t START_REG = RAW_VALUE_RGA_HIGH; + 8000774: 2017 movs r0, #23 + 8000776: 183b adds r3, r7, r0 + 8000778: 2208 movs r2, #8 + 800077a: 701a strb r2, [r3, #0] + + uint8_t msb = START_REG + channel * 2; + 800077c: 193b adds r3, r7, r4 + 800077e: 781b ldrb r3, [r3, #0] + 8000780: 18db adds r3, r3, r3 + 8000782: b2d9 uxtb r1, r3 + 8000784: 2516 movs r5, #22 + 8000786: 197b adds r3, r7, r5 + 8000788: 183a adds r2, r7, r0 + 800078a: 7812 ldrb r2, [r2, #0] + 800078c: 188a adds r2, r1, r2 + 800078e: 701a strb r2, [r3, #0] + uint8_t lsb = START_REG + channel * 2 + 1; + 8000790: 193b adds r3, r7, r4 + 8000792: 781b ldrb r3, [r3, #0] + 8000794: 18db adds r3, r3, r3 + 8000796: b2da uxtb r2, r3 + 8000798: 183b adds r3, r7, r0 + 800079a: 781b ldrb r3, [r3, #0] + 800079c: 18d3 adds r3, r2, r3 + 800079e: b2da uxtb r2, r3 + 80007a0: 2615 movs r6, #21 + 80007a2: 19bb adds r3, r7, r6 + 80007a4: 3201 adds r2, #1 + 80007a6: 701a strb r2, [r3, #0] + + uint16_t high = (virtual_read_spectral(spectral, msb, error_flag) & 0xFF) << 8; + 80007a8: 687a ldr r2, [r7, #4] + 80007aa: 197b adds r3, r7, r5 + 80007ac: 7819 ldrb r1, [r3, #0] + 80007ae: 68fb ldr r3, [r7, #12] + 80007b0: 0018 movs r0, r3 + 80007b2: f000 f87f bl 80008b4 + 80007b6: 0003 movs r3, r0 + 80007b8: b29a uxth r2, r3 + 80007ba: 2512 movs r5, #18 + 80007bc: 197b adds r3, r7, r5 + 80007be: 0212 lsls r2, r2, #8 + 80007c0: 801a strh r2, [r3, #0] + spectral->channel_data[channel] = high | (virtual_read_spectral(spectral, lsb, error_flag) & 0xFF); + 80007c2: 687a ldr r2, [r7, #4] + 80007c4: 19bb adds r3, r7, r6 + 80007c6: 7819 ldrb r1, [r3, #0] + 80007c8: 68fb ldr r3, [r7, #12] + 80007ca: 0018 movs r0, r3 + 80007cc: f000 f872 bl 80008b4 + 80007d0: 0003 movs r3, r0 + 80007d2: b299 uxth r1, r3 + 80007d4: 193b adds r3, r7, r4 + 80007d6: 781b ldrb r3, [r3, #0] + 80007d8: 197a adds r2, r7, r5 + 80007da: 8812 ldrh r2, [r2, #0] + 80007dc: 430a orrs r2, r1 + 80007de: b291 uxth r1, r2 + 80007e0: 68fa ldr r2, [r7, #12] + 80007e2: 005b lsls r3, r3, #1 + 80007e4: 18d3 adds r3, r2, r3 + 80007e6: 3304 adds r3, #4 + 80007e8: 1c0a adds r2, r1, #0 + 80007ea: 801a strh r2, [r3, #0] + } + +} + 80007ec: 46c0 nop ; (mov r8, r8) + 80007ee: 46bd mov sp, r7 + 80007f0: b007 add sp, #28 + 80007f2: bdf0 pop {r4, r5, r6, r7, pc} + +080007f4 : + +// REQUIRES: spectral is a Spectral object and 0 <= channel < 6 +// MODIFIES: nothing +// EFFECTS: Returns the spectral data of a particular channel +uint16_t get_spectral_channel_data(Spectral *spectral, uint8_t channel) +{ + 80007f4: b580 push {r7, lr} + 80007f6: b082 sub sp, #8 + 80007f8: af00 add r7, sp, #0 + 80007fa: 6078 str r0, [r7, #4] + 80007fc: 000a movs r2, r1 + 80007fe: 1cfb adds r3, r7, #3 + 8000800: 701a strb r2, [r3, #0] + return spectral->channel_data[channel]; + 8000802: 1cfb adds r3, r7, #3 + 8000804: 781b ldrb r3, [r3, #0] + 8000806: 687a ldr r2, [r7, #4] + 8000808: 005b lsls r3, r3, #1 + 800080a: 18d3 adds r3, r2, r3 + 800080c: 3304 adds r3, #4 + 800080e: 881b ldrh r3, [r3, #0] + +} + 8000810: 0018 movs r0, r3 + 8000812: 46bd mov sp, r7 + 8000814: b002 add sp, #8 + 8000816: bd80 pop {r7, pc} + +08000818 : +// REQUIRES: spectral is a Spectral object, +// v_reg is the virtual register, +// and data is the data to pass +// MODIFIES: nothing +// EFFECTS: Writes to the virtual register as explained in page 18-20 of the datasheet +void virtual_write_spectral(Spectral *spectral, uint8_t v_reg, uint8_t data) { + 8000818: b580 push {r7, lr} + 800081a: b084 sub sp, #16 + 800081c: af00 add r7, sp, #0 + 800081e: 6078 str r0, [r7, #4] + 8000820: 0008 movs r0, r1 + 8000822: 0011 movs r1, r2 + 8000824: 1cfb adds r3, r7, #3 + 8000826: 1c02 adds r2, r0, #0 + 8000828: 701a strb r2, [r3, #0] + 800082a: 1cbb adds r3, r7, #2 + 800082c: 1c0a adds r2, r1, #0 + 800082e: 701a strb r2, [r3, #0] + uint8_t status; + + while(1) { + status = smbus_read_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_STATUS_REG, DEVICE_SLAVE_ADDRESS); + 8000830: 687b ldr r3, [r7, #4] + 8000832: 681b ldr r3, [r3, #0] + 8000834: 2249 movs r2, #73 ; 0x49 + 8000836: 2100 movs r1, #0 + 8000838: 0018 movs r0, r3 + 800083a: f7ff fe6d bl 8000518 + 800083e: 0002 movs r2, r0 + 8000840: 210f movs r1, #15 + 8000842: 187b adds r3, r7, r1 + 8000844: 701a strb r2, [r3, #0] + if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0) { + 8000846: 187b adds r3, r7, r1 + 8000848: 781b ldrb r3, [r3, #0] + 800084a: 2202 movs r2, #2 + 800084c: 4013 ands r3, r2 + 800084e: d003 beq.n 8000858 + break; + } + HAL_Delay(5); + 8000850: 2005 movs r0, #5 + 8000852: f000 fa71 bl 8000d38 + status = smbus_read_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_STATUS_REG, DEVICE_SLAVE_ADDRESS); + 8000856: e7eb b.n 8000830 + break; + 8000858: 46c0 nop ; (mov r8, r8) + } + smbus_write_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_WRITE_REG, (v_reg | 0x80), DEVICE_SLAVE_ADDRESS); + 800085a: 687b ldr r3, [r7, #4] + 800085c: 6818 ldr r0, [r3, #0] + 800085e: 1cfb adds r3, r7, #3 + 8000860: 781b ldrb r3, [r3, #0] + 8000862: 2280 movs r2, #128 ; 0x80 + 8000864: 4252 negs r2, r2 + 8000866: 4313 orrs r3, r2 + 8000868: b2da uxtb r2, r3 + 800086a: 2349 movs r3, #73 ; 0x49 + 800086c: 2101 movs r1, #1 + 800086e: f7ff fedd bl 800062c + + while(1) { + status = smbus_read_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_STATUS_REG, DEVICE_SLAVE_ADDRESS); + 8000872: 687b ldr r3, [r7, #4] + 8000874: 681b ldr r3, [r3, #0] + 8000876: 2249 movs r2, #73 ; 0x49 + 8000878: 2100 movs r1, #0 + 800087a: 0018 movs r0, r3 + 800087c: f7ff fe4c bl 8000518 + 8000880: 0002 movs r2, r0 + 8000882: 210f movs r1, #15 + 8000884: 187b adds r3, r7, r1 + 8000886: 701a strb r2, [r3, #0] + if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0) { + 8000888: 187b adds r3, r7, r1 + 800088a: 781b ldrb r3, [r3, #0] + 800088c: 2202 movs r2, #2 + 800088e: 4013 ands r3, r2 + 8000890: d003 beq.n 800089a + break; + } + HAL_Delay(5); + 8000892: 2005 movs r0, #5 + 8000894: f000 fa50 bl 8000d38 + status = smbus_read_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_STATUS_REG, DEVICE_SLAVE_ADDRESS); + 8000898: e7eb b.n 8000872 + break; + 800089a: 46c0 nop ; (mov r8, r8) + } + smbus_write_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_WRITE_REG, data, DEVICE_SLAVE_ADDRESS); + 800089c: 687b ldr r3, [r7, #4] + 800089e: 6818 ldr r0, [r3, #0] + 80008a0: 1cbb adds r3, r7, #2 + 80008a2: 781a ldrb r2, [r3, #0] + 80008a4: 2349 movs r3, #73 ; 0x49 + 80008a6: 2101 movs r1, #1 + 80008a8: f7ff fec0 bl 800062c +} + 80008ac: 46c0 nop ; (mov r8, r8) + 80008ae: 46bd mov sp, r7 + 80008b0: b004 add sp, #16 + 80008b2: bd80 pop {r7, pc} + +080008b4 : +// REQUIRES: spectral is a Spectral object and +// v_reg is the virtual register +// MODIFIES: nothing +// EFFECTS: Returns the value read from the virtual register +// as explained in page 18-20 of the datasheet +uint8_t virtual_read_spectral(Spectral *spectral, uint8_t v_reg, uint8_t *error) { + 80008b4: b580 push {r7, lr} + 80008b6: b086 sub sp, #24 + 80008b8: af00 add r7, sp, #0 + 80008ba: 60f8 str r0, [r7, #12] + 80008bc: 607a str r2, [r7, #4] + 80008be: 230b movs r3, #11 + 80008c0: 18fb adds r3, r7, r3 + 80008c2: 1c0a adds r2, r1, #0 + 80008c4: 701a strb r2, [r3, #0] + // Taken from datasheet + uint8_t has_error; + uint8_t d; + uint8_t counter; + has_error = ~smbus_check_error(spectral->smbus); + 80008c6: 68fb ldr r3, [r7, #12] + 80008c8: 681b ldr r3, [r3, #0] + 80008ca: 0018 movs r0, r3 + 80008cc: f7ff fe0e bl 80004ec + 80008d0: 0003 movs r3, r0 + 80008d2: b2da uxtb r2, r3 + 80008d4: 2117 movs r1, #23 + 80008d6: 187b adds r3, r7, r1 + 80008d8: 43d2 mvns r2, r2 + 80008da: 701a strb r2, [r3, #0] + + if ((has_error & I2C_AS72XX_SLAVE_RX_VALID) != 0) { + 80008dc: 187b adds r3, r7, r1 + 80008de: 781b ldrb r3, [r3, #0] + 80008e0: 2201 movs r2, #1 + 80008e2: 4013 ands r3, r2 + 80008e4: d00a beq.n 80008fc + d = smbus_read_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_READ_REG, DEVICE_SLAVE_ADDRESS); + 80008e6: 68fb ldr r3, [r7, #12] + 80008e8: 681b ldr r3, [r3, #0] + 80008ea: 2249 movs r2, #73 ; 0x49 + 80008ec: 2102 movs r1, #2 + 80008ee: 0018 movs r0, r3 + 80008f0: f7ff fe12 bl 8000518 + 80008f4: 0002 movs r2, r0 + 80008f6: 2315 movs r3, #21 + 80008f8: 18fb adds r3, r7, r3 + 80008fa: 701a strb r2, [r3, #0] + } + + counter = 0; + 80008fc: 2316 movs r3, #22 + 80008fe: 18fb adds r3, r7, r3 + 8000900: 2200 movs r2, #0 + 8000902: 701a strb r2, [r3, #0] + while(counter < 3) { + 8000904: e013 b.n 800092e + has_error = ~smbus_check_error(spectral->smbus); + 8000906: 68fb ldr r3, [r7, #12] + 8000908: 681b ldr r3, [r3, #0] + 800090a: 0018 movs r0, r3 + 800090c: f7ff fdee bl 80004ec + 8000910: 0003 movs r3, r0 + 8000912: b2da uxtb r2, r3 + 8000914: 2317 movs r3, #23 + 8000916: 18fb adds r3, r7, r3 + 8000918: 43d2 mvns r2, r2 + 800091a: 701a strb r2, [r3, #0] + // Why leave when status == 0? + HAL_Delay(5); //delay for 5 ms + 800091c: 2005 movs r0, #5 + 800091e: f000 fa0b bl 8000d38 + ++counter; + 8000922: 2216 movs r2, #22 + 8000924: 18bb adds r3, r7, r2 + 8000926: 18ba adds r2, r7, r2 + 8000928: 7812 ldrb r2, [r2, #0] + 800092a: 3201 adds r2, #1 + 800092c: 701a strb r2, [r3, #0] + while(counter < 3) { + 800092e: 2316 movs r3, #22 + 8000930: 18fb adds r3, r7, r3 + 8000932: 781b ldrb r3, [r3, #0] + 8000934: 2b02 cmp r3, #2 + 8000936: d9e6 bls.n 8000906 + } + if ((has_error & I2C_AS72XX_SLAVE_TX_VALID) == 0) { + 8000938: 2117 movs r1, #23 + 800093a: 187b adds r3, r7, r1 + 800093c: 781b ldrb r3, [r3, #0] + 800093e: 2202 movs r2, #2 + 8000940: 4013 ands r3, r2 + 8000942: d103 bne.n 800094c + *error = has_error; + 8000944: 687b ldr r3, [r7, #4] + 8000946: 187a adds r2, r7, r1 + 8000948: 7812 ldrb r2, [r2, #0] + 800094a: 701a strb r2, [r3, #0] + } + + smbus_write_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_WRITE_REG, v_reg, DEVICE_SLAVE_ADDRESS); + 800094c: 68fb ldr r3, [r7, #12] + 800094e: 6818 ldr r0, [r3, #0] + 8000950: 230b movs r3, #11 + 8000952: 18fb adds r3, r7, r3 + 8000954: 781a ldrb r2, [r3, #0] + 8000956: 2349 movs r3, #73 ; 0x49 + 8000958: 2101 movs r1, #1 + 800095a: f7ff fe67 bl 800062c + counter = 0; + 800095e: 2316 movs r3, #22 + 8000960: 18fb adds r3, r7, r3 + 8000962: 2200 movs r2, #0 + 8000964: 701a strb r2, [r3, #0] + while(counter < 3) { + 8000966: e013 b.n 8000990 + has_error = ~smbus_check_error(spectral->smbus); + 8000968: 68fb ldr r3, [r7, #12] + 800096a: 681b ldr r3, [r3, #0] + 800096c: 0018 movs r0, r3 + 800096e: f7ff fdbd bl 80004ec + 8000972: 0003 movs r3, r0 + 8000974: b2da uxtb r2, r3 + 8000976: 2317 movs r3, #23 + 8000978: 18fb adds r3, r7, r3 + 800097a: 43d2 mvns r2, r2 + 800097c: 701a strb r2, [r3, #0] + HAL_Delay(5); //delay for 5 ms + 800097e: 2005 movs r0, #5 + 8000980: f000 f9da bl 8000d38 + ++counter; + 8000984: 2216 movs r2, #22 + 8000986: 18bb adds r3, r7, r2 + 8000988: 18ba adds r2, r7, r2 + 800098a: 7812 ldrb r2, [r2, #0] + 800098c: 3201 adds r2, #1 + 800098e: 701a strb r2, [r3, #0] + while(counter < 3) { + 8000990: 2316 movs r3, #22 + 8000992: 18fb adds r3, r7, r3 + 8000994: 781b ldrb r3, [r3, #0] + 8000996: 2b02 cmp r3, #2 + 8000998: d9e6 bls.n 8000968 + } + + if ((has_error & I2C_AS72XX_SLAVE_RX_VALID) != 0) { + 800099a: 2117 movs r1, #23 + 800099c: 187b adds r3, r7, r1 + 800099e: 781b ldrb r3, [r3, #0] + 80009a0: 2201 movs r2, #1 + 80009a2: 4013 ands r3, r2 + 80009a4: d003 beq.n 80009ae + *error = has_error; + 80009a6: 687b ldr r3, [r7, #4] + 80009a8: 187a adds r2, r7, r1 + 80009aa: 7812 ldrb r2, [r2, #0] + 80009ac: 701a strb r2, [r3, #0] + } + d = smbus_read_byte_data(spectral->smbus, I2C_AS72XX_SLAVE_READ_REG, DEVICE_SLAVE_ADDRESS); + 80009ae: 68fb ldr r3, [r7, #12] + 80009b0: 681b ldr r3, [r3, #0] + 80009b2: 2249 movs r2, #73 ; 0x49 + 80009b4: 2102 movs r1, #2 + 80009b6: 0018 movs r0, r3 + 80009b8: f7ff fdae bl 8000518 + 80009bc: 0002 movs r2, r0 + 80009be: 2115 movs r1, #21 + 80009c0: 187b adds r3, r7, r1 + 80009c2: 701a strb r2, [r3, #0] + return d; + 80009c4: 187b adds r3, r7, r1 + 80009c6: 781b ldrb r3, [r3, #0] +} + 80009c8: 0018 movs r0, r3 + 80009ca: 46bd mov sp, r7 + 80009cc: b006 add sp, #24 + 80009ce: bd80 pop {r7, pc} + +080009d0 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80009d0: b580 push {r7, lr} + 80009d2: b082 sub sp, #8 + 80009d4: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80009d6: 4b0f ldr r3, [pc, #60] ; (8000a14 ) + 80009d8: 6c1a ldr r2, [r3, #64] ; 0x40 + 80009da: 4b0e ldr r3, [pc, #56] ; (8000a14 ) + 80009dc: 2101 movs r1, #1 + 80009de: 430a orrs r2, r1 + 80009e0: 641a str r2, [r3, #64] ; 0x40 + 80009e2: 4b0c ldr r3, [pc, #48] ; (8000a14 ) + 80009e4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80009e6: 2201 movs r2, #1 + 80009e8: 4013 ands r3, r2 + 80009ea: 607b str r3, [r7, #4] + 80009ec: 687b ldr r3, [r7, #4] + __HAL_RCC_PWR_CLK_ENABLE(); + 80009ee: 4b09 ldr r3, [pc, #36] ; (8000a14 ) + 80009f0: 6bda ldr r2, [r3, #60] ; 0x3c + 80009f2: 4b08 ldr r3, [pc, #32] ; (8000a14 ) + 80009f4: 2180 movs r1, #128 ; 0x80 + 80009f6: 0549 lsls r1, r1, #21 + 80009f8: 430a orrs r2, r1 + 80009fa: 63da str r2, [r3, #60] ; 0x3c + 80009fc: 4b05 ldr r3, [pc, #20] ; (8000a14 ) + 80009fe: 6bda ldr r2, [r3, #60] ; 0x3c + 8000a00: 2380 movs r3, #128 ; 0x80 + 8000a02: 055b lsls r3, r3, #21 + 8000a04: 4013 ands r3, r2 + 8000a06: 603b str r3, [r7, #0] + 8000a08: 683b ldr r3, [r7, #0] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000a0a: 46c0 nop ; (mov r8, r8) + 8000a0c: 46bd mov sp, r7 + 8000a0e: b002 add sp, #8 + 8000a10: bd80 pop {r7, pc} + 8000a12: 46c0 nop ; (mov r8, r8) + 8000a14: 40021000 .word 0x40021000 + +08000a18 : +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + 8000a18: b590 push {r4, r7, lr} + 8000a1a: b09d sub sp, #116 ; 0x74 + 8000a1c: af00 add r7, sp, #0 + 8000a1e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000a20: 235c movs r3, #92 ; 0x5c + 8000a22: 18fb adds r3, r7, r3 + 8000a24: 0018 movs r0, r3 + 8000a26: 2314 movs r3, #20 + 8000a28: 001a movs r2, r3 + 8000a2a: 2100 movs r1, #0 + 8000a2c: f004 fb4a bl 80050c4 + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 8000a30: 2410 movs r4, #16 + 8000a32: 193b adds r3, r7, r4 + 8000a34: 0018 movs r0, r3 + 8000a36: 234c movs r3, #76 ; 0x4c + 8000a38: 001a movs r2, r3 + 8000a3a: 2100 movs r1, #0 + 8000a3c: f004 fb42 bl 80050c4 + if(hi2c->Instance==I2C1) + 8000a40: 687b ldr r3, [r7, #4] + 8000a42: 681b ldr r3, [r3, #0] + 8000a44: 4a23 ldr r2, [pc, #140] ; (8000ad4 ) + 8000a46: 4293 cmp r3, r2 + 8000a48: d13f bne.n 8000aca + + /* USER CODE END I2C1_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; + 8000a4a: 193b adds r3, r7, r4 + 8000a4c: 2220 movs r2, #32 + 8000a4e: 601a str r2, [r3, #0] + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + 8000a50: 193b adds r3, r7, r4 + 8000a52: 2200 movs r2, #0 + 8000a54: 619a str r2, [r3, #24] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8000a56: 193b adds r3, r7, r4 + 8000a58: 0018 movs r0, r3 + 8000a5a: f004 f839 bl 8004ad0 + 8000a5e: 1e03 subs r3, r0, #0 + 8000a60: d001 beq.n 8000a66 + { + Error_Handler(); + 8000a62: f7ff fd1b bl 800049c + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000a66: 4b1c ldr r3, [pc, #112] ; (8000ad8 ) + 8000a68: 6b5a ldr r2, [r3, #52] ; 0x34 + 8000a6a: 4b1b ldr r3, [pc, #108] ; (8000ad8 ) + 8000a6c: 2101 movs r1, #1 + 8000a6e: 430a orrs r2, r1 + 8000a70: 635a str r2, [r3, #52] ; 0x34 + 8000a72: 4b19 ldr r3, [pc, #100] ; (8000ad8 ) + 8000a74: 6b5b ldr r3, [r3, #52] ; 0x34 + 8000a76: 2201 movs r2, #1 + 8000a78: 4013 ands r3, r2 + 8000a7a: 60fb str r3, [r7, #12] + 8000a7c: 68fb ldr r3, [r7, #12] + /**I2C1 GPIO Configuration + PA9 ------> I2C1_SCL + PA10 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + 8000a7e: 215c movs r1, #92 ; 0x5c + 8000a80: 187b adds r3, r7, r1 + 8000a82: 22c0 movs r2, #192 ; 0xc0 + 8000a84: 00d2 lsls r2, r2, #3 + 8000a86: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8000a88: 187b adds r3, r7, r1 + 8000a8a: 2212 movs r2, #18 + 8000a8c: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8000a8e: 187b adds r3, r7, r1 + 8000a90: 2201 movs r2, #1 + 8000a92: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000a94: 187b adds r3, r7, r1 + 8000a96: 2203 movs r2, #3 + 8000a98: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF6_I2C1; + 8000a9a: 187b adds r3, r7, r1 + 8000a9c: 2206 movs r2, #6 + 8000a9e: 611a str r2, [r3, #16] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000aa0: 187a adds r2, r7, r1 + 8000aa2: 23a0 movs r3, #160 ; 0xa0 + 8000aa4: 05db lsls r3, r3, #23 + 8000aa6: 0011 movs r1, r2 + 8000aa8: 0018 movs r0, r3 + 8000aaa: f000 fb53 bl 8001154 + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 8000aae: 4b0a ldr r3, [pc, #40] ; (8000ad8 ) + 8000ab0: 6bda ldr r2, [r3, #60] ; 0x3c + 8000ab2: 4b09 ldr r3, [pc, #36] ; (8000ad8 ) + 8000ab4: 2180 movs r1, #128 ; 0x80 + 8000ab6: 0389 lsls r1, r1, #14 + 8000ab8: 430a orrs r2, r1 + 8000aba: 63da str r2, [r3, #60] ; 0x3c + 8000abc: 4b06 ldr r3, [pc, #24] ; (8000ad8 ) + 8000abe: 6bda ldr r2, [r3, #60] ; 0x3c + 8000ac0: 2380 movs r3, #128 ; 0x80 + 8000ac2: 039b lsls r3, r3, #14 + 8000ac4: 4013 ands r3, r2 + 8000ac6: 60bb str r3, [r7, #8] + 8000ac8: 68bb ldr r3, [r7, #8] + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + +} + 8000aca: 46c0 nop ; (mov r8, r8) + 8000acc: 46bd mov sp, r7 + 8000ace: b01d add sp, #116 ; 0x74 + 8000ad0: bd90 pop {r4, r7, pc} + 8000ad2: 46c0 nop ; (mov r8, r8) + 8000ad4: 40005400 .word 0x40005400 + 8000ad8: 40021000 .word 0x40021000 + +08000adc : +* This function freeze the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + 8000adc: b580 push {r7, lr} + 8000ade: b082 sub sp, #8 + 8000ae0: af00 add r7, sp, #0 + 8000ae2: 6078 str r0, [r7, #4] + if(hi2c->Instance==I2C1) + 8000ae4: 687b ldr r3, [r7, #4] + 8000ae6: 681b ldr r3, [r3, #0] + 8000ae8: 4a0e ldr r2, [pc, #56] ; (8000b24 ) + 8000aea: 4293 cmp r3, r2 + 8000aec: d115 bne.n 8000b1a + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + 8000aee: 4b0e ldr r3, [pc, #56] ; (8000b28 ) + 8000af0: 6bda ldr r2, [r3, #60] ; 0x3c + 8000af2: 4b0d ldr r3, [pc, #52] ; (8000b28 ) + 8000af4: 490d ldr r1, [pc, #52] ; (8000b2c ) + 8000af6: 400a ands r2, r1 + 8000af8: 63da str r2, [r3, #60] ; 0x3c + + /**I2C1 GPIO Configuration + PA9 ------> I2C1_SCL + PA10 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9); + 8000afa: 2380 movs r3, #128 ; 0x80 + 8000afc: 009a lsls r2, r3, #2 + 8000afe: 23a0 movs r3, #160 ; 0xa0 + 8000b00: 05db lsls r3, r3, #23 + 8000b02: 0011 movs r1, r2 + 8000b04: 0018 movs r0, r3 + 8000b06: f000 fc91 bl 800142c + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10); + 8000b0a: 2380 movs r3, #128 ; 0x80 + 8000b0c: 00da lsls r2, r3, #3 + 8000b0e: 23a0 movs r3, #160 ; 0xa0 + 8000b10: 05db lsls r3, r3, #23 + 8000b12: 0011 movs r1, r2 + 8000b14: 0018 movs r0, r3 + 8000b16: f000 fc89 bl 800142c + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } + +} + 8000b1a: 46c0 nop ; (mov r8, r8) + 8000b1c: 46bd mov sp, r7 + 8000b1e: b002 add sp, #8 + 8000b20: bd80 pop {r7, pc} + 8000b22: 46c0 nop ; (mov r8, r8) + 8000b24: 40005400 .word 0x40005400 + 8000b28: 40021000 .word 0x40021000 + 8000b2c: ffdfffff .word 0xffdfffff + +08000b30 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000b30: b580 push {r7, lr} + 8000b32: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000b34: e7fe b.n 8000b34 + +08000b36 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000b36: b580 push {r7, lr} + 8000b38: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000b3a: e7fe b.n 8000b3a + +08000b3c : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000b3c: b580 push {r7, lr} + 8000b3e: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8000b40: 46c0 nop ; (mov r8, r8) + 8000b42: 46bd mov sp, r7 + 8000b44: bd80 pop {r7, pc} + +08000b46 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000b46: b580 push {r7, lr} + 8000b48: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000b4a: 46c0 nop ; (mov r8, r8) + 8000b4c: 46bd mov sp, r7 + 8000b4e: bd80 pop {r7, pc} + +08000b50 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000b50: b580 push {r7, lr} + 8000b52: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000b54: f000 f8d4 bl 8000d00 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000b58: 46c0 nop ; (mov r8, r8) + 8000b5a: 46bd mov sp, r7 + 8000b5c: bd80 pop {r7, pc} + ... + +08000b60 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 8000b60: b580 push {r7, lr} + 8000b62: b086 sub sp, #24 + 8000b64: af00 add r7, sp, #0 + 8000b66: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 8000b68: 4a14 ldr r2, [pc, #80] ; (8000bbc <_sbrk+0x5c>) + 8000b6a: 4b15 ldr r3, [pc, #84] ; (8000bc0 <_sbrk+0x60>) + 8000b6c: 1ad3 subs r3, r2, r3 + 8000b6e: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 8000b70: 697b ldr r3, [r7, #20] + 8000b72: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 8000b74: 4b13 ldr r3, [pc, #76] ; (8000bc4 <_sbrk+0x64>) + 8000b76: 681b ldr r3, [r3, #0] + 8000b78: 2b00 cmp r3, #0 + 8000b7a: d102 bne.n 8000b82 <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 8000b7c: 4b11 ldr r3, [pc, #68] ; (8000bc4 <_sbrk+0x64>) + 8000b7e: 4a12 ldr r2, [pc, #72] ; (8000bc8 <_sbrk+0x68>) + 8000b80: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 8000b82: 4b10 ldr r3, [pc, #64] ; (8000bc4 <_sbrk+0x64>) + 8000b84: 681a ldr r2, [r3, #0] + 8000b86: 687b ldr r3, [r7, #4] + 8000b88: 18d3 adds r3, r2, r3 + 8000b8a: 693a ldr r2, [r7, #16] + 8000b8c: 429a cmp r2, r3 + 8000b8e: d207 bcs.n 8000ba0 <_sbrk+0x40> + { + errno = ENOMEM; + 8000b90: f004 fab2 bl 80050f8 <__errno> + 8000b94: 0003 movs r3, r0 + 8000b96: 220c movs r2, #12 + 8000b98: 601a str r2, [r3, #0] + return (void *)-1; + 8000b9a: 2301 movs r3, #1 + 8000b9c: 425b negs r3, r3 + 8000b9e: e009 b.n 8000bb4 <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 8000ba0: 4b08 ldr r3, [pc, #32] ; (8000bc4 <_sbrk+0x64>) + 8000ba2: 681b ldr r3, [r3, #0] + 8000ba4: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 8000ba6: 4b07 ldr r3, [pc, #28] ; (8000bc4 <_sbrk+0x64>) + 8000ba8: 681a ldr r2, [r3, #0] + 8000baa: 687b ldr r3, [r7, #4] + 8000bac: 18d2 adds r2, r2, r3 + 8000bae: 4b05 ldr r3, [pc, #20] ; (8000bc4 <_sbrk+0x64>) + 8000bb0: 601a str r2, [r3, #0] + + return (void *)prev_heap_end; + 8000bb2: 68fb ldr r3, [r7, #12] +} + 8000bb4: 0018 movs r0, r3 + 8000bb6: 46bd mov sp, r7 + 8000bb8: b006 add sp, #24 + 8000bba: bd80 pop {r7, pc} + 8000bbc: 20024000 .word 0x20024000 + 8000bc0: 00000400 .word 0x00000400 + 8000bc4: 200000e0 .word 0x200000e0 + 8000bc8: 20000230 .word 0x20000230 + +08000bcc : + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8000bcc: b580 push {r7, lr} + 8000bce: af00 add r7, sp, #0 + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000bd0: 46c0 nop ; (mov r8, r8) + 8000bd2: 46bd mov sp, r7 + 8000bd4: bd80 pop {r7, pc} + ... + +08000bd8 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 8000bd8: 480d ldr r0, [pc, #52] ; (8000c10 ) + mov sp, r0 /* set stack pointer */ + 8000bda: 4685 mov sp, r0 + +/* Call the clock system initialization function.*/ + bl SystemInit + 8000bdc: f7ff fff6 bl 8000bcc + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000be0: 480c ldr r0, [pc, #48] ; (8000c14 ) + ldr r1, =_edata + 8000be2: 490d ldr r1, [pc, #52] ; (8000c18 ) + ldr r2, =_sidata + 8000be4: 4a0d ldr r2, [pc, #52] ; (8000c1c ) + movs r3, #0 + 8000be6: 2300 movs r3, #0 + b LoopCopyDataInit + 8000be8: e002 b.n 8000bf0 + +08000bea : + +CopyDataInit: + ldr r4, [r2, r3] + 8000bea: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8000bec: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8000bee: 3304 adds r3, #4 + +08000bf0 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000bf0: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000bf2: 428c cmp r4, r1 + bcc CopyDataInit + 8000bf4: d3f9 bcc.n 8000bea + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8000bf6: 4a0a ldr r2, [pc, #40] ; (8000c20 ) + ldr r4, =_ebss + 8000bf8: 4c0a ldr r4, [pc, #40] ; (8000c24 ) + movs r3, #0 + 8000bfa: 2300 movs r3, #0 + b LoopFillZerobss + 8000bfc: e001 b.n 8000c02 + +08000bfe : + +FillZerobss: + str r3, [r2] + 8000bfe: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000c00: 3204 adds r2, #4 + +08000c02 : + +LoopFillZerobss: + cmp r2, r4 + 8000c02: 42a2 cmp r2, r4 + bcc FillZerobss + 8000c04: d3fb bcc.n 8000bfe + +/* Call static constructors */ + bl __libc_init_array + 8000c06: f004 fa7d bl 8005104 <__libc_init_array> +/* Call the application s entry point.*/ + bl main + 8000c0a: f7ff fb07 bl 800021c
+ +08000c0e : + +LoopForever: + b LoopForever + 8000c0e: e7fe b.n 8000c0e + ldr r0, =_estack + 8000c10: 20024000 .word 0x20024000 + ldr r0, =_sdata + 8000c14: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000c18: 2000005c .word 0x2000005c + ldr r2, =_sidata + 8000c1c: 080051b0 .word 0x080051b0 + ldr r2, =_sbss + 8000c20: 2000005c .word 0x2000005c + ldr r4, =_ebss + 8000c24: 20000230 .word 0x20000230 + +08000c28 : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000c28: e7fe b.n 8000c28 + ... + +08000c2c : + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000c2c: b580 push {r7, lr} + 8000c2e: b082 sub sp, #8 + 8000c30: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8000c32: 1dfb adds r3, r7, #7 + 8000c34: 2200 movs r2, #0 + 8000c36: 701a strb r2, [r3, #0] +#if (INSTRUCTION_CACHE_ENABLE == 0U) + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 8000c38: 4b0b ldr r3, [pc, #44] ; (8000c68 ) + 8000c3a: 681a ldr r2, [r3, #0] + 8000c3c: 4b0a ldr r3, [pc, #40] ; (8000c68 ) + 8000c3e: 2180 movs r1, #128 ; 0x80 + 8000c40: 0049 lsls r1, r1, #1 + 8000c42: 430a orrs r2, r1 + 8000c44: 601a str r2, [r3, #0] +#endif /* PREFETCH_ENABLE */ + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000c46: 2000 movs r0, #0 + 8000c48: f000 f810 bl 8000c6c + 8000c4c: 1e03 subs r3, r0, #0 + 8000c4e: d003 beq.n 8000c58 + { + status = HAL_ERROR; + 8000c50: 1dfb adds r3, r7, #7 + 8000c52: 2201 movs r2, #1 + 8000c54: 701a strb r2, [r3, #0] + 8000c56: e001 b.n 8000c5c + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8000c58: f7ff feba bl 80009d0 + } + + /* Return function status */ + return status; + 8000c5c: 1dfb adds r3, r7, #7 + 8000c5e: 781b ldrb r3, [r3, #0] +} + 8000c60: 0018 movs r0, r3 + 8000c62: 46bd mov sp, r7 + 8000c64: b002 add sp, #8 + 8000c66: bd80 pop {r7, pc} + 8000c68: 40022000 .word 0x40022000 + +08000c6c : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000c6c: b590 push {r4, r7, lr} + 8000c6e: b085 sub sp, #20 + 8000c70: af00 add r7, sp, #0 + 8000c72: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8000c74: 230f movs r3, #15 + 8000c76: 18fb adds r3, r7, r3 + 8000c78: 2200 movs r2, #0 + 8000c7a: 701a strb r2, [r3, #0] + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ + if ((uint32_t)uwTickFreq != 0U) + 8000c7c: 4b1d ldr r3, [pc, #116] ; (8000cf4 ) + 8000c7e: 781b ldrb r3, [r3, #0] + 8000c80: 2b00 cmp r3, #0 + 8000c82: d02b beq.n 8000cdc + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) + 8000c84: 4b1c ldr r3, [pc, #112] ; (8000cf8 ) + 8000c86: 681c ldr r4, [r3, #0] + 8000c88: 4b1a ldr r3, [pc, #104] ; (8000cf4 ) + 8000c8a: 781b ldrb r3, [r3, #0] + 8000c8c: 0019 movs r1, r3 + 8000c8e: 23fa movs r3, #250 ; 0xfa + 8000c90: 0098 lsls r0, r3, #2 + 8000c92: f7ff fa37 bl 8000104 <__udivsi3> + 8000c96: 0003 movs r3, r0 + 8000c98: 0019 movs r1, r3 + 8000c9a: 0020 movs r0, r4 + 8000c9c: f7ff fa32 bl 8000104 <__udivsi3> + 8000ca0: 0003 movs r3, r0 + 8000ca2: 0018 movs r0, r3 + 8000ca4: f000 f913 bl 8000ece + 8000ca8: 1e03 subs r3, r0, #0 + 8000caa: d112 bne.n 8000cd2 + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000cac: 687b ldr r3, [r7, #4] + 8000cae: 2b03 cmp r3, #3 + 8000cb0: d80a bhi.n 8000cc8 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000cb2: 6879 ldr r1, [r7, #4] + 8000cb4: 2301 movs r3, #1 + 8000cb6: 425b negs r3, r3 + 8000cb8: 2200 movs r2, #0 + 8000cba: 0018 movs r0, r3 + 8000cbc: f000 f8f2 bl 8000ea4 + uwTickPrio = TickPriority; + 8000cc0: 4b0e ldr r3, [pc, #56] ; (8000cfc ) + 8000cc2: 687a ldr r2, [r7, #4] + 8000cc4: 601a str r2, [r3, #0] + 8000cc6: e00d b.n 8000ce4 + } + else + { + status = HAL_ERROR; + 8000cc8: 230f movs r3, #15 + 8000cca: 18fb adds r3, r7, r3 + 8000ccc: 2201 movs r2, #1 + 8000cce: 701a strb r2, [r3, #0] + 8000cd0: e008 b.n 8000ce4 + } + } + else + { + status = HAL_ERROR; + 8000cd2: 230f movs r3, #15 + 8000cd4: 18fb adds r3, r7, r3 + 8000cd6: 2201 movs r2, #1 + 8000cd8: 701a strb r2, [r3, #0] + 8000cda: e003 b.n 8000ce4 + } + } + else + { + status = HAL_ERROR; + 8000cdc: 230f movs r3, #15 + 8000cde: 18fb adds r3, r7, r3 + 8000ce0: 2201 movs r2, #1 + 8000ce2: 701a strb r2, [r3, #0] + } + + /* Return function status */ + return status; + 8000ce4: 230f movs r3, #15 + 8000ce6: 18fb adds r3, r7, r3 + 8000ce8: 781b ldrb r3, [r3, #0] +} + 8000cea: 0018 movs r0, r3 + 8000cec: 46bd mov sp, r7 + 8000cee: b005 add sp, #20 + 8000cf0: bd90 pop {r4, r7, pc} + 8000cf2: 46c0 nop ; (mov r8, r8) + 8000cf4: 20000008 .word 0x20000008 + 8000cf8: 20000000 .word 0x20000000 + 8000cfc: 20000004 .word 0x20000004 + +08000d00 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000d00: b580 push {r7, lr} + 8000d02: af00 add r7, sp, #0 + uwTick += (uint32_t)uwTickFreq; + 8000d04: 4b05 ldr r3, [pc, #20] ; (8000d1c ) + 8000d06: 781b ldrb r3, [r3, #0] + 8000d08: 001a movs r2, r3 + 8000d0a: 4b05 ldr r3, [pc, #20] ; (8000d20 ) + 8000d0c: 681b ldr r3, [r3, #0] + 8000d0e: 18d2 adds r2, r2, r3 + 8000d10: 4b03 ldr r3, [pc, #12] ; (8000d20 ) + 8000d12: 601a str r2, [r3, #0] +} + 8000d14: 46c0 nop ; (mov r8, r8) + 8000d16: 46bd mov sp, r7 + 8000d18: bd80 pop {r7, pc} + 8000d1a: 46c0 nop ; (mov r8, r8) + 8000d1c: 20000008 .word 0x20000008 + 8000d20: 200000e4 .word 0x200000e4 + +08000d24 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000d24: b580 push {r7, lr} + 8000d26: af00 add r7, sp, #0 + return uwTick; + 8000d28: 4b02 ldr r3, [pc, #8] ; (8000d34 ) + 8000d2a: 681b ldr r3, [r3, #0] +} + 8000d2c: 0018 movs r0, r3 + 8000d2e: 46bd mov sp, r7 + 8000d30: bd80 pop {r7, pc} + 8000d32: 46c0 nop ; (mov r8, r8) + 8000d34: 200000e4 .word 0x200000e4 + +08000d38 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000d38: b580 push {r7, lr} + 8000d3a: b084 sub sp, #16 + 8000d3c: af00 add r7, sp, #0 + 8000d3e: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8000d40: f7ff fff0 bl 8000d24 + 8000d44: 0003 movs r3, r0 + 8000d46: 60bb str r3, [r7, #8] + uint32_t wait = Delay; + 8000d48: 687b ldr r3, [r7, #4] + 8000d4a: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 8000d4c: 68fb ldr r3, [r7, #12] + 8000d4e: 3301 adds r3, #1 + 8000d50: d005 beq.n 8000d5e + { + wait += (uint32_t)(uwTickFreq); + 8000d52: 4b0a ldr r3, [pc, #40] ; (8000d7c ) + 8000d54: 781b ldrb r3, [r3, #0] + 8000d56: 001a movs r2, r3 + 8000d58: 68fb ldr r3, [r7, #12] + 8000d5a: 189b adds r3, r3, r2 + 8000d5c: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait) + 8000d5e: 46c0 nop ; (mov r8, r8) + 8000d60: f7ff ffe0 bl 8000d24 + 8000d64: 0002 movs r2, r0 + 8000d66: 68bb ldr r3, [r7, #8] + 8000d68: 1ad3 subs r3, r2, r3 + 8000d6a: 68fa ldr r2, [r7, #12] + 8000d6c: 429a cmp r2, r3 + 8000d6e: d8f7 bhi.n 8000d60 + { + } +} + 8000d70: 46c0 nop ; (mov r8, r8) + 8000d72: 46c0 nop ; (mov r8, r8) + 8000d74: 46bd mov sp, r7 + 8000d76: b004 add sp, #16 + 8000d78: bd80 pop {r7, pc} + 8000d7a: 46c0 nop ; (mov r8, r8) + 8000d7c: 20000008 .word 0x20000008 + +08000d80 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000d80: b590 push {r4, r7, lr} + 8000d82: b083 sub sp, #12 + 8000d84: af00 add r7, sp, #0 + 8000d86: 0002 movs r2, r0 + 8000d88: 6039 str r1, [r7, #0] + 8000d8a: 1dfb adds r3, r7, #7 + 8000d8c: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 8000d8e: 1dfb adds r3, r7, #7 + 8000d90: 781b ldrb r3, [r3, #0] + 8000d92: 2b7f cmp r3, #127 ; 0x7f + 8000d94: d828 bhi.n 8000de8 <__NVIC_SetPriority+0x68> + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000d96: 4a2f ldr r2, [pc, #188] ; (8000e54 <__NVIC_SetPriority+0xd4>) + 8000d98: 1dfb adds r3, r7, #7 + 8000d9a: 781b ldrb r3, [r3, #0] + 8000d9c: b25b sxtb r3, r3 + 8000d9e: 089b lsrs r3, r3, #2 + 8000da0: 33c0 adds r3, #192 ; 0xc0 + 8000da2: 009b lsls r3, r3, #2 + 8000da4: 589b ldr r3, [r3, r2] + 8000da6: 1dfa adds r2, r7, #7 + 8000da8: 7812 ldrb r2, [r2, #0] + 8000daa: 0011 movs r1, r2 + 8000dac: 2203 movs r2, #3 + 8000dae: 400a ands r2, r1 + 8000db0: 00d2 lsls r2, r2, #3 + 8000db2: 21ff movs r1, #255 ; 0xff + 8000db4: 4091 lsls r1, r2 + 8000db6: 000a movs r2, r1 + 8000db8: 43d2 mvns r2, r2 + 8000dba: 401a ands r2, r3 + 8000dbc: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8000dbe: 683b ldr r3, [r7, #0] + 8000dc0: 019b lsls r3, r3, #6 + 8000dc2: 22ff movs r2, #255 ; 0xff + 8000dc4: 401a ands r2, r3 + 8000dc6: 1dfb adds r3, r7, #7 + 8000dc8: 781b ldrb r3, [r3, #0] + 8000dca: 0018 movs r0, r3 + 8000dcc: 2303 movs r3, #3 + 8000dce: 4003 ands r3, r0 + 8000dd0: 00db lsls r3, r3, #3 + 8000dd2: 409a lsls r2, r3 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000dd4: 481f ldr r0, [pc, #124] ; (8000e54 <__NVIC_SetPriority+0xd4>) + 8000dd6: 1dfb adds r3, r7, #7 + 8000dd8: 781b ldrb r3, [r3, #0] + 8000dda: b25b sxtb r3, r3 + 8000ddc: 089b lsrs r3, r3, #2 + 8000dde: 430a orrs r2, r1 + 8000de0: 33c0 adds r3, #192 ; 0xc0 + 8000de2: 009b lsls r3, r3, #2 + 8000de4: 501a str r2, [r3, r0] + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + 8000de6: e031 b.n 8000e4c <__NVIC_SetPriority+0xcc> + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000de8: 4a1b ldr r2, [pc, #108] ; (8000e58 <__NVIC_SetPriority+0xd8>) + 8000dea: 1dfb adds r3, r7, #7 + 8000dec: 781b ldrb r3, [r3, #0] + 8000dee: 0019 movs r1, r3 + 8000df0: 230f movs r3, #15 + 8000df2: 400b ands r3, r1 + 8000df4: 3b08 subs r3, #8 + 8000df6: 089b lsrs r3, r3, #2 + 8000df8: 3306 adds r3, #6 + 8000dfa: 009b lsls r3, r3, #2 + 8000dfc: 18d3 adds r3, r2, r3 + 8000dfe: 3304 adds r3, #4 + 8000e00: 681b ldr r3, [r3, #0] + 8000e02: 1dfa adds r2, r7, #7 + 8000e04: 7812 ldrb r2, [r2, #0] + 8000e06: 0011 movs r1, r2 + 8000e08: 2203 movs r2, #3 + 8000e0a: 400a ands r2, r1 + 8000e0c: 00d2 lsls r2, r2, #3 + 8000e0e: 21ff movs r1, #255 ; 0xff + 8000e10: 4091 lsls r1, r2 + 8000e12: 000a movs r2, r1 + 8000e14: 43d2 mvns r2, r2 + 8000e16: 401a ands r2, r3 + 8000e18: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8000e1a: 683b ldr r3, [r7, #0] + 8000e1c: 019b lsls r3, r3, #6 + 8000e1e: 22ff movs r2, #255 ; 0xff + 8000e20: 401a ands r2, r3 + 8000e22: 1dfb adds r3, r7, #7 + 8000e24: 781b ldrb r3, [r3, #0] + 8000e26: 0018 movs r0, r3 + 8000e28: 2303 movs r3, #3 + 8000e2a: 4003 ands r3, r0 + 8000e2c: 00db lsls r3, r3, #3 + 8000e2e: 409a lsls r2, r3 + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000e30: 4809 ldr r0, [pc, #36] ; (8000e58 <__NVIC_SetPriority+0xd8>) + 8000e32: 1dfb adds r3, r7, #7 + 8000e34: 781b ldrb r3, [r3, #0] + 8000e36: 001c movs r4, r3 + 8000e38: 230f movs r3, #15 + 8000e3a: 4023 ands r3, r4 + 8000e3c: 3b08 subs r3, #8 + 8000e3e: 089b lsrs r3, r3, #2 + 8000e40: 430a orrs r2, r1 + 8000e42: 3306 adds r3, #6 + 8000e44: 009b lsls r3, r3, #2 + 8000e46: 18c3 adds r3, r0, r3 + 8000e48: 3304 adds r3, #4 + 8000e4a: 601a str r2, [r3, #0] +} + 8000e4c: 46c0 nop ; (mov r8, r8) + 8000e4e: 46bd mov sp, r7 + 8000e50: b003 add sp, #12 + 8000e52: bd90 pop {r4, r7, pc} + 8000e54: e000e100 .word 0xe000e100 + 8000e58: e000ed00 .word 0xe000ed00 + +08000e5c : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8000e5c: b580 push {r7, lr} + 8000e5e: b082 sub sp, #8 + 8000e60: af00 add r7, sp, #0 + 8000e62: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000e64: 687b ldr r3, [r7, #4] + 8000e66: 1e5a subs r2, r3, #1 + 8000e68: 2380 movs r3, #128 ; 0x80 + 8000e6a: 045b lsls r3, r3, #17 + 8000e6c: 429a cmp r2, r3 + 8000e6e: d301 bcc.n 8000e74 + { + return (1UL); /* Reload value impossible */ + 8000e70: 2301 movs r3, #1 + 8000e72: e010 b.n 8000e96 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000e74: 4b0a ldr r3, [pc, #40] ; (8000ea0 ) + 8000e76: 687a ldr r2, [r7, #4] + 8000e78: 3a01 subs r2, #1 + 8000e7a: 605a str r2, [r3, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8000e7c: 2301 movs r3, #1 + 8000e7e: 425b negs r3, r3 + 8000e80: 2103 movs r1, #3 + 8000e82: 0018 movs r0, r3 + 8000e84: f7ff ff7c bl 8000d80 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000e88: 4b05 ldr r3, [pc, #20] ; (8000ea0 ) + 8000e8a: 2200 movs r2, #0 + 8000e8c: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000e8e: 4b04 ldr r3, [pc, #16] ; (8000ea0 ) + 8000e90: 2207 movs r2, #7 + 8000e92: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000e94: 2300 movs r3, #0 +} + 8000e96: 0018 movs r0, r3 + 8000e98: 46bd mov sp, r7 + 8000e9a: b002 add sp, #8 + 8000e9c: bd80 pop {r7, pc} + 8000e9e: 46c0 nop ; (mov r8, r8) + 8000ea0: e000e010 .word 0xe000e010 + +08000ea4 : + * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0+ based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000ea4: b580 push {r7, lr} + 8000ea6: b084 sub sp, #16 + 8000ea8: af00 add r7, sp, #0 + 8000eaa: 60b9 str r1, [r7, #8] + 8000eac: 607a str r2, [r7, #4] + 8000eae: 210f movs r1, #15 + 8000eb0: 187b adds r3, r7, r1 + 8000eb2: 1c02 adds r2, r0, #0 + 8000eb4: 701a strb r2, [r3, #0] + /* Prevent unused argument(s) compilation warning */ + UNUSED(SubPriority); + + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn, PreemptPriority); + 8000eb6: 68ba ldr r2, [r7, #8] + 8000eb8: 187b adds r3, r7, r1 + 8000eba: 781b ldrb r3, [r3, #0] + 8000ebc: b25b sxtb r3, r3 + 8000ebe: 0011 movs r1, r2 + 8000ec0: 0018 movs r0, r3 + 8000ec2: f7ff ff5d bl 8000d80 <__NVIC_SetPriority> +} + 8000ec6: 46c0 nop ; (mov r8, r8) + 8000ec8: 46bd mov sp, r7 + 8000eca: b004 add sp, #16 + 8000ecc: bd80 pop {r7, pc} + +08000ece : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8000ece: b580 push {r7, lr} + 8000ed0: b082 sub sp, #8 + 8000ed2: af00 add r7, sp, #0 + 8000ed4: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8000ed6: 687b ldr r3, [r7, #4] + 8000ed8: 0018 movs r0, r3 + 8000eda: f7ff ffbf bl 8000e5c + 8000ede: 0003 movs r3, r0 +} + 8000ee0: 0018 movs r0, r3 + 8000ee2: 46bd mov sp, r7 + 8000ee4: b002 add sp, #8 + 8000ee6: bd80 pop {r7, pc} + +08000ee8 : + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength) +{ + 8000ee8: b580 push {r7, lr} + 8000eea: b086 sub sp, #24 + 8000eec: af00 add r7, sp, #0 + 8000eee: 60f8 str r0, [r7, #12] + 8000ef0: 60b9 str r1, [r7, #8] + 8000ef2: 607a str r2, [r7, #4] + 8000ef4: 603b str r3, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8000ef6: 2317 movs r3, #23 + 8000ef8: 18fb adds r3, r7, r3 + 8000efa: 2200 movs r2, #0 + 8000efc: 701a strb r2, [r3, #0] + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + 8000efe: 68fb ldr r3, [r7, #12] + 8000f00: 2224 movs r2, #36 ; 0x24 + 8000f02: 5c9b ldrb r3, [r3, r2] + 8000f04: 2b01 cmp r3, #1 + 8000f06: d101 bne.n 8000f0c + 8000f08: 2302 movs r3, #2 + 8000f0a: e06f b.n 8000fec + 8000f0c: 68fb ldr r3, [r7, #12] + 8000f0e: 2224 movs r2, #36 ; 0x24 + 8000f10: 2101 movs r1, #1 + 8000f12: 5499 strb r1, [r3, r2] + + if (hdma->State == HAL_DMA_STATE_READY) + 8000f14: 68fb ldr r3, [r7, #12] + 8000f16: 2225 movs r2, #37 ; 0x25 + 8000f18: 5c9b ldrb r3, [r3, r2] + 8000f1a: b2db uxtb r3, r3 + 8000f1c: 2b01 cmp r3, #1 + 8000f1e: d157 bne.n 8000fd0 + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8000f20: 68fb ldr r3, [r7, #12] + 8000f22: 2225 movs r2, #37 ; 0x25 + 8000f24: 2102 movs r1, #2 + 8000f26: 5499 strb r1, [r3, r2] + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8000f28: 68fb ldr r3, [r7, #12] + 8000f2a: 2200 movs r2, #0 + 8000f2c: 63da str r2, [r3, #60] ; 0x3c + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + 8000f2e: 68fb ldr r3, [r7, #12] + 8000f30: 681b ldr r3, [r3, #0] + 8000f32: 681a ldr r2, [r3, #0] + 8000f34: 68fb ldr r3, [r7, #12] + 8000f36: 681b ldr r3, [r3, #0] + 8000f38: 2101 movs r1, #1 + 8000f3a: 438a bics r2, r1 + 8000f3c: 601a str r2, [r3, #0] + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 8000f3e: 683b ldr r3, [r7, #0] + 8000f40: 687a ldr r2, [r7, #4] + 8000f42: 68b9 ldr r1, [r7, #8] + 8000f44: 68f8 ldr r0, [r7, #12] + 8000f46: f000 f8c9 bl 80010dc + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + 8000f4a: 68fb ldr r3, [r7, #12] + 8000f4c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8000f4e: 2b00 cmp r3, #0 + 8000f50: d008 beq.n 8000f64 + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8000f52: 68fb ldr r3, [r7, #12] + 8000f54: 681b ldr r3, [r3, #0] + 8000f56: 681a ldr r2, [r3, #0] + 8000f58: 68fb ldr r3, [r7, #12] + 8000f5a: 681b ldr r3, [r3, #0] + 8000f5c: 210e movs r1, #14 + 8000f5e: 430a orrs r2, r1 + 8000f60: 601a str r2, [r3, #0] + 8000f62: e00f b.n 8000f84 + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 8000f64: 68fb ldr r3, [r7, #12] + 8000f66: 681b ldr r3, [r3, #0] + 8000f68: 681a ldr r2, [r3, #0] + 8000f6a: 68fb ldr r3, [r7, #12] + 8000f6c: 681b ldr r3, [r3, #0] + 8000f6e: 2104 movs r1, #4 + 8000f70: 438a bics r2, r1 + 8000f72: 601a str r2, [r3, #0] + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + 8000f74: 68fb ldr r3, [r7, #12] + 8000f76: 681b ldr r3, [r3, #0] + 8000f78: 681a ldr r2, [r3, #0] + 8000f7a: 68fb ldr r3, [r7, #12] + 8000f7c: 681b ldr r3, [r3, #0] + 8000f7e: 210a movs r1, #10 + 8000f80: 430a orrs r2, r1 + 8000f82: 601a str r2, [r3, #0] + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + 8000f84: 68fb ldr r3, [r7, #12] + 8000f86: 6c9b ldr r3, [r3, #72] ; 0x48 + 8000f88: 681a ldr r2, [r3, #0] + 8000f8a: 2380 movs r3, #128 ; 0x80 + 8000f8c: 025b lsls r3, r3, #9 + 8000f8e: 4013 ands r3, r2 + 8000f90: d008 beq.n 8000fa4 + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + 8000f92: 68fb ldr r3, [r7, #12] + 8000f94: 6c9b ldr r3, [r3, #72] ; 0x48 + 8000f96: 681a ldr r2, [r3, #0] + 8000f98: 68fb ldr r3, [r7, #12] + 8000f9a: 6c9b ldr r3, [r3, #72] ; 0x48 + 8000f9c: 2180 movs r1, #128 ; 0x80 + 8000f9e: 0049 lsls r1, r1, #1 + 8000fa0: 430a orrs r2, r1 + 8000fa2: 601a str r2, [r3, #0] + } + + if (hdma->DMAmuxRequestGen != 0U) + 8000fa4: 68fb ldr r3, [r7, #12] + 8000fa6: 6d5b ldr r3, [r3, #84] ; 0x54 + 8000fa8: 2b00 cmp r3, #0 + 8000faa: d008 beq.n 8000fbe + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 8000fac: 68fb ldr r3, [r7, #12] + 8000fae: 6d5b ldr r3, [r3, #84] ; 0x54 + 8000fb0: 681a ldr r2, [r3, #0] + 8000fb2: 68fb ldr r3, [r7, #12] + 8000fb4: 6d5b ldr r3, [r3, #84] ; 0x54 + 8000fb6: 2180 movs r1, #128 ; 0x80 + 8000fb8: 0049 lsls r1, r1, #1 + 8000fba: 430a orrs r2, r1 + 8000fbc: 601a str r2, [r3, #0] + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + 8000fbe: 68fb ldr r3, [r7, #12] + 8000fc0: 681b ldr r3, [r3, #0] + 8000fc2: 681a ldr r2, [r3, #0] + 8000fc4: 68fb ldr r3, [r7, #12] + 8000fc6: 681b ldr r3, [r3, #0] + 8000fc8: 2101 movs r1, #1 + 8000fca: 430a orrs r2, r1 + 8000fcc: 601a str r2, [r3, #0] + 8000fce: e00a b.n 8000fe6 + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 8000fd0: 68fb ldr r3, [r7, #12] + 8000fd2: 2280 movs r2, #128 ; 0x80 + 8000fd4: 63da str r2, [r3, #60] ; 0x3c + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8000fd6: 68fb ldr r3, [r7, #12] + 8000fd8: 2224 movs r2, #36 ; 0x24 + 8000fda: 2100 movs r1, #0 + 8000fdc: 5499 strb r1, [r3, r2] + + /* Return error status */ + status = HAL_ERROR; + 8000fde: 2317 movs r3, #23 + 8000fe0: 18fb adds r3, r7, r3 + 8000fe2: 2201 movs r2, #1 + 8000fe4: 701a strb r2, [r3, #0] + } + + return status; + 8000fe6: 2317 movs r3, #23 + 8000fe8: 18fb adds r3, r7, r3 + 8000fea: 781b ldrb r3, [r3, #0] +} + 8000fec: 0018 movs r0, r3 + 8000fee: 46bd mov sp, r7 + 8000ff0: b006 add sp, #24 + 8000ff2: bd80 pop {r7, pc} + +08000ff4 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 8000ff4: b580 push {r7, lr} + 8000ff6: b084 sub sp, #16 + 8000ff8: af00 add r7, sp, #0 + 8000ffa: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8000ffc: 210f movs r1, #15 + 8000ffe: 187b adds r3, r7, r1 + 8001000: 2200 movs r2, #0 + 8001002: 701a strb r2, [r3, #0] + + if (hdma->State != HAL_DMA_STATE_BUSY) + 8001004: 687b ldr r3, [r7, #4] + 8001006: 2225 movs r2, #37 ; 0x25 + 8001008: 5c9b ldrb r3, [r3, r2] + 800100a: b2db uxtb r3, r3 + 800100c: 2b02 cmp r3, #2 + 800100e: d006 beq.n 800101e + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8001010: 687b ldr r3, [r7, #4] + 8001012: 2204 movs r2, #4 + 8001014: 63da str r2, [r3, #60] ; 0x3c + + status = HAL_ERROR; + 8001016: 187b adds r3, r7, r1 + 8001018: 2201 movs r2, #1 + 800101a: 701a strb r2, [r3, #0] + 800101c: e048 b.n 80010b0 + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 800101e: 687b ldr r3, [r7, #4] + 8001020: 681b ldr r3, [r3, #0] + 8001022: 681a ldr r2, [r3, #0] + 8001024: 687b ldr r3, [r7, #4] + 8001026: 681b ldr r3, [r3, #0] + 8001028: 210e movs r1, #14 + 800102a: 438a bics r2, r1 + 800102c: 601a str r2, [r3, #0] + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 800102e: 687b ldr r3, [r7, #4] + 8001030: 681b ldr r3, [r3, #0] + 8001032: 681a ldr r2, [r3, #0] + 8001034: 687b ldr r3, [r7, #4] + 8001036: 681b ldr r3, [r3, #0] + 8001038: 2101 movs r1, #1 + 800103a: 438a bics r2, r1 + 800103c: 601a str r2, [r3, #0] + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 800103e: 687b ldr r3, [r7, #4] + 8001040: 6c9b ldr r3, [r3, #72] ; 0x48 + 8001042: 681a ldr r2, [r3, #0] + 8001044: 687b ldr r3, [r7, #4] + 8001046: 6c9b ldr r3, [r3, #72] ; 0x48 + 8001048: 491d ldr r1, [pc, #116] ; (80010c0 ) + 800104a: 400a ands r2, r1 + 800104c: 601a str r2, [r3, #0] + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 800104e: 687b ldr r3, [r7, #4] + 8001050: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001052: 221c movs r2, #28 + 8001054: 401a ands r2, r3 + 8001056: 687b ldr r3, [r7, #4] + 8001058: 6c1b ldr r3, [r3, #64] ; 0x40 + 800105a: 2101 movs r1, #1 + 800105c: 4091 lsls r1, r2 + 800105e: 000a movs r2, r1 + 8001060: 605a str r2, [r3, #4] +#else + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001062: 687b ldr r3, [r7, #4] + 8001064: 6cdb ldr r3, [r3, #76] ; 0x4c + 8001066: 687a ldr r2, [r7, #4] + 8001068: 6d12 ldr r2, [r2, #80] ; 0x50 + 800106a: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != 0U) + 800106c: 687b ldr r3, [r7, #4] + 800106e: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001070: 2b00 cmp r3, #0 + 8001072: d00c beq.n 800108e + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 8001074: 687b ldr r3, [r7, #4] + 8001076: 6d5b ldr r3, [r3, #84] ; 0x54 + 8001078: 681a ldr r2, [r3, #0] + 800107a: 687b ldr r3, [r7, #4] + 800107c: 6d5b ldr r3, [r3, #84] ; 0x54 + 800107e: 4910 ldr r1, [pc, #64] ; (80010c0 ) + 8001080: 400a ands r2, r1 + 8001082: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001084: 687b ldr r3, [r7, #4] + 8001086: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001088: 687a ldr r2, [r7, #4] + 800108a: 6dd2 ldr r2, [r2, #92] ; 0x5c + 800108c: 605a str r2, [r3, #4] + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 800108e: 687b ldr r3, [r7, #4] + 8001090: 2225 movs r2, #37 ; 0x25 + 8001092: 2101 movs r1, #1 + 8001094: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001096: 687b ldr r3, [r7, #4] + 8001098: 2224 movs r2, #36 ; 0x24 + 800109a: 2100 movs r1, #0 + 800109c: 5499 strb r1, [r3, r2] + + /* Call User Abort callback */ + if (hdma->XferAbortCallback != NULL) + 800109e: 687b ldr r3, [r7, #4] + 80010a0: 6b9b ldr r3, [r3, #56] ; 0x38 + 80010a2: 2b00 cmp r3, #0 + 80010a4: d004 beq.n 80010b0 + { + hdma->XferAbortCallback(hdma); + 80010a6: 687b ldr r3, [r7, #4] + 80010a8: 6b9b ldr r3, [r3, #56] ; 0x38 + 80010aa: 687a ldr r2, [r7, #4] + 80010ac: 0010 movs r0, r2 + 80010ae: 4798 blx r3 + } + } + return status; + 80010b0: 230f movs r3, #15 + 80010b2: 18fb adds r3, r7, r3 + 80010b4: 781b ldrb r3, [r3, #0] +} + 80010b6: 0018 movs r0, r3 + 80010b8: 46bd mov sp, r7 + 80010ba: b004 add sp, #16 + 80010bc: bd80 pop {r7, pc} + 80010be: 46c0 nop ; (mov r8, r8) + 80010c0: fffffeff .word 0xfffffeff + +080010c4 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + 80010c4: b580 push {r7, lr} + 80010c6: b082 sub sp, #8 + 80010c8: af00 add r7, sp, #0 + 80010ca: 6078 str r0, [r7, #4] + /* Return DMA handle state */ + return hdma->State; + 80010cc: 687b ldr r3, [r7, #4] + 80010ce: 2225 movs r2, #37 ; 0x25 + 80010d0: 5c9b ldrb r3, [r3, r2] + 80010d2: b2db uxtb r3, r3 +} + 80010d4: 0018 movs r0, r3 + 80010d6: 46bd mov sp, r7 + 80010d8: b002 add sp, #8 + 80010da: bd80 pop {r7, pc} + +080010dc : + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + 80010dc: b580 push {r7, lr} + 80010de: b084 sub sp, #16 + 80010e0: af00 add r7, sp, #0 + 80010e2: 60f8 str r0, [r7, #12] + 80010e4: 60b9 str r1, [r7, #8] + 80010e6: 607a str r2, [r7, #4] + 80010e8: 603b str r3, [r7, #0] + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 80010ea: 68fb ldr r3, [r7, #12] + 80010ec: 6cdb ldr r3, [r3, #76] ; 0x4c + 80010ee: 68fa ldr r2, [r7, #12] + 80010f0: 6d12 ldr r2, [r2, #80] ; 0x50 + 80010f2: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != 0U) + 80010f4: 68fb ldr r3, [r7, #12] + 80010f6: 6d5b ldr r3, [r3, #84] ; 0x54 + 80010f8: 2b00 cmp r3, #0 + 80010fa: d004 beq.n 8001106 + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 80010fc: 68fb ldr r3, [r7, #12] + 80010fe: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001100: 68fa ldr r2, [r7, #12] + 8001102: 6dd2 ldr r2, [r2, #92] ; 0x5c + 8001104: 605a str r2, [r3, #4] + } + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8001106: 68fb ldr r3, [r7, #12] + 8001108: 6c5b ldr r3, [r3, #68] ; 0x44 + 800110a: 221c movs r2, #28 + 800110c: 401a ands r2, r3 + 800110e: 68fb ldr r3, [r7, #12] + 8001110: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001112: 2101 movs r1, #1 + 8001114: 4091 lsls r1, r2 + 8001116: 000a movs r2, r1 + 8001118: 605a str r2, [r3, #4] +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + 800111a: 68fb ldr r3, [r7, #12] + 800111c: 681b ldr r3, [r3, #0] + 800111e: 683a ldr r2, [r7, #0] + 8001120: 605a str r2, [r3, #4] + + /* Memory to Peripheral */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 8001122: 68fb ldr r3, [r7, #12] + 8001124: 689b ldr r3, [r3, #8] + 8001126: 2b10 cmp r3, #16 + 8001128: d108 bne.n 800113c + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + 800112a: 68fb ldr r3, [r7, #12] + 800112c: 681b ldr r3, [r3, #0] + 800112e: 687a ldr r2, [r7, #4] + 8001130: 609a str r2, [r3, #8] + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + 8001132: 68fb ldr r3, [r7, #12] + 8001134: 681b ldr r3, [r3, #0] + 8001136: 68ba ldr r2, [r7, #8] + 8001138: 60da str r2, [r3, #12] + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + 800113a: e007 b.n 800114c + hdma->Instance->CPAR = SrcAddress; + 800113c: 68fb ldr r3, [r7, #12] + 800113e: 681b ldr r3, [r3, #0] + 8001140: 68ba ldr r2, [r7, #8] + 8001142: 609a str r2, [r3, #8] + hdma->Instance->CMAR = DstAddress; + 8001144: 68fb ldr r3, [r7, #12] + 8001146: 681b ldr r3, [r3, #0] + 8001148: 687a ldr r2, [r7, #4] + 800114a: 60da str r2, [r3, #12] +} + 800114c: 46c0 nop ; (mov r8, r8) + 800114e: 46bd mov sp, r7 + 8001150: b004 add sp, #16 + 8001152: bd80 pop {r7, pc} + +08001154 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8001154: b580 push {r7, lr} + 8001156: b086 sub sp, #24 + 8001158: af00 add r7, sp, #0 + 800115a: 6078 str r0, [r7, #4] + 800115c: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 800115e: 2300 movs r3, #0 + 8001160: 617b str r3, [r7, #20] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8001162: e14d b.n 8001400 + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + 8001164: 683b ldr r3, [r7, #0] + 8001166: 681b ldr r3, [r3, #0] + 8001168: 2101 movs r1, #1 + 800116a: 697a ldr r2, [r7, #20] + 800116c: 4091 lsls r1, r2 + 800116e: 000a movs r2, r1 + 8001170: 4013 ands r3, r2 + 8001172: 60fb str r3, [r7, #12] + + if (iocurrent != 0x00u) + 8001174: 68fb ldr r3, [r7, #12] + 8001176: 2b00 cmp r3, #0 + 8001178: d100 bne.n 800117c + 800117a: e13e b.n 80013fa + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 800117c: 683b ldr r3, [r7, #0] + 800117e: 685b ldr r3, [r3, #4] + 8001180: 2203 movs r2, #3 + 8001182: 4013 ands r3, r2 + 8001184: 2b01 cmp r3, #1 + 8001186: d005 beq.n 8001194 + 8001188: 683b ldr r3, [r7, #0] + 800118a: 685b ldr r3, [r3, #4] + 800118c: 2203 movs r2, #3 + 800118e: 4013 ands r3, r2 + 8001190: 2b02 cmp r3, #2 + 8001192: d130 bne.n 80011f6 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8001194: 687b ldr r3, [r7, #4] + 8001196: 689b ldr r3, [r3, #8] + 8001198: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + 800119a: 697b ldr r3, [r7, #20] + 800119c: 005b lsls r3, r3, #1 + 800119e: 2203 movs r2, #3 + 80011a0: 409a lsls r2, r3 + 80011a2: 0013 movs r3, r2 + 80011a4: 43da mvns r2, r3 + 80011a6: 693b ldr r3, [r7, #16] + 80011a8: 4013 ands r3, r2 + 80011aa: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2u)); + 80011ac: 683b ldr r3, [r7, #0] + 80011ae: 68da ldr r2, [r3, #12] + 80011b0: 697b ldr r3, [r7, #20] + 80011b2: 005b lsls r3, r3, #1 + 80011b4: 409a lsls r2, r3 + 80011b6: 0013 movs r3, r2 + 80011b8: 693a ldr r2, [r7, #16] + 80011ba: 4313 orrs r3, r2 + 80011bc: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 80011be: 687b ldr r3, [r7, #4] + 80011c0: 693a ldr r2, [r7, #16] + 80011c2: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 80011c4: 687b ldr r3, [r7, #4] + 80011c6: 685b ldr r3, [r3, #4] + 80011c8: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT0 << position) ; + 80011ca: 2201 movs r2, #1 + 80011cc: 697b ldr r3, [r7, #20] + 80011ce: 409a lsls r2, r3 + 80011d0: 0013 movs r3, r2 + 80011d2: 43da mvns r2, r3 + 80011d4: 693b ldr r3, [r7, #16] + 80011d6: 4013 ands r3, r2 + 80011d8: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 80011da: 683b ldr r3, [r7, #0] + 80011dc: 685b ldr r3, [r3, #4] + 80011de: 091b lsrs r3, r3, #4 + 80011e0: 2201 movs r2, #1 + 80011e2: 401a ands r2, r3 + 80011e4: 697b ldr r3, [r7, #20] + 80011e6: 409a lsls r2, r3 + 80011e8: 0013 movs r3, r2 + 80011ea: 693a ldr r2, [r7, #16] + 80011ec: 4313 orrs r3, r2 + 80011ee: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 80011f0: 687b ldr r3, [r7, #4] + 80011f2: 693a ldr r2, [r7, #16] + 80011f4: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 80011f6: 683b ldr r3, [r7, #0] + 80011f8: 685b ldr r3, [r3, #4] + 80011fa: 2203 movs r2, #3 + 80011fc: 4013 ands r3, r2 + 80011fe: 2b03 cmp r3, #3 + 8001200: d017 beq.n 8001232 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8001202: 687b ldr r3, [r7, #4] + 8001204: 68db ldr r3, [r3, #12] + 8001206: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + 8001208: 697b ldr r3, [r7, #20] + 800120a: 005b lsls r3, r3, #1 + 800120c: 2203 movs r2, #3 + 800120e: 409a lsls r2, r3 + 8001210: 0013 movs r3, r2 + 8001212: 43da mvns r2, r3 + 8001214: 693b ldr r3, [r7, #16] + 8001216: 4013 ands r3, r2 + 8001218: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2u)); + 800121a: 683b ldr r3, [r7, #0] + 800121c: 689a ldr r2, [r3, #8] + 800121e: 697b ldr r3, [r7, #20] + 8001220: 005b lsls r3, r3, #1 + 8001222: 409a lsls r2, r3 + 8001224: 0013 movs r3, r2 + 8001226: 693a ldr r2, [r7, #16] + 8001228: 4313 orrs r3, r2 + 800122a: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 800122c: 687b ldr r3, [r7, #4] + 800122e: 693a ldr r2, [r7, #16] + 8001230: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8001232: 683b ldr r3, [r7, #0] + 8001234: 685b ldr r3, [r3, #4] + 8001236: 2203 movs r2, #3 + 8001238: 4013 ands r3, r2 + 800123a: 2b02 cmp r3, #2 + 800123c: d123 bne.n 8001286 + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + 800123e: 697b ldr r3, [r7, #20] + 8001240: 08da lsrs r2, r3, #3 + 8001242: 687b ldr r3, [r7, #4] + 8001244: 3208 adds r2, #8 + 8001246: 0092 lsls r2, r2, #2 + 8001248: 58d3 ldr r3, [r2, r3] + 800124a: 613b str r3, [r7, #16] + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + 800124c: 697b ldr r3, [r7, #20] + 800124e: 2207 movs r2, #7 + 8001250: 4013 ands r3, r2 + 8001252: 009b lsls r3, r3, #2 + 8001254: 220f movs r2, #15 + 8001256: 409a lsls r2, r3 + 8001258: 0013 movs r3, r2 + 800125a: 43da mvns r2, r3 + 800125c: 693b ldr r3, [r7, #16] + 800125e: 4013 ands r3, r2 + 8001260: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + 8001262: 683b ldr r3, [r7, #0] + 8001264: 691a ldr r2, [r3, #16] + 8001266: 697b ldr r3, [r7, #20] + 8001268: 2107 movs r1, #7 + 800126a: 400b ands r3, r1 + 800126c: 009b lsls r3, r3, #2 + 800126e: 409a lsls r2, r3 + 8001270: 0013 movs r3, r2 + 8001272: 693a ldr r2, [r7, #16] + 8001274: 4313 orrs r3, r2 + 8001276: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3u] = temp; + 8001278: 697b ldr r3, [r7, #20] + 800127a: 08da lsrs r2, r3, #3 + 800127c: 687b ldr r3, [r7, #4] + 800127e: 3208 adds r2, #8 + 8001280: 0092 lsls r2, r2, #2 + 8001282: 6939 ldr r1, [r7, #16] + 8001284: 50d1 str r1, [r2, r3] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8001286: 687b ldr r3, [r7, #4] + 8001288: 681b ldr r3, [r3, #0] + 800128a: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + 800128c: 697b ldr r3, [r7, #20] + 800128e: 005b lsls r3, r3, #1 + 8001290: 2203 movs r2, #3 + 8001292: 409a lsls r2, r3 + 8001294: 0013 movs r3, r2 + 8001296: 43da mvns r2, r3 + 8001298: 693b ldr r3, [r7, #16] + 800129a: 4013 ands r3, r2 + 800129c: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 800129e: 683b ldr r3, [r7, #0] + 80012a0: 685b ldr r3, [r3, #4] + 80012a2: 2203 movs r2, #3 + 80012a4: 401a ands r2, r3 + 80012a6: 697b ldr r3, [r7, #20] + 80012a8: 005b lsls r3, r3, #1 + 80012aa: 409a lsls r2, r3 + 80012ac: 0013 movs r3, r2 + 80012ae: 693a ldr r2, [r7, #16] + 80012b0: 4313 orrs r3, r2 + 80012b2: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 80012b4: 687b ldr r3, [r7, #4] + 80012b6: 693a ldr r2, [r7, #16] + 80012b8: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 80012ba: 683b ldr r3, [r7, #0] + 80012bc: 685a ldr r2, [r3, #4] + 80012be: 23c0 movs r3, #192 ; 0xc0 + 80012c0: 029b lsls r3, r3, #10 + 80012c2: 4013 ands r3, r2 + 80012c4: d100 bne.n 80012c8 + 80012c6: e098 b.n 80013fa + { + temp = EXTI->EXTICR[position >> 2u]; + 80012c8: 4a53 ldr r2, [pc, #332] ; (8001418 ) + 80012ca: 697b ldr r3, [r7, #20] + 80012cc: 089b lsrs r3, r3, #2 + 80012ce: 3318 adds r3, #24 + 80012d0: 009b lsls r3, r3, #2 + 80012d2: 589b ldr r3, [r3, r2] + 80012d4: 613b str r3, [r7, #16] + temp &= ~(0x0FuL << (8u * (position & 0x03u))); + 80012d6: 697b ldr r3, [r7, #20] + 80012d8: 2203 movs r2, #3 + 80012da: 4013 ands r3, r2 + 80012dc: 00db lsls r3, r3, #3 + 80012de: 220f movs r2, #15 + 80012e0: 409a lsls r2, r3 + 80012e2: 0013 movs r3, r2 + 80012e4: 43da mvns r2, r3 + 80012e6: 693b ldr r3, [r7, #16] + 80012e8: 4013 ands r3, r2 + 80012ea: 613b str r3, [r7, #16] + temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + 80012ec: 687a ldr r2, [r7, #4] + 80012ee: 23a0 movs r3, #160 ; 0xa0 + 80012f0: 05db lsls r3, r3, #23 + 80012f2: 429a cmp r2, r3 + 80012f4: d019 beq.n 800132a + 80012f6: 687b ldr r3, [r7, #4] + 80012f8: 4a48 ldr r2, [pc, #288] ; (800141c ) + 80012fa: 4293 cmp r3, r2 + 80012fc: d013 beq.n 8001326 + 80012fe: 687b ldr r3, [r7, #4] + 8001300: 4a47 ldr r2, [pc, #284] ; (8001420 ) + 8001302: 4293 cmp r3, r2 + 8001304: d00d beq.n 8001322 + 8001306: 687b ldr r3, [r7, #4] + 8001308: 4a46 ldr r2, [pc, #280] ; (8001424 ) + 800130a: 4293 cmp r3, r2 + 800130c: d007 beq.n 800131e + 800130e: 687b ldr r3, [r7, #4] + 8001310: 4a45 ldr r2, [pc, #276] ; (8001428 ) + 8001312: 4293 cmp r3, r2 + 8001314: d101 bne.n 800131a + 8001316: 2304 movs r3, #4 + 8001318: e008 b.n 800132c + 800131a: 2305 movs r3, #5 + 800131c: e006 b.n 800132c + 800131e: 2303 movs r3, #3 + 8001320: e004 b.n 800132c + 8001322: 2302 movs r3, #2 + 8001324: e002 b.n 800132c + 8001326: 2301 movs r3, #1 + 8001328: e000 b.n 800132c + 800132a: 2300 movs r3, #0 + 800132c: 697a ldr r2, [r7, #20] + 800132e: 2103 movs r1, #3 + 8001330: 400a ands r2, r1 + 8001332: 00d2 lsls r2, r2, #3 + 8001334: 4093 lsls r3, r2 + 8001336: 693a ldr r2, [r7, #16] + 8001338: 4313 orrs r3, r2 + 800133a: 613b str r3, [r7, #16] + EXTI->EXTICR[position >> 2u] = temp; + 800133c: 4936 ldr r1, [pc, #216] ; (8001418 ) + 800133e: 697b ldr r3, [r7, #20] + 8001340: 089b lsrs r3, r3, #2 + 8001342: 3318 adds r3, #24 + 8001344: 009b lsls r3, r3, #2 + 8001346: 693a ldr r2, [r7, #16] + 8001348: 505a str r2, [r3, r1] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + 800134a: 4b33 ldr r3, [pc, #204] ; (8001418 ) + 800134c: 681b ldr r3, [r3, #0] + 800134e: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8001350: 68fb ldr r3, [r7, #12] + 8001352: 43da mvns r2, r3 + 8001354: 693b ldr r3, [r7, #16] + 8001356: 4013 ands r3, r2 + 8001358: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 800135a: 683b ldr r3, [r7, #0] + 800135c: 685a ldr r2, [r3, #4] + 800135e: 2380 movs r3, #128 ; 0x80 + 8001360: 035b lsls r3, r3, #13 + 8001362: 4013 ands r3, r2 + 8001364: d003 beq.n 800136e + { + temp |= iocurrent; + 8001366: 693a ldr r2, [r7, #16] + 8001368: 68fb ldr r3, [r7, #12] + 800136a: 4313 orrs r3, r2 + 800136c: 613b str r3, [r7, #16] + } + EXTI->RTSR1 = temp; + 800136e: 4b2a ldr r3, [pc, #168] ; (8001418 ) + 8001370: 693a ldr r2, [r7, #16] + 8001372: 601a str r2, [r3, #0] + + temp = EXTI->FTSR1; + 8001374: 4b28 ldr r3, [pc, #160] ; (8001418 ) + 8001376: 685b ldr r3, [r3, #4] + 8001378: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 800137a: 68fb ldr r3, [r7, #12] + 800137c: 43da mvns r2, r3 + 800137e: 693b ldr r3, [r7, #16] + 8001380: 4013 ands r3, r2 + 8001382: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 8001384: 683b ldr r3, [r7, #0] + 8001386: 685a ldr r2, [r3, #4] + 8001388: 2380 movs r3, #128 ; 0x80 + 800138a: 039b lsls r3, r3, #14 + 800138c: 4013 ands r3, r2 + 800138e: d003 beq.n 8001398 + { + temp |= iocurrent; + 8001390: 693a ldr r2, [r7, #16] + 8001392: 68fb ldr r3, [r7, #12] + 8001394: 4313 orrs r3, r2 + 8001396: 613b str r3, [r7, #16] + } + EXTI->FTSR1 = temp; + 8001398: 4b1f ldr r3, [pc, #124] ; (8001418 ) + 800139a: 693a ldr r2, [r7, #16] + 800139c: 605a str r2, [r3, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->EMR1; + 800139e: 4a1e ldr r2, [pc, #120] ; (8001418 ) + 80013a0: 2384 movs r3, #132 ; 0x84 + 80013a2: 58d3 ldr r3, [r2, r3] + 80013a4: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 80013a6: 68fb ldr r3, [r7, #12] + 80013a8: 43da mvns r2, r3 + 80013aa: 693b ldr r3, [r7, #16] + 80013ac: 4013 ands r3, r2 + 80013ae: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 80013b0: 683b ldr r3, [r7, #0] + 80013b2: 685a ldr r2, [r3, #4] + 80013b4: 2380 movs r3, #128 ; 0x80 + 80013b6: 029b lsls r3, r3, #10 + 80013b8: 4013 ands r3, r2 + 80013ba: d003 beq.n 80013c4 + { + temp |= iocurrent; + 80013bc: 693a ldr r2, [r7, #16] + 80013be: 68fb ldr r3, [r7, #12] + 80013c0: 4313 orrs r3, r2 + 80013c2: 613b str r3, [r7, #16] + } + EXTI->EMR1 = temp; + 80013c4: 4914 ldr r1, [pc, #80] ; (8001418 ) + 80013c6: 2284 movs r2, #132 ; 0x84 + 80013c8: 693b ldr r3, [r7, #16] + 80013ca: 508b str r3, [r1, r2] + + temp = EXTI->IMR1; + 80013cc: 4a12 ldr r2, [pc, #72] ; (8001418 ) + 80013ce: 2380 movs r3, #128 ; 0x80 + 80013d0: 58d3 ldr r3, [r2, r3] + 80013d2: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 80013d4: 68fb ldr r3, [r7, #12] + 80013d6: 43da mvns r2, r3 + 80013d8: 693b ldr r3, [r7, #16] + 80013da: 4013 ands r3, r2 + 80013dc: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 80013de: 683b ldr r3, [r7, #0] + 80013e0: 685a ldr r2, [r3, #4] + 80013e2: 2380 movs r3, #128 ; 0x80 + 80013e4: 025b lsls r3, r3, #9 + 80013e6: 4013 ands r3, r2 + 80013e8: d003 beq.n 80013f2 + { + temp |= iocurrent; + 80013ea: 693a ldr r2, [r7, #16] + 80013ec: 68fb ldr r3, [r7, #12] + 80013ee: 4313 orrs r3, r2 + 80013f0: 613b str r3, [r7, #16] + } + EXTI->IMR1 = temp; + 80013f2: 4909 ldr r1, [pc, #36] ; (8001418 ) + 80013f4: 2280 movs r2, #128 ; 0x80 + 80013f6: 693b ldr r3, [r7, #16] + 80013f8: 508b str r3, [r1, r2] + } + } + + position++; + 80013fa: 697b ldr r3, [r7, #20] + 80013fc: 3301 adds r3, #1 + 80013fe: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8001400: 683b ldr r3, [r7, #0] + 8001402: 681a ldr r2, [r3, #0] + 8001404: 697b ldr r3, [r7, #20] + 8001406: 40da lsrs r2, r3 + 8001408: 1e13 subs r3, r2, #0 + 800140a: d000 beq.n 800140e + 800140c: e6aa b.n 8001164 + } +} + 800140e: 46c0 nop ; (mov r8, r8) + 8001410: 46c0 nop ; (mov r8, r8) + 8001412: 46bd mov sp, r7 + 8001414: b006 add sp, #24 + 8001416: bd80 pop {r7, pc} + 8001418: 40021800 .word 0x40021800 + 800141c: 50000400 .word 0x50000400 + 8001420: 50000800 .word 0x50000800 + 8001424: 50000c00 .word 0x50000c00 + 8001428: 50001000 .word 0x50001000 + +0800142c : + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + 800142c: b580 push {r7, lr} + 800142e: b086 sub sp, #24 + 8001430: af00 add r7, sp, #0 + 8001432: 6078 str r0, [r7, #4] + 8001434: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 8001436: 2300 movs r3, #0 + 8001438: 617b str r3, [r7, #20] + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + 800143a: e0ba b.n 80015b2 + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + 800143c: 2201 movs r2, #1 + 800143e: 697b ldr r3, [r7, #20] + 8001440: 409a lsls r2, r3 + 8001442: 683b ldr r3, [r7, #0] + 8001444: 4013 ands r3, r2 + 8001446: 613b str r3, [r7, #16] + + if (iocurrent != 0x00u) + 8001448: 693b ldr r3, [r7, #16] + 800144a: 2b00 cmp r3, #0 + 800144c: d100 bne.n 8001450 + 800144e: e0ad b.n 80015ac + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = EXTI->EXTICR[position >> 2u]; + 8001450: 4a5d ldr r2, [pc, #372] ; (80015c8 ) + 8001452: 697b ldr r3, [r7, #20] + 8001454: 089b lsrs r3, r3, #2 + 8001456: 3318 adds r3, #24 + 8001458: 009b lsls r3, r3, #2 + 800145a: 589b ldr r3, [r3, r2] + 800145c: 60fb str r3, [r7, #12] + tmp &= (0x0FuL << (8u * (position & 0x03u))); + 800145e: 697b ldr r3, [r7, #20] + 8001460: 2203 movs r2, #3 + 8001462: 4013 ands r3, r2 + 8001464: 00db lsls r3, r3, #3 + 8001466: 220f movs r2, #15 + 8001468: 409a lsls r2, r3 + 800146a: 68fb ldr r3, [r7, #12] + 800146c: 4013 ands r3, r2 + 800146e: 60fb str r3, [r7, #12] + if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + 8001470: 687a ldr r2, [r7, #4] + 8001472: 23a0 movs r3, #160 ; 0xa0 + 8001474: 05db lsls r3, r3, #23 + 8001476: 429a cmp r2, r3 + 8001478: d019 beq.n 80014ae + 800147a: 687b ldr r3, [r7, #4] + 800147c: 4a53 ldr r2, [pc, #332] ; (80015cc ) + 800147e: 4293 cmp r3, r2 + 8001480: d013 beq.n 80014aa + 8001482: 687b ldr r3, [r7, #4] + 8001484: 4a52 ldr r2, [pc, #328] ; (80015d0 ) + 8001486: 4293 cmp r3, r2 + 8001488: d00d beq.n 80014a6 + 800148a: 687b ldr r3, [r7, #4] + 800148c: 4a51 ldr r2, [pc, #324] ; (80015d4 ) + 800148e: 4293 cmp r3, r2 + 8001490: d007 beq.n 80014a2 + 8001492: 687b ldr r3, [r7, #4] + 8001494: 4a50 ldr r2, [pc, #320] ; (80015d8 ) + 8001496: 4293 cmp r3, r2 + 8001498: d101 bne.n 800149e + 800149a: 2304 movs r3, #4 + 800149c: e008 b.n 80014b0 + 800149e: 2305 movs r3, #5 + 80014a0: e006 b.n 80014b0 + 80014a2: 2303 movs r3, #3 + 80014a4: e004 b.n 80014b0 + 80014a6: 2302 movs r3, #2 + 80014a8: e002 b.n 80014b0 + 80014aa: 2301 movs r3, #1 + 80014ac: e000 b.n 80014b0 + 80014ae: 2300 movs r3, #0 + 80014b0: 697a ldr r2, [r7, #20] + 80014b2: 2103 movs r1, #3 + 80014b4: 400a ands r2, r1 + 80014b6: 00d2 lsls r2, r2, #3 + 80014b8: 4093 lsls r3, r2 + 80014ba: 68fa ldr r2, [r7, #12] + 80014bc: 429a cmp r2, r3 + 80014be: d136 bne.n 800152e + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + 80014c0: 4a41 ldr r2, [pc, #260] ; (80015c8 ) + 80014c2: 2380 movs r3, #128 ; 0x80 + 80014c4: 58d3 ldr r3, [r2, r3] + 80014c6: 693a ldr r2, [r7, #16] + 80014c8: 43d2 mvns r2, r2 + 80014ca: 493f ldr r1, [pc, #252] ; (80015c8 ) + 80014cc: 4013 ands r3, r2 + 80014ce: 2280 movs r2, #128 ; 0x80 + 80014d0: 508b str r3, [r1, r2] + EXTI->EMR1 &= ~(iocurrent); + 80014d2: 4a3d ldr r2, [pc, #244] ; (80015c8 ) + 80014d4: 2384 movs r3, #132 ; 0x84 + 80014d6: 58d3 ldr r3, [r2, r3] + 80014d8: 693a ldr r2, [r7, #16] + 80014da: 43d2 mvns r2, r2 + 80014dc: 493a ldr r1, [pc, #232] ; (80015c8 ) + 80014de: 4013 ands r3, r2 + 80014e0: 2284 movs r2, #132 ; 0x84 + 80014e2: 508b str r3, [r1, r2] + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR1 &= ~(iocurrent); + 80014e4: 4b38 ldr r3, [pc, #224] ; (80015c8 ) + 80014e6: 685a ldr r2, [r3, #4] + 80014e8: 693b ldr r3, [r7, #16] + 80014ea: 43d9 mvns r1, r3 + 80014ec: 4b36 ldr r3, [pc, #216] ; (80015c8 ) + 80014ee: 400a ands r2, r1 + 80014f0: 605a str r2, [r3, #4] + EXTI->RTSR1 &= ~(iocurrent); + 80014f2: 4b35 ldr r3, [pc, #212] ; (80015c8 ) + 80014f4: 681a ldr r2, [r3, #0] + 80014f6: 693b ldr r3, [r7, #16] + 80014f8: 43d9 mvns r1, r3 + 80014fa: 4b33 ldr r3, [pc, #204] ; (80015c8 ) + 80014fc: 400a ands r2, r1 + 80014fe: 601a str r2, [r3, #0] + + tmp = 0x0FuL << (8u * (position & 0x03u)); + 8001500: 697b ldr r3, [r7, #20] + 8001502: 2203 movs r2, #3 + 8001504: 4013 ands r3, r2 + 8001506: 00db lsls r3, r3, #3 + 8001508: 220f movs r2, #15 + 800150a: 409a lsls r2, r3 + 800150c: 0013 movs r3, r2 + 800150e: 60fb str r3, [r7, #12] + EXTI->EXTICR[position >> 2u] &= ~tmp; + 8001510: 4a2d ldr r2, [pc, #180] ; (80015c8 ) + 8001512: 697b ldr r3, [r7, #20] + 8001514: 089b lsrs r3, r3, #2 + 8001516: 3318 adds r3, #24 + 8001518: 009b lsls r3, r3, #2 + 800151a: 589a ldr r2, [r3, r2] + 800151c: 68fb ldr r3, [r7, #12] + 800151e: 43d9 mvns r1, r3 + 8001520: 4829 ldr r0, [pc, #164] ; (80015c8 ) + 8001522: 697b ldr r3, [r7, #20] + 8001524: 089b lsrs r3, r3, #2 + 8001526: 400a ands r2, r1 + 8001528: 3318 adds r3, #24 + 800152a: 009b lsls r3, r3, #2 + 800152c: 501a str r2, [r3, r0] + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); + 800152e: 687b ldr r3, [r7, #4] + 8001530: 681a ldr r2, [r3, #0] + 8001532: 697b ldr r3, [r7, #20] + 8001534: 005b lsls r3, r3, #1 + 8001536: 2103 movs r1, #3 + 8001538: 4099 lsls r1, r3 + 800153a: 000b movs r3, r1 + 800153c: 431a orrs r2, r3 + 800153e: 687b ldr r3, [r7, #4] + 8001540: 601a str r2, [r3, #0] + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + 8001542: 697b ldr r3, [r7, #20] + 8001544: 08da lsrs r2, r3, #3 + 8001546: 687b ldr r3, [r7, #4] + 8001548: 3208 adds r2, #8 + 800154a: 0092 lsls r2, r2, #2 + 800154c: 58d3 ldr r3, [r2, r3] + 800154e: 697a ldr r2, [r7, #20] + 8001550: 2107 movs r1, #7 + 8001552: 400a ands r2, r1 + 8001554: 0092 lsls r2, r2, #2 + 8001556: 210f movs r1, #15 + 8001558: 4091 lsls r1, r2 + 800155a: 000a movs r2, r1 + 800155c: 43d1 mvns r1, r2 + 800155e: 697a ldr r2, [r7, #20] + 8001560: 08d2 lsrs r2, r2, #3 + 8001562: 4019 ands r1, r3 + 8001564: 687b ldr r3, [r7, #4] + 8001566: 3208 adds r2, #8 + 8001568: 0092 lsls r2, r2, #2 + 800156a: 50d1 str r1, [r2, r3] + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + 800156c: 687b ldr r3, [r7, #4] + 800156e: 689b ldr r3, [r3, #8] + 8001570: 697a ldr r2, [r7, #20] + 8001572: 0052 lsls r2, r2, #1 + 8001574: 2103 movs r1, #3 + 8001576: 4091 lsls r1, r2 + 8001578: 000a movs r2, r1 + 800157a: 43d2 mvns r2, r2 + 800157c: 401a ands r2, r3 + 800157e: 687b ldr r3, [r7, #4] + 8001580: 609a str r2, [r3, #8] + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + 8001582: 687b ldr r3, [r7, #4] + 8001584: 685b ldr r3, [r3, #4] + 8001586: 2101 movs r1, #1 + 8001588: 697a ldr r2, [r7, #20] + 800158a: 4091 lsls r1, r2 + 800158c: 000a movs r2, r1 + 800158e: 43d2 mvns r2, r2 + 8001590: 401a ands r2, r3 + 8001592: 687b ldr r3, [r7, #4] + 8001594: 605a str r2, [r3, #4] + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + 8001596: 687b ldr r3, [r7, #4] + 8001598: 68db ldr r3, [r3, #12] + 800159a: 697a ldr r2, [r7, #20] + 800159c: 0052 lsls r2, r2, #1 + 800159e: 2103 movs r1, #3 + 80015a0: 4091 lsls r1, r2 + 80015a2: 000a movs r2, r1 + 80015a4: 43d2 mvns r2, r2 + 80015a6: 401a ands r2, r3 + 80015a8: 687b ldr r3, [r7, #4] + 80015aa: 60da str r2, [r3, #12] + } + + position++; + 80015ac: 697b ldr r3, [r7, #20] + 80015ae: 3301 adds r3, #1 + 80015b0: 617b str r3, [r7, #20] + while ((GPIO_Pin >> position) != 0x00u) + 80015b2: 683a ldr r2, [r7, #0] + 80015b4: 697b ldr r3, [r7, #20] + 80015b6: 40da lsrs r2, r3 + 80015b8: 1e13 subs r3, r2, #0 + 80015ba: d000 beq.n 80015be + 80015bc: e73e b.n 800143c + } +} + 80015be: 46c0 nop ; (mov r8, r8) + 80015c0: 46c0 nop ; (mov r8, r8) + 80015c2: 46bd mov sp, r7 + 80015c4: b006 add sp, #24 + 80015c6: bd80 pop {r7, pc} + 80015c8: 40021800 .word 0x40021800 + 80015cc: 50000400 .word 0x50000400 + 80015d0: 50000800 .word 0x50000800 + 80015d4: 50000c00 .word 0x50000c00 + 80015d8: 50001000 .word 0x50001000 + +080015dc : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80015dc: b580 push {r7, lr} + 80015de: b082 sub sp, #8 + 80015e0: af00 add r7, sp, #0 + 80015e2: 6078 str r0, [r7, #4] + 80015e4: 0008 movs r0, r1 + 80015e6: 0011 movs r1, r2 + 80015e8: 1cbb adds r3, r7, #2 + 80015ea: 1c02 adds r2, r0, #0 + 80015ec: 801a strh r2, [r3, #0] + 80015ee: 1c7b adds r3, r7, #1 + 80015f0: 1c0a adds r2, r1, #0 + 80015f2: 701a strb r2, [r3, #0] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 80015f4: 1c7b adds r3, r7, #1 + 80015f6: 781b ldrb r3, [r3, #0] + 80015f8: 2b00 cmp r3, #0 + 80015fa: d004 beq.n 8001606 + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 80015fc: 1cbb adds r3, r7, #2 + 80015fe: 881a ldrh r2, [r3, #0] + 8001600: 687b ldr r3, [r7, #4] + 8001602: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 8001604: e003 b.n 800160e + GPIOx->BRR = (uint32_t)GPIO_Pin; + 8001606: 1cbb adds r3, r7, #2 + 8001608: 881a ldrh r2, [r3, #0] + 800160a: 687b ldr r3, [r7, #4] + 800160c: 629a str r2, [r3, #40] ; 0x28 +} + 800160e: 46c0 nop ; (mov r8, r8) + 8001610: 46bd mov sp, r7 + 8001612: b002 add sp, #8 + 8001614: bd80 pop {r7, pc} + ... + +08001618 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + 8001618: b580 push {r7, lr} + 800161a: b082 sub sp, #8 + 800161c: af00 add r7, sp, #0 + 800161e: 6078 str r0, [r7, #4] + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 8001620: 687b ldr r3, [r7, #4] + 8001622: 2b00 cmp r3, #0 + 8001624: d101 bne.n 800162a + { + return HAL_ERROR; + 8001626: 2301 movs r3, #1 + 8001628: e08f b.n 800174a + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + 800162a: 687b ldr r3, [r7, #4] + 800162c: 2241 movs r2, #65 ; 0x41 + 800162e: 5c9b ldrb r3, [r3, r2] + 8001630: b2db uxtb r3, r3 + 8001632: 2b00 cmp r3, #0 + 8001634: d107 bne.n 8001646 + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + 8001636: 687b ldr r3, [r7, #4] + 8001638: 2240 movs r2, #64 ; 0x40 + 800163a: 2100 movs r1, #0 + 800163c: 5499 strb r1, [r3, r2] + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); + 800163e: 687b ldr r3, [r7, #4] + 8001640: 0018 movs r0, r3 + 8001642: f7ff f9e9 bl 8000a18 +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + 8001646: 687b ldr r3, [r7, #4] + 8001648: 2241 movs r2, #65 ; 0x41 + 800164a: 2124 movs r1, #36 ; 0x24 + 800164c: 5499 strb r1, [r3, r2] + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 800164e: 687b ldr r3, [r7, #4] + 8001650: 681b ldr r3, [r3, #0] + 8001652: 681a ldr r2, [r3, #0] + 8001654: 687b ldr r3, [r7, #4] + 8001656: 681b ldr r3, [r3, #0] + 8001658: 2101 movs r1, #1 + 800165a: 438a bics r2, r1 + 800165c: 601a str r2, [r3, #0] + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 800165e: 687b ldr r3, [r7, #4] + 8001660: 685a ldr r2, [r3, #4] + 8001662: 687b ldr r3, [r7, #4] + 8001664: 681b ldr r3, [r3, #0] + 8001666: 493b ldr r1, [pc, #236] ; (8001754 ) + 8001668: 400a ands r2, r1 + 800166a: 611a str r2, [r3, #16] + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 800166c: 687b ldr r3, [r7, #4] + 800166e: 681b ldr r3, [r3, #0] + 8001670: 689a ldr r2, [r3, #8] + 8001672: 687b ldr r3, [r7, #4] + 8001674: 681b ldr r3, [r3, #0] + 8001676: 4938 ldr r1, [pc, #224] ; (8001758 ) + 8001678: 400a ands r2, r1 + 800167a: 609a str r2, [r3, #8] + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 800167c: 687b ldr r3, [r7, #4] + 800167e: 68db ldr r3, [r3, #12] + 8001680: 2b01 cmp r3, #1 + 8001682: d108 bne.n 8001696 + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 8001684: 687b ldr r3, [r7, #4] + 8001686: 689a ldr r2, [r3, #8] + 8001688: 687b ldr r3, [r7, #4] + 800168a: 681b ldr r3, [r3, #0] + 800168c: 2180 movs r1, #128 ; 0x80 + 800168e: 0209 lsls r1, r1, #8 + 8001690: 430a orrs r2, r1 + 8001692: 609a str r2, [r3, #8] + 8001694: e007 b.n 80016a6 + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 8001696: 687b ldr r3, [r7, #4] + 8001698: 689a ldr r2, [r3, #8] + 800169a: 687b ldr r3, [r7, #4] + 800169c: 681b ldr r3, [r3, #0] + 800169e: 2184 movs r1, #132 ; 0x84 + 80016a0: 0209 lsls r1, r1, #8 + 80016a2: 430a orrs r2, r1 + 80016a4: 609a str r2, [r3, #8] + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 80016a6: 687b ldr r3, [r7, #4] + 80016a8: 68db ldr r3, [r3, #12] + 80016aa: 2b02 cmp r3, #2 + 80016ac: d109 bne.n 80016c2 + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + 80016ae: 687b ldr r3, [r7, #4] + 80016b0: 681b ldr r3, [r3, #0] + 80016b2: 685a ldr r2, [r3, #4] + 80016b4: 687b ldr r3, [r7, #4] + 80016b6: 681b ldr r3, [r3, #0] + 80016b8: 2180 movs r1, #128 ; 0x80 + 80016ba: 0109 lsls r1, r1, #4 + 80016bc: 430a orrs r2, r1 + 80016be: 605a str r2, [r3, #4] + 80016c0: e007 b.n 80016d2 + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + 80016c2: 687b ldr r3, [r7, #4] + 80016c4: 681b ldr r3, [r3, #0] + 80016c6: 685a ldr r2, [r3, #4] + 80016c8: 687b ldr r3, [r7, #4] + 80016ca: 681b ldr r3, [r3, #0] + 80016cc: 4923 ldr r1, [pc, #140] ; (800175c ) + 80016ce: 400a ands r2, r1 + 80016d0: 605a str r2, [r3, #4] + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 80016d2: 687b ldr r3, [r7, #4] + 80016d4: 681b ldr r3, [r3, #0] + 80016d6: 685a ldr r2, [r3, #4] + 80016d8: 687b ldr r3, [r7, #4] + 80016da: 681b ldr r3, [r3, #0] + 80016dc: 4920 ldr r1, [pc, #128] ; (8001760 ) + 80016de: 430a orrs r2, r1 + 80016e0: 605a str r2, [r3, #4] + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 80016e2: 687b ldr r3, [r7, #4] + 80016e4: 681b ldr r3, [r3, #0] + 80016e6: 68da ldr r2, [r3, #12] + 80016e8: 687b ldr r3, [r7, #4] + 80016ea: 681b ldr r3, [r3, #0] + 80016ec: 491a ldr r1, [pc, #104] ; (8001758 ) + 80016ee: 400a ands r2, r1 + 80016f0: 60da str r2, [r3, #12] + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 80016f2: 687b ldr r3, [r7, #4] + 80016f4: 691a ldr r2, [r3, #16] + 80016f6: 687b ldr r3, [r7, #4] + 80016f8: 695b ldr r3, [r3, #20] + 80016fa: 431a orrs r2, r3 + 80016fc: 0011 movs r1, r2 + (hi2c->Init.OwnAddress2Masks << 8)); + 80016fe: 687b ldr r3, [r7, #4] + 8001700: 699b ldr r3, [r3, #24] + 8001702: 021a lsls r2, r3, #8 + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 8001704: 687b ldr r3, [r7, #4] + 8001706: 681b ldr r3, [r3, #0] + 8001708: 430a orrs r2, r1 + 800170a: 60da str r2, [r3, #12] + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 800170c: 687b ldr r3, [r7, #4] + 800170e: 69d9 ldr r1, [r3, #28] + 8001710: 687b ldr r3, [r7, #4] + 8001712: 6a1a ldr r2, [r3, #32] + 8001714: 687b ldr r3, [r7, #4] + 8001716: 681b ldr r3, [r3, #0] + 8001718: 430a orrs r2, r1 + 800171a: 601a str r2, [r3, #0] + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 800171c: 687b ldr r3, [r7, #4] + 800171e: 681b ldr r3, [r3, #0] + 8001720: 681a ldr r2, [r3, #0] + 8001722: 687b ldr r3, [r7, #4] + 8001724: 681b ldr r3, [r3, #0] + 8001726: 2101 movs r1, #1 + 8001728: 430a orrs r2, r1 + 800172a: 601a str r2, [r3, #0] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 800172c: 687b ldr r3, [r7, #4] + 800172e: 2200 movs r2, #0 + 8001730: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8001732: 687b ldr r3, [r7, #4] + 8001734: 2241 movs r2, #65 ; 0x41 + 8001736: 2120 movs r1, #32 + 8001738: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_NONE; + 800173a: 687b ldr r3, [r7, #4] + 800173c: 2200 movs r2, #0 + 800173e: 631a str r2, [r3, #48] ; 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8001740: 687b ldr r3, [r7, #4] + 8001742: 2242 movs r2, #66 ; 0x42 + 8001744: 2100 movs r1, #0 + 8001746: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8001748: 2300 movs r3, #0 +} + 800174a: 0018 movs r0, r3 + 800174c: 46bd mov sp, r7 + 800174e: b002 add sp, #8 + 8001750: bd80 pop {r7, pc} + 8001752: 46c0 nop ; (mov r8, r8) + 8001754: f0ffffff .word 0xf0ffffff + 8001758: ffff7fff .word 0xffff7fff + 800175c: fffff7ff .word 0xfffff7ff + 8001760: 02008000 .word 0x02008000 + +08001764 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + 8001764: b580 push {r7, lr} + 8001766: b082 sub sp, #8 + 8001768: af00 add r7, sp, #0 + 800176a: 6078 str r0, [r7, #4] + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 800176c: 687b ldr r3, [r7, #4] + 800176e: 2b00 cmp r3, #0 + 8001770: d101 bne.n 8001776 + { + return HAL_ERROR; + 8001772: 2301 movs r3, #1 + 8001774: e022 b.n 80017bc + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + 8001776: 687b ldr r3, [r7, #4] + 8001778: 2241 movs r2, #65 ; 0x41 + 800177a: 2124 movs r1, #36 ; 0x24 + 800177c: 5499 strb r1, [r3, r2] + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + 800177e: 687b ldr r3, [r7, #4] + 8001780: 681b ldr r3, [r3, #0] + 8001782: 681a ldr r2, [r3, #0] + 8001784: 687b ldr r3, [r7, #4] + 8001786: 681b ldr r3, [r3, #0] + 8001788: 2101 movs r1, #1 + 800178a: 438a bics r2, r1 + 800178c: 601a str r2, [r3, #0] + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + 800178e: 687b ldr r3, [r7, #4] + 8001790: 0018 movs r0, r3 + 8001792: f7ff f9a3 bl 8000adc +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8001796: 687b ldr r3, [r7, #4] + 8001798: 2200 movs r2, #0 + 800179a: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_RESET; + 800179c: 687b ldr r3, [r7, #4] + 800179e: 2241 movs r2, #65 ; 0x41 + 80017a0: 2100 movs r1, #0 + 80017a2: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_NONE; + 80017a4: 687b ldr r3, [r7, #4] + 80017a6: 2200 movs r2, #0 + 80017a8: 631a str r2, [r3, #48] ; 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80017aa: 687b ldr r3, [r7, #4] + 80017ac: 2242 movs r2, #66 ; 0x42 + 80017ae: 2100 movs r1, #0 + 80017b0: 5499 strb r1, [r3, r2] + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + 80017b2: 687b ldr r3, [r7, #4] + 80017b4: 2240 movs r2, #64 ; 0x40 + 80017b6: 2100 movs r1, #0 + 80017b8: 5499 strb r1, [r3, r2] + + return HAL_OK; + 80017ba: 2300 movs r3, #0 +} + 80017bc: 0018 movs r0, r3 + 80017be: 46bd mov sp, r7 + 80017c0: b002 add sp, #8 + 80017c2: bd80 pop {r7, pc} + +080017c4 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + 80017c4: b590 push {r4, r7, lr} + 80017c6: b089 sub sp, #36 ; 0x24 + 80017c8: af02 add r7, sp, #8 + 80017ca: 60f8 str r0, [r7, #12] + 80017cc: 0008 movs r0, r1 + 80017ce: 607a str r2, [r7, #4] + 80017d0: 0019 movs r1, r3 + 80017d2: 230a movs r3, #10 + 80017d4: 18fb adds r3, r7, r3 + 80017d6: 1c02 adds r2, r0, #0 + 80017d8: 801a strh r2, [r3, #0] + 80017da: 2308 movs r3, #8 + 80017dc: 18fb adds r3, r7, r3 + 80017de: 1c0a adds r2, r1, #0 + 80017e0: 801a strh r2, [r3, #0] + uint32_t tickstart; + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + 80017e2: 68fb ldr r3, [r7, #12] + 80017e4: 2241 movs r2, #65 ; 0x41 + 80017e6: 5c9b ldrb r3, [r3, r2] + 80017e8: b2db uxtb r3, r3 + 80017ea: 2b20 cmp r3, #32 + 80017ec: d000 beq.n 80017f0 + 80017ee: e10a b.n 8001a06 + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 80017f0: 68fb ldr r3, [r7, #12] + 80017f2: 2240 movs r2, #64 ; 0x40 + 80017f4: 5c9b ldrb r3, [r3, r2] + 80017f6: 2b01 cmp r3, #1 + 80017f8: d101 bne.n 80017fe + 80017fa: 2302 movs r3, #2 + 80017fc: e104 b.n 8001a08 + 80017fe: 68fb ldr r3, [r7, #12] + 8001800: 2240 movs r2, #64 ; 0x40 + 8001802: 2101 movs r1, #1 + 8001804: 5499 strb r1, [r3, r2] + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001806: f7ff fa8d bl 8000d24 + 800180a: 0003 movs r3, r0 + 800180c: 613b str r3, [r7, #16] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 800180e: 2380 movs r3, #128 ; 0x80 + 8001810: 0219 lsls r1, r3, #8 + 8001812: 68f8 ldr r0, [r7, #12] + 8001814: 693b ldr r3, [r7, #16] + 8001816: 9300 str r3, [sp, #0] + 8001818: 2319 movs r3, #25 + 800181a: 2201 movs r2, #1 + 800181c: f001 ffee bl 80037fc + 8001820: 1e03 subs r3, r0, #0 + 8001822: d001 beq.n 8001828 + { + return HAL_ERROR; + 8001824: 2301 movs r3, #1 + 8001826: e0ef b.n 8001a08 + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + 8001828: 68fb ldr r3, [r7, #12] + 800182a: 2241 movs r2, #65 ; 0x41 + 800182c: 2121 movs r1, #33 ; 0x21 + 800182e: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_MASTER; + 8001830: 68fb ldr r3, [r7, #12] + 8001832: 2242 movs r2, #66 ; 0x42 + 8001834: 2110 movs r1, #16 + 8001836: 5499 strb r1, [r3, r2] + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8001838: 68fb ldr r3, [r7, #12] + 800183a: 2200 movs r2, #0 + 800183c: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 800183e: 68fb ldr r3, [r7, #12] + 8001840: 687a ldr r2, [r7, #4] + 8001842: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 8001844: 68fb ldr r3, [r7, #12] + 8001846: 2208 movs r2, #8 + 8001848: 18ba adds r2, r7, r2 + 800184a: 8812 ldrh r2, [r2, #0] + 800184c: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 800184e: 68fb ldr r3, [r7, #12] + 8001850: 2200 movs r2, #0 + 8001852: 635a str r2, [r3, #52] ; 0x34 + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8001854: 68fb ldr r3, [r7, #12] + 8001856: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001858: b29b uxth r3, r3 + 800185a: 2bff cmp r3, #255 ; 0xff + 800185c: d906 bls.n 800186c + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 800185e: 68fb ldr r3, [r7, #12] + 8001860: 22ff movs r2, #255 ; 0xff + 8001862: 851a strh r2, [r3, #40] ; 0x28 + xfermode = I2C_RELOAD_MODE; + 8001864: 2380 movs r3, #128 ; 0x80 + 8001866: 045b lsls r3, r3, #17 + 8001868: 617b str r3, [r7, #20] + 800186a: e007 b.n 800187c + } + else + { + hi2c->XferSize = hi2c->XferCount; + 800186c: 68fb ldr r3, [r7, #12] + 800186e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001870: b29a uxth r2, r3 + 8001872: 68fb ldr r3, [r7, #12] + 8001874: 851a strh r2, [r3, #40] ; 0x28 + xfermode = I2C_AUTOEND_MODE; + 8001876: 2380 movs r3, #128 ; 0x80 + 8001878: 049b lsls r3, r3, #18 + 800187a: 617b str r3, [r7, #20] + } + + if (hi2c->XferSize > 0U) + 800187c: 68fb ldr r3, [r7, #12] + 800187e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001880: 2b00 cmp r3, #0 + 8001882: d027 beq.n 80018d4 + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 8001884: 68fb ldr r3, [r7, #12] + 8001886: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001888: 781a ldrb r2, [r3, #0] + 800188a: 68fb ldr r3, [r7, #12] + 800188c: 681b ldr r3, [r3, #0] + 800188e: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8001890: 68fb ldr r3, [r7, #12] + 8001892: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001894: 1c5a adds r2, r3, #1 + 8001896: 68fb ldr r3, [r7, #12] + 8001898: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferCount--; + 800189a: 68fb ldr r3, [r7, #12] + 800189c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800189e: b29b uxth r3, r3 + 80018a0: 3b01 subs r3, #1 + 80018a2: b29a uxth r2, r3 + 80018a4: 68fb ldr r3, [r7, #12] + 80018a6: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 80018a8: 68fb ldr r3, [r7, #12] + 80018aa: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80018ac: 3b01 subs r3, #1 + 80018ae: b29a uxth r2, r3 + 80018b0: 68fb ldr r3, [r7, #12] + 80018b2: 851a strh r2, [r3, #40] ; 0x28 + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + 80018b4: 68fb ldr r3, [r7, #12] + 80018b6: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80018b8: b2db uxtb r3, r3 + 80018ba: 3301 adds r3, #1 + 80018bc: b2da uxtb r2, r3 + 80018be: 697c ldr r4, [r7, #20] + 80018c0: 230a movs r3, #10 + 80018c2: 18fb adds r3, r7, r3 + 80018c4: 8819 ldrh r1, [r3, #0] + 80018c6: 68f8 ldr r0, [r7, #12] + 80018c8: 4b51 ldr r3, [pc, #324] ; (8001a10 ) + 80018ca: 9300 str r3, [sp, #0] + 80018cc: 0023 movs r3, r4 + 80018ce: f002 fa15 bl 8003cfc + 80018d2: e06f b.n 80019b4 + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + 80018d4: 68fb ldr r3, [r7, #12] + 80018d6: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80018d8: b2da uxtb r2, r3 + 80018da: 697c ldr r4, [r7, #20] + 80018dc: 230a movs r3, #10 + 80018de: 18fb adds r3, r7, r3 + 80018e0: 8819 ldrh r1, [r3, #0] + 80018e2: 68f8 ldr r0, [r7, #12] + 80018e4: 4b4a ldr r3, [pc, #296] ; (8001a10 ) + 80018e6: 9300 str r3, [sp, #0] + 80018e8: 0023 movs r3, r4 + 80018ea: f002 fa07 bl 8003cfc + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + 80018ee: e061 b.n 80019b4 + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 80018f0: 693a ldr r2, [r7, #16] + 80018f2: 6ab9 ldr r1, [r7, #40] ; 0x28 + 80018f4: 68fb ldr r3, [r7, #12] + 80018f6: 0018 movs r0, r3 + 80018f8: f001 ffd8 bl 80038ac + 80018fc: 1e03 subs r3, r0, #0 + 80018fe: d001 beq.n 8001904 + { + return HAL_ERROR; + 8001900: 2301 movs r3, #1 + 8001902: e081 b.n 8001a08 + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 8001904: 68fb ldr r3, [r7, #12] + 8001906: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001908: 781a ldrb r2, [r3, #0] + 800190a: 68fb ldr r3, [r7, #12] + 800190c: 681b ldr r3, [r3, #0] + 800190e: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8001910: 68fb ldr r3, [r7, #12] + 8001912: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001914: 1c5a adds r2, r3, #1 + 8001916: 68fb ldr r3, [r7, #12] + 8001918: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferCount--; + 800191a: 68fb ldr r3, [r7, #12] + 800191c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800191e: b29b uxth r3, r3 + 8001920: 3b01 subs r3, #1 + 8001922: b29a uxth r2, r3 + 8001924: 68fb ldr r3, [r7, #12] + 8001926: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 8001928: 68fb ldr r3, [r7, #12] + 800192a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800192c: 3b01 subs r3, #1 + 800192e: b29a uxth r2, r3 + 8001930: 68fb ldr r3, [r7, #12] + 8001932: 851a strh r2, [r3, #40] ; 0x28 + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8001934: 68fb ldr r3, [r7, #12] + 8001936: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001938: b29b uxth r3, r3 + 800193a: 2b00 cmp r3, #0 + 800193c: d03a beq.n 80019b4 + 800193e: 68fb ldr r3, [r7, #12] + 8001940: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001942: 2b00 cmp r3, #0 + 8001944: d136 bne.n 80019b4 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 8001946: 6aba ldr r2, [r7, #40] ; 0x28 + 8001948: 68f8 ldr r0, [r7, #12] + 800194a: 693b ldr r3, [r7, #16] + 800194c: 9300 str r3, [sp, #0] + 800194e: 0013 movs r3, r2 + 8001950: 2200 movs r2, #0 + 8001952: 2180 movs r1, #128 ; 0x80 + 8001954: f001 ff52 bl 80037fc + 8001958: 1e03 subs r3, r0, #0 + 800195a: d001 beq.n 8001960 + { + return HAL_ERROR; + 800195c: 2301 movs r3, #1 + 800195e: e053 b.n 8001a08 + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8001960: 68fb ldr r3, [r7, #12] + 8001962: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001964: b29b uxth r3, r3 + 8001966: 2bff cmp r3, #255 ; 0xff + 8001968: d911 bls.n 800198e + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 800196a: 68fb ldr r3, [r7, #12] + 800196c: 22ff movs r2, #255 ; 0xff + 800196e: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8001970: 68fb ldr r3, [r7, #12] + 8001972: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001974: b2da uxtb r2, r3 + 8001976: 2380 movs r3, #128 ; 0x80 + 8001978: 045c lsls r4, r3, #17 + 800197a: 230a movs r3, #10 + 800197c: 18fb adds r3, r7, r3 + 800197e: 8819 ldrh r1, [r3, #0] + 8001980: 68f8 ldr r0, [r7, #12] + 8001982: 2300 movs r3, #0 + 8001984: 9300 str r3, [sp, #0] + 8001986: 0023 movs r3, r4 + 8001988: f002 f9b8 bl 8003cfc + 800198c: e012 b.n 80019b4 + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 800198e: 68fb ldr r3, [r7, #12] + 8001990: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001992: b29a uxth r2, r3 + 8001994: 68fb ldr r3, [r7, #12] + 8001996: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8001998: 68fb ldr r3, [r7, #12] + 800199a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800199c: b2da uxtb r2, r3 + 800199e: 2380 movs r3, #128 ; 0x80 + 80019a0: 049c lsls r4, r3, #18 + 80019a2: 230a movs r3, #10 + 80019a4: 18fb adds r3, r7, r3 + 80019a6: 8819 ldrh r1, [r3, #0] + 80019a8: 68f8 ldr r0, [r7, #12] + 80019aa: 2300 movs r3, #0 + 80019ac: 9300 str r3, [sp, #0] + 80019ae: 0023 movs r3, r4 + 80019b0: f002 f9a4 bl 8003cfc + while (hi2c->XferCount > 0U) + 80019b4: 68fb ldr r3, [r7, #12] + 80019b6: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80019b8: b29b uxth r3, r3 + 80019ba: 2b00 cmp r3, #0 + 80019bc: d198 bne.n 80018f0 + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 80019be: 693a ldr r2, [r7, #16] + 80019c0: 6ab9 ldr r1, [r7, #40] ; 0x28 + 80019c2: 68fb ldr r3, [r7, #12] + 80019c4: 0018 movs r0, r3 + 80019c6: f001 ffb7 bl 8003938 + 80019ca: 1e03 subs r3, r0, #0 + 80019cc: d001 beq.n 80019d2 + { + return HAL_ERROR; + 80019ce: 2301 movs r3, #1 + 80019d0: e01a b.n 8001a08 + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 80019d2: 68fb ldr r3, [r7, #12] + 80019d4: 681b ldr r3, [r3, #0] + 80019d6: 2220 movs r2, #32 + 80019d8: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 80019da: 68fb ldr r3, [r7, #12] + 80019dc: 681b ldr r3, [r3, #0] + 80019de: 685a ldr r2, [r3, #4] + 80019e0: 68fb ldr r3, [r7, #12] + 80019e2: 681b ldr r3, [r3, #0] + 80019e4: 490b ldr r1, [pc, #44] ; (8001a14 ) + 80019e6: 400a ands r2, r1 + 80019e8: 605a str r2, [r3, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 80019ea: 68fb ldr r3, [r7, #12] + 80019ec: 2241 movs r2, #65 ; 0x41 + 80019ee: 2120 movs r1, #32 + 80019f0: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 80019f2: 68fb ldr r3, [r7, #12] + 80019f4: 2242 movs r2, #66 ; 0x42 + 80019f6: 2100 movs r1, #0 + 80019f8: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80019fa: 68fb ldr r3, [r7, #12] + 80019fc: 2240 movs r2, #64 ; 0x40 + 80019fe: 2100 movs r1, #0 + 8001a00: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8001a02: 2300 movs r3, #0 + 8001a04: e000 b.n 8001a08 + } + else + { + return HAL_BUSY; + 8001a06: 2302 movs r3, #2 + } +} + 8001a08: 0018 movs r0, r3 + 8001a0a: 46bd mov sp, r7 + 8001a0c: b007 add sp, #28 + 8001a0e: bd90 pop {r4, r7, pc} + 8001a10: 80002000 .word 0x80002000 + 8001a14: fe00e800 .word 0xfe00e800 + +08001a18 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + 8001a18: b590 push {r4, r7, lr} + 8001a1a: b089 sub sp, #36 ; 0x24 + 8001a1c: af02 add r7, sp, #8 + 8001a1e: 60f8 str r0, [r7, #12] + 8001a20: 0008 movs r0, r1 + 8001a22: 607a str r2, [r7, #4] + 8001a24: 0019 movs r1, r3 + 8001a26: 230a movs r3, #10 + 8001a28: 18fb adds r3, r7, r3 + 8001a2a: 1c02 adds r2, r0, #0 + 8001a2c: 801a strh r2, [r3, #0] + 8001a2e: 2308 movs r3, #8 + 8001a30: 18fb adds r3, r7, r3 + 8001a32: 1c0a adds r2, r1, #0 + 8001a34: 801a strh r2, [r3, #0] + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + 8001a36: 68fb ldr r3, [r7, #12] + 8001a38: 2241 movs r2, #65 ; 0x41 + 8001a3a: 5c9b ldrb r3, [r3, r2] + 8001a3c: b2db uxtb r3, r3 + 8001a3e: 2b20 cmp r3, #32 + 8001a40: d000 beq.n 8001a44 + 8001a42: e0e8 b.n 8001c16 + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8001a44: 68fb ldr r3, [r7, #12] + 8001a46: 2240 movs r2, #64 ; 0x40 + 8001a48: 5c9b ldrb r3, [r3, r2] + 8001a4a: 2b01 cmp r3, #1 + 8001a4c: d101 bne.n 8001a52 + 8001a4e: 2302 movs r3, #2 + 8001a50: e0e2 b.n 8001c18 + 8001a52: 68fb ldr r3, [r7, #12] + 8001a54: 2240 movs r2, #64 ; 0x40 + 8001a56: 2101 movs r1, #1 + 8001a58: 5499 strb r1, [r3, r2] + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001a5a: f7ff f963 bl 8000d24 + 8001a5e: 0003 movs r3, r0 + 8001a60: 617b str r3, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 8001a62: 2380 movs r3, #128 ; 0x80 + 8001a64: 0219 lsls r1, r3, #8 + 8001a66: 68f8 ldr r0, [r7, #12] + 8001a68: 697b ldr r3, [r7, #20] + 8001a6a: 9300 str r3, [sp, #0] + 8001a6c: 2319 movs r3, #25 + 8001a6e: 2201 movs r2, #1 + 8001a70: f001 fec4 bl 80037fc + 8001a74: 1e03 subs r3, r0, #0 + 8001a76: d001 beq.n 8001a7c + { + return HAL_ERROR; + 8001a78: 2301 movs r3, #1 + 8001a7a: e0cd b.n 8001c18 + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + 8001a7c: 68fb ldr r3, [r7, #12] + 8001a7e: 2241 movs r2, #65 ; 0x41 + 8001a80: 2122 movs r1, #34 ; 0x22 + 8001a82: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_MASTER; + 8001a84: 68fb ldr r3, [r7, #12] + 8001a86: 2242 movs r2, #66 ; 0x42 + 8001a88: 2110 movs r1, #16 + 8001a8a: 5499 strb r1, [r3, r2] + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8001a8c: 68fb ldr r3, [r7, #12] + 8001a8e: 2200 movs r2, #0 + 8001a90: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 8001a92: 68fb ldr r3, [r7, #12] + 8001a94: 687a ldr r2, [r7, #4] + 8001a96: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 8001a98: 68fb ldr r3, [r7, #12] + 8001a9a: 2208 movs r2, #8 + 8001a9c: 18ba adds r2, r7, r2 + 8001a9e: 8812 ldrh r2, [r2, #0] + 8001aa0: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 8001aa2: 68fb ldr r3, [r7, #12] + 8001aa4: 2200 movs r2, #0 + 8001aa6: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8001aa8: 68fb ldr r3, [r7, #12] + 8001aaa: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001aac: b29b uxth r3, r3 + 8001aae: 2bff cmp r3, #255 ; 0xff + 8001ab0: d911 bls.n 8001ad6 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8001ab2: 68fb ldr r3, [r7, #12] + 8001ab4: 22ff movs r2, #255 ; 0xff + 8001ab6: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8001ab8: 68fb ldr r3, [r7, #12] + 8001aba: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001abc: b2da uxtb r2, r3 + 8001abe: 2380 movs r3, #128 ; 0x80 + 8001ac0: 045c lsls r4, r3, #17 + 8001ac2: 230a movs r3, #10 + 8001ac4: 18fb adds r3, r7, r3 + 8001ac6: 8819 ldrh r1, [r3, #0] + 8001ac8: 68f8 ldr r0, [r7, #12] + 8001aca: 4b55 ldr r3, [pc, #340] ; (8001c20 ) + 8001acc: 9300 str r3, [sp, #0] + 8001ace: 0023 movs r3, r4 + 8001ad0: f002 f914 bl 8003cfc + 8001ad4: e076 b.n 8001bc4 + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8001ad6: 68fb ldr r3, [r7, #12] + 8001ad8: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001ada: b29a uxth r2, r3 + 8001adc: 68fb ldr r3, [r7, #12] + 8001ade: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8001ae0: 68fb ldr r3, [r7, #12] + 8001ae2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001ae4: b2da uxtb r2, r3 + 8001ae6: 2380 movs r3, #128 ; 0x80 + 8001ae8: 049c lsls r4, r3, #18 + 8001aea: 230a movs r3, #10 + 8001aec: 18fb adds r3, r7, r3 + 8001aee: 8819 ldrh r1, [r3, #0] + 8001af0: 68f8 ldr r0, [r7, #12] + 8001af2: 4b4b ldr r3, [pc, #300] ; (8001c20 ) + 8001af4: 9300 str r3, [sp, #0] + 8001af6: 0023 movs r3, r4 + 8001af8: f002 f900 bl 8003cfc + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + 8001afc: e062 b.n 8001bc4 + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8001afe: 697a ldr r2, [r7, #20] + 8001b00: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8001b02: 68fb ldr r3, [r7, #12] + 8001b04: 0018 movs r0, r3 + 8001b06: f001 ff5b bl 80039c0 + 8001b0a: 1e03 subs r3, r0, #0 + 8001b0c: d001 beq.n 8001b12 + { + return HAL_ERROR; + 8001b0e: 2301 movs r3, #1 + 8001b10: e082 b.n 8001c18 + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 8001b12: 68fb ldr r3, [r7, #12] + 8001b14: 681b ldr r3, [r3, #0] + 8001b16: 6a5a ldr r2, [r3, #36] ; 0x24 + 8001b18: 68fb ldr r3, [r7, #12] + 8001b1a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001b1c: b2d2 uxtb r2, r2 + 8001b1e: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8001b20: 68fb ldr r3, [r7, #12] + 8001b22: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001b24: 1c5a adds r2, r3, #1 + 8001b26: 68fb ldr r3, [r7, #12] + 8001b28: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferSize--; + 8001b2a: 68fb ldr r3, [r7, #12] + 8001b2c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001b2e: 3b01 subs r3, #1 + 8001b30: b29a uxth r2, r3 + 8001b32: 68fb ldr r3, [r7, #12] + 8001b34: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8001b36: 68fb ldr r3, [r7, #12] + 8001b38: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001b3a: b29b uxth r3, r3 + 8001b3c: 3b01 subs r3, #1 + 8001b3e: b29a uxth r2, r3 + 8001b40: 68fb ldr r3, [r7, #12] + 8001b42: 855a strh r2, [r3, #42] ; 0x2a + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8001b44: 68fb ldr r3, [r7, #12] + 8001b46: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001b48: b29b uxth r3, r3 + 8001b4a: 2b00 cmp r3, #0 + 8001b4c: d03a beq.n 8001bc4 + 8001b4e: 68fb ldr r3, [r7, #12] + 8001b50: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001b52: 2b00 cmp r3, #0 + 8001b54: d136 bne.n 8001bc4 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 8001b56: 6aba ldr r2, [r7, #40] ; 0x28 + 8001b58: 68f8 ldr r0, [r7, #12] + 8001b5a: 697b ldr r3, [r7, #20] + 8001b5c: 9300 str r3, [sp, #0] + 8001b5e: 0013 movs r3, r2 + 8001b60: 2200 movs r2, #0 + 8001b62: 2180 movs r1, #128 ; 0x80 + 8001b64: f001 fe4a bl 80037fc + 8001b68: 1e03 subs r3, r0, #0 + 8001b6a: d001 beq.n 8001b70 + { + return HAL_ERROR; + 8001b6c: 2301 movs r3, #1 + 8001b6e: e053 b.n 8001c18 + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8001b70: 68fb ldr r3, [r7, #12] + 8001b72: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001b74: b29b uxth r3, r3 + 8001b76: 2bff cmp r3, #255 ; 0xff + 8001b78: d911 bls.n 8001b9e + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8001b7a: 68fb ldr r3, [r7, #12] + 8001b7c: 22ff movs r2, #255 ; 0xff + 8001b7e: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8001b80: 68fb ldr r3, [r7, #12] + 8001b82: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001b84: b2da uxtb r2, r3 + 8001b86: 2380 movs r3, #128 ; 0x80 + 8001b88: 045c lsls r4, r3, #17 + 8001b8a: 230a movs r3, #10 + 8001b8c: 18fb adds r3, r7, r3 + 8001b8e: 8819 ldrh r1, [r3, #0] + 8001b90: 68f8 ldr r0, [r7, #12] + 8001b92: 2300 movs r3, #0 + 8001b94: 9300 str r3, [sp, #0] + 8001b96: 0023 movs r3, r4 + 8001b98: f002 f8b0 bl 8003cfc + 8001b9c: e012 b.n 8001bc4 + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8001b9e: 68fb ldr r3, [r7, #12] + 8001ba0: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001ba2: b29a uxth r2, r3 + 8001ba4: 68fb ldr r3, [r7, #12] + 8001ba6: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8001ba8: 68fb ldr r3, [r7, #12] + 8001baa: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001bac: b2da uxtb r2, r3 + 8001bae: 2380 movs r3, #128 ; 0x80 + 8001bb0: 049c lsls r4, r3, #18 + 8001bb2: 230a movs r3, #10 + 8001bb4: 18fb adds r3, r7, r3 + 8001bb6: 8819 ldrh r1, [r3, #0] + 8001bb8: 68f8 ldr r0, [r7, #12] + 8001bba: 2300 movs r3, #0 + 8001bbc: 9300 str r3, [sp, #0] + 8001bbe: 0023 movs r3, r4 + 8001bc0: f002 f89c bl 8003cfc + while (hi2c->XferCount > 0U) + 8001bc4: 68fb ldr r3, [r7, #12] + 8001bc6: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001bc8: b29b uxth r3, r3 + 8001bca: 2b00 cmp r3, #0 + 8001bcc: d197 bne.n 8001afe + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8001bce: 697a ldr r2, [r7, #20] + 8001bd0: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8001bd2: 68fb ldr r3, [r7, #12] + 8001bd4: 0018 movs r0, r3 + 8001bd6: f001 feaf bl 8003938 + 8001bda: 1e03 subs r3, r0, #0 + 8001bdc: d001 beq.n 8001be2 + { + return HAL_ERROR; + 8001bde: 2301 movs r3, #1 + 8001be0: e01a b.n 8001c18 + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8001be2: 68fb ldr r3, [r7, #12] + 8001be4: 681b ldr r3, [r3, #0] + 8001be6: 2220 movs r2, #32 + 8001be8: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8001bea: 68fb ldr r3, [r7, #12] + 8001bec: 681b ldr r3, [r3, #0] + 8001bee: 685a ldr r2, [r3, #4] + 8001bf0: 68fb ldr r3, [r7, #12] + 8001bf2: 681b ldr r3, [r3, #0] + 8001bf4: 490b ldr r1, [pc, #44] ; (8001c24 ) + 8001bf6: 400a ands r2, r1 + 8001bf8: 605a str r2, [r3, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 8001bfa: 68fb ldr r3, [r7, #12] + 8001bfc: 2241 movs r2, #65 ; 0x41 + 8001bfe: 2120 movs r1, #32 + 8001c00: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 8001c02: 68fb ldr r3, [r7, #12] + 8001c04: 2242 movs r2, #66 ; 0x42 + 8001c06: 2100 movs r1, #0 + 8001c08: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8001c0a: 68fb ldr r3, [r7, #12] + 8001c0c: 2240 movs r2, #64 ; 0x40 + 8001c0e: 2100 movs r1, #0 + 8001c10: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8001c12: 2300 movs r3, #0 + 8001c14: e000 b.n 8001c18 + } + else + { + return HAL_BUSY; + 8001c16: 2302 movs r3, #2 + } +} + 8001c18: 0018 movs r0, r3 + 8001c1a: 46bd mov sp, r7 + 8001c1c: b007 add sp, #28 + 8001c1e: bd90 pop {r4, r7, pc} + 8001c20: 80002400 .word 0x80002400 + 8001c24: fe00e800 .word 0xfe00e800 + +08001c28 : + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + 8001c28: b5b0 push {r4, r5, r7, lr} + 8001c2a: b08a sub sp, #40 ; 0x28 + 8001c2c: af02 add r7, sp, #8 + 8001c2e: 60f8 str r0, [r7, #12] + 8001c30: 0008 movs r0, r1 + 8001c32: 607a str r2, [r7, #4] + 8001c34: 0019 movs r1, r3 + 8001c36: 230a movs r3, #10 + 8001c38: 18fb adds r3, r7, r3 + 8001c3a: 1c02 adds r2, r0, #0 + 8001c3c: 801a strh r2, [r3, #0] + 8001c3e: 2308 movs r3, #8 + 8001c40: 18fb adds r3, r7, r3 + 8001c42: 1c0a adds r2, r1, #0 + 8001c44: 801a strh r2, [r3, #0] + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; + 8001c46: 2300 movs r3, #0 + 8001c48: 61bb str r3, [r7, #24] + + if (hi2c->State == HAL_I2C_STATE_READY) + 8001c4a: 68fb ldr r3, [r7, #12] + 8001c4c: 2241 movs r2, #65 ; 0x41 + 8001c4e: 5c9b ldrb r3, [r3, r2] + 8001c50: b2db uxtb r3, r3 + 8001c52: 2b20 cmp r3, #32 + 8001c54: d000 beq.n 8001c58 + 8001c56: e0ff b.n 8001e58 + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 8001c58: 68fb ldr r3, [r7, #12] + 8001c5a: 681b ldr r3, [r3, #0] + 8001c5c: 699a ldr r2, [r3, #24] + 8001c5e: 2380 movs r3, #128 ; 0x80 + 8001c60: 021b lsls r3, r3, #8 + 8001c62: 401a ands r2, r3 + 8001c64: 2380 movs r3, #128 ; 0x80 + 8001c66: 021b lsls r3, r3, #8 + 8001c68: 429a cmp r2, r3 + 8001c6a: d101 bne.n 8001c70 + { + return HAL_BUSY; + 8001c6c: 2302 movs r3, #2 + 8001c6e: e0f4 b.n 8001e5a + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + 8001c70: 68fb ldr r3, [r7, #12] + 8001c72: 2240 movs r2, #64 ; 0x40 + 8001c74: 5c9b ldrb r3, [r3, r2] + 8001c76: 2b01 cmp r3, #1 + 8001c78: d101 bne.n 8001c7e + 8001c7a: 2302 movs r3, #2 + 8001c7c: e0ed b.n 8001e5a + 8001c7e: 68fb ldr r3, [r7, #12] + 8001c80: 2240 movs r2, #64 ; 0x40 + 8001c82: 2101 movs r1, #1 + 8001c84: 5499 strb r1, [r3, r2] + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + 8001c86: 68fb ldr r3, [r7, #12] + 8001c88: 2241 movs r2, #65 ; 0x41 + 8001c8a: 2121 movs r1, #33 ; 0x21 + 8001c8c: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_MASTER; + 8001c8e: 68fb ldr r3, [r7, #12] + 8001c90: 2242 movs r2, #66 ; 0x42 + 8001c92: 2110 movs r1, #16 + 8001c94: 5499 strb r1, [r3, r2] + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8001c96: 68fb ldr r3, [r7, #12] + 8001c98: 2200 movs r2, #0 + 8001c9a: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 8001c9c: 68fb ldr r3, [r7, #12] + 8001c9e: 687a ldr r2, [r7, #4] + 8001ca0: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 8001ca2: 68fb ldr r3, [r7, #12] + 8001ca4: 2208 movs r2, #8 + 8001ca6: 18ba adds r2, r7, r2 + 8001ca8: 8812 ldrh r2, [r2, #0] + 8001caa: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 8001cac: 68fb ldr r3, [r7, #12] + 8001cae: 4a6d ldr r2, [pc, #436] ; (8001e64 ) + 8001cb0: 62da str r2, [r3, #44] ; 0x2c + hi2c->XferISR = I2C_Master_ISR_DMA; + 8001cb2: 68fb ldr r3, [r7, #12] + 8001cb4: 4a6c ldr r2, [pc, #432] ; (8001e68 ) + 8001cb6: 635a str r2, [r3, #52] ; 0x34 + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8001cb8: 68fb ldr r3, [r7, #12] + 8001cba: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001cbc: b29b uxth r3, r3 + 8001cbe: 2bff cmp r3, #255 ; 0xff + 8001cc0: d906 bls.n 8001cd0 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8001cc2: 68fb ldr r3, [r7, #12] + 8001cc4: 22ff movs r2, #255 ; 0xff + 8001cc6: 851a strh r2, [r3, #40] ; 0x28 + xfermode = I2C_RELOAD_MODE; + 8001cc8: 2380 movs r3, #128 ; 0x80 + 8001cca: 045b lsls r3, r3, #17 + 8001ccc: 61fb str r3, [r7, #28] + 8001cce: e007 b.n 8001ce0 + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8001cd0: 68fb ldr r3, [r7, #12] + 8001cd2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001cd4: b29a uxth r2, r3 + 8001cd6: 68fb ldr r3, [r7, #12] + 8001cd8: 851a strh r2, [r3, #40] ; 0x28 + xfermode = I2C_AUTOEND_MODE; + 8001cda: 2380 movs r3, #128 ; 0x80 + 8001cdc: 049b lsls r3, r3, #18 + 8001cde: 61fb str r3, [r7, #28] + } + + if (hi2c->XferSize > 0U) + 8001ce0: 68fb ldr r3, [r7, #12] + 8001ce2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001ce4: 2b00 cmp r3, #0 + 8001ce6: d01a beq.n 8001d1e + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 8001ce8: 68fb ldr r3, [r7, #12] + 8001cea: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001cec: 781a ldrb r2, [r3, #0] + 8001cee: 68fb ldr r3, [r7, #12] + 8001cf0: 681b ldr r3, [r3, #0] + 8001cf2: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8001cf4: 68fb ldr r3, [r7, #12] + 8001cf6: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001cf8: 1c5a adds r2, r3, #1 + 8001cfa: 68fb ldr r3, [r7, #12] + 8001cfc: 625a str r2, [r3, #36] ; 0x24 + + sizetoxfer = hi2c->XferSize; + 8001cfe: 68fb ldr r3, [r7, #12] + 8001d00: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001d02: 61bb str r3, [r7, #24] + hi2c->XferCount--; + 8001d04: 68fb ldr r3, [r7, #12] + 8001d06: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001d08: b29b uxth r3, r3 + 8001d0a: 3b01 subs r3, #1 + 8001d0c: b29a uxth r2, r3 + 8001d0e: 68fb ldr r3, [r7, #12] + 8001d10: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 8001d12: 68fb ldr r3, [r7, #12] + 8001d14: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001d16: 3b01 subs r3, #1 + 8001d18: b29a uxth r2, r3 + 8001d1a: 68fb ldr r3, [r7, #12] + 8001d1c: 851a strh r2, [r3, #40] ; 0x28 + } + + if (hi2c->XferSize > 0U) + 8001d1e: 68fb ldr r3, [r7, #12] + 8001d20: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001d22: 2b00 cmp r3, #0 + 8001d24: d100 bne.n 8001d28 + 8001d26: e07c b.n 8001e22 + { + if (hi2c->hdmatx != NULL) + 8001d28: 68fb ldr r3, [r7, #12] + 8001d2a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8001d2c: 2b00 cmp r3, #0 + 8001d2e: d025 beq.n 8001d7c + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + 8001d30: 68fb ldr r3, [r7, #12] + 8001d32: 6b9b ldr r3, [r3, #56] ; 0x38 + 8001d34: 4a4d ldr r2, [pc, #308] ; (8001e6c ) + 8001d36: 62da str r2, [r3, #44] ; 0x2c + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + 8001d38: 68fb ldr r3, [r7, #12] + 8001d3a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8001d3c: 4a4c ldr r2, [pc, #304] ; (8001e70 ) + 8001d3e: 635a str r2, [r3, #52] ; 0x34 + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + 8001d40: 68fb ldr r3, [r7, #12] + 8001d42: 6b9b ldr r3, [r3, #56] ; 0x38 + 8001d44: 2200 movs r2, #0 + 8001d46: 631a str r2, [r3, #48] ; 0x30 + hi2c->hdmatx->XferAbortCallback = NULL; + 8001d48: 68fb ldr r3, [r7, #12] + 8001d4a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8001d4c: 2200 movs r2, #0 + 8001d4e: 639a str r2, [r3, #56] ; 0x38 + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + 8001d50: 68fb ldr r3, [r7, #12] + 8001d52: 6b98 ldr r0, [r3, #56] ; 0x38 + 8001d54: 68fb ldr r3, [r7, #12] + 8001d56: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001d58: 0019 movs r1, r3 + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + 8001d5a: 68fb ldr r3, [r7, #12] + 8001d5c: 681b ldr r3, [r3, #0] + 8001d5e: 3328 adds r3, #40 ; 0x28 + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + 8001d60: 001a movs r2, r3 + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + 8001d62: 68fb ldr r3, [r7, #12] + 8001d64: 8d1b ldrh r3, [r3, #40] ; 0x28 + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + 8001d66: 2517 movs r5, #23 + 8001d68: 197c adds r4, r7, r5 + 8001d6a: f7ff f8bd bl 8000ee8 + 8001d6e: 0003 movs r3, r0 + 8001d70: 7023 strb r3, [r4, #0] + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + 8001d72: 197b adds r3, r7, r5 + 8001d74: 781b ldrb r3, [r3, #0] + 8001d76: 2b00 cmp r3, #0 + 8001d78: d13f bne.n 8001dfa + 8001d7a: e013 b.n 8001da4 + hi2c->State = HAL_I2C_STATE_READY; + 8001d7c: 68fb ldr r3, [r7, #12] + 8001d7e: 2241 movs r2, #65 ; 0x41 + 8001d80: 2120 movs r1, #32 + 8001d82: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 8001d84: 68fb ldr r3, [r7, #12] + 8001d86: 2242 movs r2, #66 ; 0x42 + 8001d88: 2100 movs r1, #0 + 8001d8a: 5499 strb r1, [r3, r2] + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + 8001d8c: 68fb ldr r3, [r7, #12] + 8001d8e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001d90: 2280 movs r2, #128 ; 0x80 + 8001d92: 431a orrs r2, r3 + 8001d94: 68fb ldr r3, [r7, #12] + 8001d96: 645a str r2, [r3, #68] ; 0x44 + __HAL_UNLOCK(hi2c); + 8001d98: 68fb ldr r3, [r7, #12] + 8001d9a: 2240 movs r2, #64 ; 0x40 + 8001d9c: 2100 movs r1, #0 + 8001d9e: 5499 strb r1, [r3, r2] + return HAL_ERROR; + 8001da0: 2301 movs r3, #1 + 8001da2: e05a b.n 8001e5a + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), + 8001da4: 68fb ldr r3, [r7, #12] + 8001da6: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001da8: b2db uxtb r3, r3 + 8001daa: 3301 adds r3, #1 + 8001dac: b2da uxtb r2, r3 + 8001dae: 69fc ldr r4, [r7, #28] + 8001db0: 230a movs r3, #10 + 8001db2: 18fb adds r3, r7, r3 + 8001db4: 8819 ldrh r1, [r3, #0] + 8001db6: 68f8 ldr r0, [r7, #12] + 8001db8: 4b2e ldr r3, [pc, #184] ; (8001e74 ) + 8001dba: 9300 str r3, [sp, #0] + 8001dbc: 0023 movs r3, r4 + 8001dbe: f001 ff9d bl 8003cfc + xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + 8001dc2: 68fb ldr r3, [r7, #12] + 8001dc4: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001dc6: b29a uxth r2, r3 + 8001dc8: 68fb ldr r3, [r7, #12] + 8001dca: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001dcc: 1ad3 subs r3, r2, r3 + 8001dce: b29a uxth r2, r3 + 8001dd0: 68fb ldr r3, [r7, #12] + 8001dd2: 855a strh r2, [r3, #42] ; 0x2a + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8001dd4: 68fb ldr r3, [r7, #12] + 8001dd6: 2240 movs r2, #64 ; 0x40 + 8001dd8: 2100 movs r1, #0 + 8001dda: 5499 strb r1, [r3, r2] + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 8001ddc: 68fb ldr r3, [r7, #12] + 8001dde: 2110 movs r1, #16 + 8001de0: 0018 movs r0, r3 + 8001de2: f001 ffc5 bl 8003d70 + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 8001de6: 68fb ldr r3, [r7, #12] + 8001de8: 681b ldr r3, [r3, #0] + 8001dea: 681a ldr r2, [r3, #0] + 8001dec: 68fb ldr r3, [r7, #12] + 8001dee: 681b ldr r3, [r3, #0] + 8001df0: 2180 movs r1, #128 ; 0x80 + 8001df2: 01c9 lsls r1, r1, #7 + 8001df4: 430a orrs r2, r1 + 8001df6: 601a str r2, [r3, #0] + 8001df8: e02c b.n 8001e54 + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + 8001dfa: 68fb ldr r3, [r7, #12] + 8001dfc: 2241 movs r2, #65 ; 0x41 + 8001dfe: 2120 movs r1, #32 + 8001e00: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 8001e02: 68fb ldr r3, [r7, #12] + 8001e04: 2242 movs r2, #66 ; 0x42 + 8001e06: 2100 movs r1, #0 + 8001e08: 5499 strb r1, [r3, r2] + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + 8001e0a: 68fb ldr r3, [r7, #12] + 8001e0c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001e0e: 2210 movs r2, #16 + 8001e10: 431a orrs r2, r3 + 8001e12: 68fb ldr r3, [r7, #12] + 8001e14: 645a str r2, [r3, #68] ; 0x44 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8001e16: 68fb ldr r3, [r7, #12] + 8001e18: 2240 movs r2, #64 ; 0x40 + 8001e1a: 2100 movs r1, #0 + 8001e1c: 5499 strb r1, [r3, r2] + + return HAL_ERROR; + 8001e1e: 2301 movs r3, #1 + 8001e20: e01b b.n 8001e5a + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + 8001e22: 68fb ldr r3, [r7, #12] + 8001e24: 4a14 ldr r2, [pc, #80] ; (8001e78 ) + 8001e26: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, + 8001e28: 69bb ldr r3, [r7, #24] + 8001e2a: b2da uxtb r2, r3 + 8001e2c: 2380 movs r3, #128 ; 0x80 + 8001e2e: 049c lsls r4, r3, #18 + 8001e30: 230a movs r3, #10 + 8001e32: 18fb adds r3, r7, r3 + 8001e34: 8819 ldrh r1, [r3, #0] + 8001e36: 68f8 ldr r0, [r7, #12] + 8001e38: 4b0e ldr r3, [pc, #56] ; (8001e74 ) + 8001e3a: 9300 str r3, [sp, #0] + 8001e3c: 0023 movs r3, r4 + 8001e3e: f001 ff5d bl 8003cfc + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8001e42: 68fb ldr r3, [r7, #12] + 8001e44: 2240 movs r2, #64 ; 0x40 + 8001e46: 2100 movs r1, #0 + 8001e48: 5499 strb r1, [r3, r2] + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 8001e4a: 68fb ldr r3, [r7, #12] + 8001e4c: 2101 movs r1, #1 + 8001e4e: 0018 movs r0, r3 + 8001e50: f001 ff8e bl 8003d70 + } + + return HAL_OK; + 8001e54: 2300 movs r3, #0 + 8001e56: e000 b.n 8001e5a + } + else + { + return HAL_BUSY; + 8001e58: 2302 movs r3, #2 + } +} + 8001e5a: 0018 movs r0, r3 + 8001e5c: 46bd mov sp, r7 + 8001e5e: b008 add sp, #32 + 8001e60: bdb0 pop {r4, r5, r7, pc} + 8001e62: 46c0 nop ; (mov r8, r8) + 8001e64: ffff0000 .word 0xffff0000 + 8001e68: 080025a1 .word 0x080025a1 + 8001e6c: 0800364d .word 0x0800364d + 8001e70: 0800378d .word 0x0800378d + 8001e74: 80002000 .word 0x80002000 + 8001e78: 08002139 .word 0x08002139 + +08001e7c : + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + 8001e7c: b5b0 push {r4, r5, r7, lr} + 8001e7e: b088 sub sp, #32 + 8001e80: af02 add r7, sp, #8 + 8001e82: 60f8 str r0, [r7, #12] + 8001e84: 0008 movs r0, r1 + 8001e86: 607a str r2, [r7, #4] + 8001e88: 0019 movs r1, r3 + 8001e8a: 230a movs r3, #10 + 8001e8c: 18fb adds r3, r7, r3 + 8001e8e: 1c02 adds r2, r0, #0 + 8001e90: 801a strh r2, [r3, #0] + 8001e92: 2308 movs r3, #8 + 8001e94: 18fb adds r3, r7, r3 + 8001e96: 1c0a adds r2, r1, #0 + 8001e98: 801a strh r2, [r3, #0] + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + 8001e9a: 68fb ldr r3, [r7, #12] + 8001e9c: 2241 movs r2, #65 ; 0x41 + 8001e9e: 5c9b ldrb r3, [r3, r2] + 8001ea0: b2db uxtb r3, r3 + 8001ea2: 2b20 cmp r3, #32 + 8001ea4: d000 beq.n 8001ea8 + 8001ea6: e0dd b.n 8002064 + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 8001ea8: 68fb ldr r3, [r7, #12] + 8001eaa: 681b ldr r3, [r3, #0] + 8001eac: 699a ldr r2, [r3, #24] + 8001eae: 2380 movs r3, #128 ; 0x80 + 8001eb0: 021b lsls r3, r3, #8 + 8001eb2: 401a ands r2, r3 + 8001eb4: 2380 movs r3, #128 ; 0x80 + 8001eb6: 021b lsls r3, r3, #8 + 8001eb8: 429a cmp r2, r3 + 8001eba: d101 bne.n 8001ec0 + { + return HAL_BUSY; + 8001ebc: 2302 movs r3, #2 + 8001ebe: e0d2 b.n 8002066 + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + 8001ec0: 68fb ldr r3, [r7, #12] + 8001ec2: 2240 movs r2, #64 ; 0x40 + 8001ec4: 5c9b ldrb r3, [r3, r2] + 8001ec6: 2b01 cmp r3, #1 + 8001ec8: d101 bne.n 8001ece + 8001eca: 2302 movs r3, #2 + 8001ecc: e0cb b.n 8002066 + 8001ece: 68fb ldr r3, [r7, #12] + 8001ed0: 2240 movs r2, #64 ; 0x40 + 8001ed2: 2101 movs r1, #1 + 8001ed4: 5499 strb r1, [r3, r2] + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + 8001ed6: 68fb ldr r3, [r7, #12] + 8001ed8: 2241 movs r2, #65 ; 0x41 + 8001eda: 2122 movs r1, #34 ; 0x22 + 8001edc: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_MASTER; + 8001ede: 68fb ldr r3, [r7, #12] + 8001ee0: 2242 movs r2, #66 ; 0x42 + 8001ee2: 2110 movs r1, #16 + 8001ee4: 5499 strb r1, [r3, r2] + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8001ee6: 68fb ldr r3, [r7, #12] + 8001ee8: 2200 movs r2, #0 + 8001eea: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 8001eec: 68fb ldr r3, [r7, #12] + 8001eee: 687a ldr r2, [r7, #4] + 8001ef0: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 8001ef2: 68fb ldr r3, [r7, #12] + 8001ef4: 2208 movs r2, #8 + 8001ef6: 18ba adds r2, r7, r2 + 8001ef8: 8812 ldrh r2, [r2, #0] + 8001efa: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 8001efc: 68fb ldr r3, [r7, #12] + 8001efe: 4a5c ldr r2, [pc, #368] ; (8002070 ) + 8001f00: 62da str r2, [r3, #44] ; 0x2c + hi2c->XferISR = I2C_Master_ISR_DMA; + 8001f02: 68fb ldr r3, [r7, #12] + 8001f04: 4a5b ldr r2, [pc, #364] ; (8002074 ) + 8001f06: 635a str r2, [r3, #52] ; 0x34 + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8001f08: 68fb ldr r3, [r7, #12] + 8001f0a: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001f0c: b29b uxth r3, r3 + 8001f0e: 2bff cmp r3, #255 ; 0xff + 8001f10: d906 bls.n 8001f20 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8001f12: 68fb ldr r3, [r7, #12] + 8001f14: 22ff movs r2, #255 ; 0xff + 8001f16: 851a strh r2, [r3, #40] ; 0x28 + xfermode = I2C_RELOAD_MODE; + 8001f18: 2380 movs r3, #128 ; 0x80 + 8001f1a: 045b lsls r3, r3, #17 + 8001f1c: 617b str r3, [r7, #20] + 8001f1e: e007 b.n 8001f30 + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8001f20: 68fb ldr r3, [r7, #12] + 8001f22: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001f24: b29a uxth r2, r3 + 8001f26: 68fb ldr r3, [r7, #12] + 8001f28: 851a strh r2, [r3, #40] ; 0x28 + xfermode = I2C_AUTOEND_MODE; + 8001f2a: 2380 movs r3, #128 ; 0x80 + 8001f2c: 049b lsls r3, r3, #18 + 8001f2e: 617b str r3, [r7, #20] + } + + if (hi2c->XferSize > 0U) + 8001f30: 68fb ldr r3, [r7, #12] + 8001f32: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001f34: 2b00 cmp r3, #0 + 8001f36: d100 bne.n 8001f3a + 8001f38: e078 b.n 800202c + { + if (hi2c->hdmarx != NULL) + 8001f3a: 68fb ldr r3, [r7, #12] + 8001f3c: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001f3e: 2b00 cmp r3, #0 + 8001f40: d023 beq.n 8001f8a + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + 8001f42: 68fb ldr r3, [r7, #12] + 8001f44: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001f46: 4a4c ldr r2, [pc, #304] ; (8002078 ) + 8001f48: 62da str r2, [r3, #44] ; 0x2c + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + 8001f4a: 68fb ldr r3, [r7, #12] + 8001f4c: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001f4e: 4a4b ldr r2, [pc, #300] ; (800207c ) + 8001f50: 635a str r2, [r3, #52] ; 0x34 + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + 8001f52: 68fb ldr r3, [r7, #12] + 8001f54: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001f56: 2200 movs r2, #0 + 8001f58: 631a str r2, [r3, #48] ; 0x30 + hi2c->hdmarx->XferAbortCallback = NULL; + 8001f5a: 68fb ldr r3, [r7, #12] + 8001f5c: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001f5e: 2200 movs r2, #0 + 8001f60: 639a str r2, [r3, #56] ; 0x38 + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + 8001f62: 68fb ldr r3, [r7, #12] + 8001f64: 6bd8 ldr r0, [r3, #60] ; 0x3c + 8001f66: 68fb ldr r3, [r7, #12] + 8001f68: 681b ldr r3, [r3, #0] + 8001f6a: 3324 adds r3, #36 ; 0x24 + 8001f6c: 0019 movs r1, r3 + 8001f6e: 687a ldr r2, [r7, #4] + hi2c->XferSize); + 8001f70: 68fb ldr r3, [r7, #12] + 8001f72: 8d1b ldrh r3, [r3, #40] ; 0x28 + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + 8001f74: 2513 movs r5, #19 + 8001f76: 197c adds r4, r7, r5 + 8001f78: f7fe ffb6 bl 8000ee8 + 8001f7c: 0003 movs r3, r0 + 8001f7e: 7023 strb r3, [r4, #0] + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + 8001f80: 197b adds r3, r7, r5 + 8001f82: 781b ldrb r3, [r3, #0] + 8001f84: 2b00 cmp r3, #0 + 8001f86: d13d bne.n 8002004 + 8001f88: e013 b.n 8001fb2 + hi2c->State = HAL_I2C_STATE_READY; + 8001f8a: 68fb ldr r3, [r7, #12] + 8001f8c: 2241 movs r2, #65 ; 0x41 + 8001f8e: 2120 movs r1, #32 + 8001f90: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 8001f92: 68fb ldr r3, [r7, #12] + 8001f94: 2242 movs r2, #66 ; 0x42 + 8001f96: 2100 movs r1, #0 + 8001f98: 5499 strb r1, [r3, r2] + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + 8001f9a: 68fb ldr r3, [r7, #12] + 8001f9c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001f9e: 2280 movs r2, #128 ; 0x80 + 8001fa0: 431a orrs r2, r3 + 8001fa2: 68fb ldr r3, [r7, #12] + 8001fa4: 645a str r2, [r3, #68] ; 0x44 + __HAL_UNLOCK(hi2c); + 8001fa6: 68fb ldr r3, [r7, #12] + 8001fa8: 2240 movs r2, #64 ; 0x40 + 8001faa: 2100 movs r1, #0 + 8001fac: 5499 strb r1, [r3, r2] + return HAL_ERROR; + 8001fae: 2301 movs r3, #1 + 8001fb0: e059 b.n 8002066 + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + 8001fb2: 68fb ldr r3, [r7, #12] + 8001fb4: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001fb6: b2da uxtb r2, r3 + 8001fb8: 697c ldr r4, [r7, #20] + 8001fba: 230a movs r3, #10 + 8001fbc: 18fb adds r3, r7, r3 + 8001fbe: 8819 ldrh r1, [r3, #0] + 8001fc0: 68f8 ldr r0, [r7, #12] + 8001fc2: 4b2f ldr r3, [pc, #188] ; (8002080 ) + 8001fc4: 9300 str r3, [sp, #0] + 8001fc6: 0023 movs r3, r4 + 8001fc8: f001 fe98 bl 8003cfc + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + 8001fcc: 68fb ldr r3, [r7, #12] + 8001fce: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8001fd0: b29a uxth r2, r3 + 8001fd2: 68fb ldr r3, [r7, #12] + 8001fd4: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8001fd6: 1ad3 subs r3, r2, r3 + 8001fd8: b29a uxth r2, r3 + 8001fda: 68fb ldr r3, [r7, #12] + 8001fdc: 855a strh r2, [r3, #42] ; 0x2a + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8001fde: 68fb ldr r3, [r7, #12] + 8001fe0: 2240 movs r2, #64 ; 0x40 + 8001fe2: 2100 movs r1, #0 + 8001fe4: 5499 strb r1, [r3, r2] + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 8001fe6: 68fb ldr r3, [r7, #12] + 8001fe8: 2110 movs r1, #16 + 8001fea: 0018 movs r0, r3 + 8001fec: f001 fec0 bl 8003d70 + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 8001ff0: 68fb ldr r3, [r7, #12] + 8001ff2: 681b ldr r3, [r3, #0] + 8001ff4: 681a ldr r2, [r3, #0] + 8001ff6: 68fb ldr r3, [r7, #12] + 8001ff8: 681b ldr r3, [r3, #0] + 8001ffa: 2180 movs r1, #128 ; 0x80 + 8001ffc: 0209 lsls r1, r1, #8 + 8001ffe: 430a orrs r2, r1 + 8002000: 601a str r2, [r3, #0] + 8002002: e02d b.n 8002060 + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + 8002004: 68fb ldr r3, [r7, #12] + 8002006: 2241 movs r2, #65 ; 0x41 + 8002008: 2120 movs r1, #32 + 800200a: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 800200c: 68fb ldr r3, [r7, #12] + 800200e: 2242 movs r2, #66 ; 0x42 + 8002010: 2100 movs r1, #0 + 8002012: 5499 strb r1, [r3, r2] + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + 8002014: 68fb ldr r3, [r7, #12] + 8002016: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002018: 2210 movs r2, #16 + 800201a: 431a orrs r2, r3 + 800201c: 68fb ldr r3, [r7, #12] + 800201e: 645a str r2, [r3, #68] ; 0x44 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8002020: 68fb ldr r3, [r7, #12] + 8002022: 2240 movs r2, #64 ; 0x40 + 8002024: 2100 movs r1, #0 + 8002026: 5499 strb r1, [r3, r2] + + return HAL_ERROR; + 8002028: 2301 movs r3, #1 + 800202a: e01c b.n 8002066 + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + 800202c: 68fb ldr r3, [r7, #12] + 800202e: 4a15 ldr r2, [pc, #84] ; (8002084 ) + 8002030: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8002032: 68fb ldr r3, [r7, #12] + 8002034: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002036: b2da uxtb r2, r3 + 8002038: 2380 movs r3, #128 ; 0x80 + 800203a: 049c lsls r4, r3, #18 + 800203c: 230a movs r3, #10 + 800203e: 18fb adds r3, r7, r3 + 8002040: 8819 ldrh r1, [r3, #0] + 8002042: 68f8 ldr r0, [r7, #12] + 8002044: 4b0e ldr r3, [pc, #56] ; (8002080 ) + 8002046: 9300 str r3, [sp, #0] + 8002048: 0023 movs r3, r4 + 800204a: f001 fe57 bl 8003cfc + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800204e: 68fb ldr r3, [r7, #12] + 8002050: 2240 movs r2, #64 ; 0x40 + 8002052: 2100 movs r1, #0 + 8002054: 5499 strb r1, [r3, r2] + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + 8002056: 68fb ldr r3, [r7, #12] + 8002058: 2102 movs r1, #2 + 800205a: 0018 movs r0, r3 + 800205c: f001 fe88 bl 8003d70 + } + + return HAL_OK; + 8002060: 2300 movs r3, #0 + 8002062: e000 b.n 8002066 + } + else + { + return HAL_BUSY; + 8002064: 2302 movs r3, #2 + } +} + 8002066: 0018 movs r0, r3 + 8002068: 46bd mov sp, r7 + 800206a: b006 add sp, #24 + 800206c: bdb0 pop {r4, r5, r7, pc} + 800206e: 46c0 nop ; (mov r8, r8) + 8002070: ffff0000 .word 0xffff0000 + 8002074: 080025a1 .word 0x080025a1 + 8002078: 080036ed .word 0x080036ed + 800207c: 0800378d .word 0x0800378d + 8002080: 80002400 .word 0x80002400 + 8002084: 08002139 .word 0x08002139 + +08002088 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + 8002088: b580 push {r7, lr} + 800208a: b082 sub sp, #8 + 800208c: af00 add r7, sp, #0 + 800208e: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + 8002090: 46c0 nop ; (mov r8, r8) + 8002092: 46bd mov sp, r7 + 8002094: b002 add sp, #8 + 8002096: bd80 pop {r7, pc} + +08002098 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + 8002098: b580 push {r7, lr} + 800209a: b082 sub sp, #8 + 800209c: af00 add r7, sp, #0 + 800209e: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + 80020a0: 46c0 nop ; (mov r8, r8) + 80020a2: 46bd mov sp, r7 + 80020a4: b002 add sp, #8 + 80020a6: bd80 pop {r7, pc} + +080020a8 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + 80020a8: b580 push {r7, lr} + 80020aa: b082 sub sp, #8 + 80020ac: af00 add r7, sp, #0 + 80020ae: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + 80020b0: 46c0 nop ; (mov r8, r8) + 80020b2: 46bd mov sp, r7 + 80020b4: b002 add sp, #8 + 80020b6: bd80 pop {r7, pc} + +080020b8 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + 80020b8: b580 push {r7, lr} + 80020ba: b082 sub sp, #8 + 80020bc: af00 add r7, sp, #0 + 80020be: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + 80020c0: 46c0 nop ; (mov r8, r8) + 80020c2: 46bd mov sp, r7 + 80020c4: b002 add sp, #8 + 80020c6: bd80 pop {r7, pc} + +080020c8 : + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + 80020c8: b580 push {r7, lr} + 80020ca: b082 sub sp, #8 + 80020cc: af00 add r7, sp, #0 + 80020ce: 6078 str r0, [r7, #4] + 80020d0: 0008 movs r0, r1 + 80020d2: 0011 movs r1, r2 + 80020d4: 1cfb adds r3, r7, #3 + 80020d6: 1c02 adds r2, r0, #0 + 80020d8: 701a strb r2, [r3, #0] + 80020da: 003b movs r3, r7 + 80020dc: 1c0a adds r2, r1, #0 + 80020de: 801a strh r2, [r3, #0] + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + 80020e0: 46c0 nop ; (mov r8, r8) + 80020e2: 46bd mov sp, r7 + 80020e4: b002 add sp, #8 + 80020e6: bd80 pop {r7, pc} + +080020e8 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + 80020e8: b580 push {r7, lr} + 80020ea: b082 sub sp, #8 + 80020ec: af00 add r7, sp, #0 + 80020ee: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + 80020f0: 46c0 nop ; (mov r8, r8) + 80020f2: 46bd mov sp, r7 + 80020f4: b002 add sp, #8 + 80020f6: bd80 pop {r7, pc} + +080020f8 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + 80020f8: b580 push {r7, lr} + 80020fa: b082 sub sp, #8 + 80020fc: af00 add r7, sp, #0 + 80020fe: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + 8002100: 46c0 nop ; (mov r8, r8) + 8002102: 46bd mov sp, r7 + 8002104: b002 add sp, #8 + 8002106: bd80 pop {r7, pc} + +08002108 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + 8002108: b580 push {r7, lr} + 800210a: b082 sub sp, #8 + 800210c: af00 add r7, sp, #0 + 800210e: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + 8002110: 46c0 nop ; (mov r8, r8) + 8002112: 46bd mov sp, r7 + 8002114: b002 add sp, #8 + 8002116: bd80 pop {r7, pc} + +08002118 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + 8002118: b580 push {r7, lr} + 800211a: b082 sub sp, #8 + 800211c: af00 add r7, sp, #0 + 800211e: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + 8002120: 46c0 nop ; (mov r8, r8) + 8002122: 46bd mov sp, r7 + 8002124: b002 add sp, #8 + 8002126: bd80 pop {r7, pc} + +08002128 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + 8002128: b580 push {r7, lr} + 800212a: b082 sub sp, #8 + 800212c: af00 add r7, sp, #0 + 800212e: 6078 str r0, [r7, #4] + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + 8002130: 46c0 nop ; (mov r8, r8) + 8002132: 46bd mov sp, r7 + 8002134: b002 add sp, #8 + 8002136: bd80 pop {r7, pc} + +08002138 : + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + 8002138: b590 push {r4, r7, lr} + 800213a: b089 sub sp, #36 ; 0x24 + 800213c: af02 add r7, sp, #8 + 800213e: 60f8 str r0, [r7, #12] + 8002140: 60b9 str r1, [r7, #8] + 8002142: 607a str r2, [r7, #4] + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + 8002144: 68bb ldr r3, [r7, #8] + 8002146: 617b str r3, [r7, #20] + + /* Process Locked */ + __HAL_LOCK(hi2c); + 8002148: 68fb ldr r3, [r7, #12] + 800214a: 2240 movs r2, #64 ; 0x40 + 800214c: 5c9b ldrb r3, [r3, r2] + 800214e: 2b01 cmp r3, #1 + 8002150: d101 bne.n 8002156 + 8002152: 2302 movs r3, #2 + 8002154: e11d b.n 8002392 + 8002156: 68fb ldr r3, [r7, #12] + 8002158: 2240 movs r2, #64 ; 0x40 + 800215a: 2101 movs r1, #1 + 800215c: 5499 strb r1, [r3, r2] + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 800215e: 697b ldr r3, [r7, #20] + 8002160: 2210 movs r2, #16 + 8002162: 4013 ands r3, r2 + 8002164: d012 beq.n 800218c + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 8002166: 687b ldr r3, [r7, #4] + 8002168: 2210 movs r2, #16 + 800216a: 4013 ands r3, r2 + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 800216c: d00e beq.n 800218c + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 800216e: 68fb ldr r3, [r7, #12] + 8002170: 681b ldr r3, [r3, #0] + 8002172: 2210 movs r2, #16 + 8002174: 61da str r2, [r3, #28] + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 8002176: 68fb ldr r3, [r7, #12] + 8002178: 6c5b ldr r3, [r3, #68] ; 0x44 + 800217a: 2204 movs r2, #4 + 800217c: 431a orrs r2, r3 + 800217e: 68fb ldr r3, [r7, #12] + 8002180: 645a str r2, [r3, #68] ; 0x44 + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 8002182: 68fb ldr r3, [r7, #12] + 8002184: 0018 movs r0, r3 + 8002186: f001 fa3e bl 8003606 + 800218a: e0ef b.n 800236c + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + 800218c: 697b ldr r3, [r7, #20] + 800218e: 2204 movs r2, #4 + 8002190: 4013 ands r3, r2 + 8002192: d021 beq.n 80021d8 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 8002194: 687b ldr r3, [r7, #4] + 8002196: 2204 movs r2, #4 + 8002198: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + 800219a: d01d beq.n 80021d8 + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + 800219c: 697b ldr r3, [r7, #20] + 800219e: 2204 movs r2, #4 + 80021a0: 4393 bics r3, r2 + 80021a2: 617b str r3, [r7, #20] + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 80021a4: 68fb ldr r3, [r7, #12] + 80021a6: 681b ldr r3, [r3, #0] + 80021a8: 6a5a ldr r2, [r3, #36] ; 0x24 + 80021aa: 68fb ldr r3, [r7, #12] + 80021ac: 6a5b ldr r3, [r3, #36] ; 0x24 + 80021ae: b2d2 uxtb r2, r2 + 80021b0: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 80021b2: 68fb ldr r3, [r7, #12] + 80021b4: 6a5b ldr r3, [r3, #36] ; 0x24 + 80021b6: 1c5a adds r2, r3, #1 + 80021b8: 68fb ldr r3, [r7, #12] + 80021ba: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferSize--; + 80021bc: 68fb ldr r3, [r7, #12] + 80021be: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80021c0: 3b01 subs r3, #1 + 80021c2: b29a uxth r2, r3 + 80021c4: 68fb ldr r3, [r7, #12] + 80021c6: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 80021c8: 68fb ldr r3, [r7, #12] + 80021ca: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80021cc: b29b uxth r3, r3 + 80021ce: 3b01 subs r3, #1 + 80021d0: b29a uxth r2, r3 + 80021d2: 68fb ldr r3, [r7, #12] + 80021d4: 855a strh r2, [r3, #42] ; 0x2a + 80021d6: e0c9 b.n 800236c + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ + 80021d8: 697b ldr r3, [r7, #20] + 80021da: 2240 movs r2, #64 ; 0x40 + 80021dc: 4013 ands r3, r2 + 80021de: d126 bne.n 800222e + ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 80021e0: 697b ldr r3, [r7, #20] + 80021e2: 2202 movs r2, #2 + 80021e4: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ + 80021e6: d022 beq.n 800222e + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) + 80021e8: 687b ldr r3, [r7, #4] + 80021ea: 2202 movs r2, #2 + 80021ec: 4013 ands r3, r2 + ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 80021ee: d01e beq.n 800222e + { + /* Write data to TXDR */ + if (hi2c->XferCount != 0U) + 80021f0: 68fb ldr r3, [r7, #12] + 80021f2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80021f4: b29b uxth r3, r3 + 80021f6: 2b00 cmp r3, #0 + 80021f8: d100 bne.n 80021fc + 80021fa: e0b7 b.n 800236c + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 80021fc: 68fb ldr r3, [r7, #12] + 80021fe: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002200: 781a ldrb r2, [r3, #0] + 8002202: 68fb ldr r3, [r7, #12] + 8002204: 681b ldr r3, [r3, #0] + 8002206: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8002208: 68fb ldr r3, [r7, #12] + 800220a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800220c: 1c5a adds r2, r3, #1 + 800220e: 68fb ldr r3, [r7, #12] + 8002210: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferSize--; + 8002212: 68fb ldr r3, [r7, #12] + 8002214: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002216: 3b01 subs r3, #1 + 8002218: b29a uxth r2, r3 + 800221a: 68fb ldr r3, [r7, #12] + 800221c: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 800221e: 68fb ldr r3, [r7, #12] + 8002220: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002222: b29b uxth r3, r3 + 8002224: 3b01 subs r3, #1 + 8002226: b29a uxth r2, r3 + 8002228: 68fb ldr r3, [r7, #12] + 800222a: 855a strh r2, [r3, #42] ; 0x2a + if (hi2c->XferCount != 0U) + 800222c: e09e b.n 800236c + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + 800222e: 697b ldr r3, [r7, #20] + 8002230: 2280 movs r2, #128 ; 0x80 + 8002232: 4013 ands r3, r2 + 8002234: d100 bne.n 8002238 + 8002236: e069 b.n 800230c + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 8002238: 687b ldr r3, [r7, #4] + 800223a: 2240 movs r2, #64 ; 0x40 + 800223c: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + 800223e: d065 beq.n 800230c + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8002240: 68fb ldr r3, [r7, #12] + 8002242: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002244: b29b uxth r3, r3 + 8002246: 2b00 cmp r3, #0 + 8002248: d04a beq.n 80022e0 + 800224a: 68fb ldr r3, [r7, #12] + 800224c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800224e: 2b00 cmp r3, #0 + 8002250: d146 bne.n 80022e0 + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + 8002252: 68fb ldr r3, [r7, #12] + 8002254: 681b ldr r3, [r3, #0] + 8002256: 685b ldr r3, [r3, #4] + 8002258: b29a uxth r2, r3 + 800225a: 2112 movs r1, #18 + 800225c: 187b adds r3, r7, r1 + 800225e: 0592 lsls r2, r2, #22 + 8002260: 0d92 lsrs r2, r2, #22 + 8002262: 801a strh r2, [r3, #0] + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8002264: 68fb ldr r3, [r7, #12] + 8002266: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002268: b29b uxth r3, r3 + 800226a: 2bff cmp r3, #255 ; 0xff + 800226c: d910 bls.n 8002290 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 800226e: 68fb ldr r3, [r7, #12] + 8002270: 22ff movs r2, #255 ; 0xff + 8002272: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 8002274: 68fb ldr r3, [r7, #12] + 8002276: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002278: b2da uxtb r2, r3 + 800227a: 2380 movs r3, #128 ; 0x80 + 800227c: 045c lsls r4, r3, #17 + 800227e: 187b adds r3, r7, r1 + 8002280: 8819 ldrh r1, [r3, #0] + 8002282: 68f8 ldr r0, [r7, #12] + 8002284: 2300 movs r3, #0 + 8002286: 9300 str r3, [sp, #0] + 8002288: 0023 movs r3, r4 + 800228a: f001 fd37 bl 8003cfc + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 800228e: e03c b.n 800230a + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8002290: 68fb ldr r3, [r7, #12] + 8002292: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002294: b29a uxth r2, r3 + 8002296: 68fb ldr r3, [r7, #12] + 8002298: 851a strh r2, [r3, #40] ; 0x28 + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 800229a: 68fb ldr r3, [r7, #12] + 800229c: 6adb ldr r3, [r3, #44] ; 0x2c + 800229e: 4a3f ldr r2, [pc, #252] ; (800239c ) + 80022a0: 4293 cmp r3, r2 + 80022a2: d00e beq.n 80022c2 + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + 80022a4: 68fb ldr r3, [r7, #12] + 80022a6: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80022a8: b2da uxtb r2, r3 + hi2c->XferOptions, I2C_NO_STARTSTOP); + 80022aa: 68fb ldr r3, [r7, #12] + 80022ac: 6adc ldr r4, [r3, #44] ; 0x2c + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + 80022ae: 2312 movs r3, #18 + 80022b0: 18fb adds r3, r7, r3 + 80022b2: 8819 ldrh r1, [r3, #0] + 80022b4: 68f8 ldr r0, [r7, #12] + 80022b6: 2300 movs r3, #0 + 80022b8: 9300 str r3, [sp, #0] + 80022ba: 0023 movs r3, r4 + 80022bc: f001 fd1e bl 8003cfc + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 80022c0: e023 b.n 800230a + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + 80022c2: 68fb ldr r3, [r7, #12] + 80022c4: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80022c6: b2da uxtb r2, r3 + 80022c8: 2380 movs r3, #128 ; 0x80 + 80022ca: 049c lsls r4, r3, #18 + 80022cc: 2312 movs r3, #18 + 80022ce: 18fb adds r3, r7, r3 + 80022d0: 8819 ldrh r1, [r3, #0] + 80022d2: 68f8 ldr r0, [r7, #12] + 80022d4: 2300 movs r3, #0 + 80022d6: 9300 str r3, [sp, #0] + 80022d8: 0023 movs r3, r4 + 80022da: f001 fd0f bl 8003cfc + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 80022de: e014 b.n 800230a + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 80022e0: 68fb ldr r3, [r7, #12] + 80022e2: 681b ldr r3, [r3, #0] + 80022e4: 685a ldr r2, [r3, #4] + 80022e6: 2380 movs r3, #128 ; 0x80 + 80022e8: 049b lsls r3, r3, #18 + 80022ea: 401a ands r2, r3 + 80022ec: 2380 movs r3, #128 ; 0x80 + 80022ee: 049b lsls r3, r3, #18 + 80022f0: 429a cmp r2, r3 + 80022f2: d004 beq.n 80022fe + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + 80022f4: 68fb ldr r3, [r7, #12] + 80022f6: 0018 movs r0, r3 + 80022f8: f000 fd06 bl 8002d08 + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 80022fc: e036 b.n 800236c + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 80022fe: 68fb ldr r3, [r7, #12] + 8002300: 2140 movs r1, #64 ; 0x40 + 8002302: 0018 movs r0, r3 + 8002304: f001 f854 bl 80033b0 + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8002308: e030 b.n 800236c + 800230a: e02f b.n 800236c + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + 800230c: 697b ldr r3, [r7, #20] + 800230e: 2240 movs r2, #64 ; 0x40 + 8002310: 4013 ands r3, r2 + 8002312: d02b beq.n 800236c + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 8002314: 687b ldr r3, [r7, #4] + 8002316: 2240 movs r2, #64 ; 0x40 + 8002318: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + 800231a: d027 beq.n 800236c + { + if (hi2c->XferCount == 0U) + 800231c: 68fb ldr r3, [r7, #12] + 800231e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002320: b29b uxth r3, r3 + 8002322: 2b00 cmp r3, #0 + 8002324: d11d bne.n 8002362 + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 8002326: 68fb ldr r3, [r7, #12] + 8002328: 681b ldr r3, [r3, #0] + 800232a: 685a ldr r2, [r3, #4] + 800232c: 2380 movs r3, #128 ; 0x80 + 800232e: 049b lsls r3, r3, #18 + 8002330: 401a ands r2, r3 + 8002332: 2380 movs r3, #128 ; 0x80 + 8002334: 049b lsls r3, r3, #18 + 8002336: 429a cmp r2, r3 + 8002338: d018 beq.n 800236c + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + 800233a: 68fb ldr r3, [r7, #12] + 800233c: 6adb ldr r3, [r3, #44] ; 0x2c + 800233e: 4a17 ldr r2, [pc, #92] ; (800239c ) + 8002340: 4293 cmp r3, r2 + 8002342: d109 bne.n 8002358 + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + 8002344: 68fb ldr r3, [r7, #12] + 8002346: 681b ldr r3, [r3, #0] + 8002348: 685a ldr r2, [r3, #4] + 800234a: 68fb ldr r3, [r7, #12] + 800234c: 681b ldr r3, [r3, #0] + 800234e: 2180 movs r1, #128 ; 0x80 + 8002350: 01c9 lsls r1, r1, #7 + 8002352: 430a orrs r2, r1 + 8002354: 605a str r2, [r3, #4] + 8002356: e009 b.n 800236c + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + 8002358: 68fb ldr r3, [r7, #12] + 800235a: 0018 movs r0, r3 + 800235c: f000 fcd4 bl 8002d08 + 8002360: e004 b.n 800236c + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 8002362: 68fb ldr r3, [r7, #12] + 8002364: 2140 movs r1, #64 ; 0x40 + 8002366: 0018 movs r0, r3 + 8002368: f001 f822 bl 80033b0 + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + 800236c: 697b ldr r3, [r7, #20] + 800236e: 2220 movs r2, #32 + 8002370: 4013 ands r3, r2 + 8002372: d009 beq.n 8002388 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 8002374: 687b ldr r3, [r7, #4] + 8002376: 2220 movs r2, #32 + 8002378: 4013 ands r3, r2 + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + 800237a: d005 beq.n 8002388 + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + 800237c: 697a ldr r2, [r7, #20] + 800237e: 68fb ldr r3, [r7, #12] + 8002380: 0011 movs r1, r2 + 8002382: 0018 movs r0, r3 + 8002384: f000 fd66 bl 8002e54 + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8002388: 68fb ldr r3, [r7, #12] + 800238a: 2240 movs r2, #64 ; 0x40 + 800238c: 2100 movs r1, #0 + 800238e: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8002390: 2300 movs r3, #0 +} + 8002392: 0018 movs r0, r3 + 8002394: 46bd mov sp, r7 + 8002396: b007 add sp, #28 + 8002398: bd90 pop {r4, r7, pc} + 800239a: 46c0 nop ; (mov r8, r8) + 800239c: ffff0000 .word 0xffff0000 + +080023a0 : + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + 80023a0: b580 push {r7, lr} + 80023a2: b086 sub sp, #24 + 80023a4: af00 add r7, sp, #0 + 80023a6: 60f8 str r0, [r7, #12] + 80023a8: 60b9 str r1, [r7, #8] + 80023aa: 607a str r2, [r7, #4] + uint32_t tmpoptions = hi2c->XferOptions; + 80023ac: 68fb ldr r3, [r7, #12] + 80023ae: 6adb ldr r3, [r3, #44] ; 0x2c + 80023b0: 617b str r3, [r7, #20] + uint32_t tmpITFlags = ITFlags; + 80023b2: 68bb ldr r3, [r7, #8] + 80023b4: 613b str r3, [r7, #16] + + /* Process locked */ + __HAL_LOCK(hi2c); + 80023b6: 68fb ldr r3, [r7, #12] + 80023b8: 2240 movs r2, #64 ; 0x40 + 80023ba: 5c9b ldrb r3, [r3, r2] + 80023bc: 2b01 cmp r3, #1 + 80023be: d101 bne.n 80023c4 + 80023c0: 2302 movs r3, #2 + 80023c2: e0e7 b.n 8002594 + 80023c4: 68fb ldr r3, [r7, #12] + 80023c6: 2240 movs r2, #64 ; 0x40 + 80023c8: 2101 movs r1, #1 + 80023ca: 5499 strb r1, [r3, r2] + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + 80023cc: 693b ldr r3, [r7, #16] + 80023ce: 2220 movs r2, #32 + 80023d0: 4013 ands r3, r2 + 80023d2: d00a beq.n 80023ea + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 80023d4: 687b ldr r3, [r7, #4] + 80023d6: 2220 movs r2, #32 + 80023d8: 4013 ands r3, r2 + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + 80023da: d006 beq.n 80023ea + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + 80023dc: 693a ldr r2, [r7, #16] + 80023de: 68fb ldr r3, [r7, #12] + 80023e0: 0011 movs r1, r2 + 80023e2: 0018 movs r0, r3 + 80023e4: f000 fe04 bl 8002ff0 + 80023e8: e0cf b.n 800258a + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 80023ea: 693b ldr r3, [r7, #16] + 80023ec: 2210 movs r2, #16 + 80023ee: 4013 ands r3, r2 + 80023f0: d052 beq.n 8002498 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 80023f2: 687b ldr r3, [r7, #4] + 80023f4: 2210 movs r2, #16 + 80023f6: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 80023f8: d04e beq.n 8002498 + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + 80023fa: 68fb ldr r3, [r7, #12] + 80023fc: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80023fe: b29b uxth r3, r3 + 8002400: 2b00 cmp r3, #0 + 8002402: d12d bne.n 8002460 + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + 8002404: 68fb ldr r3, [r7, #12] + 8002406: 2241 movs r2, #65 ; 0x41 + 8002408: 5c9b ldrb r3, [r3, r2] + 800240a: b2db uxtb r3, r3 + 800240c: 2b28 cmp r3, #40 ; 0x28 + 800240e: d10b bne.n 8002428 + 8002410: 697a ldr r2, [r7, #20] + 8002412: 2380 movs r3, #128 ; 0x80 + 8002414: 049b lsls r3, r3, #18 + 8002416: 429a cmp r2, r3 + 8002418: d106 bne.n 8002428 + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + 800241a: 693a ldr r2, [r7, #16] + 800241c: 68fb ldr r3, [r7, #12] + 800241e: 0011 movs r1, r2 + 8002420: 0018 movs r0, r3 + 8002422: f000 ff6d bl 8003300 + 8002426: e036 b.n 8002496 + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + 8002428: 68fb ldr r3, [r7, #12] + 800242a: 2241 movs r2, #65 ; 0x41 + 800242c: 5c9b ldrb r3, [r3, r2] + 800242e: b2db uxtb r3, r3 + 8002430: 2b29 cmp r3, #41 ; 0x29 + 8002432: d110 bne.n 8002456 + 8002434: 697b ldr r3, [r7, #20] + 8002436: 4a59 ldr r2, [pc, #356] ; (800259c ) + 8002438: 4293 cmp r3, r2 + 800243a: d00c beq.n 8002456 + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 800243c: 68fb ldr r3, [r7, #12] + 800243e: 681b ldr r3, [r3, #0] + 8002440: 2210 movs r2, #16 + 8002442: 61da str r2, [r3, #28] + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 8002444: 68fb ldr r3, [r7, #12] + 8002446: 0018 movs r0, r3 + 8002448: f001 f8dd bl 8003606 + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + 800244c: 68fb ldr r3, [r7, #12] + 800244e: 0018 movs r0, r3 + 8002450: f000 fc9c bl 8002d8c + 8002454: e01f b.n 8002496 + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8002456: 68fb ldr r3, [r7, #12] + 8002458: 681b ldr r3, [r3, #0] + 800245a: 2210 movs r2, #16 + 800245c: 61da str r2, [r3, #28] + if (hi2c->XferCount == 0U) + 800245e: e091 b.n 8002584 + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8002460: 68fb ldr r3, [r7, #12] + 8002462: 681b ldr r3, [r3, #0] + 8002464: 2210 movs r2, #16 + 8002466: 61da str r2, [r3, #28] + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 8002468: 68fb ldr r3, [r7, #12] + 800246a: 6c5b ldr r3, [r3, #68] ; 0x44 + 800246c: 2204 movs r2, #4 + 800246e: 431a orrs r2, r3 + 8002470: 68fb ldr r3, [r7, #12] + 8002472: 645a str r2, [r3, #68] ; 0x44 + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + 8002474: 697b ldr r3, [r7, #20] + 8002476: 2b00 cmp r3, #0 + 8002478: d005 beq.n 8002486 + 800247a: 697a ldr r2, [r7, #20] + 800247c: 2380 movs r3, #128 ; 0x80 + 800247e: 045b lsls r3, r3, #17 + 8002480: 429a cmp r2, r3 + 8002482: d000 beq.n 8002486 + 8002484: e07e b.n 8002584 + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + 8002486: 68fb ldr r3, [r7, #12] + 8002488: 6c5a ldr r2, [r3, #68] ; 0x44 + 800248a: 68fb ldr r3, [r7, #12] + 800248c: 0011 movs r1, r2 + 800248e: 0018 movs r0, r3 + 8002490: f000 ff8e bl 80033b0 + if (hi2c->XferCount == 0U) + 8002494: e076 b.n 8002584 + 8002496: e075 b.n 8002584 + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + 8002498: 693b ldr r3, [r7, #16] + 800249a: 2204 movs r2, #4 + 800249c: 4013 ands r3, r2 + 800249e: d02f beq.n 8002500 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 80024a0: 687b ldr r3, [r7, #4] + 80024a2: 2204 movs r2, #4 + 80024a4: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + 80024a6: d02b beq.n 8002500 + { + if (hi2c->XferCount > 0U) + 80024a8: 68fb ldr r3, [r7, #12] + 80024aa: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80024ac: b29b uxth r3, r3 + 80024ae: 2b00 cmp r3, #0 + 80024b0: d018 beq.n 80024e4 + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 80024b2: 68fb ldr r3, [r7, #12] + 80024b4: 681b ldr r3, [r3, #0] + 80024b6: 6a5a ldr r2, [r3, #36] ; 0x24 + 80024b8: 68fb ldr r3, [r7, #12] + 80024ba: 6a5b ldr r3, [r3, #36] ; 0x24 + 80024bc: b2d2 uxtb r2, r2 + 80024be: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 80024c0: 68fb ldr r3, [r7, #12] + 80024c2: 6a5b ldr r3, [r3, #36] ; 0x24 + 80024c4: 1c5a adds r2, r3, #1 + 80024c6: 68fb ldr r3, [r7, #12] + 80024c8: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferSize--; + 80024ca: 68fb ldr r3, [r7, #12] + 80024cc: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80024ce: 3b01 subs r3, #1 + 80024d0: b29a uxth r2, r3 + 80024d2: 68fb ldr r3, [r7, #12] + 80024d4: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 80024d6: 68fb ldr r3, [r7, #12] + 80024d8: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80024da: b29b uxth r3, r3 + 80024dc: 3b01 subs r3, #1 + 80024de: b29a uxth r2, r3 + 80024e0: 68fb ldr r3, [r7, #12] + 80024e2: 855a strh r2, [r3, #42] ; 0x2a + } + + if ((hi2c->XferCount == 0U) && \ + 80024e4: 68fb ldr r3, [r7, #12] + 80024e6: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80024e8: b29b uxth r3, r3 + 80024ea: 2b00 cmp r3, #0 + 80024ec: d14c bne.n 8002588 + 80024ee: 697b ldr r3, [r7, #20] + 80024f0: 4a2a ldr r2, [pc, #168] ; (800259c ) + 80024f2: 4293 cmp r3, r2 + 80024f4: d048 beq.n 8002588 + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + 80024f6: 68fb ldr r3, [r7, #12] + 80024f8: 0018 movs r0, r3 + 80024fa: f000 fc47 bl 8002d8c + if ((hi2c->XferCount == 0U) && \ + 80024fe: e043 b.n 8002588 + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + 8002500: 693b ldr r3, [r7, #16] + 8002502: 2208 movs r2, #8 + 8002504: 4013 ands r3, r2 + 8002506: d00a beq.n 800251e + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 8002508: 687b ldr r3, [r7, #4] + 800250a: 2208 movs r2, #8 + 800250c: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + 800250e: d006 beq.n 800251e + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + 8002510: 693a ldr r2, [r7, #16] + 8002512: 68fb ldr r3, [r7, #12] + 8002514: 0011 movs r1, r2 + 8002516: 0018 movs r0, r3 + 8002518: f000 fb52 bl 8002bc0 + 800251c: e035 b.n 800258a + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 800251e: 693b ldr r3, [r7, #16] + 8002520: 2202 movs r2, #2 + 8002522: 4013 ands r3, r2 + 8002524: d031 beq.n 800258a + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 8002526: 687b ldr r3, [r7, #4] + 8002528: 2202 movs r2, #2 + 800252a: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 800252c: d02d beq.n 800258a + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + 800252e: 68fb ldr r3, [r7, #12] + 8002530: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002532: b29b uxth r3, r3 + 8002534: 2b00 cmp r3, #0 + 8002536: d018 beq.n 800256a + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 8002538: 68fb ldr r3, [r7, #12] + 800253a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800253c: 781a ldrb r2, [r3, #0] + 800253e: 68fb ldr r3, [r7, #12] + 8002540: 681b ldr r3, [r3, #0] + 8002542: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8002544: 68fb ldr r3, [r7, #12] + 8002546: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002548: 1c5a adds r2, r3, #1 + 800254a: 68fb ldr r3, [r7, #12] + 800254c: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferCount--; + 800254e: 68fb ldr r3, [r7, #12] + 8002550: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002552: b29b uxth r3, r3 + 8002554: 3b01 subs r3, #1 + 8002556: b29a uxth r2, r3 + 8002558: 68fb ldr r3, [r7, #12] + 800255a: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 800255c: 68fb ldr r3, [r7, #12] + 800255e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002560: 3b01 subs r3, #1 + 8002562: b29a uxth r2, r3 + 8002564: 68fb ldr r3, [r7, #12] + 8002566: 851a strh r2, [r3, #40] ; 0x28 + 8002568: e00f b.n 800258a + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + 800256a: 697a ldr r2, [r7, #20] + 800256c: 2380 movs r3, #128 ; 0x80 + 800256e: 045b lsls r3, r3, #17 + 8002570: 429a cmp r2, r3 + 8002572: d002 beq.n 800257a + 8002574: 697b ldr r3, [r7, #20] + 8002576: 2b00 cmp r3, #0 + 8002578: d107 bne.n 800258a + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + 800257a: 68fb ldr r3, [r7, #12] + 800257c: 0018 movs r0, r3 + 800257e: f000 fc05 bl 8002d8c + 8002582: e002 b.n 800258a + if (hi2c->XferCount == 0U) + 8002584: 46c0 nop ; (mov r8, r8) + 8002586: e000 b.n 800258a + if ((hi2c->XferCount == 0U) && \ + 8002588: 46c0 nop ; (mov r8, r8) + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800258a: 68fb ldr r3, [r7, #12] + 800258c: 2240 movs r2, #64 ; 0x40 + 800258e: 2100 movs r1, #0 + 8002590: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8002592: 2300 movs r3, #0 +} + 8002594: 0018 movs r0, r3 + 8002596: 46bd mov sp, r7 + 8002598: b006 add sp, #24 + 800259a: bd80 pop {r7, pc} + 800259c: ffff0000 .word 0xffff0000 + +080025a0 : + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + 80025a0: b590 push {r4, r7, lr} + 80025a2: b089 sub sp, #36 ; 0x24 + 80025a4: af02 add r7, sp, #8 + 80025a6: 60f8 str r0, [r7, #12] + 80025a8: 60b9 str r1, [r7, #8] + 80025aa: 607a str r2, [r7, #4] + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + 80025ac: 68fb ldr r3, [r7, #12] + 80025ae: 2240 movs r2, #64 ; 0x40 + 80025b0: 5c9b ldrb r3, [r3, r2] + 80025b2: 2b01 cmp r3, #1 + 80025b4: d101 bne.n 80025ba + 80025b6: 2302 movs r3, #2 + 80025b8: e0e7 b.n 800278a + 80025ba: 68fb ldr r3, [r7, #12] + 80025bc: 2240 movs r2, #64 ; 0x40 + 80025be: 2101 movs r1, #1 + 80025c0: 5499 strb r1, [r3, r2] + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 80025c2: 68bb ldr r3, [r7, #8] + 80025c4: 2210 movs r2, #16 + 80025c6: 4013 ands r3, r2 + 80025c8: d017 beq.n 80025fa + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 80025ca: 687b ldr r3, [r7, #4] + 80025cc: 2210 movs r2, #16 + 80025ce: 4013 ands r3, r2 + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 80025d0: d013 beq.n 80025fa + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 80025d2: 68fb ldr r3, [r7, #12] + 80025d4: 681b ldr r3, [r3, #0] + 80025d6: 2210 movs r2, #16 + 80025d8: 61da str r2, [r3, #28] + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 80025da: 68fb ldr r3, [r7, #12] + 80025dc: 6c5b ldr r3, [r3, #68] ; 0x44 + 80025de: 2204 movs r2, #4 + 80025e0: 431a orrs r2, r3 + 80025e2: 68fb ldr r3, [r7, #12] + 80025e4: 645a str r2, [r3, #68] ; 0x44 + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 80025e6: 68fb ldr r3, [r7, #12] + 80025e8: 2120 movs r1, #32 + 80025ea: 0018 movs r0, r3 + 80025ec: f001 fbc0 bl 8003d70 + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 80025f0: 68fb ldr r3, [r7, #12] + 80025f2: 0018 movs r0, r3 + 80025f4: f001 f807 bl 8003606 + 80025f8: e0c2 b.n 8002780 + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + 80025fa: 68bb ldr r3, [r7, #8] + 80025fc: 2280 movs r2, #128 ; 0x80 + 80025fe: 4013 ands r3, r2 + 8002600: d100 bne.n 8002604 + 8002602: e07c b.n 80026fe + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 8002604: 687b ldr r3, [r7, #4] + 8002606: 2240 movs r2, #64 ; 0x40 + 8002608: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + 800260a: d100 bne.n 800260e + 800260c: e077 b.n 80026fe + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + 800260e: 68fb ldr r3, [r7, #12] + 8002610: 681b ldr r3, [r3, #0] + 8002612: 681a ldr r2, [r3, #0] + 8002614: 68fb ldr r3, [r7, #12] + 8002616: 681b ldr r3, [r3, #0] + 8002618: 2140 movs r1, #64 ; 0x40 + 800261a: 438a bics r2, r1 + 800261c: 601a str r2, [r3, #0] + + if (hi2c->XferCount != 0U) + 800261e: 68fb ldr r3, [r7, #12] + 8002620: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002622: b29b uxth r3, r3 + 8002624: 2b00 cmp r3, #0 + 8002626: d055 beq.n 80026d4 + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + 8002628: 68fb ldr r3, [r7, #12] + 800262a: 681b ldr r3, [r3, #0] + 800262c: 685b ldr r3, [r3, #4] + 800262e: b29a uxth r2, r3 + 8002630: 2312 movs r3, #18 + 8002632: 18fb adds r3, r7, r3 + 8002634: 0592 lsls r2, r2, #22 + 8002636: 0d92 lsrs r2, r2, #22 + 8002638: 801a strh r2, [r3, #0] + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 800263a: 68fb ldr r3, [r7, #12] + 800263c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800263e: b29b uxth r3, r3 + 8002640: 2bff cmp r3, #255 ; 0xff + 8002642: d906 bls.n 8002652 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8002644: 68fb ldr r3, [r7, #12] + 8002646: 22ff movs r2, #255 ; 0xff + 8002648: 851a strh r2, [r3, #40] ; 0x28 + xfermode = I2C_RELOAD_MODE; + 800264a: 2380 movs r3, #128 ; 0x80 + 800264c: 045b lsls r3, r3, #17 + 800264e: 617b str r3, [r7, #20] + 8002650: e010 b.n 8002674 + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8002652: 68fb ldr r3, [r7, #12] + 8002654: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002656: b29a uxth r2, r3 + 8002658: 68fb ldr r3, [r7, #12] + 800265a: 851a strh r2, [r3, #40] ; 0x28 + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 800265c: 68fb ldr r3, [r7, #12] + 800265e: 6adb ldr r3, [r3, #44] ; 0x2c + 8002660: 4a4c ldr r2, [pc, #304] ; (8002794 ) + 8002662: 4293 cmp r3, r2 + 8002664: d003 beq.n 800266e + { + xfermode = hi2c->XferOptions; + 8002666: 68fb ldr r3, [r7, #12] + 8002668: 6adb ldr r3, [r3, #44] ; 0x2c + 800266a: 617b str r3, [r7, #20] + 800266c: e002 b.n 8002674 + } + else + { + xfermode = I2C_AUTOEND_MODE; + 800266e: 2380 movs r3, #128 ; 0x80 + 8002670: 049b lsls r3, r3, #18 + 8002672: 617b str r3, [r7, #20] + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + 8002674: 68fb ldr r3, [r7, #12] + 8002676: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002678: b2da uxtb r2, r3 + 800267a: 697c ldr r4, [r7, #20] + 800267c: 2312 movs r3, #18 + 800267e: 18fb adds r3, r7, r3 + 8002680: 8819 ldrh r1, [r3, #0] + 8002682: 68f8 ldr r0, [r7, #12] + 8002684: 2300 movs r3, #0 + 8002686: 9300 str r3, [sp, #0] + 8002688: 0023 movs r3, r4 + 800268a: f001 fb37 bl 8003cfc + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + 800268e: 68fb ldr r3, [r7, #12] + 8002690: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002692: b29a uxth r2, r3 + 8002694: 68fb ldr r3, [r7, #12] + 8002696: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002698: 1ad3 subs r3, r2, r3 + 800269a: b29a uxth r2, r3 + 800269c: 68fb ldr r3, [r7, #12] + 800269e: 855a strh r2, [r3, #42] ; 0x2a + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 80026a0: 68fb ldr r3, [r7, #12] + 80026a2: 2241 movs r2, #65 ; 0x41 + 80026a4: 5c9b ldrb r3, [r3, r2] + 80026a6: b2db uxtb r3, r3 + 80026a8: 2b22 cmp r3, #34 ; 0x22 + 80026aa: d109 bne.n 80026c0 + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 80026ac: 68fb ldr r3, [r7, #12] + 80026ae: 681b ldr r3, [r3, #0] + 80026b0: 681a ldr r2, [r3, #0] + 80026b2: 68fb ldr r3, [r7, #12] + 80026b4: 681b ldr r3, [r3, #0] + 80026b6: 2180 movs r1, #128 ; 0x80 + 80026b8: 0209 lsls r1, r1, #8 + 80026ba: 430a orrs r2, r1 + 80026bc: 601a str r2, [r3, #0] + if (hi2c->XferCount != 0U) + 80026be: e05f b.n 8002780 + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 80026c0: 68fb ldr r3, [r7, #12] + 80026c2: 681b ldr r3, [r3, #0] + 80026c4: 681a ldr r2, [r3, #0] + 80026c6: 68fb ldr r3, [r7, #12] + 80026c8: 681b ldr r3, [r3, #0] + 80026ca: 2180 movs r1, #128 ; 0x80 + 80026cc: 01c9 lsls r1, r1, #7 + 80026ce: 430a orrs r2, r1 + 80026d0: 601a str r2, [r3, #0] + if (hi2c->XferCount != 0U) + 80026d2: e055 b.n 8002780 + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 80026d4: 68fb ldr r3, [r7, #12] + 80026d6: 681b ldr r3, [r3, #0] + 80026d8: 685a ldr r2, [r3, #4] + 80026da: 2380 movs r3, #128 ; 0x80 + 80026dc: 049b lsls r3, r3, #18 + 80026de: 401a ands r2, r3 + 80026e0: 2380 movs r3, #128 ; 0x80 + 80026e2: 049b lsls r3, r3, #18 + 80026e4: 429a cmp r2, r3 + 80026e6: d004 beq.n 80026f2 + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + 80026e8: 68fb ldr r3, [r7, #12] + 80026ea: 0018 movs r0, r3 + 80026ec: f000 fb0c bl 8002d08 + if (hi2c->XferCount != 0U) + 80026f0: e046 b.n 8002780 + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 80026f2: 68fb ldr r3, [r7, #12] + 80026f4: 2140 movs r1, #64 ; 0x40 + 80026f6: 0018 movs r0, r3 + 80026f8: f000 fe5a bl 80033b0 + if (hi2c->XferCount != 0U) + 80026fc: e040 b.n 8002780 + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + 80026fe: 68bb ldr r3, [r7, #8] + 8002700: 2240 movs r2, #64 ; 0x40 + 8002702: 4013 ands r3, r2 + 8002704: d02c beq.n 8002760 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 8002706: 687b ldr r3, [r7, #4] + 8002708: 2240 movs r2, #64 ; 0x40 + 800270a: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + 800270c: d028 beq.n 8002760 + { + if (hi2c->XferCount == 0U) + 800270e: 68fb ldr r3, [r7, #12] + 8002710: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002712: b29b uxth r3, r3 + 8002714: 2b00 cmp r3, #0 + 8002716: d11d bne.n 8002754 + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 8002718: 68fb ldr r3, [r7, #12] + 800271a: 681b ldr r3, [r3, #0] + 800271c: 685a ldr r2, [r3, #4] + 800271e: 2380 movs r3, #128 ; 0x80 + 8002720: 049b lsls r3, r3, #18 + 8002722: 401a ands r2, r3 + 8002724: 2380 movs r3, #128 ; 0x80 + 8002726: 049b lsls r3, r3, #18 + 8002728: 429a cmp r2, r3 + 800272a: d028 beq.n 800277e + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + 800272c: 68fb ldr r3, [r7, #12] + 800272e: 6adb ldr r3, [r3, #44] ; 0x2c + 8002730: 4a18 ldr r2, [pc, #96] ; (8002794 ) + 8002732: 4293 cmp r3, r2 + 8002734: d109 bne.n 800274a + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + 8002736: 68fb ldr r3, [r7, #12] + 8002738: 681b ldr r3, [r3, #0] + 800273a: 685a ldr r2, [r3, #4] + 800273c: 68fb ldr r3, [r7, #12] + 800273e: 681b ldr r3, [r3, #0] + 8002740: 2180 movs r1, #128 ; 0x80 + 8002742: 01c9 lsls r1, r1, #7 + 8002744: 430a orrs r2, r1 + 8002746: 605a str r2, [r3, #4] + if (hi2c->XferCount == 0U) + 8002748: e019 b.n 800277e + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + 800274a: 68fb ldr r3, [r7, #12] + 800274c: 0018 movs r0, r3 + 800274e: f000 fadb bl 8002d08 + if (hi2c->XferCount == 0U) + 8002752: e014 b.n 800277e + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 8002754: 68fb ldr r3, [r7, #12] + 8002756: 2140 movs r1, #64 ; 0x40 + 8002758: 0018 movs r0, r3 + 800275a: f000 fe29 bl 80033b0 + if (hi2c->XferCount == 0U) + 800275e: e00e b.n 800277e + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 8002760: 68bb ldr r3, [r7, #8] + 8002762: 2220 movs r2, #32 + 8002764: 4013 ands r3, r2 + 8002766: d00b beq.n 8002780 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 8002768: 687b ldr r3, [r7, #4] + 800276a: 2220 movs r2, #32 + 800276c: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 800276e: d007 beq.n 8002780 + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + 8002770: 68ba ldr r2, [r7, #8] + 8002772: 68fb ldr r3, [r7, #12] + 8002774: 0011 movs r1, r2 + 8002776: 0018 movs r0, r3 + 8002778: f000 fb6c bl 8002e54 + 800277c: e000 b.n 8002780 + if (hi2c->XferCount == 0U) + 800277e: 46c0 nop ; (mov r8, r8) + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8002780: 68fb ldr r3, [r7, #12] + 8002782: 2240 movs r2, #64 ; 0x40 + 8002784: 2100 movs r1, #0 + 8002786: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8002788: 2300 movs r3, #0 +} + 800278a: 0018 movs r0, r3 + 800278c: 46bd mov sp, r7 + 800278e: b007 add sp, #28 + 8002790: bd90 pop {r4, r7, pc} + 8002792: 46c0 nop ; (mov r8, r8) + 8002794: ffff0000 .word 0xffff0000 + +08002798 : + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + 8002798: b590 push {r4, r7, lr} + 800279a: b089 sub sp, #36 ; 0x24 + 800279c: af02 add r7, sp, #8 + 800279e: 60f8 str r0, [r7, #12] + 80027a0: 60b9 str r1, [r7, #8] + 80027a2: 607a str r2, [r7, #4] + uint32_t direction = I2C_GENERATE_START_WRITE; + 80027a4: 4b90 ldr r3, [pc, #576] ; (80029e8 ) + 80027a6: 617b str r3, [r7, #20] + + /* Process Locked */ + __HAL_LOCK(hi2c); + 80027a8: 68fb ldr r3, [r7, #12] + 80027aa: 2240 movs r2, #64 ; 0x40 + 80027ac: 5c9b ldrb r3, [r3, r2] + 80027ae: 2b01 cmp r3, #1 + 80027b0: d101 bne.n 80027b6 + 80027b2: 2302 movs r3, #2 + 80027b4: e113 b.n 80029de + 80027b6: 68fb ldr r3, [r7, #12] + 80027b8: 2240 movs r2, #64 ; 0x40 + 80027ba: 2101 movs r1, #1 + 80027bc: 5499 strb r1, [r3, r2] + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 80027be: 68bb ldr r3, [r7, #8] + 80027c0: 2210 movs r2, #16 + 80027c2: 4013 ands r3, r2 + 80027c4: d017 beq.n 80027f6 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 80027c6: 687b ldr r3, [r7, #4] + 80027c8: 2210 movs r2, #16 + 80027ca: 4013 ands r3, r2 + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 80027cc: d013 beq.n 80027f6 + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 80027ce: 68fb ldr r3, [r7, #12] + 80027d0: 681b ldr r3, [r3, #0] + 80027d2: 2210 movs r2, #16 + 80027d4: 61da str r2, [r3, #28] + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 80027d6: 68fb ldr r3, [r7, #12] + 80027d8: 6c5b ldr r3, [r3, #68] ; 0x44 + 80027da: 2204 movs r2, #4 + 80027dc: 431a orrs r2, r3 + 80027de: 68fb ldr r3, [r7, #12] + 80027e0: 645a str r2, [r3, #68] ; 0x44 + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 80027e2: 68fb ldr r3, [r7, #12] + 80027e4: 2120 movs r1, #32 + 80027e6: 0018 movs r0, r3 + 80027e8: f001 fac2 bl 8003d70 + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 80027ec: 68fb ldr r3, [r7, #12] + 80027ee: 0018 movs r0, r3 + 80027f0: f000 ff09 bl 8003606 + 80027f4: e0ee b.n 80029d4 + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + 80027f6: 68bb ldr r3, [r7, #8] + 80027f8: 2202 movs r2, #2 + 80027fa: 4013 ands r3, r2 + 80027fc: d00d beq.n 800281a + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 80027fe: 687b ldr r3, [r7, #4] + 8002800: 2202 movs r2, #2 + 8002802: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + 8002804: d009 beq.n 800281a + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + 8002806: 68fb ldr r3, [r7, #12] + 8002808: 681b ldr r3, [r3, #0] + 800280a: 68fa ldr r2, [r7, #12] + 800280c: 6d12 ldr r2, [r2, #80] ; 0x50 + 800280e: 629a str r2, [r3, #40] ; 0x28 + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + 8002810: 68fb ldr r3, [r7, #12] + 8002812: 2201 movs r2, #1 + 8002814: 4252 negs r2, r2 + 8002816: 651a str r2, [r3, #80] ; 0x50 + 8002818: e0dc b.n 80029d4 + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + 800281a: 68bb ldr r3, [r7, #8] + 800281c: 2280 movs r2, #128 ; 0x80 + 800281e: 4013 ands r3, r2 + 8002820: d063 beq.n 80028ea + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 8002822: 687b ldr r3, [r7, #4] + 8002824: 2240 movs r2, #64 ; 0x40 + 8002826: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + 8002828: d05f beq.n 80028ea + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 800282a: 68fb ldr r3, [r7, #12] + 800282c: 2101 movs r1, #1 + 800282e: 0018 movs r0, r3 + 8002830: f001 fb28 bl 8003e84 + + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 8002834: 68fb ldr r3, [r7, #12] + 8002836: 2110 movs r1, #16 + 8002838: 0018 movs r0, r3 + 800283a: f001 fa99 bl 8003d70 + + if (hi2c->XferCount != 0U) + 800283e: 68fb ldr r3, [r7, #12] + 8002840: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002842: b29b uxth r3, r3 + 8002844: 2b00 cmp r3, #0 + 8002846: d04a beq.n 80028de + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8002848: 68fb ldr r3, [r7, #12] + 800284a: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800284c: b29b uxth r3, r3 + 800284e: 2bff cmp r3, #255 ; 0xff + 8002850: d910 bls.n 8002874 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8002852: 68fb ldr r3, [r7, #12] + 8002854: 22ff movs r2, #255 ; 0xff + 8002856: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 8002858: 68fb ldr r3, [r7, #12] + 800285a: 6cdb ldr r3, [r3, #76] ; 0x4c + 800285c: b299 uxth r1, r3 + 800285e: 68fb ldr r3, [r7, #12] + 8002860: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002862: b2da uxtb r2, r3 + 8002864: 2380 movs r3, #128 ; 0x80 + 8002866: 045b lsls r3, r3, #17 + 8002868: 68f8 ldr r0, [r7, #12] + 800286a: 2400 movs r4, #0 + 800286c: 9400 str r4, [sp, #0] + 800286e: f001 fa45 bl 8003cfc + 8002872: e011 b.n 8002898 + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8002874: 68fb ldr r3, [r7, #12] + 8002876: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002878: b29a uxth r2, r3 + 800287a: 68fb ldr r3, [r7, #12] + 800287c: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 800287e: 68fb ldr r3, [r7, #12] + 8002880: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002882: b299 uxth r1, r3 + 8002884: 68fb ldr r3, [r7, #12] + 8002886: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002888: b2da uxtb r2, r3 + 800288a: 2380 movs r3, #128 ; 0x80 + 800288c: 049b lsls r3, r3, #18 + 800288e: 68f8 ldr r0, [r7, #12] + 8002890: 2400 movs r4, #0 + 8002892: 9400 str r4, [sp, #0] + 8002894: f001 fa32 bl 8003cfc + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + 8002898: 68fb ldr r3, [r7, #12] + 800289a: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800289c: b29a uxth r2, r3 + 800289e: 68fb ldr r3, [r7, #12] + 80028a0: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80028a2: 1ad3 subs r3, r2, r3 + 80028a4: b29a uxth r2, r3 + 80028a6: 68fb ldr r3, [r7, #12] + 80028a8: 855a strh r2, [r3, #42] ; 0x2a + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 80028aa: 68fb ldr r3, [r7, #12] + 80028ac: 2241 movs r2, #65 ; 0x41 + 80028ae: 5c9b ldrb r3, [r3, r2] + 80028b0: b2db uxtb r3, r3 + 80028b2: 2b22 cmp r3, #34 ; 0x22 + 80028b4: d109 bne.n 80028ca + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 80028b6: 68fb ldr r3, [r7, #12] + 80028b8: 681b ldr r3, [r3, #0] + 80028ba: 681a ldr r2, [r3, #0] + 80028bc: 68fb ldr r3, [r7, #12] + 80028be: 681b ldr r3, [r3, #0] + 80028c0: 2180 movs r1, #128 ; 0x80 + 80028c2: 0209 lsls r1, r1, #8 + 80028c4: 430a orrs r2, r1 + 80028c6: 601a str r2, [r3, #0] + if (hi2c->XferCount != 0U) + 80028c8: e084 b.n 80029d4 + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 80028ca: 68fb ldr r3, [r7, #12] + 80028cc: 681b ldr r3, [r3, #0] + 80028ce: 681a ldr r2, [r3, #0] + 80028d0: 68fb ldr r3, [r7, #12] + 80028d2: 681b ldr r3, [r3, #0] + 80028d4: 2180 movs r1, #128 ; 0x80 + 80028d6: 01c9 lsls r1, r1, #7 + 80028d8: 430a orrs r2, r1 + 80028da: 601a str r2, [r3, #0] + if (hi2c->XferCount != 0U) + 80028dc: e07a b.n 80029d4 + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 80028de: 68fb ldr r3, [r7, #12] + 80028e0: 2140 movs r1, #64 ; 0x40 + 80028e2: 0018 movs r0, r3 + 80028e4: f000 fd64 bl 80033b0 + if (hi2c->XferCount != 0U) + 80028e8: e074 b.n 80029d4 + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + 80028ea: 68bb ldr r3, [r7, #8] + 80028ec: 2240 movs r2, #64 ; 0x40 + 80028ee: 4013 ands r3, r2 + 80028f0: d062 beq.n 80029b8 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 80028f2: 687b ldr r3, [r7, #4] + 80028f4: 2240 movs r2, #64 ; 0x40 + 80028f6: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + 80028f8: d05e beq.n 80029b8 + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 80028fa: 68fb ldr r3, [r7, #12] + 80028fc: 2101 movs r1, #1 + 80028fe: 0018 movs r0, r3 + 8002900: f001 fac0 bl 8003e84 + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 8002904: 68fb ldr r3, [r7, #12] + 8002906: 2110 movs r1, #16 + 8002908: 0018 movs r0, r3 + 800290a: f001 fa31 bl 8003d70 + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 800290e: 68fb ldr r3, [r7, #12] + 8002910: 2241 movs r2, #65 ; 0x41 + 8002912: 5c9b ldrb r3, [r3, r2] + 8002914: b2db uxtb r3, r3 + 8002916: 2b22 cmp r3, #34 ; 0x22 + 8002918: d101 bne.n 800291e + { + direction = I2C_GENERATE_START_READ; + 800291a: 4b34 ldr r3, [pc, #208] ; (80029ec ) + 800291c: 617b str r3, [r7, #20] + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 800291e: 68fb ldr r3, [r7, #12] + 8002920: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002922: b29b uxth r3, r3 + 8002924: 2bff cmp r3, #255 ; 0xff + 8002926: d911 bls.n 800294c + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8002928: 68fb ldr r3, [r7, #12] + 800292a: 22ff movs r2, #255 ; 0xff + 800292c: 851a strh r2, [r3, #40] ; 0x28 + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 800292e: 68fb ldr r3, [r7, #12] + 8002930: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002932: b299 uxth r1, r3 + 8002934: 68fb ldr r3, [r7, #12] + 8002936: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002938: b2da uxtb r2, r3 + 800293a: 2380 movs r3, #128 ; 0x80 + 800293c: 045c lsls r4, r3, #17 + 800293e: 68f8 ldr r0, [r7, #12] + 8002940: 697b ldr r3, [r7, #20] + 8002942: 9300 str r3, [sp, #0] + 8002944: 0023 movs r3, r4 + 8002946: f001 f9d9 bl 8003cfc + 800294a: e012 b.n 8002972 + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 800294c: 68fb ldr r3, [r7, #12] + 800294e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002950: b29a uxth r2, r3 + 8002952: 68fb ldr r3, [r7, #12] + 8002954: 851a strh r2, [r3, #40] ; 0x28 + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 8002956: 68fb ldr r3, [r7, #12] + 8002958: 6cdb ldr r3, [r3, #76] ; 0x4c + 800295a: b299 uxth r1, r3 + 800295c: 68fb ldr r3, [r7, #12] + 800295e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8002960: b2da uxtb r2, r3 + 8002962: 2380 movs r3, #128 ; 0x80 + 8002964: 049c lsls r4, r3, #18 + 8002966: 68f8 ldr r0, [r7, #12] + 8002968: 697b ldr r3, [r7, #20] + 800296a: 9300 str r3, [sp, #0] + 800296c: 0023 movs r3, r4 + 800296e: f001 f9c5 bl 8003cfc + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + 8002972: 68fb ldr r3, [r7, #12] + 8002974: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8002976: b29a uxth r2, r3 + 8002978: 68fb ldr r3, [r7, #12] + 800297a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800297c: 1ad3 subs r3, r2, r3 + 800297e: b29a uxth r2, r3 + 8002980: 68fb ldr r3, [r7, #12] + 8002982: 855a strh r2, [r3, #42] ; 0x2a + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 8002984: 68fb ldr r3, [r7, #12] + 8002986: 2241 movs r2, #65 ; 0x41 + 8002988: 5c9b ldrb r3, [r3, r2] + 800298a: b2db uxtb r3, r3 + 800298c: 2b22 cmp r3, #34 ; 0x22 + 800298e: d109 bne.n 80029a4 + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 8002990: 68fb ldr r3, [r7, #12] + 8002992: 681b ldr r3, [r3, #0] + 8002994: 681a ldr r2, [r3, #0] + 8002996: 68fb ldr r3, [r7, #12] + 8002998: 681b ldr r3, [r3, #0] + 800299a: 2180 movs r1, #128 ; 0x80 + 800299c: 0209 lsls r1, r1, #8 + 800299e: 430a orrs r2, r1 + 80029a0: 601a str r2, [r3, #0] + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 80029a2: e017 b.n 80029d4 + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 80029a4: 68fb ldr r3, [r7, #12] + 80029a6: 681b ldr r3, [r3, #0] + 80029a8: 681a ldr r2, [r3, #0] + 80029aa: 68fb ldr r3, [r7, #12] + 80029ac: 681b ldr r3, [r3, #0] + 80029ae: 2180 movs r1, #128 ; 0x80 + 80029b0: 01c9 lsls r1, r1, #7 + 80029b2: 430a orrs r2, r1 + 80029b4: 601a str r2, [r3, #0] + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 80029b6: e00d b.n 80029d4 + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 80029b8: 68bb ldr r3, [r7, #8] + 80029ba: 2220 movs r2, #32 + 80029bc: 4013 ands r3, r2 + 80029be: d009 beq.n 80029d4 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 80029c0: 687b ldr r3, [r7, #4] + 80029c2: 2220 movs r2, #32 + 80029c4: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 80029c6: d005 beq.n 80029d4 + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + 80029c8: 68ba ldr r2, [r7, #8] + 80029ca: 68fb ldr r3, [r7, #12] + 80029cc: 0011 movs r1, r2 + 80029ce: 0018 movs r0, r3 + 80029d0: f000 fa40 bl 8002e54 + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80029d4: 68fb ldr r3, [r7, #12] + 80029d6: 2240 movs r2, #64 ; 0x40 + 80029d8: 2100 movs r1, #0 + 80029da: 5499 strb r1, [r3, r2] + + return HAL_OK; + 80029dc: 2300 movs r3, #0 +} + 80029de: 0018 movs r0, r3 + 80029e0: 46bd mov sp, r7 + 80029e2: b007 add sp, #28 + 80029e4: bd90 pop {r4, r7, pc} + 80029e6: 46c0 nop ; (mov r8, r8) + 80029e8: 80002000 .word 0x80002000 + 80029ec: 80002400 .word 0x80002400 + +080029f0 : + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + 80029f0: b580 push {r7, lr} + 80029f2: b088 sub sp, #32 + 80029f4: af00 add r7, sp, #0 + 80029f6: 60f8 str r0, [r7, #12] + 80029f8: 60b9 str r1, [r7, #8] + 80029fa: 607a str r2, [r7, #4] + uint32_t tmpoptions = hi2c->XferOptions; + 80029fc: 68fb ldr r3, [r7, #12] + 80029fe: 6adb ldr r3, [r3, #44] ; 0x2c + 8002a00: 61bb str r3, [r7, #24] + uint32_t treatdmanack = 0U; + 8002a02: 2300 movs r3, #0 + 8002a04: 61fb str r3, [r7, #28] + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + 8002a06: 68fb ldr r3, [r7, #12] + 8002a08: 2240 movs r2, #64 ; 0x40 + 8002a0a: 5c9b ldrb r3, [r3, r2] + 8002a0c: 2b01 cmp r3, #1 + 8002a0e: d101 bne.n 8002a14 + 8002a10: 2302 movs r3, #2 + 8002a12: e0ce b.n 8002bb2 + 8002a14: 68fb ldr r3, [r7, #12] + 8002a16: 2240 movs r2, #64 ; 0x40 + 8002a18: 2101 movs r1, #1 + 8002a1a: 5499 strb r1, [r3, r2] + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 8002a1c: 68bb ldr r3, [r7, #8] + 8002a1e: 2220 movs r2, #32 + 8002a20: 4013 ands r3, r2 + 8002a22: d00a beq.n 8002a3a + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 8002a24: 687b ldr r3, [r7, #4] + 8002a26: 2220 movs r2, #32 + 8002a28: 4013 ands r3, r2 + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 8002a2a: d006 beq.n 8002a3a + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + 8002a2c: 68ba ldr r2, [r7, #8] + 8002a2e: 68fb ldr r3, [r7, #12] + 8002a30: 0011 movs r1, r2 + 8002a32: 0018 movs r0, r3 + 8002a34: f000 fadc bl 8002ff0 + 8002a38: e0b6 b.n 8002ba8 + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 8002a3a: 68bb ldr r3, [r7, #8] + 8002a3c: 2210 movs r2, #16 + 8002a3e: 4013 ands r3, r2 + 8002a40: d100 bne.n 8002a44 + 8002a42: e0a3 b.n 8002b8c + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 8002a44: 687b ldr r3, [r7, #4] + 8002a46: 2210 movs r2, #16 + 8002a48: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 8002a4a: d100 bne.n 8002a4e + 8002a4c: e09e b.n 8002b8c + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + 8002a4e: 687a ldr r2, [r7, #4] + 8002a50: 2380 movs r3, #128 ; 0x80 + 8002a52: 01db lsls r3, r3, #7 + 8002a54: 4013 ands r3, r2 + 8002a56: d105 bne.n 8002a64 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 8002a58: 687a ldr r2, [r7, #4] + 8002a5a: 2380 movs r3, #128 ; 0x80 + 8002a5c: 021b lsls r3, r3, #8 + 8002a5e: 4013 ands r3, r2 + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + 8002a60: d100 bne.n 8002a64 + 8002a62: e08c b.n 8002b7e + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + 8002a64: 68fb ldr r3, [r7, #12] + 8002a66: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002a68: 2b00 cmp r3, #0 + 8002a6a: d00c beq.n 8002a86 + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + 8002a6c: 687a ldr r2, [r7, #4] + 8002a6e: 2380 movs r3, #128 ; 0x80 + 8002a70: 021b lsls r3, r3, #8 + 8002a72: 4013 ands r3, r2 + 8002a74: d007 beq.n 8002a86 + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + 8002a76: 68fb ldr r3, [r7, #12] + 8002a78: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002a7a: 681b ldr r3, [r3, #0] + 8002a7c: 685b ldr r3, [r3, #4] + 8002a7e: 2b00 cmp r3, #0 + 8002a80: d101 bne.n 8002a86 + { + treatdmanack = 1U; + 8002a82: 2301 movs r3, #1 + 8002a84: 61fb str r3, [r7, #28] + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + 8002a86: 68fb ldr r3, [r7, #12] + 8002a88: 6b9b ldr r3, [r3, #56] ; 0x38 + 8002a8a: 2b00 cmp r3, #0 + 8002a8c: d00c beq.n 8002aa8 + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + 8002a8e: 687a ldr r2, [r7, #4] + 8002a90: 2380 movs r3, #128 ; 0x80 + 8002a92: 01db lsls r3, r3, #7 + 8002a94: 4013 ands r3, r2 + 8002a96: d007 beq.n 8002aa8 + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + 8002a98: 68fb ldr r3, [r7, #12] + 8002a9a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8002a9c: 681b ldr r3, [r3, #0] + 8002a9e: 685b ldr r3, [r3, #4] + 8002aa0: 2b00 cmp r3, #0 + 8002aa2: d101 bne.n 8002aa8 + { + treatdmanack = 1U; + 8002aa4: 2301 movs r3, #1 + 8002aa6: 61fb str r3, [r7, #28] + } + } + } + + if (treatdmanack == 1U) + 8002aa8: 69fb ldr r3, [r7, #28] + 8002aaa: 2b01 cmp r3, #1 + 8002aac: d12d bne.n 8002b0a + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + 8002aae: 68fb ldr r3, [r7, #12] + 8002ab0: 2241 movs r2, #65 ; 0x41 + 8002ab2: 5c9b ldrb r3, [r3, r2] + 8002ab4: b2db uxtb r3, r3 + 8002ab6: 2b28 cmp r3, #40 ; 0x28 + 8002ab8: d10b bne.n 8002ad2 + 8002aba: 69ba ldr r2, [r7, #24] + 8002abc: 2380 movs r3, #128 ; 0x80 + 8002abe: 049b lsls r3, r3, #18 + 8002ac0: 429a cmp r2, r3 + 8002ac2: d106 bne.n 8002ad2 + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + 8002ac4: 68ba ldr r2, [r7, #8] + 8002ac6: 68fb ldr r3, [r7, #12] + 8002ac8: 0011 movs r1, r2 + 8002aca: 0018 movs r0, r3 + 8002acc: f000 fc18 bl 8003300 + 8002ad0: e054 b.n 8002b7c + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + 8002ad2: 68fb ldr r3, [r7, #12] + 8002ad4: 2241 movs r2, #65 ; 0x41 + 8002ad6: 5c9b ldrb r3, [r3, r2] + 8002ad8: b2db uxtb r3, r3 + 8002ada: 2b29 cmp r3, #41 ; 0x29 + 8002adc: d110 bne.n 8002b00 + 8002ade: 69bb ldr r3, [r7, #24] + 8002ae0: 4a36 ldr r2, [pc, #216] ; (8002bbc ) + 8002ae2: 4293 cmp r3, r2 + 8002ae4: d00c beq.n 8002b00 + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8002ae6: 68fb ldr r3, [r7, #12] + 8002ae8: 681b ldr r3, [r3, #0] + 8002aea: 2210 movs r2, #16 + 8002aec: 61da str r2, [r3, #28] + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 8002aee: 68fb ldr r3, [r7, #12] + 8002af0: 0018 movs r0, r3 + 8002af2: f000 fd88 bl 8003606 + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + 8002af6: 68fb ldr r3, [r7, #12] + 8002af8: 0018 movs r0, r3 + 8002afa: f000 f947 bl 8002d8c + 8002afe: e03d b.n 8002b7c + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8002b00: 68fb ldr r3, [r7, #12] + 8002b02: 681b ldr r3, [r3, #0] + 8002b04: 2210 movs r2, #16 + 8002b06: 61da str r2, [r3, #28] + if (treatdmanack == 1U) + 8002b08: e03e b.n 8002b88 + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8002b0a: 68fb ldr r3, [r7, #12] + 8002b0c: 681b ldr r3, [r3, #0] + 8002b0e: 2210 movs r2, #16 + 8002b10: 61da str r2, [r3, #28] + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 8002b12: 68fb ldr r3, [r7, #12] + 8002b14: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002b16: 2204 movs r2, #4 + 8002b18: 431a orrs r2, r3 + 8002b1a: 68fb ldr r3, [r7, #12] + 8002b1c: 645a str r2, [r3, #68] ; 0x44 + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + 8002b1e: 2317 movs r3, #23 + 8002b20: 18fb adds r3, r7, r3 + 8002b22: 68fa ldr r2, [r7, #12] + 8002b24: 2141 movs r1, #65 ; 0x41 + 8002b26: 5c52 ldrb r2, [r2, r1] + 8002b28: 701a strb r2, [r3, #0] + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + 8002b2a: 69bb ldr r3, [r7, #24] + 8002b2c: 2b00 cmp r3, #0 + 8002b2e: d004 beq.n 8002b3a + 8002b30: 69ba ldr r2, [r7, #24] + 8002b32: 2380 movs r3, #128 ; 0x80 + 8002b34: 045b lsls r3, r3, #17 + 8002b36: 429a cmp r2, r3 + 8002b38: d126 bne.n 8002b88 + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + 8002b3a: 2217 movs r2, #23 + 8002b3c: 18bb adds r3, r7, r2 + 8002b3e: 781b ldrb r3, [r3, #0] + 8002b40: 2b21 cmp r3, #33 ; 0x21 + 8002b42: d003 beq.n 8002b4c + 8002b44: 18bb adds r3, r7, r2 + 8002b46: 781b ldrb r3, [r3, #0] + 8002b48: 2b29 cmp r3, #41 ; 0x29 + 8002b4a: d103 bne.n 8002b54 + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 8002b4c: 68fb ldr r3, [r7, #12] + 8002b4e: 2221 movs r2, #33 ; 0x21 + 8002b50: 631a str r2, [r3, #48] ; 0x30 + 8002b52: e00b b.n 8002b6c + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 8002b54: 2217 movs r2, #23 + 8002b56: 18bb adds r3, r7, r2 + 8002b58: 781b ldrb r3, [r3, #0] + 8002b5a: 2b22 cmp r3, #34 ; 0x22 + 8002b5c: d003 beq.n 8002b66 + 8002b5e: 18bb adds r3, r7, r2 + 8002b60: 781b ldrb r3, [r3, #0] + 8002b62: 2b2a cmp r3, #42 ; 0x2a + 8002b64: d102 bne.n 8002b6c + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 8002b66: 68fb ldr r3, [r7, #12] + 8002b68: 2222 movs r2, #34 ; 0x22 + 8002b6a: 631a str r2, [r3, #48] ; 0x30 + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + 8002b6c: 68fb ldr r3, [r7, #12] + 8002b6e: 6c5a ldr r2, [r3, #68] ; 0x44 + 8002b70: 68fb ldr r3, [r7, #12] + 8002b72: 0011 movs r1, r2 + 8002b74: 0018 movs r0, r3 + 8002b76: f000 fc1b bl 80033b0 + if (treatdmanack == 1U) + 8002b7a: e005 b.n 8002b88 + 8002b7c: e004 b.n 8002b88 + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8002b7e: 68fb ldr r3, [r7, #12] + 8002b80: 681b ldr r3, [r3, #0] + 8002b82: 2210 movs r2, #16 + 8002b84: 61da str r2, [r3, #28] + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + 8002b86: e00f b.n 8002ba8 + if (treatdmanack == 1U) + 8002b88: 46c0 nop ; (mov r8, r8) + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + 8002b8a: e00d b.n 8002ba8 + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + 8002b8c: 68bb ldr r3, [r7, #8] + 8002b8e: 2208 movs r2, #8 + 8002b90: 4013 ands r3, r2 + 8002b92: d009 beq.n 8002ba8 + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 8002b94: 687b ldr r3, [r7, #4] + 8002b96: 2208 movs r2, #8 + 8002b98: 4013 ands r3, r2 + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + 8002b9a: d005 beq.n 8002ba8 + { + I2C_ITAddrCplt(hi2c, ITFlags); + 8002b9c: 68ba ldr r2, [r7, #8] + 8002b9e: 68fb ldr r3, [r7, #12] + 8002ba0: 0011 movs r1, r2 + 8002ba2: 0018 movs r0, r3 + 8002ba4: f000 f80c bl 8002bc0 + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8002ba8: 68fb ldr r3, [r7, #12] + 8002baa: 2240 movs r2, #64 ; 0x40 + 8002bac: 2100 movs r1, #0 + 8002bae: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8002bb0: 2300 movs r3, #0 +} + 8002bb2: 0018 movs r0, r3 + 8002bb4: 46bd mov sp, r7 + 8002bb6: b008 add sp, #32 + 8002bb8: bd80 pop {r7, pc} + 8002bba: 46c0 nop ; (mov r8, r8) + 8002bbc: ffff0000 .word 0xffff0000 + +08002bc0 : + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + 8002bc0: b5b0 push {r4, r5, r7, lr} + 8002bc2: b084 sub sp, #16 + 8002bc4: af00 add r7, sp, #0 + 8002bc6: 6078 str r0, [r7, #4] + 8002bc8: 6039 str r1, [r7, #0] + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + 8002bca: 687b ldr r3, [r7, #4] + 8002bcc: 2241 movs r2, #65 ; 0x41 + 8002bce: 5c9b ldrb r3, [r3, r2] + 8002bd0: b2db uxtb r3, r3 + 8002bd2: 001a movs r2, r3 + 8002bd4: 2328 movs r3, #40 ; 0x28 + 8002bd6: 4013 ands r3, r2 + 8002bd8: 2b28 cmp r3, #40 ; 0x28 + 8002bda: d000 beq.n 8002bde + 8002bdc: e088 b.n 8002cf0 + { + transferdirection = I2C_GET_DIR(hi2c); + 8002bde: 687b ldr r3, [r7, #4] + 8002be0: 681b ldr r3, [r3, #0] + 8002be2: 699b ldr r3, [r3, #24] + 8002be4: 0c1b lsrs r3, r3, #16 + 8002be6: b2da uxtb r2, r3 + 8002be8: 250f movs r5, #15 + 8002bea: 197b adds r3, r7, r5 + 8002bec: 2101 movs r1, #1 + 8002bee: 400a ands r2, r1 + 8002bf0: 701a strb r2, [r3, #0] + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 8002bf2: 687b ldr r3, [r7, #4] + 8002bf4: 681b ldr r3, [r3, #0] + 8002bf6: 699b ldr r3, [r3, #24] + 8002bf8: 0c1b lsrs r3, r3, #16 + 8002bfa: b29a uxth r2, r3 + 8002bfc: 200c movs r0, #12 + 8002bfe: 183b adds r3, r7, r0 + 8002c00: 21fe movs r1, #254 ; 0xfe + 8002c02: 400a ands r2, r1 + 8002c04: 801a strh r2, [r3, #0] + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 8002c06: 687b ldr r3, [r7, #4] + 8002c08: 681b ldr r3, [r3, #0] + 8002c0a: 689b ldr r3, [r3, #8] + 8002c0c: b29a uxth r2, r3 + 8002c0e: 240a movs r4, #10 + 8002c10: 193b adds r3, r7, r4 + 8002c12: 0592 lsls r2, r2, #22 + 8002c14: 0d92 lsrs r2, r2, #22 + 8002c16: 801a strh r2, [r3, #0] + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 8002c18: 687b ldr r3, [r7, #4] + 8002c1a: 681b ldr r3, [r3, #0] + 8002c1c: 68db ldr r3, [r3, #12] + 8002c1e: b29a uxth r2, r3 + 8002c20: 2308 movs r3, #8 + 8002c22: 18fb adds r3, r7, r3 + 8002c24: 21fe movs r1, #254 ; 0xfe + 8002c26: 400a ands r2, r1 + 8002c28: 801a strh r2, [r3, #0] + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 8002c2a: 687b ldr r3, [r7, #4] + 8002c2c: 68db ldr r3, [r3, #12] + 8002c2e: 2b02 cmp r3, #2 + 8002c30: d148 bne.n 8002cc4 + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + 8002c32: 0021 movs r1, r4 + 8002c34: 187b adds r3, r7, r1 + 8002c36: 881b ldrh r3, [r3, #0] + 8002c38: 09db lsrs r3, r3, #7 + 8002c3a: b29a uxth r2, r3 + 8002c3c: 183b adds r3, r7, r0 + 8002c3e: 881b ldrh r3, [r3, #0] + 8002c40: 4053 eors r3, r2 + 8002c42: b29b uxth r3, r3 + 8002c44: 001a movs r2, r3 + 8002c46: 2306 movs r3, #6 + 8002c48: 4013 ands r3, r2 + 8002c4a: d120 bne.n 8002c8e + { + slaveaddrcode = ownadd1code; + 8002c4c: 183b adds r3, r7, r0 + 8002c4e: 187a adds r2, r7, r1 + 8002c50: 8812 ldrh r2, [r2, #0] + 8002c52: 801a strh r2, [r3, #0] + hi2c->AddrEventCount++; + 8002c54: 687b ldr r3, [r7, #4] + 8002c56: 6c9b ldr r3, [r3, #72] ; 0x48 + 8002c58: 1c5a adds r2, r3, #1 + 8002c5a: 687b ldr r3, [r7, #4] + 8002c5c: 649a str r2, [r3, #72] ; 0x48 + if (hi2c->AddrEventCount == 2U) + 8002c5e: 687b ldr r3, [r7, #4] + 8002c60: 6c9b ldr r3, [r3, #72] ; 0x48 + 8002c62: 2b02 cmp r3, #2 + 8002c64: d14c bne.n 8002d00 + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + 8002c66: 687b ldr r3, [r7, #4] + 8002c68: 2200 movs r2, #0 + 8002c6a: 649a str r2, [r3, #72] ; 0x48 + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 8002c6c: 687b ldr r3, [r7, #4] + 8002c6e: 681b ldr r3, [r3, #0] + 8002c70: 2208 movs r2, #8 + 8002c72: 61da str r2, [r3, #28] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8002c74: 687b ldr r3, [r7, #4] + 8002c76: 2240 movs r2, #64 ; 0x40 + 8002c78: 2100 movs r1, #0 + 8002c7a: 5499 strb r1, [r3, r2] + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + 8002c7c: 183b adds r3, r7, r0 + 8002c7e: 881a ldrh r2, [r3, #0] + 8002c80: 197b adds r3, r7, r5 + 8002c82: 7819 ldrb r1, [r3, #0] + 8002c84: 687b ldr r3, [r7, #4] + 8002c86: 0018 movs r0, r3 + 8002c88: f7ff fa1e bl 80020c8 + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + 8002c8c: e038 b.n 8002d00 + slaveaddrcode = ownadd2code; + 8002c8e: 240c movs r4, #12 + 8002c90: 193b adds r3, r7, r4 + 8002c92: 2208 movs r2, #8 + 8002c94: 18ba adds r2, r7, r2 + 8002c96: 8812 ldrh r2, [r2, #0] + 8002c98: 801a strh r2, [r3, #0] + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + 8002c9a: 2380 movs r3, #128 ; 0x80 + 8002c9c: 021a lsls r2, r3, #8 + 8002c9e: 687b ldr r3, [r7, #4] + 8002ca0: 0011 movs r1, r2 + 8002ca2: 0018 movs r0, r3 + 8002ca4: f001 f8ee bl 8003e84 + __HAL_UNLOCK(hi2c); + 8002ca8: 687b ldr r3, [r7, #4] + 8002caa: 2240 movs r2, #64 ; 0x40 + 8002cac: 2100 movs r1, #0 + 8002cae: 5499 strb r1, [r3, r2] + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + 8002cb0: 193b adds r3, r7, r4 + 8002cb2: 881a ldrh r2, [r3, #0] + 8002cb4: 230f movs r3, #15 + 8002cb6: 18fb adds r3, r7, r3 + 8002cb8: 7819 ldrb r1, [r3, #0] + 8002cba: 687b ldr r3, [r7, #4] + 8002cbc: 0018 movs r0, r3 + 8002cbe: f7ff fa03 bl 80020c8 +} + 8002cc2: e01d b.n 8002d00 + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + 8002cc4: 2380 movs r3, #128 ; 0x80 + 8002cc6: 021a lsls r2, r3, #8 + 8002cc8: 687b ldr r3, [r7, #4] + 8002cca: 0011 movs r1, r2 + 8002ccc: 0018 movs r0, r3 + 8002cce: f001 f8d9 bl 8003e84 + __HAL_UNLOCK(hi2c); + 8002cd2: 687b ldr r3, [r7, #4] + 8002cd4: 2240 movs r2, #64 ; 0x40 + 8002cd6: 2100 movs r1, #0 + 8002cd8: 5499 strb r1, [r3, r2] + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + 8002cda: 230c movs r3, #12 + 8002cdc: 18fb adds r3, r7, r3 + 8002cde: 881a ldrh r2, [r3, #0] + 8002ce0: 230f movs r3, #15 + 8002ce2: 18fb adds r3, r7, r3 + 8002ce4: 7819 ldrb r1, [r3, #0] + 8002ce6: 687b ldr r3, [r7, #4] + 8002ce8: 0018 movs r0, r3 + 8002cea: f7ff f9ed bl 80020c8 +} + 8002cee: e007 b.n 8002d00 + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 8002cf0: 687b ldr r3, [r7, #4] + 8002cf2: 681b ldr r3, [r3, #0] + 8002cf4: 2208 movs r2, #8 + 8002cf6: 61da str r2, [r3, #28] + __HAL_UNLOCK(hi2c); + 8002cf8: 687b ldr r3, [r7, #4] + 8002cfa: 2240 movs r2, #64 ; 0x40 + 8002cfc: 2100 movs r1, #0 + 8002cfe: 5499 strb r1, [r3, r2] +} + 8002d00: 46c0 nop ; (mov r8, r8) + 8002d02: 46bd mov sp, r7 + 8002d04: b004 add sp, #16 + 8002d06: bdb0 pop {r4, r5, r7, pc} + +08002d08 : + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + 8002d08: b580 push {r7, lr} + 8002d0a: b082 sub sp, #8 + 8002d0c: af00 add r7, sp, #0 + 8002d0e: 6078 str r0, [r7, #4] + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + 8002d10: 687b ldr r3, [r7, #4] + 8002d12: 2242 movs r2, #66 ; 0x42 + 8002d14: 2100 movs r1, #0 + 8002d16: 5499 strb r1, [r3, r2] + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + 8002d18: 687b ldr r3, [r7, #4] + 8002d1a: 2241 movs r2, #65 ; 0x41 + 8002d1c: 5c9b ldrb r3, [r3, r2] + 8002d1e: b2db uxtb r3, r3 + 8002d20: 2b21 cmp r3, #33 ; 0x21 + 8002d22: d117 bne.n 8002d54 + { + hi2c->State = HAL_I2C_STATE_READY; + 8002d24: 687b ldr r3, [r7, #4] + 8002d26: 2241 movs r2, #65 ; 0x41 + 8002d28: 2120 movs r1, #32 + 8002d2a: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 8002d2c: 687b ldr r3, [r7, #4] + 8002d2e: 2211 movs r2, #17 + 8002d30: 631a str r2, [r3, #48] ; 0x30 + hi2c->XferISR = NULL; + 8002d32: 687b ldr r3, [r7, #4] + 8002d34: 2200 movs r2, #0 + 8002d36: 635a str r2, [r3, #52] ; 0x34 + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 8002d38: 687b ldr r3, [r7, #4] + 8002d3a: 2101 movs r1, #1 + 8002d3c: 0018 movs r0, r3 + 8002d3e: f001 f8a1 bl 8003e84 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8002d42: 687b ldr r3, [r7, #4] + 8002d44: 2240 movs r2, #64 ; 0x40 + 8002d46: 2100 movs r1, #0 + 8002d48: 5499 strb r1, [r3, r2] + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); + 8002d4a: 687b ldr r3, [r7, #4] + 8002d4c: 0018 movs r0, r3 + 8002d4e: f7ff f99b bl 8002088 + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + 8002d52: e016 b.n 8002d82 + hi2c->State = HAL_I2C_STATE_READY; + 8002d54: 687b ldr r3, [r7, #4] + 8002d56: 2241 movs r2, #65 ; 0x41 + 8002d58: 2120 movs r1, #32 + 8002d5a: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 8002d5c: 687b ldr r3, [r7, #4] + 8002d5e: 2212 movs r2, #18 + 8002d60: 631a str r2, [r3, #48] ; 0x30 + hi2c->XferISR = NULL; + 8002d62: 687b ldr r3, [r7, #4] + 8002d64: 2200 movs r2, #0 + 8002d66: 635a str r2, [r3, #52] ; 0x34 + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + 8002d68: 687b ldr r3, [r7, #4] + 8002d6a: 2102 movs r1, #2 + 8002d6c: 0018 movs r0, r3 + 8002d6e: f001 f889 bl 8003e84 + __HAL_UNLOCK(hi2c); + 8002d72: 687b ldr r3, [r7, #4] + 8002d74: 2240 movs r2, #64 ; 0x40 + 8002d76: 2100 movs r1, #0 + 8002d78: 5499 strb r1, [r3, r2] + HAL_I2C_MasterRxCpltCallback(hi2c); + 8002d7a: 687b ldr r3, [r7, #4] + 8002d7c: 0018 movs r0, r3 + 8002d7e: f7ff f98b bl 8002098 +} + 8002d82: 46c0 nop ; (mov r8, r8) + 8002d84: 46bd mov sp, r7 + 8002d86: b002 add sp, #8 + 8002d88: bd80 pop {r7, pc} + ... + +08002d8c : + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + 8002d8c: b580 push {r7, lr} + 8002d8e: b084 sub sp, #16 + 8002d90: af00 add r7, sp, #0 + 8002d92: 6078 str r0, [r7, #4] + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 8002d94: 687b ldr r3, [r7, #4] + 8002d96: 681b ldr r3, [r3, #0] + 8002d98: 681b ldr r3, [r3, #0] + 8002d9a: 60fb str r3, [r7, #12] + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + 8002d9c: 687b ldr r3, [r7, #4] + 8002d9e: 2242 movs r2, #66 ; 0x42 + 8002da0: 2100 movs r1, #0 + 8002da2: 5499 strb r1, [r3, r2] + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + 8002da4: 68fa ldr r2, [r7, #12] + 8002da6: 2380 movs r3, #128 ; 0x80 + 8002da8: 01db lsls r3, r3, #7 + 8002daa: 4013 ands r3, r2 + 8002dac: d008 beq.n 8002dc0 + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 8002dae: 687b ldr r3, [r7, #4] + 8002db0: 681b ldr r3, [r3, #0] + 8002db2: 681a ldr r2, [r3, #0] + 8002db4: 687b ldr r3, [r7, #4] + 8002db6: 681b ldr r3, [r3, #0] + 8002db8: 4924 ldr r1, [pc, #144] ; (8002e4c ) + 8002dba: 400a ands r2, r1 + 8002dbc: 601a str r2, [r3, #0] + 8002dbe: e00c b.n 8002dda + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + 8002dc0: 68fa ldr r2, [r7, #12] + 8002dc2: 2380 movs r3, #128 ; 0x80 + 8002dc4: 021b lsls r3, r3, #8 + 8002dc6: 4013 ands r3, r2 + 8002dc8: d007 beq.n 8002dda + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 8002dca: 687b ldr r3, [r7, #4] + 8002dcc: 681b ldr r3, [r3, #0] + 8002dce: 681a ldr r2, [r3, #0] + 8002dd0: 687b ldr r3, [r7, #4] + 8002dd2: 681b ldr r3, [r3, #0] + 8002dd4: 491e ldr r1, [pc, #120] ; (8002e50 ) + 8002dd6: 400a ands r2, r1 + 8002dd8: 601a str r2, [r3, #0] + else + { + /* Do nothing */ + } + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + 8002dda: 687b ldr r3, [r7, #4] + 8002ddc: 2241 movs r2, #65 ; 0x41 + 8002dde: 5c9b ldrb r3, [r3, r2] + 8002de0: b2db uxtb r3, r3 + 8002de2: 2b29 cmp r3, #41 ; 0x29 + 8002de4: d114 bne.n 8002e10 + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + 8002de6: 687b ldr r3, [r7, #4] + 8002de8: 2241 movs r2, #65 ; 0x41 + 8002dea: 2128 movs r1, #40 ; 0x28 + 8002dec: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 8002dee: 687b ldr r3, [r7, #4] + 8002df0: 2221 movs r2, #33 ; 0x21 + 8002df2: 631a str r2, [r3, #48] ; 0x30 + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 8002df4: 687b ldr r3, [r7, #4] + 8002df6: 2101 movs r1, #1 + 8002df8: 0018 movs r0, r3 + 8002dfa: f001 f843 bl 8003e84 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8002dfe: 687b ldr r3, [r7, #4] + 8002e00: 2240 movs r2, #64 ; 0x40 + 8002e02: 2100 movs r1, #0 + 8002e04: 5499 strb r1, [r3, r2] + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); + 8002e06: 687b ldr r3, [r7, #4] + 8002e08: 0018 movs r0, r3 + 8002e0a: f7ff f94d bl 80020a8 + } + else + { + /* Nothing to do */ + } +} + 8002e0e: e019 b.n 8002e44 + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + 8002e10: 687b ldr r3, [r7, #4] + 8002e12: 2241 movs r2, #65 ; 0x41 + 8002e14: 5c9b ldrb r3, [r3, r2] + 8002e16: b2db uxtb r3, r3 + 8002e18: 2b2a cmp r3, #42 ; 0x2a + 8002e1a: d113 bne.n 8002e44 + hi2c->State = HAL_I2C_STATE_LISTEN; + 8002e1c: 687b ldr r3, [r7, #4] + 8002e1e: 2241 movs r2, #65 ; 0x41 + 8002e20: 2128 movs r1, #40 ; 0x28 + 8002e22: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 8002e24: 687b ldr r3, [r7, #4] + 8002e26: 2222 movs r2, #34 ; 0x22 + 8002e28: 631a str r2, [r3, #48] ; 0x30 + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + 8002e2a: 687b ldr r3, [r7, #4] + 8002e2c: 2102 movs r1, #2 + 8002e2e: 0018 movs r0, r3 + 8002e30: f001 f828 bl 8003e84 + __HAL_UNLOCK(hi2c); + 8002e34: 687b ldr r3, [r7, #4] + 8002e36: 2240 movs r2, #64 ; 0x40 + 8002e38: 2100 movs r1, #0 + 8002e3a: 5499 strb r1, [r3, r2] + HAL_I2C_SlaveRxCpltCallback(hi2c); + 8002e3c: 687b ldr r3, [r7, #4] + 8002e3e: 0018 movs r0, r3 + 8002e40: f7ff f93a bl 80020b8 +} + 8002e44: 46c0 nop ; (mov r8, r8) + 8002e46: 46bd mov sp, r7 + 8002e48: b004 add sp, #16 + 8002e4a: bd80 pop {r7, pc} + 8002e4c: ffffbfff .word 0xffffbfff + 8002e50: ffff7fff .word 0xffff7fff + +08002e54 : + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + 8002e54: b580 push {r7, lr} + 8002e56: b086 sub sp, #24 + 8002e58: af00 add r7, sp, #0 + 8002e5a: 6078 str r0, [r7, #4] + 8002e5c: 6039 str r1, [r7, #0] + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + 8002e5e: 683b ldr r3, [r7, #0] + 8002e60: 617b str r3, [r7, #20] + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8002e62: 687b ldr r3, [r7, #4] + 8002e64: 681b ldr r3, [r3, #0] + 8002e66: 2220 movs r2, #32 + 8002e68: 61da str r2, [r3, #28] + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + 8002e6a: 687b ldr r3, [r7, #4] + 8002e6c: 2241 movs r2, #65 ; 0x41 + 8002e6e: 5c9b ldrb r3, [r3, r2] + 8002e70: b2db uxtb r3, r3 + 8002e72: 2b21 cmp r3, #33 ; 0x21 + 8002e74: d108 bne.n 8002e88 + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 8002e76: 687b ldr r3, [r7, #4] + 8002e78: 2101 movs r1, #1 + 8002e7a: 0018 movs r0, r3 + 8002e7c: f001 f802 bl 8003e84 + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 8002e80: 687b ldr r3, [r7, #4] + 8002e82: 2211 movs r2, #17 + 8002e84: 631a str r2, [r3, #48] ; 0x30 + 8002e86: e00d b.n 8002ea4 + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 8002e88: 687b ldr r3, [r7, #4] + 8002e8a: 2241 movs r2, #65 ; 0x41 + 8002e8c: 5c9b ldrb r3, [r3, r2] + 8002e8e: b2db uxtb r3, r3 + 8002e90: 2b22 cmp r3, #34 ; 0x22 + 8002e92: d107 bne.n 8002ea4 + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + 8002e94: 687b ldr r3, [r7, #4] + 8002e96: 2102 movs r1, #2 + 8002e98: 0018 movs r0, r3 + 8002e9a: f000 fff3 bl 8003e84 + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 8002e9e: 687b ldr r3, [r7, #4] + 8002ea0: 2212 movs r2, #18 + 8002ea2: 631a str r2, [r3, #48] ; 0x30 + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8002ea4: 687b ldr r3, [r7, #4] + 8002ea6: 681b ldr r3, [r3, #0] + 8002ea8: 685a ldr r2, [r3, #4] + 8002eaa: 687b ldr r3, [r7, #4] + 8002eac: 681b ldr r3, [r3, #0] + 8002eae: 494e ldr r1, [pc, #312] ; (8002fe8 ) + 8002eb0: 400a ands r2, r1 + 8002eb2: 605a str r2, [r3, #4] + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + 8002eb4: 687b ldr r3, [r7, #4] + 8002eb6: 2200 movs r2, #0 + 8002eb8: 635a str r2, [r3, #52] ; 0x34 + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 8002eba: 687b ldr r3, [r7, #4] + 8002ebc: 4a4b ldr r2, [pc, #300] ; (8002fec ) + 8002ebe: 62da str r2, [r3, #44] ; 0x2c + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + 8002ec0: 697b ldr r3, [r7, #20] + 8002ec2: 2210 movs r2, #16 + 8002ec4: 4013 ands r3, r2 + 8002ec6: d009 beq.n 8002edc + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8002ec8: 687b ldr r3, [r7, #4] + 8002eca: 681b ldr r3, [r3, #0] + 8002ecc: 2210 movs r2, #16 + 8002ece: 61da str r2, [r3, #28] + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 8002ed0: 687b ldr r3, [r7, #4] + 8002ed2: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002ed4: 2204 movs r2, #4 + 8002ed6: 431a orrs r2, r3 + 8002ed8: 687b ldr r3, [r7, #4] + 8002eda: 645a str r2, [r3, #68] ; 0x44 + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + 8002edc: 687b ldr r3, [r7, #4] + 8002ede: 2241 movs r2, #65 ; 0x41 + 8002ee0: 5c9b ldrb r3, [r3, r2] + 8002ee2: b2db uxtb r3, r3 + 8002ee4: 2b60 cmp r3, #96 ; 0x60 + 8002ee6: d109 bne.n 8002efc + 8002ee8: 697b ldr r3, [r7, #20] + 8002eea: 2204 movs r2, #4 + 8002eec: 4013 ands r3, r2 + 8002eee: d005 beq.n 8002efc + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + 8002ef0: 687b ldr r3, [r7, #4] + 8002ef2: 681b ldr r3, [r3, #0] + 8002ef4: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002ef6: b2db uxtb r3, r3 + 8002ef8: 60fb str r3, [r7, #12] + UNUSED(tmpreg); + 8002efa: 68fb ldr r3, [r7, #12] + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 8002efc: 687b ldr r3, [r7, #4] + 8002efe: 0018 movs r0, r3 + 8002f00: f000 fb81 bl 8003606 + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + 8002f04: 687b ldr r3, [r7, #4] + 8002f06: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002f08: 613b str r3, [r7, #16] + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + 8002f0a: 687b ldr r3, [r7, #4] + 8002f0c: 2241 movs r2, #65 ; 0x41 + 8002f0e: 5c9b ldrb r3, [r3, r2] + 8002f10: b2db uxtb r3, r3 + 8002f12: 2b60 cmp r3, #96 ; 0x60 + 8002f14: d002 beq.n 8002f1c + 8002f16: 693b ldr r3, [r7, #16] + 8002f18: 2b00 cmp r3, #0 + 8002f1a: d007 beq.n 8002f2c + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + 8002f1c: 687b ldr r3, [r7, #4] + 8002f1e: 6c5a ldr r2, [r3, #68] ; 0x44 + 8002f20: 687b ldr r3, [r7, #4] + 8002f22: 0011 movs r1, r2 + 8002f24: 0018 movs r0, r3 + 8002f26: f000 fa43 bl 80033b0 + } + else + { + /* Nothing to do */ + } +} + 8002f2a: e058 b.n 8002fde + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + 8002f2c: 687b ldr r3, [r7, #4] + 8002f2e: 2241 movs r2, #65 ; 0x41 + 8002f30: 5c9b ldrb r3, [r3, r2] + 8002f32: b2db uxtb r3, r3 + 8002f34: 2b21 cmp r3, #33 ; 0x21 + 8002f36: d126 bne.n 8002f86 + hi2c->State = HAL_I2C_STATE_READY; + 8002f38: 687b ldr r3, [r7, #4] + 8002f3a: 2241 movs r2, #65 ; 0x41 + 8002f3c: 2120 movs r1, #32 + 8002f3e: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_NONE; + 8002f40: 687b ldr r3, [r7, #4] + 8002f42: 2200 movs r2, #0 + 8002f44: 631a str r2, [r3, #48] ; 0x30 + if (hi2c->Mode == HAL_I2C_MODE_MEM) + 8002f46: 687b ldr r3, [r7, #4] + 8002f48: 2242 movs r2, #66 ; 0x42 + 8002f4a: 5c9b ldrb r3, [r3, r2] + 8002f4c: b2db uxtb r3, r3 + 8002f4e: 2b40 cmp r3, #64 ; 0x40 + 8002f50: d10c bne.n 8002f6c + hi2c->Mode = HAL_I2C_MODE_NONE; + 8002f52: 687b ldr r3, [r7, #4] + 8002f54: 2242 movs r2, #66 ; 0x42 + 8002f56: 2100 movs r1, #0 + 8002f58: 5499 strb r1, [r3, r2] + __HAL_UNLOCK(hi2c); + 8002f5a: 687b ldr r3, [r7, #4] + 8002f5c: 2240 movs r2, #64 ; 0x40 + 8002f5e: 2100 movs r1, #0 + 8002f60: 5499 strb r1, [r3, r2] + HAL_I2C_MemTxCpltCallback(hi2c); + 8002f62: 687b ldr r3, [r7, #4] + 8002f64: 0018 movs r0, r3 + 8002f66: f7ff f8c7 bl 80020f8 +} + 8002f6a: e038 b.n 8002fde + hi2c->Mode = HAL_I2C_MODE_NONE; + 8002f6c: 687b ldr r3, [r7, #4] + 8002f6e: 2242 movs r2, #66 ; 0x42 + 8002f70: 2100 movs r1, #0 + 8002f72: 5499 strb r1, [r3, r2] + __HAL_UNLOCK(hi2c); + 8002f74: 687b ldr r3, [r7, #4] + 8002f76: 2240 movs r2, #64 ; 0x40 + 8002f78: 2100 movs r1, #0 + 8002f7a: 5499 strb r1, [r3, r2] + HAL_I2C_MasterTxCpltCallback(hi2c); + 8002f7c: 687b ldr r3, [r7, #4] + 8002f7e: 0018 movs r0, r3 + 8002f80: f7ff f882 bl 8002088 +} + 8002f84: e02b b.n 8002fde + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 8002f86: 687b ldr r3, [r7, #4] + 8002f88: 2241 movs r2, #65 ; 0x41 + 8002f8a: 5c9b ldrb r3, [r3, r2] + 8002f8c: b2db uxtb r3, r3 + 8002f8e: 2b22 cmp r3, #34 ; 0x22 + 8002f90: d125 bne.n 8002fde + hi2c->State = HAL_I2C_STATE_READY; + 8002f92: 687b ldr r3, [r7, #4] + 8002f94: 2241 movs r2, #65 ; 0x41 + 8002f96: 2120 movs r1, #32 + 8002f98: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_NONE; + 8002f9a: 687b ldr r3, [r7, #4] + 8002f9c: 2200 movs r2, #0 + 8002f9e: 631a str r2, [r3, #48] ; 0x30 + if (hi2c->Mode == HAL_I2C_MODE_MEM) + 8002fa0: 687b ldr r3, [r7, #4] + 8002fa2: 2242 movs r2, #66 ; 0x42 + 8002fa4: 5c9b ldrb r3, [r3, r2] + 8002fa6: b2db uxtb r3, r3 + 8002fa8: 2b40 cmp r3, #64 ; 0x40 + 8002faa: d10c bne.n 8002fc6 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8002fac: 687b ldr r3, [r7, #4] + 8002fae: 2242 movs r2, #66 ; 0x42 + 8002fb0: 2100 movs r1, #0 + 8002fb2: 5499 strb r1, [r3, r2] + __HAL_UNLOCK(hi2c); + 8002fb4: 687b ldr r3, [r7, #4] + 8002fb6: 2240 movs r2, #64 ; 0x40 + 8002fb8: 2100 movs r1, #0 + 8002fba: 5499 strb r1, [r3, r2] + HAL_I2C_MemRxCpltCallback(hi2c); + 8002fbc: 687b ldr r3, [r7, #4] + 8002fbe: 0018 movs r0, r3 + 8002fc0: f7ff f8a2 bl 8002108 +} + 8002fc4: e00b b.n 8002fde + hi2c->Mode = HAL_I2C_MODE_NONE; + 8002fc6: 687b ldr r3, [r7, #4] + 8002fc8: 2242 movs r2, #66 ; 0x42 + 8002fca: 2100 movs r1, #0 + 8002fcc: 5499 strb r1, [r3, r2] + __HAL_UNLOCK(hi2c); + 8002fce: 687b ldr r3, [r7, #4] + 8002fd0: 2240 movs r2, #64 ; 0x40 + 8002fd2: 2100 movs r1, #0 + 8002fd4: 5499 strb r1, [r3, r2] + HAL_I2C_MasterRxCpltCallback(hi2c); + 8002fd6: 687b ldr r3, [r7, #4] + 8002fd8: 0018 movs r0, r3 + 8002fda: f7ff f85d bl 8002098 +} + 8002fde: 46c0 nop ; (mov r8, r8) + 8002fe0: 46bd mov sp, r7 + 8002fe2: b006 add sp, #24 + 8002fe4: bd80 pop {r7, pc} + 8002fe6: 46c0 nop ; (mov r8, r8) + 8002fe8: fe00e800 .word 0xfe00e800 + 8002fec: ffff0000 .word 0xffff0000 + +08002ff0 : + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + 8002ff0: b580 push {r7, lr} + 8002ff2: b086 sub sp, #24 + 8002ff4: af00 add r7, sp, #0 + 8002ff6: 6078 str r0, [r7, #4] + 8002ff8: 6039 str r1, [r7, #0] + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 8002ffa: 687b ldr r3, [r7, #4] + 8002ffc: 681b ldr r3, [r3, #0] + 8002ffe: 681b ldr r3, [r3, #0] + 8003000: 613b str r3, [r7, #16] + uint32_t tmpITFlags = ITFlags; + 8003002: 683b ldr r3, [r7, #0] + 8003004: 617b str r3, [r7, #20] + uint32_t tmpoptions = hi2c->XferOptions; + 8003006: 687b ldr r3, [r7, #4] + 8003008: 6adb ldr r3, [r3, #44] ; 0x2c + 800300a: 60fb str r3, [r7, #12] + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 800300c: 200b movs r0, #11 + 800300e: 183b adds r3, r7, r0 + 8003010: 687a ldr r2, [r7, #4] + 8003012: 2141 movs r1, #65 ; 0x41 + 8003014: 5c52 ldrb r2, [r2, r1] + 8003016: 701a strb r2, [r3, #0] + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8003018: 687b ldr r3, [r7, #4] + 800301a: 681b ldr r3, [r3, #0] + 800301c: 2220 movs r2, #32 + 800301e: 61da str r2, [r3, #28] + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + 8003020: 183b adds r3, r7, r0 + 8003022: 781b ldrb r3, [r3, #0] + 8003024: 2b21 cmp r3, #33 ; 0x21 + 8003026: d003 beq.n 8003030 + 8003028: 183b adds r3, r7, r0 + 800302a: 781b ldrb r3, [r3, #0] + 800302c: 2b29 cmp r3, #41 ; 0x29 + 800302e: d109 bne.n 8003044 + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + 8003030: 4aac ldr r2, [pc, #688] ; (80032e4 ) + 8003032: 687b ldr r3, [r7, #4] + 8003034: 0011 movs r1, r2 + 8003036: 0018 movs r0, r3 + 8003038: f000 ff24 bl 8003e84 + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 800303c: 687b ldr r3, [r7, #4] + 800303e: 2221 movs r2, #33 ; 0x21 + 8003040: 631a str r2, [r3, #48] ; 0x30 + 8003042: e020 b.n 8003086 + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 8003044: 220b movs r2, #11 + 8003046: 18bb adds r3, r7, r2 + 8003048: 781b ldrb r3, [r3, #0] + 800304a: 2b22 cmp r3, #34 ; 0x22 + 800304c: d003 beq.n 8003056 + 800304e: 18bb adds r3, r7, r2 + 8003050: 781b ldrb r3, [r3, #0] + 8003052: 2b2a cmp r3, #42 ; 0x2a + 8003054: d109 bne.n 800306a + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + 8003056: 4aa4 ldr r2, [pc, #656] ; (80032e8 ) + 8003058: 687b ldr r3, [r7, #4] + 800305a: 0011 movs r1, r2 + 800305c: 0018 movs r0, r3 + 800305e: f000 ff11 bl 8003e84 + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 8003062: 687b ldr r3, [r7, #4] + 8003064: 2222 movs r2, #34 ; 0x22 + 8003066: 631a str r2, [r3, #48] ; 0x30 + 8003068: e00d b.n 8003086 + } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + 800306a: 230b movs r3, #11 + 800306c: 18fb adds r3, r7, r3 + 800306e: 781b ldrb r3, [r3, #0] + 8003070: 2b28 cmp r3, #40 ; 0x28 + 8003072: d108 bne.n 8003086 + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + 8003074: 4a9d ldr r2, [pc, #628] ; (80032ec ) + 8003076: 687b ldr r3, [r7, #4] + 8003078: 0011 movs r1, r2 + 800307a: 0018 movs r0, r3 + 800307c: f000 ff02 bl 8003e84 + hi2c->PreviousState = I2C_STATE_NONE; + 8003080: 687b ldr r3, [r7, #4] + 8003082: 2200 movs r2, #0 + 8003084: 631a str r2, [r3, #48] ; 0x30 + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + 8003086: 687b ldr r3, [r7, #4] + 8003088: 681b ldr r3, [r3, #0] + 800308a: 685a ldr r2, [r3, #4] + 800308c: 687b ldr r3, [r7, #4] + 800308e: 681b ldr r3, [r3, #0] + 8003090: 2180 movs r1, #128 ; 0x80 + 8003092: 0209 lsls r1, r1, #8 + 8003094: 430a orrs r2, r1 + 8003096: 605a str r2, [r3, #4] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8003098: 687b ldr r3, [r7, #4] + 800309a: 681b ldr r3, [r3, #0] + 800309c: 685a ldr r2, [r3, #4] + 800309e: 687b ldr r3, [r7, #4] + 80030a0: 681b ldr r3, [r3, #0] + 80030a2: 4993 ldr r1, [pc, #588] ; (80032f0 ) + 80030a4: 400a ands r2, r1 + 80030a6: 605a str r2, [r3, #4] + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 80030a8: 687b ldr r3, [r7, #4] + 80030aa: 0018 movs r0, r3 + 80030ac: f000 faab bl 8003606 + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + 80030b0: 693a ldr r2, [r7, #16] + 80030b2: 2380 movs r3, #128 ; 0x80 + 80030b4: 01db lsls r3, r3, #7 + 80030b6: 4013 ands r3, r2 + 80030b8: d013 beq.n 80030e2 + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 80030ba: 687b ldr r3, [r7, #4] + 80030bc: 681b ldr r3, [r3, #0] + 80030be: 681a ldr r2, [r3, #0] + 80030c0: 687b ldr r3, [r7, #4] + 80030c2: 681b ldr r3, [r3, #0] + 80030c4: 498b ldr r1, [pc, #556] ; (80032f4 ) + 80030c6: 400a ands r2, r1 + 80030c8: 601a str r2, [r3, #0] + + if (hi2c->hdmatx != NULL) + 80030ca: 687b ldr r3, [r7, #4] + 80030cc: 6b9b ldr r3, [r3, #56] ; 0x38 + 80030ce: 2b00 cmp r3, #0 + 80030d0: d01f beq.n 8003112 + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + 80030d2: 687b ldr r3, [r7, #4] + 80030d4: 6b9b ldr r3, [r3, #56] ; 0x38 + 80030d6: 681b ldr r3, [r3, #0] + 80030d8: 685b ldr r3, [r3, #4] + 80030da: b29a uxth r2, r3 + 80030dc: 687b ldr r3, [r7, #4] + 80030de: 855a strh r2, [r3, #42] ; 0x2a + 80030e0: e017 b.n 8003112 + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + 80030e2: 693a ldr r2, [r7, #16] + 80030e4: 2380 movs r3, #128 ; 0x80 + 80030e6: 021b lsls r3, r3, #8 + 80030e8: 4013 ands r3, r2 + 80030ea: d012 beq.n 8003112 + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 80030ec: 687b ldr r3, [r7, #4] + 80030ee: 681b ldr r3, [r3, #0] + 80030f0: 681a ldr r2, [r3, #0] + 80030f2: 687b ldr r3, [r7, #4] + 80030f4: 681b ldr r3, [r3, #0] + 80030f6: 4980 ldr r1, [pc, #512] ; (80032f8 ) + 80030f8: 400a ands r2, r1 + 80030fa: 601a str r2, [r3, #0] + + if (hi2c->hdmarx != NULL) + 80030fc: 687b ldr r3, [r7, #4] + 80030fe: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003100: 2b00 cmp r3, #0 + 8003102: d006 beq.n 8003112 + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + 8003104: 687b ldr r3, [r7, #4] + 8003106: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003108: 681b ldr r3, [r3, #0] + 800310a: 685b ldr r3, [r3, #4] + 800310c: b29a uxth r2, r3 + 800310e: 687b ldr r3, [r7, #4] + 8003110: 855a strh r2, [r3, #42] ; 0x2a + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + 8003112: 697b ldr r3, [r7, #20] + 8003114: 2204 movs r2, #4 + 8003116: 4013 ands r3, r2 + 8003118: d020 beq.n 800315c + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + 800311a: 697b ldr r3, [r7, #20] + 800311c: 2204 movs r2, #4 + 800311e: 4393 bics r3, r2 + 8003120: 617b str r3, [r7, #20] + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 8003122: 687b ldr r3, [r7, #4] + 8003124: 681b ldr r3, [r3, #0] + 8003126: 6a5a ldr r2, [r3, #36] ; 0x24 + 8003128: 687b ldr r3, [r7, #4] + 800312a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800312c: b2d2 uxtb r2, r2 + 800312e: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8003130: 687b ldr r3, [r7, #4] + 8003132: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003134: 1c5a adds r2, r3, #1 + 8003136: 687b ldr r3, [r7, #4] + 8003138: 625a str r2, [r3, #36] ; 0x24 + + if ((hi2c->XferSize > 0U)) + 800313a: 687b ldr r3, [r7, #4] + 800313c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800313e: 2b00 cmp r3, #0 + 8003140: d00c beq.n 800315c + { + hi2c->XferSize--; + 8003142: 687b ldr r3, [r7, #4] + 8003144: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003146: 3b01 subs r3, #1 + 8003148: b29a uxth r2, r3 + 800314a: 687b ldr r3, [r7, #4] + 800314c: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 800314e: 687b ldr r3, [r7, #4] + 8003150: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003152: b29b uxth r3, r3 + 8003154: 3b01 subs r3, #1 + 8003156: b29a uxth r2, r3 + 8003158: 687b ldr r3, [r7, #4] + 800315a: 855a strh r2, [r3, #42] ; 0x2a + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + 800315c: 687b ldr r3, [r7, #4] + 800315e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003160: b29b uxth r3, r3 + 8003162: 2b00 cmp r3, #0 + 8003164: d005 beq.n 8003172 + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 8003166: 687b ldr r3, [r7, #4] + 8003168: 6c5b ldr r3, [r3, #68] ; 0x44 + 800316a: 2204 movs r2, #4 + 800316c: 431a orrs r2, r3 + 800316e: 687b ldr r3, [r7, #4] + 8003170: 645a str r2, [r3, #68] ; 0x44 + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 8003172: 697b ldr r3, [r7, #20] + 8003174: 2210 movs r2, #16 + 8003176: 4013 ands r3, r2 + 8003178: d04f beq.n 800321a + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + 800317a: 693b ldr r3, [r7, #16] + 800317c: 2210 movs r2, #16 + 800317e: 4013 ands r3, r2 + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 8003180: d04b beq.n 800321a + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + 8003182: 687b ldr r3, [r7, #4] + 8003184: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003186: b29b uxth r3, r3 + 8003188: 2b00 cmp r3, #0 + 800318a: d12d bne.n 80031e8 + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + 800318c: 687b ldr r3, [r7, #4] + 800318e: 2241 movs r2, #65 ; 0x41 + 8003190: 5c9b ldrb r3, [r3, r2] + 8003192: b2db uxtb r3, r3 + 8003194: 2b28 cmp r3, #40 ; 0x28 + 8003196: d10b bne.n 80031b0 + 8003198: 68fa ldr r2, [r7, #12] + 800319a: 2380 movs r3, #128 ; 0x80 + 800319c: 049b lsls r3, r3, #18 + 800319e: 429a cmp r2, r3 + 80031a0: d106 bne.n 80031b0 + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + 80031a2: 697a ldr r2, [r7, #20] + 80031a4: 687b ldr r3, [r7, #4] + 80031a6: 0011 movs r1, r2 + 80031a8: 0018 movs r0, r3 + 80031aa: f000 f8a9 bl 8003300 + 80031ae: e034 b.n 800321a + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + 80031b0: 687b ldr r3, [r7, #4] + 80031b2: 2241 movs r2, #65 ; 0x41 + 80031b4: 5c9b ldrb r3, [r3, r2] + 80031b6: b2db uxtb r3, r3 + 80031b8: 2b29 cmp r3, #41 ; 0x29 + 80031ba: d110 bne.n 80031de + 80031bc: 68fb ldr r3, [r7, #12] + 80031be: 4a4f ldr r2, [pc, #316] ; (80032fc ) + 80031c0: 4293 cmp r3, r2 + 80031c2: d00c beq.n 80031de + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 80031c4: 687b ldr r3, [r7, #4] + 80031c6: 681b ldr r3, [r3, #0] + 80031c8: 2210 movs r2, #16 + 80031ca: 61da str r2, [r3, #28] + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 80031cc: 687b ldr r3, [r7, #4] + 80031ce: 0018 movs r0, r3 + 80031d0: f000 fa19 bl 8003606 + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + 80031d4: 687b ldr r3, [r7, #4] + 80031d6: 0018 movs r0, r3 + 80031d8: f7ff fdd8 bl 8002d8c + 80031dc: e01d b.n 800321a + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 80031de: 687b ldr r3, [r7, #4] + 80031e0: 681b ldr r3, [r3, #0] + 80031e2: 2210 movs r2, #16 + 80031e4: 61da str r2, [r3, #28] + 80031e6: e018 b.n 800321a + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 80031e8: 687b ldr r3, [r7, #4] + 80031ea: 681b ldr r3, [r3, #0] + 80031ec: 2210 movs r2, #16 + 80031ee: 61da str r2, [r3, #28] + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 80031f0: 687b ldr r3, [r7, #4] + 80031f2: 6c5b ldr r3, [r3, #68] ; 0x44 + 80031f4: 2204 movs r2, #4 + 80031f6: 431a orrs r2, r3 + 80031f8: 687b ldr r3, [r7, #4] + 80031fa: 645a str r2, [r3, #68] ; 0x44 + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + 80031fc: 68fb ldr r3, [r7, #12] + 80031fe: 2b00 cmp r3, #0 + 8003200: d004 beq.n 800320c + 8003202: 68fa ldr r2, [r7, #12] + 8003204: 2380 movs r3, #128 ; 0x80 + 8003206: 045b lsls r3, r3, #17 + 8003208: 429a cmp r2, r3 + 800320a: d106 bne.n 800321a + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + 800320c: 687b ldr r3, [r7, #4] + 800320e: 6c5a ldr r2, [r3, #68] ; 0x44 + 8003210: 687b ldr r3, [r7, #4] + 8003212: 0011 movs r1, r2 + 8003214: 0018 movs r0, r3 + 8003216: f000 f8cb bl 80033b0 + } + } + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + 800321a: 687b ldr r3, [r7, #4] + 800321c: 2242 movs r2, #66 ; 0x42 + 800321e: 2100 movs r1, #0 + 8003220: 5499 strb r1, [r3, r2] + hi2c->XferISR = NULL; + 8003222: 687b ldr r3, [r7, #4] + 8003224: 2200 movs r2, #0 + 8003226: 635a str r2, [r3, #52] ; 0x34 + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + 8003228: 687b ldr r3, [r7, #4] + 800322a: 6c5b ldr r3, [r3, #68] ; 0x44 + 800322c: 2b00 cmp r3, #0 + 800322e: d013 beq.n 8003258 + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + 8003230: 687b ldr r3, [r7, #4] + 8003232: 6c5a ldr r2, [r3, #68] ; 0x44 + 8003234: 687b ldr r3, [r7, #4] + 8003236: 0011 movs r1, r2 + 8003238: 0018 movs r0, r3 + 800323a: f000 f8b9 bl 80033b0 + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + 800323e: 687b ldr r3, [r7, #4] + 8003240: 2241 movs r2, #65 ; 0x41 + 8003242: 5c9b ldrb r3, [r3, r2] + 8003244: b2db uxtb r3, r3 + 8003246: 2b28 cmp r3, #40 ; 0x28 + 8003248: d147 bne.n 80032da + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + 800324a: 697a ldr r2, [r7, #20] + 800324c: 687b ldr r3, [r7, #4] + 800324e: 0011 movs r1, r2 + 8003250: 0018 movs r0, r3 + 8003252: f000 f855 bl 8003300 + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + 8003256: e040 b.n 80032da + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 8003258: 687b ldr r3, [r7, #4] + 800325a: 6adb ldr r3, [r3, #44] ; 0x2c + 800325c: 4a27 ldr r2, [pc, #156] ; (80032fc ) + 800325e: 4293 cmp r3, r2 + 8003260: d016 beq.n 8003290 + I2C_ITSlaveSeqCplt(hi2c); + 8003262: 687b ldr r3, [r7, #4] + 8003264: 0018 movs r0, r3 + 8003266: f7ff fd91 bl 8002d8c + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 800326a: 687b ldr r3, [r7, #4] + 800326c: 4a23 ldr r2, [pc, #140] ; (80032fc ) + 800326e: 62da str r2, [r3, #44] ; 0x2c + hi2c->State = HAL_I2C_STATE_READY; + 8003270: 687b ldr r3, [r7, #4] + 8003272: 2241 movs r2, #65 ; 0x41 + 8003274: 2120 movs r1, #32 + 8003276: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_NONE; + 8003278: 687b ldr r3, [r7, #4] + 800327a: 2200 movs r2, #0 + 800327c: 631a str r2, [r3, #48] ; 0x30 + __HAL_UNLOCK(hi2c); + 800327e: 687b ldr r3, [r7, #4] + 8003280: 2240 movs r2, #64 ; 0x40 + 8003282: 2100 movs r1, #0 + 8003284: 5499 strb r1, [r3, r2] + HAL_I2C_ListenCpltCallback(hi2c); + 8003286: 687b ldr r3, [r7, #4] + 8003288: 0018 movs r0, r3 + 800328a: f7fe ff2d bl 80020e8 +} + 800328e: e024 b.n 80032da + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 8003290: 687b ldr r3, [r7, #4] + 8003292: 2241 movs r2, #65 ; 0x41 + 8003294: 5c9b ldrb r3, [r3, r2] + 8003296: b2db uxtb r3, r3 + 8003298: 2b22 cmp r3, #34 ; 0x22 + 800329a: d10f bne.n 80032bc + hi2c->State = HAL_I2C_STATE_READY; + 800329c: 687b ldr r3, [r7, #4] + 800329e: 2241 movs r2, #65 ; 0x41 + 80032a0: 2120 movs r1, #32 + 80032a2: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_NONE; + 80032a4: 687b ldr r3, [r7, #4] + 80032a6: 2200 movs r2, #0 + 80032a8: 631a str r2, [r3, #48] ; 0x30 + __HAL_UNLOCK(hi2c); + 80032aa: 687b ldr r3, [r7, #4] + 80032ac: 2240 movs r2, #64 ; 0x40 + 80032ae: 2100 movs r1, #0 + 80032b0: 5499 strb r1, [r3, r2] + HAL_I2C_SlaveRxCpltCallback(hi2c); + 80032b2: 687b ldr r3, [r7, #4] + 80032b4: 0018 movs r0, r3 + 80032b6: f7fe feff bl 80020b8 +} + 80032ba: e00e b.n 80032da + hi2c->State = HAL_I2C_STATE_READY; + 80032bc: 687b ldr r3, [r7, #4] + 80032be: 2241 movs r2, #65 ; 0x41 + 80032c0: 2120 movs r1, #32 + 80032c2: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_NONE; + 80032c4: 687b ldr r3, [r7, #4] + 80032c6: 2200 movs r2, #0 + 80032c8: 631a str r2, [r3, #48] ; 0x30 + __HAL_UNLOCK(hi2c); + 80032ca: 687b ldr r3, [r7, #4] + 80032cc: 2240 movs r2, #64 ; 0x40 + 80032ce: 2100 movs r1, #0 + 80032d0: 5499 strb r1, [r3, r2] + HAL_I2C_SlaveTxCpltCallback(hi2c); + 80032d2: 687b ldr r3, [r7, #4] + 80032d4: 0018 movs r0, r3 + 80032d6: f7fe fee7 bl 80020a8 +} + 80032da: 46c0 nop ; (mov r8, r8) + 80032dc: 46bd mov sp, r7 + 80032de: b006 add sp, #24 + 80032e0: bd80 pop {r7, pc} + 80032e2: 46c0 nop ; (mov r8, r8) + 80032e4: 00008001 .word 0x00008001 + 80032e8: 00008002 .word 0x00008002 + 80032ec: 00008003 .word 0x00008003 + 80032f0: fe00e800 .word 0xfe00e800 + 80032f4: ffffbfff .word 0xffffbfff + 80032f8: ffff7fff .word 0xffff7fff + 80032fc: ffff0000 .word 0xffff0000 + +08003300 : + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + 8003300: b580 push {r7, lr} + 8003302: b082 sub sp, #8 + 8003304: af00 add r7, sp, #0 + 8003306: 6078 str r0, [r7, #4] + 8003308: 6039 str r1, [r7, #0] + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 800330a: 687b ldr r3, [r7, #4] + 800330c: 4a26 ldr r2, [pc, #152] ; (80033a8 ) + 800330e: 62da str r2, [r3, #44] ; 0x2c + hi2c->PreviousState = I2C_STATE_NONE; + 8003310: 687b ldr r3, [r7, #4] + 8003312: 2200 movs r2, #0 + 8003314: 631a str r2, [r3, #48] ; 0x30 + hi2c->State = HAL_I2C_STATE_READY; + 8003316: 687b ldr r3, [r7, #4] + 8003318: 2241 movs r2, #65 ; 0x41 + 800331a: 2120 movs r1, #32 + 800331c: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 800331e: 687b ldr r3, [r7, #4] + 8003320: 2242 movs r2, #66 ; 0x42 + 8003322: 2100 movs r1, #0 + 8003324: 5499 strb r1, [r3, r2] + hi2c->XferISR = NULL; + 8003326: 687b ldr r3, [r7, #4] + 8003328: 2200 movs r2, #0 + 800332a: 635a str r2, [r3, #52] ; 0x34 + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + 800332c: 683b ldr r3, [r7, #0] + 800332e: 2204 movs r2, #4 + 8003330: 4013 ands r3, r2 + 8003332: d022 beq.n 800337a + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 8003334: 687b ldr r3, [r7, #4] + 8003336: 681b ldr r3, [r3, #0] + 8003338: 6a5a ldr r2, [r3, #36] ; 0x24 + 800333a: 687b ldr r3, [r7, #4] + 800333c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800333e: b2d2 uxtb r2, r2 + 8003340: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8003342: 687b ldr r3, [r7, #4] + 8003344: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003346: 1c5a adds r2, r3, #1 + 8003348: 687b ldr r3, [r7, #4] + 800334a: 625a str r2, [r3, #36] ; 0x24 + + if ((hi2c->XferSize > 0U)) + 800334c: 687b ldr r3, [r7, #4] + 800334e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003350: 2b00 cmp r3, #0 + 8003352: d012 beq.n 800337a + { + hi2c->XferSize--; + 8003354: 687b ldr r3, [r7, #4] + 8003356: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003358: 3b01 subs r3, #1 + 800335a: b29a uxth r2, r3 + 800335c: 687b ldr r3, [r7, #4] + 800335e: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8003360: 687b ldr r3, [r7, #4] + 8003362: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003364: b29b uxth r3, r3 + 8003366: 3b01 subs r3, #1 + 8003368: b29a uxth r2, r3 + 800336a: 687b ldr r3, [r7, #4] + 800336c: 855a strh r2, [r3, #42] ; 0x2a + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 800336e: 687b ldr r3, [r7, #4] + 8003370: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003372: 2204 movs r2, #4 + 8003374: 431a orrs r2, r3 + 8003376: 687b ldr r3, [r7, #4] + 8003378: 645a str r2, [r3, #68] ; 0x44 + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + 800337a: 4a0c ldr r2, [pc, #48] ; (80033ac ) + 800337c: 687b ldr r3, [r7, #4] + 800337e: 0011 movs r1, r2 + 8003380: 0018 movs r0, r3 + 8003382: f000 fd7f bl 8003e84 + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8003386: 687b ldr r3, [r7, #4] + 8003388: 681b ldr r3, [r3, #0] + 800338a: 2210 movs r2, #16 + 800338c: 61da str r2, [r3, #28] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800338e: 687b ldr r3, [r7, #4] + 8003390: 2240 movs r2, #64 ; 0x40 + 8003392: 2100 movs r1, #0 + 8003394: 5499 strb r1, [r3, r2] + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); + 8003396: 687b ldr r3, [r7, #4] + 8003398: 0018 movs r0, r3 + 800339a: f7fe fea5 bl 80020e8 +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + 800339e: 46c0 nop ; (mov r8, r8) + 80033a0: 46bd mov sp, r7 + 80033a2: b002 add sp, #8 + 80033a4: bd80 pop {r7, pc} + 80033a6: 46c0 nop ; (mov r8, r8) + 80033a8: ffff0000 .word 0xffff0000 + 80033ac: 00008003 .word 0x00008003 + +080033b0 : + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + 80033b0: b580 push {r7, lr} + 80033b2: b084 sub sp, #16 + 80033b4: af00 add r7, sp, #0 + 80033b6: 6078 str r0, [r7, #4] + 80033b8: 6039 str r1, [r7, #0] + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 80033ba: 200f movs r0, #15 + 80033bc: 183b adds r3, r7, r0 + 80033be: 687a ldr r2, [r7, #4] + 80033c0: 2141 movs r1, #65 ; 0x41 + 80033c2: 5c52 ldrb r2, [r2, r1] + 80033c4: 701a strb r2, [r3, #0] + + uint32_t tmppreviousstate; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + 80033c6: 687b ldr r3, [r7, #4] + 80033c8: 2242 movs r2, #66 ; 0x42 + 80033ca: 2100 movs r1, #0 + 80033cc: 5499 strb r1, [r3, r2] + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 80033ce: 687b ldr r3, [r7, #4] + 80033d0: 4a72 ldr r2, [pc, #456] ; (800359c ) + 80033d2: 62da str r2, [r3, #44] ; 0x2c + hi2c->XferCount = 0U; + 80033d4: 687b ldr r3, [r7, #4] + 80033d6: 2200 movs r2, #0 + 80033d8: 855a strh r2, [r3, #42] ; 0x2a + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + 80033da: 687b ldr r3, [r7, #4] + 80033dc: 6c5a ldr r2, [r3, #68] ; 0x44 + 80033de: 683b ldr r3, [r7, #0] + 80033e0: 431a orrs r2, r3 + 80033e2: 687b ldr r3, [r7, #4] + 80033e4: 645a str r2, [r3, #68] ; 0x44 + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + 80033e6: 183b adds r3, r7, r0 + 80033e8: 781b ldrb r3, [r3, #0] + 80033ea: 2b28 cmp r3, #40 ; 0x28 + 80033ec: d007 beq.n 80033fe + 80033ee: 183b adds r3, r7, r0 + 80033f0: 781b ldrb r3, [r3, #0] + 80033f2: 2b29 cmp r3, #41 ; 0x29 + 80033f4: d003 beq.n 80033fe + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 80033f6: 183b adds r3, r7, r0 + 80033f8: 781b ldrb r3, [r3, #0] + 80033fa: 2b2a cmp r3, #42 ; 0x2a + 80033fc: d10c bne.n 8003418 + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + 80033fe: 687b ldr r3, [r7, #4] + 8003400: 2103 movs r1, #3 + 8003402: 0018 movs r0, r3 + 8003404: f000 fd3e bl 8003e84 + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + 8003408: 687b ldr r3, [r7, #4] + 800340a: 2241 movs r2, #65 ; 0x41 + 800340c: 2128 movs r1, #40 ; 0x28 + 800340e: 5499 strb r1, [r3, r2] + hi2c->XferISR = I2C_Slave_ISR_IT; + 8003410: 687b ldr r3, [r7, #4] + 8003412: 4a63 ldr r2, [pc, #396] ; (80035a0 ) + 8003414: 635a str r2, [r3, #52] ; 0x34 + 8003416: e032 b.n 800347e + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + 8003418: 4a62 ldr r2, [pc, #392] ; (80035a4 ) + 800341a: 687b ldr r3, [r7, #4] + 800341c: 0011 movs r1, r2 + 800341e: 0018 movs r0, r3 + 8003420: f000 fd30 bl 8003e84 + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 8003424: 687b ldr r3, [r7, #4] + 8003426: 0018 movs r0, r3 + 8003428: f000 f8ed bl 8003606 + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + 800342c: 687b ldr r3, [r7, #4] + 800342e: 2241 movs r2, #65 ; 0x41 + 8003430: 5c9b ldrb r3, [r3, r2] + 8003432: b2db uxtb r3, r3 + 8003434: 2b60 cmp r3, #96 ; 0x60 + 8003436: d01f beq.n 8003478 + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + 8003438: 687b ldr r3, [r7, #4] + 800343a: 2241 movs r2, #65 ; 0x41 + 800343c: 2120 movs r1, #32 + 800343e: 5499 strb r1, [r3, r2] + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + 8003440: 687b ldr r3, [r7, #4] + 8003442: 681b ldr r3, [r3, #0] + 8003444: 699b ldr r3, [r3, #24] + 8003446: 2220 movs r2, #32 + 8003448: 4013 ands r3, r2 + 800344a: 2b20 cmp r3, #32 + 800344c: d114 bne.n 8003478 + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 800344e: 687b ldr r3, [r7, #4] + 8003450: 681b ldr r3, [r3, #0] + 8003452: 699b ldr r3, [r3, #24] + 8003454: 2210 movs r2, #16 + 8003456: 4013 ands r3, r2 + 8003458: 2b10 cmp r3, #16 + 800345a: d109 bne.n 8003470 + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 800345c: 687b ldr r3, [r7, #4] + 800345e: 681b ldr r3, [r3, #0] + 8003460: 2210 movs r2, #16 + 8003462: 61da str r2, [r3, #28] + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 8003464: 687b ldr r3, [r7, #4] + 8003466: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003468: 2204 movs r2, #4 + 800346a: 431a orrs r2, r3 + 800346c: 687b ldr r3, [r7, #4] + 800346e: 645a str r2, [r3, #68] ; 0x44 + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8003470: 687b ldr r3, [r7, #4] + 8003472: 681b ldr r3, [r3, #0] + 8003474: 2220 movs r2, #32 + 8003476: 61da str r2, [r3, #28] + } + + } + hi2c->XferISR = NULL; + 8003478: 687b ldr r3, [r7, #4] + 800347a: 2200 movs r2, #0 + 800347c: 635a str r2, [r3, #52] ; 0x34 + } + + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + 800347e: 687b ldr r3, [r7, #4] + 8003480: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003482: 60bb str r3, [r7, #8] + + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + 8003484: 687b ldr r3, [r7, #4] + 8003486: 6b9b ldr r3, [r3, #56] ; 0x38 + 8003488: 2b00 cmp r3, #0 + 800348a: d03b beq.n 8003504 + 800348c: 68bb ldr r3, [r7, #8] + 800348e: 2b11 cmp r3, #17 + 8003490: d002 beq.n 8003498 + 8003492: 68bb ldr r3, [r7, #8] + 8003494: 2b21 cmp r3, #33 ; 0x21 + 8003496: d135 bne.n 8003504 + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + 8003498: 687b ldr r3, [r7, #4] + 800349a: 681b ldr r3, [r3, #0] + 800349c: 681a ldr r2, [r3, #0] + 800349e: 2380 movs r3, #128 ; 0x80 + 80034a0: 01db lsls r3, r3, #7 + 80034a2: 401a ands r2, r3 + 80034a4: 2380 movs r3, #128 ; 0x80 + 80034a6: 01db lsls r3, r3, #7 + 80034a8: 429a cmp r2, r3 + 80034aa: d107 bne.n 80034bc + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 80034ac: 687b ldr r3, [r7, #4] + 80034ae: 681b ldr r3, [r3, #0] + 80034b0: 681a ldr r2, [r3, #0] + 80034b2: 687b ldr r3, [r7, #4] + 80034b4: 681b ldr r3, [r3, #0] + 80034b6: 493c ldr r1, [pc, #240] ; (80035a8 ) + 80034b8: 400a ands r2, r1 + 80034ba: 601a str r2, [r3, #0] + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + 80034bc: 687b ldr r3, [r7, #4] + 80034be: 6b9b ldr r3, [r3, #56] ; 0x38 + 80034c0: 0018 movs r0, r3 + 80034c2: f7fd fdff bl 80010c4 + 80034c6: 0003 movs r3, r0 + 80034c8: 2b01 cmp r3, #1 + 80034ca: d016 beq.n 80034fa + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + 80034cc: 687b ldr r3, [r7, #4] + 80034ce: 6b9b ldr r3, [r3, #56] ; 0x38 + 80034d0: 4a36 ldr r2, [pc, #216] ; (80035ac ) + 80034d2: 639a str r2, [r3, #56] ; 0x38 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80034d4: 687b ldr r3, [r7, #4] + 80034d6: 2240 movs r2, #64 ; 0x40 + 80034d8: 2100 movs r1, #0 + 80034da: 5499 strb r1, [r3, r2] + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + 80034dc: 687b ldr r3, [r7, #4] + 80034de: 6b9b ldr r3, [r3, #56] ; 0x38 + 80034e0: 0018 movs r0, r3 + 80034e2: f7fd fd87 bl 8000ff4 + 80034e6: 1e03 subs r3, r0, #0 + 80034e8: d051 beq.n 800358e + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + 80034ea: 687b ldr r3, [r7, #4] + 80034ec: 6b9b ldr r3, [r3, #56] ; 0x38 + 80034ee: 6b9a ldr r2, [r3, #56] ; 0x38 + 80034f0: 687b ldr r3, [r7, #4] + 80034f2: 6b9b ldr r3, [r3, #56] ; 0x38 + 80034f4: 0018 movs r0, r3 + 80034f6: 4790 blx r2 + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + 80034f8: e049 b.n 800358e + } + } + else + { + I2C_TreatErrorCallback(hi2c); + 80034fa: 687b ldr r3, [r7, #4] + 80034fc: 0018 movs r0, r3 + 80034fe: f000 f859 bl 80035b4 + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + 8003502: e044 b.n 800358e + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + 8003504: 687b ldr r3, [r7, #4] + 8003506: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003508: 2b00 cmp r3, #0 + 800350a: d03b beq.n 8003584 + 800350c: 68bb ldr r3, [r7, #8] + 800350e: 2b12 cmp r3, #18 + 8003510: d002 beq.n 8003518 + 8003512: 68bb ldr r3, [r7, #8] + 8003514: 2b22 cmp r3, #34 ; 0x22 + 8003516: d135 bne.n 8003584 + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + 8003518: 687b ldr r3, [r7, #4] + 800351a: 681b ldr r3, [r3, #0] + 800351c: 681a ldr r2, [r3, #0] + 800351e: 2380 movs r3, #128 ; 0x80 + 8003520: 021b lsls r3, r3, #8 + 8003522: 401a ands r2, r3 + 8003524: 2380 movs r3, #128 ; 0x80 + 8003526: 021b lsls r3, r3, #8 + 8003528: 429a cmp r2, r3 + 800352a: d107 bne.n 800353c + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 800352c: 687b ldr r3, [r7, #4] + 800352e: 681b ldr r3, [r3, #0] + 8003530: 681a ldr r2, [r3, #0] + 8003532: 687b ldr r3, [r7, #4] + 8003534: 681b ldr r3, [r3, #0] + 8003536: 491e ldr r1, [pc, #120] ; (80035b0 ) + 8003538: 400a ands r2, r1 + 800353a: 601a str r2, [r3, #0] + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + 800353c: 687b ldr r3, [r7, #4] + 800353e: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003540: 0018 movs r0, r3 + 8003542: f7fd fdbf bl 80010c4 + 8003546: 0003 movs r3, r0 + 8003548: 2b01 cmp r3, #1 + 800354a: d016 beq.n 800357a + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + 800354c: 687b ldr r3, [r7, #4] + 800354e: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003550: 4a16 ldr r2, [pc, #88] ; (80035ac ) + 8003552: 639a str r2, [r3, #56] ; 0x38 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003554: 687b ldr r3, [r7, #4] + 8003556: 2240 movs r2, #64 ; 0x40 + 8003558: 2100 movs r1, #0 + 800355a: 5499 strb r1, [r3, r2] + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + 800355c: 687b ldr r3, [r7, #4] + 800355e: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003560: 0018 movs r0, r3 + 8003562: f7fd fd47 bl 8000ff4 + 8003566: 1e03 subs r3, r0, #0 + 8003568: d013 beq.n 8003592 + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + 800356a: 687b ldr r3, [r7, #4] + 800356c: 6bdb ldr r3, [r3, #60] ; 0x3c + 800356e: 6b9a ldr r2, [r3, #56] ; 0x38 + 8003570: 687b ldr r3, [r7, #4] + 8003572: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003574: 0018 movs r0, r3 + 8003576: 4790 blx r2 + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + 8003578: e00b b.n 8003592 + } + } + else + { + I2C_TreatErrorCallback(hi2c); + 800357a: 687b ldr r3, [r7, #4] + 800357c: 0018 movs r0, r3 + 800357e: f000 f819 bl 80035b4 + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + 8003582: e006 b.n 8003592 + } + } + else + { + I2C_TreatErrorCallback(hi2c); + 8003584: 687b ldr r3, [r7, #4] + 8003586: 0018 movs r0, r3 + 8003588: f000 f814 bl 80035b4 + } +} + 800358c: e002 b.n 8003594 + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + 800358e: 46c0 nop ; (mov r8, r8) + 8003590: e000 b.n 8003594 + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + 8003592: 46c0 nop ; (mov r8, r8) +} + 8003594: 46c0 nop ; (mov r8, r8) + 8003596: 46bd mov sp, r7 + 8003598: b004 add sp, #16 + 800359a: bd80 pop {r7, pc} + 800359c: ffff0000 .word 0xffff0000 + 80035a0: 080023a1 .word 0x080023a1 + 80035a4: 00008003 .word 0x00008003 + 80035a8: ffffbfff .word 0xffffbfff + 80035ac: 080037bf .word 0x080037bf + 80035b0: ffff7fff .word 0xffff7fff + +080035b4 : + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + 80035b4: b580 push {r7, lr} + 80035b6: b082 sub sp, #8 + 80035b8: af00 add r7, sp, #0 + 80035ba: 6078 str r0, [r7, #4] + if (hi2c->State == HAL_I2C_STATE_ABORT) + 80035bc: 687b ldr r3, [r7, #4] + 80035be: 2241 movs r2, #65 ; 0x41 + 80035c0: 5c9b ldrb r3, [r3, r2] + 80035c2: b2db uxtb r3, r3 + 80035c4: 2b60 cmp r3, #96 ; 0x60 + 80035c6: d10f bne.n 80035e8 + { + hi2c->State = HAL_I2C_STATE_READY; + 80035c8: 687b ldr r3, [r7, #4] + 80035ca: 2241 movs r2, #65 ; 0x41 + 80035cc: 2120 movs r1, #32 + 80035ce: 5499 strb r1, [r3, r2] + hi2c->PreviousState = I2C_STATE_NONE; + 80035d0: 687b ldr r3, [r7, #4] + 80035d2: 2200 movs r2, #0 + 80035d4: 631a str r2, [r3, #48] ; 0x30 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80035d6: 687b ldr r3, [r7, #4] + 80035d8: 2240 movs r2, #64 ; 0x40 + 80035da: 2100 movs r1, #0 + 80035dc: 5499 strb r1, [r3, r2] + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); + 80035de: 687b ldr r3, [r7, #4] + 80035e0: 0018 movs r0, r3 + 80035e2: f7fe fda1 bl 8002128 + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + 80035e6: e00a b.n 80035fe + hi2c->PreviousState = I2C_STATE_NONE; + 80035e8: 687b ldr r3, [r7, #4] + 80035ea: 2200 movs r2, #0 + 80035ec: 631a str r2, [r3, #48] ; 0x30 + __HAL_UNLOCK(hi2c); + 80035ee: 687b ldr r3, [r7, #4] + 80035f0: 2240 movs r2, #64 ; 0x40 + 80035f2: 2100 movs r1, #0 + 80035f4: 5499 strb r1, [r3, r2] + HAL_I2C_ErrorCallback(hi2c); + 80035f6: 687b ldr r3, [r7, #4] + 80035f8: 0018 movs r0, r3 + 80035fa: f7fe fd8d bl 8002118 +} + 80035fe: 46c0 nop ; (mov r8, r8) + 8003600: 46bd mov sp, r7 + 8003602: b002 add sp, #8 + 8003604: bd80 pop {r7, pc} + +08003606 : + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + 8003606: b580 push {r7, lr} + 8003608: b082 sub sp, #8 + 800360a: af00 add r7, sp, #0 + 800360c: 6078 str r0, [r7, #4] + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 800360e: 687b ldr r3, [r7, #4] + 8003610: 681b ldr r3, [r3, #0] + 8003612: 699b ldr r3, [r3, #24] + 8003614: 2202 movs r2, #2 + 8003616: 4013 ands r3, r2 + 8003618: 2b02 cmp r3, #2 + 800361a: d103 bne.n 8003624 + { + hi2c->Instance->TXDR = 0x00U; + 800361c: 687b ldr r3, [r7, #4] + 800361e: 681b ldr r3, [r3, #0] + 8003620: 2200 movs r2, #0 + 8003622: 629a str r2, [r3, #40] ; 0x28 + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 8003624: 687b ldr r3, [r7, #4] + 8003626: 681b ldr r3, [r3, #0] + 8003628: 699b ldr r3, [r3, #24] + 800362a: 2201 movs r2, #1 + 800362c: 4013 ands r3, r2 + 800362e: 2b01 cmp r3, #1 + 8003630: d007 beq.n 8003642 + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 8003632: 687b ldr r3, [r7, #4] + 8003634: 681b ldr r3, [r3, #0] + 8003636: 699a ldr r2, [r3, #24] + 8003638: 687b ldr r3, [r7, #4] + 800363a: 681b ldr r3, [r3, #0] + 800363c: 2101 movs r1, #1 + 800363e: 430a orrs r2, r1 + 8003640: 619a str r2, [r3, #24] + } +} + 8003642: 46c0 nop ; (mov r8, r8) + 8003644: 46bd mov sp, r7 + 8003646: b002 add sp, #8 + 8003648: bd80 pop {r7, pc} + ... + +0800364c : + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + 800364c: b580 push {r7, lr} + 800364e: b084 sub sp, #16 + 8003650: af00 add r7, sp, #0 + 8003652: 6078 str r0, [r7, #4] + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 8003654: 687b ldr r3, [r7, #4] + 8003656: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003658: 60fb str r3, [r7, #12] + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 800365a: 68fb ldr r3, [r7, #12] + 800365c: 681b ldr r3, [r3, #0] + 800365e: 681a ldr r2, [r3, #0] + 8003660: 68fb ldr r3, [r7, #12] + 8003662: 681b ldr r3, [r3, #0] + 8003664: 4920 ldr r1, [pc, #128] ; (80036e8 ) + 8003666: 400a ands r2, r1 + 8003668: 601a str r2, [r3, #0] + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + 800366a: 68fb ldr r3, [r7, #12] + 800366c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800366e: b29b uxth r3, r3 + 8003670: 2b00 cmp r3, #0 + 8003672: d105 bne.n 8003680 + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 8003674: 68fb ldr r3, [r7, #12] + 8003676: 2120 movs r1, #32 + 8003678: 0018 movs r0, r3 + 800367a: f000 fb79 bl 8003d70 + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + 800367e: e02e b.n 80036de + hi2c->pBuffPtr += hi2c->XferSize; + 8003680: 68fb ldr r3, [r7, #12] + 8003682: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003684: 68fa ldr r2, [r7, #12] + 8003686: 8d12 ldrh r2, [r2, #40] ; 0x28 + 8003688: 189a adds r2, r3, r2 + 800368a: 68fb ldr r3, [r7, #12] + 800368c: 625a str r2, [r3, #36] ; 0x24 + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 800368e: 68fb ldr r3, [r7, #12] + 8003690: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003692: b29b uxth r3, r3 + 8003694: 2bff cmp r3, #255 ; 0xff + 8003696: d903 bls.n 80036a0 + hi2c->XferSize = MAX_NBYTE_SIZE; + 8003698: 68fb ldr r3, [r7, #12] + 800369a: 22ff movs r2, #255 ; 0xff + 800369c: 851a strh r2, [r3, #40] ; 0x28 + 800369e: e004 b.n 80036aa + hi2c->XferSize = hi2c->XferCount; + 80036a0: 68fb ldr r3, [r7, #12] + 80036a2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80036a4: b29a uxth r2, r3 + 80036a6: 68fb ldr r3, [r7, #12] + 80036a8: 851a strh r2, [r3, #40] ; 0x28 + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 80036aa: 68fb ldr r3, [r7, #12] + 80036ac: 6b98 ldr r0, [r3, #56] ; 0x38 + 80036ae: 68fb ldr r3, [r7, #12] + 80036b0: 6a5b ldr r3, [r3, #36] ; 0x24 + 80036b2: 0019 movs r1, r3 + 80036b4: 68fb ldr r3, [r7, #12] + 80036b6: 681b ldr r3, [r3, #0] + 80036b8: 3328 adds r3, #40 ; 0x28 + 80036ba: 001a movs r2, r3 + hi2c->XferSize) != HAL_OK) + 80036bc: 68fb ldr r3, [r7, #12] + 80036be: 8d1b ldrh r3, [r3, #40] ; 0x28 + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 80036c0: f7fd fc12 bl 8000ee8 + 80036c4: 1e03 subs r3, r0, #0 + 80036c6: d005 beq.n 80036d4 + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + 80036c8: 68fb ldr r3, [r7, #12] + 80036ca: 2110 movs r1, #16 + 80036cc: 0018 movs r0, r3 + 80036ce: f7ff fe6f bl 80033b0 +} + 80036d2: e004 b.n 80036de + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + 80036d4: 68fb ldr r3, [r7, #12] + 80036d6: 2140 movs r1, #64 ; 0x40 + 80036d8: 0018 movs r0, r3 + 80036da: f000 fb49 bl 8003d70 +} + 80036de: 46c0 nop ; (mov r8, r8) + 80036e0: 46bd mov sp, r7 + 80036e2: b004 add sp, #16 + 80036e4: bd80 pop {r7, pc} + 80036e6: 46c0 nop ; (mov r8, r8) + 80036e8: ffffbfff .word 0xffffbfff + +080036ec : + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + 80036ec: b580 push {r7, lr} + 80036ee: b084 sub sp, #16 + 80036f0: af00 add r7, sp, #0 + 80036f2: 6078 str r0, [r7, #4] + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 80036f4: 687b ldr r3, [r7, #4] + 80036f6: 6a9b ldr r3, [r3, #40] ; 0x28 + 80036f8: 60fb str r3, [r7, #12] + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 80036fa: 68fb ldr r3, [r7, #12] + 80036fc: 681b ldr r3, [r3, #0] + 80036fe: 681a ldr r2, [r3, #0] + 8003700: 68fb ldr r3, [r7, #12] + 8003702: 681b ldr r3, [r3, #0] + 8003704: 4920 ldr r1, [pc, #128] ; (8003788 ) + 8003706: 400a ands r2, r1 + 8003708: 601a str r2, [r3, #0] + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + 800370a: 68fb ldr r3, [r7, #12] + 800370c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800370e: b29b uxth r3, r3 + 8003710: 2b00 cmp r3, #0 + 8003712: d105 bne.n 8003720 + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 8003714: 68fb ldr r3, [r7, #12] + 8003716: 2120 movs r1, #32 + 8003718: 0018 movs r0, r3 + 800371a: f000 fb29 bl 8003d70 + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + 800371e: e02e b.n 800377e + hi2c->pBuffPtr += hi2c->XferSize; + 8003720: 68fb ldr r3, [r7, #12] + 8003722: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003724: 68fa ldr r2, [r7, #12] + 8003726: 8d12 ldrh r2, [r2, #40] ; 0x28 + 8003728: 189a adds r2, r3, r2 + 800372a: 68fb ldr r3, [r7, #12] + 800372c: 625a str r2, [r3, #36] ; 0x24 + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 800372e: 68fb ldr r3, [r7, #12] + 8003730: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003732: b29b uxth r3, r3 + 8003734: 2bff cmp r3, #255 ; 0xff + 8003736: d903 bls.n 8003740 + hi2c->XferSize = MAX_NBYTE_SIZE; + 8003738: 68fb ldr r3, [r7, #12] + 800373a: 22ff movs r2, #255 ; 0xff + 800373c: 851a strh r2, [r3, #40] ; 0x28 + 800373e: e004 b.n 800374a + hi2c->XferSize = hi2c->XferCount; + 8003740: 68fb ldr r3, [r7, #12] + 8003742: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003744: b29a uxth r2, r3 + 8003746: 68fb ldr r3, [r7, #12] + 8003748: 851a strh r2, [r3, #40] ; 0x28 + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + 800374a: 68fb ldr r3, [r7, #12] + 800374c: 6bd8 ldr r0, [r3, #60] ; 0x3c + 800374e: 68fb ldr r3, [r7, #12] + 8003750: 681b ldr r3, [r3, #0] + 8003752: 3324 adds r3, #36 ; 0x24 + 8003754: 0019 movs r1, r3 + 8003756: 68fb ldr r3, [r7, #12] + 8003758: 6a5b ldr r3, [r3, #36] ; 0x24 + 800375a: 001a movs r2, r3 + hi2c->XferSize) != HAL_OK) + 800375c: 68fb ldr r3, [r7, #12] + 800375e: 8d1b ldrh r3, [r3, #40] ; 0x28 + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + 8003760: f7fd fbc2 bl 8000ee8 + 8003764: 1e03 subs r3, r0, #0 + 8003766: d005 beq.n 8003774 + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + 8003768: 68fb ldr r3, [r7, #12] + 800376a: 2110 movs r1, #16 + 800376c: 0018 movs r0, r3 + 800376e: f7ff fe1f bl 80033b0 +} + 8003772: e004 b.n 800377e + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + 8003774: 68fb ldr r3, [r7, #12] + 8003776: 2140 movs r1, #64 ; 0x40 + 8003778: 0018 movs r0, r3 + 800377a: f000 faf9 bl 8003d70 +} + 800377e: 46c0 nop ; (mov r8, r8) + 8003780: 46bd mov sp, r7 + 8003782: b004 add sp, #16 + 8003784: bd80 pop {r7, pc} + 8003786: 46c0 nop ; (mov r8, r8) + 8003788: ffff7fff .word 0xffff7fff + +0800378c : + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + 800378c: b580 push {r7, lr} + 800378e: b084 sub sp, #16 + 8003790: af00 add r7, sp, #0 + 8003792: 6078 str r0, [r7, #4] + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 8003794: 687b ldr r3, [r7, #4] + 8003796: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003798: 60fb str r3, [r7, #12] + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + 800379a: 68fb ldr r3, [r7, #12] + 800379c: 681b ldr r3, [r3, #0] + 800379e: 685a ldr r2, [r3, #4] + 80037a0: 68fb ldr r3, [r7, #12] + 80037a2: 681b ldr r3, [r3, #0] + 80037a4: 2180 movs r1, #128 ; 0x80 + 80037a6: 0209 lsls r1, r1, #8 + 80037a8: 430a orrs r2, r1 + 80037aa: 605a str r2, [r3, #4] + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + 80037ac: 68fb ldr r3, [r7, #12] + 80037ae: 2110 movs r1, #16 + 80037b0: 0018 movs r0, r3 + 80037b2: f7ff fdfd bl 80033b0 +} + 80037b6: 46c0 nop ; (mov r8, r8) + 80037b8: 46bd mov sp, r7 + 80037ba: b004 add sp, #16 + 80037bc: bd80 pop {r7, pc} + +080037be : + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + 80037be: b580 push {r7, lr} + 80037c0: b084 sub sp, #16 + 80037c2: af00 add r7, sp, #0 + 80037c4: 6078 str r0, [r7, #4] + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 80037c6: 687b ldr r3, [r7, #4] + 80037c8: 6a9b ldr r3, [r3, #40] ; 0x28 + 80037ca: 60fb str r3, [r7, #12] + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + 80037cc: 68fb ldr r3, [r7, #12] + 80037ce: 6b9b ldr r3, [r3, #56] ; 0x38 + 80037d0: 2b00 cmp r3, #0 + 80037d2: d003 beq.n 80037dc + { + hi2c->hdmatx->XferAbortCallback = NULL; + 80037d4: 68fb ldr r3, [r7, #12] + 80037d6: 6b9b ldr r3, [r3, #56] ; 0x38 + 80037d8: 2200 movs r2, #0 + 80037da: 639a str r2, [r3, #56] ; 0x38 + } + if (hi2c->hdmarx != NULL) + 80037dc: 68fb ldr r3, [r7, #12] + 80037de: 6bdb ldr r3, [r3, #60] ; 0x3c + 80037e0: 2b00 cmp r3, #0 + 80037e2: d003 beq.n 80037ec + { + hi2c->hdmarx->XferAbortCallback = NULL; + 80037e4: 68fb ldr r3, [r7, #12] + 80037e6: 6bdb ldr r3, [r3, #60] ; 0x3c + 80037e8: 2200 movs r2, #0 + 80037ea: 639a str r2, [r3, #56] ; 0x38 + } + + I2C_TreatErrorCallback(hi2c); + 80037ec: 68fb ldr r3, [r7, #12] + 80037ee: 0018 movs r0, r3 + 80037f0: f7ff fee0 bl 80035b4 +} + 80037f4: 46c0 nop ; (mov r8, r8) + 80037f6: 46bd mov sp, r7 + 80037f8: b004 add sp, #16 + 80037fa: bd80 pop {r7, pc} + +080037fc : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + 80037fc: b580 push {r7, lr} + 80037fe: b084 sub sp, #16 + 8003800: af00 add r7, sp, #0 + 8003802: 60f8 str r0, [r7, #12] + 8003804: 60b9 str r1, [r7, #8] + 8003806: 603b str r3, [r7, #0] + 8003808: 1dfb adds r3, r7, #7 + 800380a: 701a strb r2, [r3, #0] + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 800380c: e03a b.n 8003884 + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 800380e: 69ba ldr r2, [r7, #24] + 8003810: 6839 ldr r1, [r7, #0] + 8003812: 68fb ldr r3, [r7, #12] + 8003814: 0018 movs r0, r3 + 8003816: f000 f971 bl 8003afc + 800381a: 1e03 subs r3, r0, #0 + 800381c: d001 beq.n 8003822 + { + return HAL_ERROR; + 800381e: 2301 movs r3, #1 + 8003820: e040 b.n 80038a4 + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8003822: 683b ldr r3, [r7, #0] + 8003824: 3301 adds r3, #1 + 8003826: d02d beq.n 8003884 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8003828: f7fd fa7c bl 8000d24 + 800382c: 0002 movs r2, r0 + 800382e: 69bb ldr r3, [r7, #24] + 8003830: 1ad3 subs r3, r2, r3 + 8003832: 683a ldr r2, [r7, #0] + 8003834: 429a cmp r2, r3 + 8003836: d302 bcc.n 800383e + 8003838: 683b ldr r3, [r7, #0] + 800383a: 2b00 cmp r3, #0 + 800383c: d122 bne.n 8003884 + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + 800383e: 68fb ldr r3, [r7, #12] + 8003840: 681b ldr r3, [r3, #0] + 8003842: 699b ldr r3, [r3, #24] + 8003844: 68ba ldr r2, [r7, #8] + 8003846: 4013 ands r3, r2 + 8003848: 68ba ldr r2, [r7, #8] + 800384a: 1ad3 subs r3, r2, r3 + 800384c: 425a negs r2, r3 + 800384e: 4153 adcs r3, r2 + 8003850: b2db uxtb r3, r3 + 8003852: 001a movs r2, r3 + 8003854: 1dfb adds r3, r7, #7 + 8003856: 781b ldrb r3, [r3, #0] + 8003858: 429a cmp r2, r3 + 800385a: d113 bne.n 8003884 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 800385c: 68fb ldr r3, [r7, #12] + 800385e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003860: 2220 movs r2, #32 + 8003862: 431a orrs r2, r3 + 8003864: 68fb ldr r3, [r7, #12] + 8003866: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8003868: 68fb ldr r3, [r7, #12] + 800386a: 2241 movs r2, #65 ; 0x41 + 800386c: 2120 movs r1, #32 + 800386e: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 8003870: 68fb ldr r3, [r7, #12] + 8003872: 2242 movs r2, #66 ; 0x42 + 8003874: 2100 movs r1, #0 + 8003876: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003878: 68fb ldr r3, [r7, #12] + 800387a: 2240 movs r2, #64 ; 0x40 + 800387c: 2100 movs r1, #0 + 800387e: 5499 strb r1, [r3, r2] + return HAL_ERROR; + 8003880: 2301 movs r3, #1 + 8003882: e00f b.n 80038a4 + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 8003884: 68fb ldr r3, [r7, #12] + 8003886: 681b ldr r3, [r3, #0] + 8003888: 699b ldr r3, [r3, #24] + 800388a: 68ba ldr r2, [r7, #8] + 800388c: 4013 ands r3, r2 + 800388e: 68ba ldr r2, [r7, #8] + 8003890: 1ad3 subs r3, r2, r3 + 8003892: 425a negs r2, r3 + 8003894: 4153 adcs r3, r2 + 8003896: b2db uxtb r3, r3 + 8003898: 001a movs r2, r3 + 800389a: 1dfb adds r3, r7, #7 + 800389c: 781b ldrb r3, [r3, #0] + 800389e: 429a cmp r2, r3 + 80038a0: d0b5 beq.n 800380e + } + } + } + } + return HAL_OK; + 80038a2: 2300 movs r3, #0 +} + 80038a4: 0018 movs r0, r3 + 80038a6: 46bd mov sp, r7 + 80038a8: b004 add sp, #16 + 80038aa: bd80 pop {r7, pc} + +080038ac : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 80038ac: b580 push {r7, lr} + 80038ae: b084 sub sp, #16 + 80038b0: af00 add r7, sp, #0 + 80038b2: 60f8 str r0, [r7, #12] + 80038b4: 60b9 str r1, [r7, #8] + 80038b6: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 80038b8: e032 b.n 8003920 + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 80038ba: 687a ldr r2, [r7, #4] + 80038bc: 68b9 ldr r1, [r7, #8] + 80038be: 68fb ldr r3, [r7, #12] + 80038c0: 0018 movs r0, r3 + 80038c2: f000 f91b bl 8003afc + 80038c6: 1e03 subs r3, r0, #0 + 80038c8: d001 beq.n 80038ce + { + return HAL_ERROR; + 80038ca: 2301 movs r3, #1 + 80038cc: e030 b.n 8003930 + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 80038ce: 68bb ldr r3, [r7, #8] + 80038d0: 3301 adds r3, #1 + 80038d2: d025 beq.n 8003920 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 80038d4: f7fd fa26 bl 8000d24 + 80038d8: 0002 movs r2, r0 + 80038da: 687b ldr r3, [r7, #4] + 80038dc: 1ad3 subs r3, r2, r3 + 80038de: 68ba ldr r2, [r7, #8] + 80038e0: 429a cmp r2, r3 + 80038e2: d302 bcc.n 80038ea + 80038e4: 68bb ldr r3, [r7, #8] + 80038e6: 2b00 cmp r3, #0 + 80038e8: d11a bne.n 8003920 + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + 80038ea: 68fb ldr r3, [r7, #12] + 80038ec: 681b ldr r3, [r3, #0] + 80038ee: 699b ldr r3, [r3, #24] + 80038f0: 2202 movs r2, #2 + 80038f2: 4013 ands r3, r2 + 80038f4: 2b02 cmp r3, #2 + 80038f6: d013 beq.n 8003920 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 80038f8: 68fb ldr r3, [r7, #12] + 80038fa: 6c5b ldr r3, [r3, #68] ; 0x44 + 80038fc: 2220 movs r2, #32 + 80038fe: 431a orrs r2, r3 + 8003900: 68fb ldr r3, [r7, #12] + 8003902: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8003904: 68fb ldr r3, [r7, #12] + 8003906: 2241 movs r2, #65 ; 0x41 + 8003908: 2120 movs r1, #32 + 800390a: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 800390c: 68fb ldr r3, [r7, #12] + 800390e: 2242 movs r2, #66 ; 0x42 + 8003910: 2100 movs r1, #0 + 8003912: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003914: 68fb ldr r3, [r7, #12] + 8003916: 2240 movs r2, #64 ; 0x40 + 8003918: 2100 movs r1, #0 + 800391a: 5499 strb r1, [r3, r2] + + return HAL_ERROR; + 800391c: 2301 movs r3, #1 + 800391e: e007 b.n 8003930 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 8003920: 68fb ldr r3, [r7, #12] + 8003922: 681b ldr r3, [r3, #0] + 8003924: 699b ldr r3, [r3, #24] + 8003926: 2202 movs r2, #2 + 8003928: 4013 ands r3, r2 + 800392a: 2b02 cmp r3, #2 + 800392c: d1c5 bne.n 80038ba + } + } + } + } + return HAL_OK; + 800392e: 2300 movs r3, #0 +} + 8003930: 0018 movs r0, r3 + 8003932: 46bd mov sp, r7 + 8003934: b004 add sp, #16 + 8003936: bd80 pop {r7, pc} + +08003938 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 8003938: b580 push {r7, lr} + 800393a: b084 sub sp, #16 + 800393c: af00 add r7, sp, #0 + 800393e: 60f8 str r0, [r7, #12] + 8003940: 60b9 str r1, [r7, #8] + 8003942: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8003944: e02f b.n 80039a6 + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 8003946: 687a ldr r2, [r7, #4] + 8003948: 68b9 ldr r1, [r7, #8] + 800394a: 68fb ldr r3, [r7, #12] + 800394c: 0018 movs r0, r3 + 800394e: f000 f8d5 bl 8003afc + 8003952: 1e03 subs r3, r0, #0 + 8003954: d001 beq.n 800395a + { + return HAL_ERROR; + 8003956: 2301 movs r3, #1 + 8003958: e02d b.n 80039b6 + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800395a: f7fd f9e3 bl 8000d24 + 800395e: 0002 movs r2, r0 + 8003960: 687b ldr r3, [r7, #4] + 8003962: 1ad3 subs r3, r2, r3 + 8003964: 68ba ldr r2, [r7, #8] + 8003966: 429a cmp r2, r3 + 8003968: d302 bcc.n 8003970 + 800396a: 68bb ldr r3, [r7, #8] + 800396c: 2b00 cmp r3, #0 + 800396e: d11a bne.n 80039a6 + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + 8003970: 68fb ldr r3, [r7, #12] + 8003972: 681b ldr r3, [r3, #0] + 8003974: 699b ldr r3, [r3, #24] + 8003976: 2220 movs r2, #32 + 8003978: 4013 ands r3, r2 + 800397a: 2b20 cmp r3, #32 + 800397c: d013 beq.n 80039a6 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 800397e: 68fb ldr r3, [r7, #12] + 8003980: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003982: 2220 movs r2, #32 + 8003984: 431a orrs r2, r3 + 8003986: 68fb ldr r3, [r7, #12] + 8003988: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 800398a: 68fb ldr r3, [r7, #12] + 800398c: 2241 movs r2, #65 ; 0x41 + 800398e: 2120 movs r1, #32 + 8003990: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 8003992: 68fb ldr r3, [r7, #12] + 8003994: 2242 movs r2, #66 ; 0x42 + 8003996: 2100 movs r1, #0 + 8003998: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800399a: 68fb ldr r3, [r7, #12] + 800399c: 2240 movs r2, #64 ; 0x40 + 800399e: 2100 movs r1, #0 + 80039a0: 5499 strb r1, [r3, r2] + + return HAL_ERROR; + 80039a2: 2301 movs r3, #1 + 80039a4: e007 b.n 80039b6 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 80039a6: 68fb ldr r3, [r7, #12] + 80039a8: 681b ldr r3, [r3, #0] + 80039aa: 699b ldr r3, [r3, #24] + 80039ac: 2220 movs r2, #32 + 80039ae: 4013 ands r3, r2 + 80039b0: 2b20 cmp r3, #32 + 80039b2: d1c8 bne.n 8003946 + } + } + } + return HAL_OK; + 80039b4: 2300 movs r3, #0 +} + 80039b6: 0018 movs r0, r3 + 80039b8: 46bd mov sp, r7 + 80039ba: b004 add sp, #16 + 80039bc: bd80 pop {r7, pc} + ... + +080039c0 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 80039c0: b580 push {r7, lr} + 80039c2: b086 sub sp, #24 + 80039c4: af00 add r7, sp, #0 + 80039c6: 60f8 str r0, [r7, #12] + 80039c8: 60b9 str r1, [r7, #8] + 80039ca: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 80039cc: 2317 movs r3, #23 + 80039ce: 18fb adds r3, r7, r3 + 80039d0: 2200 movs r2, #0 + 80039d2: 701a strb r2, [r3, #0] + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) + 80039d4: e07b b.n 8003ace + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 80039d6: 687a ldr r2, [r7, #4] + 80039d8: 68b9 ldr r1, [r7, #8] + 80039da: 68fb ldr r3, [r7, #12] + 80039dc: 0018 movs r0, r3 + 80039de: f000 f88d bl 8003afc + 80039e2: 1e03 subs r3, r0, #0 + 80039e4: d003 beq.n 80039ee + { + status = HAL_ERROR; + 80039e6: 2317 movs r3, #23 + 80039e8: 18fb adds r3, r7, r3 + 80039ea: 2201 movs r2, #1 + 80039ec: 701a strb r2, [r3, #0] + } + + /* Check if a STOPF is detected */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) + 80039ee: 68fb ldr r3, [r7, #12] + 80039f0: 681b ldr r3, [r3, #0] + 80039f2: 699b ldr r3, [r3, #24] + 80039f4: 2220 movs r2, #32 + 80039f6: 4013 ands r3, r2 + 80039f8: 2b20 cmp r3, #32 + 80039fa: d140 bne.n 8003a7e + 80039fc: 2117 movs r1, #23 + 80039fe: 187b adds r3, r7, r1 + 8003a00: 781b ldrb r3, [r3, #0] + 8003a02: 2b00 cmp r3, #0 + 8003a04: d13b bne.n 8003a7e + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + 8003a06: 68fb ldr r3, [r7, #12] + 8003a08: 681b ldr r3, [r3, #0] + 8003a0a: 699b ldr r3, [r3, #24] + 8003a0c: 2204 movs r2, #4 + 8003a0e: 4013 ands r3, r2 + 8003a10: 2b04 cmp r3, #4 + 8003a12: d106 bne.n 8003a22 + 8003a14: 68fb ldr r3, [r7, #12] + 8003a16: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003a18: 2b00 cmp r3, #0 + 8003a1a: d002 beq.n 8003a22 + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + status = HAL_OK; + 8003a1c: 187b adds r3, r7, r1 + 8003a1e: 2200 movs r2, #0 + 8003a20: 701a strb r2, [r3, #0] + } + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 8003a22: 68fb ldr r3, [r7, #12] + 8003a24: 681b ldr r3, [r3, #0] + 8003a26: 699b ldr r3, [r3, #24] + 8003a28: 2210 movs r2, #16 + 8003a2a: 4013 ands r3, r2 + 8003a2c: 2b10 cmp r3, #16 + 8003a2e: d123 bne.n 8003a78 + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8003a30: 68fb ldr r3, [r7, #12] + 8003a32: 681b ldr r3, [r3, #0] + 8003a34: 2210 movs r2, #16 + 8003a36: 61da str r2, [r3, #28] + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + 8003a38: 68fb ldr r3, [r7, #12] + 8003a3a: 2204 movs r2, #4 + 8003a3c: 645a str r2, [r3, #68] ; 0x44 + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8003a3e: 68fb ldr r3, [r7, #12] + 8003a40: 681b ldr r3, [r3, #0] + 8003a42: 2220 movs r2, #32 + 8003a44: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8003a46: 68fb ldr r3, [r7, #12] + 8003a48: 681b ldr r3, [r3, #0] + 8003a4a: 685a ldr r2, [r3, #4] + 8003a4c: 68fb ldr r3, [r7, #12] + 8003a4e: 681b ldr r3, [r3, #0] + 8003a50: 4929 ldr r1, [pc, #164] ; (8003af8 ) + 8003a52: 400a ands r2, r1 + 8003a54: 605a str r2, [r3, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 8003a56: 68fb ldr r3, [r7, #12] + 8003a58: 2241 movs r2, #65 ; 0x41 + 8003a5a: 2120 movs r1, #32 + 8003a5c: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 8003a5e: 68fb ldr r3, [r7, #12] + 8003a60: 2242 movs r2, #66 ; 0x42 + 8003a62: 2100 movs r1, #0 + 8003a64: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003a66: 68fb ldr r3, [r7, #12] + 8003a68: 2240 movs r2, #64 ; 0x40 + 8003a6a: 2100 movs r1, #0 + 8003a6c: 5499 strb r1, [r3, r2] + + status = HAL_ERROR; + 8003a6e: 2317 movs r3, #23 + 8003a70: 18fb adds r3, r7, r3 + 8003a72: 2201 movs r2, #1 + 8003a74: 701a strb r2, [r3, #0] + 8003a76: e002 b.n 8003a7e + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8003a78: 68fb ldr r3, [r7, #12] + 8003a7a: 2200 movs r2, #0 + 8003a7c: 645a str r2, [r3, #68] ; 0x44 + } + } + + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) + 8003a7e: f7fd f951 bl 8000d24 + 8003a82: 0002 movs r2, r0 + 8003a84: 687b ldr r3, [r7, #4] + 8003a86: 1ad3 subs r3, r2, r3 + 8003a88: 68ba ldr r2, [r7, #8] + 8003a8a: 429a cmp r2, r3 + 8003a8c: d302 bcc.n 8003a94 + 8003a8e: 68bb ldr r3, [r7, #8] + 8003a90: 2b00 cmp r3, #0 + 8003a92: d11c bne.n 8003ace + 8003a94: 2017 movs r0, #23 + 8003a96: 183b adds r3, r7, r0 + 8003a98: 781b ldrb r3, [r3, #0] + 8003a9a: 2b00 cmp r3, #0 + 8003a9c: d117 bne.n 8003ace + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + 8003a9e: 68fb ldr r3, [r7, #12] + 8003aa0: 681b ldr r3, [r3, #0] + 8003aa2: 699b ldr r3, [r3, #24] + 8003aa4: 2204 movs r2, #4 + 8003aa6: 4013 ands r3, r2 + 8003aa8: 2b04 cmp r3, #4 + 8003aaa: d010 beq.n 8003ace + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8003aac: 68fb ldr r3, [r7, #12] + 8003aae: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003ab0: 2220 movs r2, #32 + 8003ab2: 431a orrs r2, r3 + 8003ab4: 68fb ldr r3, [r7, #12] + 8003ab6: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8003ab8: 68fb ldr r3, [r7, #12] + 8003aba: 2241 movs r2, #65 ; 0x41 + 8003abc: 2120 movs r1, #32 + 8003abe: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003ac0: 68fb ldr r3, [r7, #12] + 8003ac2: 2240 movs r2, #64 ; 0x40 + 8003ac4: 2100 movs r1, #0 + 8003ac6: 5499 strb r1, [r3, r2] + + status = HAL_ERROR; + 8003ac8: 183b adds r3, r7, r0 + 8003aca: 2201 movs r2, #1 + 8003acc: 701a strb r2, [r3, #0] + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) + 8003ace: 68fb ldr r3, [r7, #12] + 8003ad0: 681b ldr r3, [r3, #0] + 8003ad2: 699b ldr r3, [r3, #24] + 8003ad4: 2204 movs r2, #4 + 8003ad6: 4013 ands r3, r2 + 8003ad8: 2b04 cmp r3, #4 + 8003ada: d005 beq.n 8003ae8 + 8003adc: 2317 movs r3, #23 + 8003ade: 18fb adds r3, r7, r3 + 8003ae0: 781b ldrb r3, [r3, #0] + 8003ae2: 2b00 cmp r3, #0 + 8003ae4: d100 bne.n 8003ae8 + 8003ae6: e776 b.n 80039d6 + } + } + } + return status; + 8003ae8: 2317 movs r3, #23 + 8003aea: 18fb adds r3, r7, r3 + 8003aec: 781b ldrb r3, [r3, #0] +} + 8003aee: 0018 movs r0, r3 + 8003af0: 46bd mov sp, r7 + 8003af2: b006 add sp, #24 + 8003af4: bd80 pop {r7, pc} + 8003af6: 46c0 nop ; (mov r8, r8) + 8003af8: fe00e800 .word 0xfe00e800 + +08003afc : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 8003afc: b590 push {r4, r7, lr} + 8003afe: b08b sub sp, #44 ; 0x2c + 8003b00: af00 add r7, sp, #0 + 8003b02: 60f8 str r0, [r7, #12] + 8003b04: 60b9 str r1, [r7, #8] + 8003b06: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8003b08: 2327 movs r3, #39 ; 0x27 + 8003b0a: 18fb adds r3, r7, r3 + 8003b0c: 2200 movs r2, #0 + 8003b0e: 701a strb r2, [r3, #0] + uint32_t itflag = hi2c->Instance->ISR; + 8003b10: 68fb ldr r3, [r7, #12] + 8003b12: 681b ldr r3, [r3, #0] + 8003b14: 699b ldr r3, [r3, #24] + 8003b16: 61bb str r3, [r7, #24] + uint32_t error_code = 0; + 8003b18: 2300 movs r3, #0 + 8003b1a: 623b str r3, [r7, #32] + uint32_t tickstart = Tickstart; + 8003b1c: 687b ldr r3, [r7, #4] + 8003b1e: 61fb str r3, [r7, #28] + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + 8003b20: 69bb ldr r3, [r7, #24] + 8003b22: 2210 movs r2, #16 + 8003b24: 4013 ands r3, r2 + 8003b26: d100 bne.n 8003b2a + 8003b28: e082 b.n 8003c30 + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8003b2a: 68fb ldr r3, [r7, #12] + 8003b2c: 681b ldr r3, [r3, #0] + 8003b2e: 2210 movs r2, #16 + 8003b30: 61da str r2, [r3, #28] + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + 8003b32: e060 b.n 8003bf6 + 8003b34: 2427 movs r4, #39 ; 0x27 + 8003b36: 193b adds r3, r7, r4 + 8003b38: 193a adds r2, r7, r4 + 8003b3a: 7812 ldrb r2, [r2, #0] + 8003b3c: 701a strb r2, [r3, #0] + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8003b3e: 68bb ldr r3, [r7, #8] + 8003b40: 3301 adds r3, #1 + 8003b42: d058 beq.n 8003bf6 + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 8003b44: f7fd f8ee bl 8000d24 + 8003b48: 0002 movs r2, r0 + 8003b4a: 69fb ldr r3, [r7, #28] + 8003b4c: 1ad3 subs r3, r2, r3 + 8003b4e: 68ba ldr r2, [r7, #8] + 8003b50: 429a cmp r2, r3 + 8003b52: d306 bcc.n 8003b62 + 8003b54: 193b adds r3, r7, r4 + 8003b56: 193a adds r2, r7, r4 + 8003b58: 7812 ldrb r2, [r2, #0] + 8003b5a: 701a strb r2, [r3, #0] + 8003b5c: 68bb ldr r3, [r7, #8] + 8003b5e: 2b00 cmp r3, #0 + 8003b60: d149 bne.n 8003bf6 + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + 8003b62: 68fb ldr r3, [r7, #12] + 8003b64: 681b ldr r3, [r3, #0] + 8003b66: 685a ldr r2, [r3, #4] + 8003b68: 2380 movs r3, #128 ; 0x80 + 8003b6a: 01db lsls r3, r3, #7 + 8003b6c: 4013 ands r3, r2 + 8003b6e: 617b str r3, [r7, #20] + tmp2 = hi2c->Mode; + 8003b70: 2013 movs r0, #19 + 8003b72: 183b adds r3, r7, r0 + 8003b74: 68fa ldr r2, [r7, #12] + 8003b76: 2142 movs r1, #66 ; 0x42 + 8003b78: 5c52 ldrb r2, [r2, r1] + 8003b7a: 701a strb r2, [r3, #0] + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + 8003b7c: 68fb ldr r3, [r7, #12] + 8003b7e: 681b ldr r3, [r3, #0] + 8003b80: 699a ldr r2, [r3, #24] + 8003b82: 2380 movs r3, #128 ; 0x80 + 8003b84: 021b lsls r3, r3, #8 + 8003b86: 401a ands r2, r3 + 8003b88: 2380 movs r3, #128 ; 0x80 + 8003b8a: 021b lsls r3, r3, #8 + 8003b8c: 429a cmp r2, r3 + 8003b8e: d126 bne.n 8003bde + 8003b90: 697a ldr r2, [r7, #20] + 8003b92: 2380 movs r3, #128 ; 0x80 + 8003b94: 01db lsls r3, r3, #7 + 8003b96: 429a cmp r2, r3 + 8003b98: d021 beq.n 8003bde + (tmp1 != I2C_CR2_STOP) && \ + 8003b9a: 183b adds r3, r7, r0 + 8003b9c: 781b ldrb r3, [r3, #0] + 8003b9e: 2b20 cmp r3, #32 + 8003ba0: d01d beq.n 8003bde + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + 8003ba2: 68fb ldr r3, [r7, #12] + 8003ba4: 681b ldr r3, [r3, #0] + 8003ba6: 685a ldr r2, [r3, #4] + 8003ba8: 68fb ldr r3, [r7, #12] + 8003baa: 681b ldr r3, [r3, #0] + 8003bac: 2180 movs r1, #128 ; 0x80 + 8003bae: 01c9 lsls r1, r1, #7 + 8003bb0: 430a orrs r2, r1 + 8003bb2: 605a str r2, [r3, #4] + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + 8003bb4: f7fd f8b6 bl 8000d24 + 8003bb8: 0003 movs r3, r0 + 8003bba: 61fb str r3, [r7, #28] + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8003bbc: e00f b.n 8003bde + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + 8003bbe: f7fd f8b1 bl 8000d24 + 8003bc2: 0002 movs r2, r0 + 8003bc4: 69fb ldr r3, [r7, #28] + 8003bc6: 1ad3 subs r3, r2, r3 + 8003bc8: 2b19 cmp r3, #25 + 8003bca: d908 bls.n 8003bde + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + 8003bcc: 6a3b ldr r3, [r7, #32] + 8003bce: 2220 movs r2, #32 + 8003bd0: 4313 orrs r3, r2 + 8003bd2: 623b str r3, [r7, #32] + + status = HAL_ERROR; + 8003bd4: 2327 movs r3, #39 ; 0x27 + 8003bd6: 18fb adds r3, r7, r3 + 8003bd8: 2201 movs r2, #1 + 8003bda: 701a strb r2, [r3, #0] + + break; + 8003bdc: e00b b.n 8003bf6 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8003bde: 68fb ldr r3, [r7, #12] + 8003be0: 681b ldr r3, [r3, #0] + 8003be2: 699b ldr r3, [r3, #24] + 8003be4: 2220 movs r2, #32 + 8003be6: 4013 ands r3, r2 + 8003be8: 2127 movs r1, #39 ; 0x27 + 8003bea: 187a adds r2, r7, r1 + 8003bec: 1879 adds r1, r7, r1 + 8003bee: 7809 ldrb r1, [r1, #0] + 8003bf0: 7011 strb r1, [r2, #0] + 8003bf2: 2b20 cmp r3, #32 + 8003bf4: d1e3 bne.n 8003bbe + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + 8003bf6: 68fb ldr r3, [r7, #12] + 8003bf8: 681b ldr r3, [r3, #0] + 8003bfa: 699b ldr r3, [r3, #24] + 8003bfc: 2220 movs r2, #32 + 8003bfe: 4013 ands r3, r2 + 8003c00: 2b20 cmp r3, #32 + 8003c02: d004 beq.n 8003c0e + 8003c04: 2327 movs r3, #39 ; 0x27 + 8003c06: 18fb adds r3, r7, r3 + 8003c08: 781b ldrb r3, [r3, #0] + 8003c0a: 2b00 cmp r3, #0 + 8003c0c: d092 beq.n 8003b34 + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + 8003c0e: 2327 movs r3, #39 ; 0x27 + 8003c10: 18fb adds r3, r7, r3 + 8003c12: 781b ldrb r3, [r3, #0] + 8003c14: 2b00 cmp r3, #0 + 8003c16: d103 bne.n 8003c20 + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8003c18: 68fb ldr r3, [r7, #12] + 8003c1a: 681b ldr r3, [r3, #0] + 8003c1c: 2220 movs r2, #32 + 8003c1e: 61da str r2, [r3, #28] + } + + error_code |= HAL_I2C_ERROR_AF; + 8003c20: 6a3b ldr r3, [r7, #32] + 8003c22: 2204 movs r2, #4 + 8003c24: 4313 orrs r3, r2 + 8003c26: 623b str r3, [r7, #32] + + status = HAL_ERROR; + 8003c28: 2327 movs r3, #39 ; 0x27 + 8003c2a: 18fb adds r3, r7, r3 + 8003c2c: 2201 movs r2, #1 + 8003c2e: 701a strb r2, [r3, #0] + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + 8003c30: 68fb ldr r3, [r7, #12] + 8003c32: 681b ldr r3, [r3, #0] + 8003c34: 699b ldr r3, [r3, #24] + 8003c36: 61bb str r3, [r7, #24] + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + 8003c38: 69ba ldr r2, [r7, #24] + 8003c3a: 2380 movs r3, #128 ; 0x80 + 8003c3c: 005b lsls r3, r3, #1 + 8003c3e: 4013 ands r3, r2 + 8003c40: d00c beq.n 8003c5c + { + error_code |= HAL_I2C_ERROR_BERR; + 8003c42: 6a3b ldr r3, [r7, #32] + 8003c44: 2201 movs r2, #1 + 8003c46: 4313 orrs r3, r2 + 8003c48: 623b str r3, [r7, #32] + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + 8003c4a: 68fb ldr r3, [r7, #12] + 8003c4c: 681b ldr r3, [r3, #0] + 8003c4e: 2280 movs r2, #128 ; 0x80 + 8003c50: 0052 lsls r2, r2, #1 + 8003c52: 61da str r2, [r3, #28] + + status = HAL_ERROR; + 8003c54: 2327 movs r3, #39 ; 0x27 + 8003c56: 18fb adds r3, r7, r3 + 8003c58: 2201 movs r2, #1 + 8003c5a: 701a strb r2, [r3, #0] + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + 8003c5c: 69ba ldr r2, [r7, #24] + 8003c5e: 2380 movs r3, #128 ; 0x80 + 8003c60: 00db lsls r3, r3, #3 + 8003c62: 4013 ands r3, r2 + 8003c64: d00c beq.n 8003c80 + { + error_code |= HAL_I2C_ERROR_OVR; + 8003c66: 6a3b ldr r3, [r7, #32] + 8003c68: 2208 movs r2, #8 + 8003c6a: 4313 orrs r3, r2 + 8003c6c: 623b str r3, [r7, #32] + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + 8003c6e: 68fb ldr r3, [r7, #12] + 8003c70: 681b ldr r3, [r3, #0] + 8003c72: 2280 movs r2, #128 ; 0x80 + 8003c74: 00d2 lsls r2, r2, #3 + 8003c76: 61da str r2, [r3, #28] + + status = HAL_ERROR; + 8003c78: 2327 movs r3, #39 ; 0x27 + 8003c7a: 18fb adds r3, r7, r3 + 8003c7c: 2201 movs r2, #1 + 8003c7e: 701a strb r2, [r3, #0] + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + 8003c80: 69ba ldr r2, [r7, #24] + 8003c82: 2380 movs r3, #128 ; 0x80 + 8003c84: 009b lsls r3, r3, #2 + 8003c86: 4013 ands r3, r2 + 8003c88: d00c beq.n 8003ca4 + { + error_code |= HAL_I2C_ERROR_ARLO; + 8003c8a: 6a3b ldr r3, [r7, #32] + 8003c8c: 2202 movs r2, #2 + 8003c8e: 4313 orrs r3, r2 + 8003c90: 623b str r3, [r7, #32] + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + 8003c92: 68fb ldr r3, [r7, #12] + 8003c94: 681b ldr r3, [r3, #0] + 8003c96: 2280 movs r2, #128 ; 0x80 + 8003c98: 0092 lsls r2, r2, #2 + 8003c9a: 61da str r2, [r3, #28] + + status = HAL_ERROR; + 8003c9c: 2327 movs r3, #39 ; 0x27 + 8003c9e: 18fb adds r3, r7, r3 + 8003ca0: 2201 movs r2, #1 + 8003ca2: 701a strb r2, [r3, #0] + } + + if (status != HAL_OK) + 8003ca4: 2327 movs r3, #39 ; 0x27 + 8003ca6: 18fb adds r3, r7, r3 + 8003ca8: 781b ldrb r3, [r3, #0] + 8003caa: 2b00 cmp r3, #0 + 8003cac: d01d beq.n 8003cea + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 8003cae: 68fb ldr r3, [r7, #12] + 8003cb0: 0018 movs r0, r3 + 8003cb2: f7ff fca8 bl 8003606 + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8003cb6: 68fb ldr r3, [r7, #12] + 8003cb8: 681b ldr r3, [r3, #0] + 8003cba: 685a ldr r2, [r3, #4] + 8003cbc: 68fb ldr r3, [r7, #12] + 8003cbe: 681b ldr r3, [r3, #0] + 8003cc0: 490d ldr r1, [pc, #52] ; (8003cf8 ) + 8003cc2: 400a ands r2, r1 + 8003cc4: 605a str r2, [r3, #4] + + hi2c->ErrorCode |= error_code; + 8003cc6: 68fb ldr r3, [r7, #12] + 8003cc8: 6c5a ldr r2, [r3, #68] ; 0x44 + 8003cca: 6a3b ldr r3, [r7, #32] + 8003ccc: 431a orrs r2, r3 + 8003cce: 68fb ldr r3, [r7, #12] + 8003cd0: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8003cd2: 68fb ldr r3, [r7, #12] + 8003cd4: 2241 movs r2, #65 ; 0x41 + 8003cd6: 2120 movs r1, #32 + 8003cd8: 5499 strb r1, [r3, r2] + hi2c->Mode = HAL_I2C_MODE_NONE; + 8003cda: 68fb ldr r3, [r7, #12] + 8003cdc: 2242 movs r2, #66 ; 0x42 + 8003cde: 2100 movs r1, #0 + 8003ce0: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003ce2: 68fb ldr r3, [r7, #12] + 8003ce4: 2240 movs r2, #64 ; 0x40 + 8003ce6: 2100 movs r1, #0 + 8003ce8: 5499 strb r1, [r3, r2] + } + + return status; + 8003cea: 2327 movs r3, #39 ; 0x27 + 8003cec: 18fb adds r3, r7, r3 + 8003cee: 781b ldrb r3, [r3, #0] +} + 8003cf0: 0018 movs r0, r3 + 8003cf2: 46bd mov sp, r7 + 8003cf4: b00b add sp, #44 ; 0x2c + 8003cf6: bd90 pop {r4, r7, pc} + 8003cf8: fe00e800 .word 0xfe00e800 + +08003cfc : + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + 8003cfc: b590 push {r4, r7, lr} + 8003cfe: b087 sub sp, #28 + 8003d00: af00 add r7, sp, #0 + 8003d02: 60f8 str r0, [r7, #12] + 8003d04: 0008 movs r0, r1 + 8003d06: 0011 movs r1, r2 + 8003d08: 607b str r3, [r7, #4] + 8003d0a: 240a movs r4, #10 + 8003d0c: 193b adds r3, r7, r4 + 8003d0e: 1c02 adds r2, r0, #0 + 8003d10: 801a strh r2, [r3, #0] + 8003d12: 2009 movs r0, #9 + 8003d14: 183b adds r3, r7, r0 + 8003d16: 1c0a adds r2, r1, #0 + 8003d18: 701a strb r2, [r3, #0] + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + 8003d1a: 193b adds r3, r7, r4 + 8003d1c: 881b ldrh r3, [r3, #0] + 8003d1e: 059b lsls r3, r3, #22 + 8003d20: 0d9a lsrs r2, r3, #22 + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 8003d22: 183b adds r3, r7, r0 + 8003d24: 781b ldrb r3, [r3, #0] + 8003d26: 0419 lsls r1, r3, #16 + 8003d28: 23ff movs r3, #255 ; 0xff + 8003d2a: 041b lsls r3, r3, #16 + 8003d2c: 400b ands r3, r1 + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + 8003d2e: 431a orrs r2, r3 + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 8003d30: 687b ldr r3, [r7, #4] + 8003d32: 431a orrs r2, r3 + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + 8003d34: 6abb ldr r3, [r7, #40] ; 0x28 + 8003d36: 4313 orrs r3, r2 + 8003d38: 005b lsls r3, r3, #1 + 8003d3a: 085b lsrs r3, r3, #1 + 8003d3c: 617b str r3, [r7, #20] + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + 8003d3e: 68fb ldr r3, [r7, #12] + 8003d40: 681b ldr r3, [r3, #0] + 8003d42: 685b ldr r3, [r3, #4] + 8003d44: 6aba ldr r2, [r7, #40] ; 0x28 + 8003d46: 0d51 lsrs r1, r2, #21 + 8003d48: 2280 movs r2, #128 ; 0x80 + 8003d4a: 00d2 lsls r2, r2, #3 + 8003d4c: 400a ands r2, r1 + 8003d4e: 4907 ldr r1, [pc, #28] ; (8003d6c ) + 8003d50: 430a orrs r2, r1 + 8003d52: 43d2 mvns r2, r2 + 8003d54: 401a ands r2, r3 + 8003d56: 0011 movs r1, r2 + 8003d58: 68fb ldr r3, [r7, #12] + 8003d5a: 681b ldr r3, [r3, #0] + 8003d5c: 697a ldr r2, [r7, #20] + 8003d5e: 430a orrs r2, r1 + 8003d60: 605a str r2, [r3, #4] + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + 8003d62: 46c0 nop ; (mov r8, r8) + 8003d64: 46bd mov sp, r7 + 8003d66: b007 add sp, #28 + 8003d68: bd90 pop {r4, r7, pc} + 8003d6a: 46c0 nop ; (mov r8, r8) + 8003d6c: 03ff63ff .word 0x03ff63ff + +08003d70 : + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + 8003d70: b580 push {r7, lr} + 8003d72: b084 sub sp, #16 + 8003d74: af00 add r7, sp, #0 + 8003d76: 6078 str r0, [r7, #4] + 8003d78: 000a movs r2, r1 + 8003d7a: 1cbb adds r3, r7, #2 + 8003d7c: 801a strh r2, [r3, #0] + uint32_t tmpisr = 0U; + 8003d7e: 2300 movs r3, #0 + 8003d80: 60fb str r3, [r7, #12] + + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + 8003d82: 687b ldr r3, [r7, #4] + 8003d84: 6b5a ldr r2, [r3, #52] ; 0x34 + 8003d86: 4b3c ldr r3, [pc, #240] ; (8003e78 ) + 8003d88: 429a cmp r2, r3 + 8003d8a: d035 beq.n 8003df8 + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + 8003d8c: 687b ldr r3, [r7, #4] + 8003d8e: 6b5a ldr r2, [r3, #52] ; 0x34 + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + 8003d90: 4b3a ldr r3, [pc, #232] ; (8003e7c ) + 8003d92: 429a cmp r2, r3 + 8003d94: d030 beq.n 8003df8 + (hi2c->XferISR != I2C_Mem_ISR_DMA)) + 8003d96: 687b ldr r3, [r7, #4] + 8003d98: 6b5a ldr r2, [r3, #52] ; 0x34 + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + 8003d9a: 4b39 ldr r3, [pc, #228] ; (8003e80 ) + 8003d9c: 429a cmp r2, r3 + 8003d9e: d02b beq.n 8003df8 + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 8003da0: 1cbb adds r3, r7, #2 + 8003da2: 2200 movs r2, #0 + 8003da4: 5e9b ldrsh r3, [r3, r2] + 8003da6: 2b00 cmp r3, #0 + 8003da8: da03 bge.n 8003db2 + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 8003daa: 68fb ldr r3, [r7, #12] + 8003dac: 22b8 movs r2, #184 ; 0xb8 + 8003dae: 4313 orrs r3, r2 + 8003db0: 60fb str r3, [r7, #12] + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 8003db2: 1cbb adds r3, r7, #2 + 8003db4: 881b ldrh r3, [r3, #0] + 8003db6: 2201 movs r2, #1 + 8003db8: 4013 ands r3, r2 + 8003dba: d003 beq.n 8003dc4 + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 8003dbc: 68fb ldr r3, [r7, #12] + 8003dbe: 22f2 movs r2, #242 ; 0xf2 + 8003dc0: 4313 orrs r3, r2 + 8003dc2: 60fb str r3, [r7, #12] + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 8003dc4: 1cbb adds r3, r7, #2 + 8003dc6: 881b ldrh r3, [r3, #0] + 8003dc8: 2202 movs r2, #2 + 8003dca: 4013 ands r3, r2 + 8003dcc: d003 beq.n 8003dd6 + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 8003dce: 68fb ldr r3, [r7, #12] + 8003dd0: 22f4 movs r2, #244 ; 0xf4 + 8003dd2: 4313 orrs r3, r2 + 8003dd4: 60fb str r3, [r7, #12] + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + 8003dd6: 1cbb adds r3, r7, #2 + 8003dd8: 881b ldrh r3, [r3, #0] + 8003dda: 2b10 cmp r3, #16 + 8003ddc: d103 bne.n 8003de6 + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + 8003dde: 68fb ldr r3, [r7, #12] + 8003de0: 2290 movs r2, #144 ; 0x90 + 8003de2: 4313 orrs r3, r2 + 8003de4: 60fb str r3, [r7, #12] + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + 8003de6: 1cbb adds r3, r7, #2 + 8003de8: 881b ldrh r3, [r3, #0] + 8003dea: 2b20 cmp r3, #32 + 8003dec: d137 bne.n 8003e5e + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + 8003dee: 68fb ldr r3, [r7, #12] + 8003df0: 2220 movs r2, #32 + 8003df2: 4313 orrs r3, r2 + 8003df4: 60fb str r3, [r7, #12] + if (InterruptRequest == I2C_XFER_CPLT_IT) + 8003df6: e032 b.n 8003e5e + } + } + + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 8003df8: 1cbb adds r3, r7, #2 + 8003dfa: 2200 movs r2, #0 + 8003dfc: 5e9b ldrsh r3, [r3, r2] + 8003dfe: 2b00 cmp r3, #0 + 8003e00: da03 bge.n 8003e0a + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 8003e02: 68fb ldr r3, [r7, #12] + 8003e04: 22b8 movs r2, #184 ; 0xb8 + 8003e06: 4313 orrs r3, r2 + 8003e08: 60fb str r3, [r7, #12] + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 8003e0a: 1cbb adds r3, r7, #2 + 8003e0c: 881b ldrh r3, [r3, #0] + 8003e0e: 2201 movs r2, #1 + 8003e10: 4013 ands r3, r2 + 8003e12: d003 beq.n 8003e1c + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 8003e14: 68fb ldr r3, [r7, #12] + 8003e16: 22f2 movs r2, #242 ; 0xf2 + 8003e18: 4313 orrs r3, r2 + 8003e1a: 60fb str r3, [r7, #12] + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 8003e1c: 1cbb adds r3, r7, #2 + 8003e1e: 881b ldrh r3, [r3, #0] + 8003e20: 2202 movs r2, #2 + 8003e22: 4013 ands r3, r2 + 8003e24: d003 beq.n 8003e2e + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 8003e26: 68fb ldr r3, [r7, #12] + 8003e28: 22f4 movs r2, #244 ; 0xf4 + 8003e2a: 4313 orrs r3, r2 + 8003e2c: 60fb str r3, [r7, #12] + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + 8003e2e: 1cbb adds r3, r7, #2 + 8003e30: 881b ldrh r3, [r3, #0] + 8003e32: 2b10 cmp r3, #16 + 8003e34: d103 bne.n 8003e3e + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + 8003e36: 68fb ldr r3, [r7, #12] + 8003e38: 2290 movs r2, #144 ; 0x90 + 8003e3a: 4313 orrs r3, r2 + 8003e3c: 60fb str r3, [r7, #12] + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + 8003e3e: 1cbb adds r3, r7, #2 + 8003e40: 881b ldrh r3, [r3, #0] + 8003e42: 2b20 cmp r3, #32 + 8003e44: d103 bne.n 8003e4e + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + 8003e46: 68fb ldr r3, [r7, #12] + 8003e48: 2260 movs r2, #96 ; 0x60 + 8003e4a: 4313 orrs r3, r2 + 8003e4c: 60fb str r3, [r7, #12] + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + 8003e4e: 1cbb adds r3, r7, #2 + 8003e50: 881b ldrh r3, [r3, #0] + 8003e52: 2b40 cmp r3, #64 ; 0x40 + 8003e54: d103 bne.n 8003e5e + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + 8003e56: 68fb ldr r3, [r7, #12] + 8003e58: 2240 movs r2, #64 ; 0x40 + 8003e5a: 4313 orrs r3, r2 + 8003e5c: 60fb str r3, [r7, #12] + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + 8003e5e: 687b ldr r3, [r7, #4] + 8003e60: 681b ldr r3, [r3, #0] + 8003e62: 6819 ldr r1, [r3, #0] + 8003e64: 687b ldr r3, [r7, #4] + 8003e66: 681b ldr r3, [r3, #0] + 8003e68: 68fa ldr r2, [r7, #12] + 8003e6a: 430a orrs r2, r1 + 8003e6c: 601a str r2, [r3, #0] +} + 8003e6e: 46c0 nop ; (mov r8, r8) + 8003e70: 46bd mov sp, r7 + 8003e72: b004 add sp, #16 + 8003e74: bd80 pop {r7, pc} + 8003e76: 46c0 nop ; (mov r8, r8) + 8003e78: 080025a1 .word 0x080025a1 + 8003e7c: 080029f1 .word 0x080029f1 + 8003e80: 08002799 .word 0x08002799 + +08003e84 : + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + 8003e84: b580 push {r7, lr} + 8003e86: b084 sub sp, #16 + 8003e88: af00 add r7, sp, #0 + 8003e8a: 6078 str r0, [r7, #4] + 8003e8c: 000a movs r2, r1 + 8003e8e: 1cbb adds r3, r7, #2 + 8003e90: 801a strh r2, [r3, #0] + uint32_t tmpisr = 0U; + 8003e92: 2300 movs r3, #0 + 8003e94: 60fb str r3, [r7, #12] + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 8003e96: 1cbb adds r3, r7, #2 + 8003e98: 881b ldrh r3, [r3, #0] + 8003e9a: 2201 movs r2, #1 + 8003e9c: 4013 ands r3, r2 + 8003e9e: d010 beq.n 8003ec2 + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + 8003ea0: 68fb ldr r3, [r7, #12] + 8003ea2: 2242 movs r2, #66 ; 0x42 + 8003ea4: 4313 orrs r3, r2 + 8003ea6: 60fb str r3, [r7, #12] + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 8003ea8: 687b ldr r3, [r7, #4] + 8003eaa: 2241 movs r2, #65 ; 0x41 + 8003eac: 5c9b ldrb r3, [r3, r2] + 8003eae: b2db uxtb r3, r3 + 8003eb0: 001a movs r2, r3 + 8003eb2: 2328 movs r3, #40 ; 0x28 + 8003eb4: 4013 ands r3, r2 + 8003eb6: 2b28 cmp r3, #40 ; 0x28 + 8003eb8: d003 beq.n 8003ec2 + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 8003eba: 68fb ldr r3, [r7, #12] + 8003ebc: 22b0 movs r2, #176 ; 0xb0 + 8003ebe: 4313 orrs r3, r2 + 8003ec0: 60fb str r3, [r7, #12] + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 8003ec2: 1cbb adds r3, r7, #2 + 8003ec4: 881b ldrh r3, [r3, #0] + 8003ec6: 2202 movs r2, #2 + 8003ec8: 4013 ands r3, r2 + 8003eca: d010 beq.n 8003eee + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + 8003ecc: 68fb ldr r3, [r7, #12] + 8003ece: 2244 movs r2, #68 ; 0x44 + 8003ed0: 4313 orrs r3, r2 + 8003ed2: 60fb str r3, [r7, #12] + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 8003ed4: 687b ldr r3, [r7, #4] + 8003ed6: 2241 movs r2, #65 ; 0x41 + 8003ed8: 5c9b ldrb r3, [r3, r2] + 8003eda: b2db uxtb r3, r3 + 8003edc: 001a movs r2, r3 + 8003ede: 2328 movs r3, #40 ; 0x28 + 8003ee0: 4013 ands r3, r2 + 8003ee2: 2b28 cmp r3, #40 ; 0x28 + 8003ee4: d003 beq.n 8003eee + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 8003ee6: 68fb ldr r3, [r7, #12] + 8003ee8: 22b0 movs r2, #176 ; 0xb0 + 8003eea: 4313 orrs r3, r2 + 8003eec: 60fb str r3, [r7, #12] + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 8003eee: 1cbb adds r3, r7, #2 + 8003ef0: 2200 movs r2, #0 + 8003ef2: 5e9b ldrsh r3, [r3, r2] + 8003ef4: 2b00 cmp r3, #0 + 8003ef6: da03 bge.n 8003f00 + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 8003ef8: 68fb ldr r3, [r7, #12] + 8003efa: 22b8 movs r2, #184 ; 0xb8 + 8003efc: 4313 orrs r3, r2 + 8003efe: 60fb str r3, [r7, #12] + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + 8003f00: 1cbb adds r3, r7, #2 + 8003f02: 881b ldrh r3, [r3, #0] + 8003f04: 2b10 cmp r3, #16 + 8003f06: d103 bne.n 8003f10 + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + 8003f08: 68fb ldr r3, [r7, #12] + 8003f0a: 2290 movs r2, #144 ; 0x90 + 8003f0c: 4313 orrs r3, r2 + 8003f0e: 60fb str r3, [r7, #12] + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + 8003f10: 1cbb adds r3, r7, #2 + 8003f12: 881b ldrh r3, [r3, #0] + 8003f14: 2b20 cmp r3, #32 + 8003f16: d103 bne.n 8003f20 + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + 8003f18: 68fb ldr r3, [r7, #12] + 8003f1a: 2220 movs r2, #32 + 8003f1c: 4313 orrs r3, r2 + 8003f1e: 60fb str r3, [r7, #12] + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + 8003f20: 1cbb adds r3, r7, #2 + 8003f22: 881b ldrh r3, [r3, #0] + 8003f24: 2b40 cmp r3, #64 ; 0x40 + 8003f26: d103 bne.n 8003f30 + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + 8003f28: 68fb ldr r3, [r7, #12] + 8003f2a: 2240 movs r2, #64 ; 0x40 + 8003f2c: 4313 orrs r3, r2 + 8003f2e: 60fb str r3, [r7, #12] + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + 8003f30: 687b ldr r3, [r7, #4] + 8003f32: 681b ldr r3, [r3, #0] + 8003f34: 681a ldr r2, [r3, #0] + 8003f36: 68fb ldr r3, [r7, #12] + 8003f38: 43d9 mvns r1, r3 + 8003f3a: 687b ldr r3, [r7, #4] + 8003f3c: 681b ldr r3, [r3, #0] + 8003f3e: 400a ands r2, r1 + 8003f40: 601a str r2, [r3, #0] +} + 8003f42: 46c0 nop ; (mov r8, r8) + 8003f44: 46bd mov sp, r7 + 8003f46: b004 add sp, #16 + 8003f48: bd80 pop {r7, pc} + ... + +08003f4c : + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + 8003f4c: b580 push {r7, lr} + 8003f4e: b082 sub sp, #8 + 8003f50: af00 add r7, sp, #0 + 8003f52: 6078 str r0, [r7, #4] + 8003f54: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 8003f56: 687b ldr r3, [r7, #4] + 8003f58: 2241 movs r2, #65 ; 0x41 + 8003f5a: 5c9b ldrb r3, [r3, r2] + 8003f5c: b2db uxtb r3, r3 + 8003f5e: 2b20 cmp r3, #32 + 8003f60: d138 bne.n 8003fd4 + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8003f62: 687b ldr r3, [r7, #4] + 8003f64: 2240 movs r2, #64 ; 0x40 + 8003f66: 5c9b ldrb r3, [r3, r2] + 8003f68: 2b01 cmp r3, #1 + 8003f6a: d101 bne.n 8003f70 + 8003f6c: 2302 movs r3, #2 + 8003f6e: e032 b.n 8003fd6 + 8003f70: 687b ldr r3, [r7, #4] + 8003f72: 2240 movs r2, #64 ; 0x40 + 8003f74: 2101 movs r1, #1 + 8003f76: 5499 strb r1, [r3, r2] + + hi2c->State = HAL_I2C_STATE_BUSY; + 8003f78: 687b ldr r3, [r7, #4] + 8003f7a: 2241 movs r2, #65 ; 0x41 + 8003f7c: 2124 movs r1, #36 ; 0x24 + 8003f7e: 5499 strb r1, [r3, r2] + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8003f80: 687b ldr r3, [r7, #4] + 8003f82: 681b ldr r3, [r3, #0] + 8003f84: 681a ldr r2, [r3, #0] + 8003f86: 687b ldr r3, [r7, #4] + 8003f88: 681b ldr r3, [r3, #0] + 8003f8a: 2101 movs r1, #1 + 8003f8c: 438a bics r2, r1 + 8003f8e: 601a str r2, [r3, #0] + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 8003f90: 687b ldr r3, [r7, #4] + 8003f92: 681b ldr r3, [r3, #0] + 8003f94: 681a ldr r2, [r3, #0] + 8003f96: 687b ldr r3, [r7, #4] + 8003f98: 681b ldr r3, [r3, #0] + 8003f9a: 4911 ldr r1, [pc, #68] ; (8003fe0 ) + 8003f9c: 400a ands r2, r1 + 8003f9e: 601a str r2, [r3, #0] + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + 8003fa0: 687b ldr r3, [r7, #4] + 8003fa2: 681b ldr r3, [r3, #0] + 8003fa4: 6819 ldr r1, [r3, #0] + 8003fa6: 687b ldr r3, [r7, #4] + 8003fa8: 681b ldr r3, [r3, #0] + 8003faa: 683a ldr r2, [r7, #0] + 8003fac: 430a orrs r2, r1 + 8003fae: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 8003fb0: 687b ldr r3, [r7, #4] + 8003fb2: 681b ldr r3, [r3, #0] + 8003fb4: 681a ldr r2, [r3, #0] + 8003fb6: 687b ldr r3, [r7, #4] + 8003fb8: 681b ldr r3, [r3, #0] + 8003fba: 2101 movs r1, #1 + 8003fbc: 430a orrs r2, r1 + 8003fbe: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 8003fc0: 687b ldr r3, [r7, #4] + 8003fc2: 2241 movs r2, #65 ; 0x41 + 8003fc4: 2120 movs r1, #32 + 8003fc6: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003fc8: 687b ldr r3, [r7, #4] + 8003fca: 2240 movs r2, #64 ; 0x40 + 8003fcc: 2100 movs r1, #0 + 8003fce: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8003fd0: 2300 movs r3, #0 + 8003fd2: e000 b.n 8003fd6 + } + else + { + return HAL_BUSY; + 8003fd4: 2302 movs r3, #2 + } +} + 8003fd6: 0018 movs r0, r3 + 8003fd8: 46bd mov sp, r7 + 8003fda: b002 add sp, #8 + 8003fdc: bd80 pop {r7, pc} + 8003fde: 46c0 nop ; (mov r8, r8) + 8003fe0: ffffefff .word 0xffffefff + +08003fe4 : + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + 8003fe4: b580 push {r7, lr} + 8003fe6: b084 sub sp, #16 + 8003fe8: af00 add r7, sp, #0 + 8003fea: 6078 str r0, [r7, #4] + 8003fec: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 8003fee: 687b ldr r3, [r7, #4] + 8003ff0: 2241 movs r2, #65 ; 0x41 + 8003ff2: 5c9b ldrb r3, [r3, r2] + 8003ff4: b2db uxtb r3, r3 + 8003ff6: 2b20 cmp r3, #32 + 8003ff8: d139 bne.n 800406e + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8003ffa: 687b ldr r3, [r7, #4] + 8003ffc: 2240 movs r2, #64 ; 0x40 + 8003ffe: 5c9b ldrb r3, [r3, r2] + 8004000: 2b01 cmp r3, #1 + 8004002: d101 bne.n 8004008 + 8004004: 2302 movs r3, #2 + 8004006: e033 b.n 8004070 + 8004008: 687b ldr r3, [r7, #4] + 800400a: 2240 movs r2, #64 ; 0x40 + 800400c: 2101 movs r1, #1 + 800400e: 5499 strb r1, [r3, r2] + + hi2c->State = HAL_I2C_STATE_BUSY; + 8004010: 687b ldr r3, [r7, #4] + 8004012: 2241 movs r2, #65 ; 0x41 + 8004014: 2124 movs r1, #36 ; 0x24 + 8004016: 5499 strb r1, [r3, r2] + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8004018: 687b ldr r3, [r7, #4] + 800401a: 681b ldr r3, [r3, #0] + 800401c: 681a ldr r2, [r3, #0] + 800401e: 687b ldr r3, [r7, #4] + 8004020: 681b ldr r3, [r3, #0] + 8004022: 2101 movs r1, #1 + 8004024: 438a bics r2, r1 + 8004026: 601a str r2, [r3, #0] + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + 8004028: 687b ldr r3, [r7, #4] + 800402a: 681b ldr r3, [r3, #0] + 800402c: 681b ldr r3, [r3, #0] + 800402e: 60fb str r3, [r7, #12] + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + 8004030: 68fb ldr r3, [r7, #12] + 8004032: 4a11 ldr r2, [pc, #68] ; (8004078 ) + 8004034: 4013 ands r3, r2 + 8004036: 60fb str r3, [r7, #12] + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + 8004038: 683b ldr r3, [r7, #0] + 800403a: 021b lsls r3, r3, #8 + 800403c: 68fa ldr r2, [r7, #12] + 800403e: 4313 orrs r3, r2 + 8004040: 60fb str r3, [r7, #12] + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + 8004042: 687b ldr r3, [r7, #4] + 8004044: 681b ldr r3, [r3, #0] + 8004046: 68fa ldr r2, [r7, #12] + 8004048: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 800404a: 687b ldr r3, [r7, #4] + 800404c: 681b ldr r3, [r3, #0] + 800404e: 681a ldr r2, [r3, #0] + 8004050: 687b ldr r3, [r7, #4] + 8004052: 681b ldr r3, [r3, #0] + 8004054: 2101 movs r1, #1 + 8004056: 430a orrs r2, r1 + 8004058: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 800405a: 687b ldr r3, [r7, #4] + 800405c: 2241 movs r2, #65 ; 0x41 + 800405e: 2120 movs r1, #32 + 8004060: 5499 strb r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004062: 687b ldr r3, [r7, #4] + 8004064: 2240 movs r2, #64 ; 0x40 + 8004066: 2100 movs r1, #0 + 8004068: 5499 strb r1, [r3, r2] + + return HAL_OK; + 800406a: 2300 movs r3, #0 + 800406c: e000 b.n 8004070 + } + else + { + return HAL_BUSY; + 800406e: 2302 movs r3, #2 + } +} + 8004070: 0018 movs r0, r3 + 8004072: 46bd mov sp, r7 + 8004074: b004 add sp, #16 + 8004076: bd80 pop {r7, pc} + 8004078: fffff0ff .word 0xfffff0ff + +0800407c : + * cleared before returning the status. If the flag is not cleared within + * 6 microseconds, HAL_TIMEOUT status is reported. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + 800407c: b580 push {r7, lr} + 800407e: b084 sub sp, #16 + 8004080: af00 add r7, sp, #0 + 8004082: 6078 str r0, [r7, #4] + uint32_t wait_loop_index; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Modify voltage scaling range */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); + 8004084: 4b19 ldr r3, [pc, #100] ; (80040ec ) + 8004086: 681b ldr r3, [r3, #0] + 8004088: 4a19 ldr r2, [pc, #100] ; (80040f0 ) + 800408a: 4013 ands r3, r2 + 800408c: 0019 movs r1, r3 + 800408e: 4b17 ldr r3, [pc, #92] ; (80040ec ) + 8004090: 687a ldr r2, [r7, #4] + 8004092: 430a orrs r2, r1 + 8004094: 601a str r2, [r3, #0] + + /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + 8004096: 687a ldr r2, [r7, #4] + 8004098: 2380 movs r3, #128 ; 0x80 + 800409a: 009b lsls r3, r3, #2 + 800409c: 429a cmp r2, r3 + 800409e: d11f bne.n 80040e0 + { + /* Set timeout value */ + wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; + 80040a0: 4b14 ldr r3, [pc, #80] ; (80040f4 ) + 80040a2: 681a ldr r2, [r3, #0] + 80040a4: 0013 movs r3, r2 + 80040a6: 005b lsls r3, r3, #1 + 80040a8: 189b adds r3, r3, r2 + 80040aa: 005b lsls r3, r3, #1 + 80040ac: 4912 ldr r1, [pc, #72] ; (80040f8 ) + 80040ae: 0018 movs r0, r3 + 80040b0: f7fc f828 bl 8000104 <__udivsi3> + 80040b4: 0003 movs r3, r0 + 80040b6: 3301 adds r3, #1 + 80040b8: 60fb str r3, [r7, #12] + + /* Wait until VOSF is reset */ + while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + 80040ba: e008 b.n 80040ce + { + if (wait_loop_index != 0U) + 80040bc: 68fb ldr r3, [r7, #12] + 80040be: 2b00 cmp r3, #0 + 80040c0: d003 beq.n 80040ca + { + wait_loop_index--; + 80040c2: 68fb ldr r3, [r7, #12] + 80040c4: 3b01 subs r3, #1 + 80040c6: 60fb str r3, [r7, #12] + 80040c8: e001 b.n 80040ce + } + else + { + return HAL_TIMEOUT; + 80040ca: 2303 movs r3, #3 + 80040cc: e009 b.n 80040e2 + while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + 80040ce: 4b07 ldr r3, [pc, #28] ; (80040ec ) + 80040d0: 695a ldr r2, [r3, #20] + 80040d2: 2380 movs r3, #128 ; 0x80 + 80040d4: 00db lsls r3, r3, #3 + 80040d6: 401a ands r2, r3 + 80040d8: 2380 movs r3, #128 ; 0x80 + 80040da: 00db lsls r3, r3, #3 + 80040dc: 429a cmp r2, r3 + 80040de: d0ed beq.n 80040bc + } + } + } + + return HAL_OK; + 80040e0: 2300 movs r3, #0 +} + 80040e2: 0018 movs r0, r3 + 80040e4: 46bd mov sp, r7 + 80040e6: b004 add sp, #16 + 80040e8: bd80 pop {r7, pc} + 80040ea: 46c0 nop ; (mov r8, r8) + 80040ec: 40007000 .word 0x40007000 + 80040f0: fffff9ff .word 0xfffff9ff + 80040f4: 20000000 .word 0x20000000 + 80040f8: 000f4240 .word 0x000f4240 + +080040fc : + * supported by this function. User should request a transition to LSE Off + * first and then to LSE On or LSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 80040fc: b580 push {r7, lr} + 80040fe: b088 sub sp, #32 + 8004100: af00 add r7, sp, #0 + 8004102: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t temp_sysclksrc; + uint32_t temp_pllckcfg; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8004104: 687b ldr r3, [r7, #4] + 8004106: 2b00 cmp r3, #0 + 8004108: d102 bne.n 8004110 + { + return HAL_ERROR; + 800410a: 2301 movs r3, #1 + 800410c: f000 fb50 bl 80047b0 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8004110: 687b ldr r3, [r7, #4] + 8004112: 681b ldr r3, [r3, #0] + 8004114: 2201 movs r2, #1 + 8004116: 4013 ands r3, r2 + 8004118: d100 bne.n 800411c + 800411a: e07c b.n 8004216 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 800411c: 4bc3 ldr r3, [pc, #780] ; (800442c ) + 800411e: 689b ldr r3, [r3, #8] + 8004120: 2238 movs r2, #56 ; 0x38 + 8004122: 4013 ands r3, r2 + 8004124: 61bb str r3, [r7, #24] + temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8004126: 4bc1 ldr r3, [pc, #772] ; (800442c ) + 8004128: 68db ldr r3, [r3, #12] + 800412a: 2203 movs r2, #3 + 800412c: 4013 ands r3, r2 + 800412e: 617b str r3, [r7, #20] + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) + 8004130: 69bb ldr r3, [r7, #24] + 8004132: 2b10 cmp r3, #16 + 8004134: d102 bne.n 800413c + 8004136: 697b ldr r3, [r7, #20] + 8004138: 2b03 cmp r3, #3 + 800413a: d002 beq.n 8004142 + || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) + 800413c: 69bb ldr r3, [r7, #24] + 800413e: 2b08 cmp r3, #8 + 8004140: d10b bne.n 800415a + { + if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8004142: 4bba ldr r3, [pc, #744] ; (800442c ) + 8004144: 681a ldr r2, [r3, #0] + 8004146: 2380 movs r3, #128 ; 0x80 + 8004148: 029b lsls r3, r3, #10 + 800414a: 4013 ands r3, r2 + 800414c: d062 beq.n 8004214 + 800414e: 687b ldr r3, [r7, #4] + 8004150: 685b ldr r3, [r3, #4] + 8004152: 2b00 cmp r3, #0 + 8004154: d15e bne.n 8004214 + { + return HAL_ERROR; + 8004156: 2301 movs r3, #1 + 8004158: e32a b.n 80047b0 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 800415a: 687b ldr r3, [r7, #4] + 800415c: 685a ldr r2, [r3, #4] + 800415e: 2380 movs r3, #128 ; 0x80 + 8004160: 025b lsls r3, r3, #9 + 8004162: 429a cmp r2, r3 + 8004164: d107 bne.n 8004176 + 8004166: 4bb1 ldr r3, [pc, #708] ; (800442c ) + 8004168: 681a ldr r2, [r3, #0] + 800416a: 4bb0 ldr r3, [pc, #704] ; (800442c ) + 800416c: 2180 movs r1, #128 ; 0x80 + 800416e: 0249 lsls r1, r1, #9 + 8004170: 430a orrs r2, r1 + 8004172: 601a str r2, [r3, #0] + 8004174: e020 b.n 80041b8 + 8004176: 687b ldr r3, [r7, #4] + 8004178: 685a ldr r2, [r3, #4] + 800417a: 23a0 movs r3, #160 ; 0xa0 + 800417c: 02db lsls r3, r3, #11 + 800417e: 429a cmp r2, r3 + 8004180: d10e bne.n 80041a0 + 8004182: 4baa ldr r3, [pc, #680] ; (800442c ) + 8004184: 681a ldr r2, [r3, #0] + 8004186: 4ba9 ldr r3, [pc, #676] ; (800442c ) + 8004188: 2180 movs r1, #128 ; 0x80 + 800418a: 02c9 lsls r1, r1, #11 + 800418c: 430a orrs r2, r1 + 800418e: 601a str r2, [r3, #0] + 8004190: 4ba6 ldr r3, [pc, #664] ; (800442c ) + 8004192: 681a ldr r2, [r3, #0] + 8004194: 4ba5 ldr r3, [pc, #660] ; (800442c ) + 8004196: 2180 movs r1, #128 ; 0x80 + 8004198: 0249 lsls r1, r1, #9 + 800419a: 430a orrs r2, r1 + 800419c: 601a str r2, [r3, #0] + 800419e: e00b b.n 80041b8 + 80041a0: 4ba2 ldr r3, [pc, #648] ; (800442c ) + 80041a2: 681a ldr r2, [r3, #0] + 80041a4: 4ba1 ldr r3, [pc, #644] ; (800442c ) + 80041a6: 49a2 ldr r1, [pc, #648] ; (8004430 ) + 80041a8: 400a ands r2, r1 + 80041aa: 601a str r2, [r3, #0] + 80041ac: 4b9f ldr r3, [pc, #636] ; (800442c ) + 80041ae: 681a ldr r2, [r3, #0] + 80041b0: 4b9e ldr r3, [pc, #632] ; (800442c ) + 80041b2: 49a0 ldr r1, [pc, #640] ; (8004434 ) + 80041b4: 400a ands r2, r1 + 80041b6: 601a str r2, [r3, #0] + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80041b8: 687b ldr r3, [r7, #4] + 80041ba: 685b ldr r3, [r3, #4] + 80041bc: 2b00 cmp r3, #0 + 80041be: d014 beq.n 80041ea + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80041c0: f7fc fdb0 bl 8000d24 + 80041c4: 0003 movs r3, r0 + 80041c6: 613b str r3, [r7, #16] + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 80041c8: e008 b.n 80041dc + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 80041ca: f7fc fdab bl 8000d24 + 80041ce: 0002 movs r2, r0 + 80041d0: 693b ldr r3, [r7, #16] + 80041d2: 1ad3 subs r3, r2, r3 + 80041d4: 2b64 cmp r3, #100 ; 0x64 + 80041d6: d901 bls.n 80041dc + { + return HAL_TIMEOUT; + 80041d8: 2303 movs r3, #3 + 80041da: e2e9 b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 80041dc: 4b93 ldr r3, [pc, #588] ; (800442c ) + 80041de: 681a ldr r2, [r3, #0] + 80041e0: 2380 movs r3, #128 ; 0x80 + 80041e2: 029b lsls r3, r3, #10 + 80041e4: 4013 ands r3, r2 + 80041e6: d0f0 beq.n 80041ca + 80041e8: e015 b.n 8004216 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80041ea: f7fc fd9b bl 8000d24 + 80041ee: 0003 movs r3, r0 + 80041f0: 613b str r3, [r7, #16] + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + 80041f2: e008 b.n 8004206 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 80041f4: f7fc fd96 bl 8000d24 + 80041f8: 0002 movs r2, r0 + 80041fa: 693b ldr r3, [r7, #16] + 80041fc: 1ad3 subs r3, r2, r3 + 80041fe: 2b64 cmp r3, #100 ; 0x64 + 8004200: d901 bls.n 8004206 + { + return HAL_TIMEOUT; + 8004202: 2303 movs r3, #3 + 8004204: e2d4 b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + 8004206: 4b89 ldr r3, [pc, #548] ; (800442c ) + 8004208: 681a ldr r2, [r3, #0] + 800420a: 2380 movs r3, #128 ; 0x80 + 800420c: 029b lsls r3, r3, #10 + 800420e: 4013 ands r3, r2 + 8004210: d1f0 bne.n 80041f4 + 8004212: e000 b.n 8004216 + if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8004214: 46c0 nop ; (mov r8, r8) + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8004216: 687b ldr r3, [r7, #4] + 8004218: 681b ldr r3, [r3, #0] + 800421a: 2202 movs r2, #2 + 800421c: 4013 ands r3, r2 + 800421e: d100 bne.n 8004222 + 8004220: e099 b.n 8004356 + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); + + /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8004222: 4b82 ldr r3, [pc, #520] ; (800442c ) + 8004224: 689b ldr r3, [r3, #8] + 8004226: 2238 movs r2, #56 ; 0x38 + 8004228: 4013 ands r3, r2 + 800422a: 61bb str r3, [r7, #24] + temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + 800422c: 4b7f ldr r3, [pc, #508] ; (800442c ) + 800422e: 68db ldr r3, [r3, #12] + 8004230: 2203 movs r2, #3 + 8004232: 4013 ands r3, r2 + 8004234: 617b str r3, [r7, #20] + if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) + 8004236: 69bb ldr r3, [r7, #24] + 8004238: 2b10 cmp r3, #16 + 800423a: d102 bne.n 8004242 + 800423c: 697b ldr r3, [r7, #20] + 800423e: 2b02 cmp r3, #2 + 8004240: d002 beq.n 8004248 + || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) + 8004242: 69bb ldr r3, [r7, #24] + 8004244: 2b00 cmp r3, #0 + 8004246: d135 bne.n 80042b4 + { + /* When HSI is used as system clock or as PLL input clock it can not be disabled */ + if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + 8004248: 4b78 ldr r3, [pc, #480] ; (800442c ) + 800424a: 681a ldr r2, [r3, #0] + 800424c: 2380 movs r3, #128 ; 0x80 + 800424e: 00db lsls r3, r3, #3 + 8004250: 4013 ands r3, r2 + 8004252: d005 beq.n 8004260 + 8004254: 687b ldr r3, [r7, #4] + 8004256: 68db ldr r3, [r3, #12] + 8004258: 2b00 cmp r3, #0 + 800425a: d101 bne.n 8004260 + { + return HAL_ERROR; + 800425c: 2301 movs r3, #1 + 800425e: e2a7 b.n 80047b0 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8004260: 4b72 ldr r3, [pc, #456] ; (800442c ) + 8004262: 685b ldr r3, [r3, #4] + 8004264: 4a74 ldr r2, [pc, #464] ; (8004438 ) + 8004266: 4013 ands r3, r2 + 8004268: 0019 movs r1, r3 + 800426a: 687b ldr r3, [r7, #4] + 800426c: 695b ldr r3, [r3, #20] + 800426e: 021a lsls r2, r3, #8 + 8004270: 4b6e ldr r3, [pc, #440] ; (800442c ) + 8004272: 430a orrs r2, r1 + 8004274: 605a str r2, [r3, #4] + + if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) + 8004276: 69bb ldr r3, [r7, #24] + 8004278: 2b00 cmp r3, #0 + 800427a: d112 bne.n 80042a2 + { + /* Adjust the HSI16 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + 800427c: 4b6b ldr r3, [pc, #428] ; (800442c ) + 800427e: 681b ldr r3, [r3, #0] + 8004280: 4a6e ldr r2, [pc, #440] ; (800443c ) + 8004282: 4013 ands r3, r2 + 8004284: 0019 movs r1, r3 + 8004286: 687b ldr r3, [r7, #4] + 8004288: 691a ldr r2, [r3, #16] + 800428a: 4b68 ldr r3, [pc, #416] ; (800442c ) + 800428c: 430a orrs r2, r1 + 800428e: 601a str r2, [r3, #0] + + /* Update the SystemCoreClock global variable with HSISYS value */ + SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); + 8004290: 4b66 ldr r3, [pc, #408] ; (800442c ) + 8004292: 681b ldr r3, [r3, #0] + 8004294: 0adb lsrs r3, r3, #11 + 8004296: 2207 movs r2, #7 + 8004298: 4013 ands r3, r2 + 800429a: 4a69 ldr r2, [pc, #420] ; (8004440 ) + 800429c: 40da lsrs r2, r3 + 800429e: 4b69 ldr r3, [pc, #420] ; (8004444 ) + 80042a0: 601a str r2, [r3, #0] + } + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + 80042a2: 4b69 ldr r3, [pc, #420] ; (8004448 ) + 80042a4: 681b ldr r3, [r3, #0] + 80042a6: 0018 movs r0, r3 + 80042a8: f7fc fce0 bl 8000c6c + 80042ac: 1e03 subs r3, r0, #0 + 80042ae: d051 beq.n 8004354 + { + return HAL_ERROR; + 80042b0: 2301 movs r3, #1 + 80042b2: e27d b.n 80047b0 + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 80042b4: 687b ldr r3, [r7, #4] + 80042b6: 68db ldr r3, [r3, #12] + 80042b8: 2b00 cmp r3, #0 + 80042ba: d030 beq.n 800431e + { + /* Configure the HSI16 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + 80042bc: 4b5b ldr r3, [pc, #364] ; (800442c ) + 80042be: 681b ldr r3, [r3, #0] + 80042c0: 4a5e ldr r2, [pc, #376] ; (800443c ) + 80042c2: 4013 ands r3, r2 + 80042c4: 0019 movs r1, r3 + 80042c6: 687b ldr r3, [r7, #4] + 80042c8: 691a ldr r2, [r3, #16] + 80042ca: 4b58 ldr r3, [pc, #352] ; (800442c ) + 80042cc: 430a orrs r2, r1 + 80042ce: 601a str r2, [r3, #0] + + /* Enable the Internal High Speed oscillator (HSI16). */ + __HAL_RCC_HSI_ENABLE(); + 80042d0: 4b56 ldr r3, [pc, #344] ; (800442c ) + 80042d2: 681a ldr r2, [r3, #0] + 80042d4: 4b55 ldr r3, [pc, #340] ; (800442c ) + 80042d6: 2180 movs r1, #128 ; 0x80 + 80042d8: 0049 lsls r1, r1, #1 + 80042da: 430a orrs r2, r1 + 80042dc: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80042de: f7fc fd21 bl 8000d24 + 80042e2: 0003 movs r3, r0 + 80042e4: 613b str r3, [r7, #16] + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 80042e6: e008 b.n 80042fa + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80042e8: f7fc fd1c bl 8000d24 + 80042ec: 0002 movs r2, r0 + 80042ee: 693b ldr r3, [r7, #16] + 80042f0: 1ad3 subs r3, r2, r3 + 80042f2: 2b02 cmp r3, #2 + 80042f4: d901 bls.n 80042fa + { + return HAL_TIMEOUT; + 80042f6: 2303 movs r3, #3 + 80042f8: e25a b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 80042fa: 4b4c ldr r3, [pc, #304] ; (800442c ) + 80042fc: 681a ldr r2, [r3, #0] + 80042fe: 2380 movs r3, #128 ; 0x80 + 8004300: 00db lsls r3, r3, #3 + 8004302: 4013 ands r3, r2 + 8004304: d0f0 beq.n 80042e8 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8004306: 4b49 ldr r3, [pc, #292] ; (800442c ) + 8004308: 685b ldr r3, [r3, #4] + 800430a: 4a4b ldr r2, [pc, #300] ; (8004438 ) + 800430c: 4013 ands r3, r2 + 800430e: 0019 movs r1, r3 + 8004310: 687b ldr r3, [r7, #4] + 8004312: 695b ldr r3, [r3, #20] + 8004314: 021a lsls r2, r3, #8 + 8004316: 4b45 ldr r3, [pc, #276] ; (800442c ) + 8004318: 430a orrs r2, r1 + 800431a: 605a str r2, [r3, #4] + 800431c: e01b b.n 8004356 + } + else + { + /* Disable the Internal High Speed oscillator (HSI16). */ + __HAL_RCC_HSI_DISABLE(); + 800431e: 4b43 ldr r3, [pc, #268] ; (800442c ) + 8004320: 681a ldr r2, [r3, #0] + 8004322: 4b42 ldr r3, [pc, #264] ; (800442c ) + 8004324: 4949 ldr r1, [pc, #292] ; (800444c ) + 8004326: 400a ands r2, r1 + 8004328: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800432a: f7fc fcfb bl 8000d24 + 800432e: 0003 movs r3, r0 + 8004330: 613b str r3, [r7, #16] + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + 8004332: e008 b.n 8004346 + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8004334: f7fc fcf6 bl 8000d24 + 8004338: 0002 movs r2, r0 + 800433a: 693b ldr r3, [r7, #16] + 800433c: 1ad3 subs r3, r2, r3 + 800433e: 2b02 cmp r3, #2 + 8004340: d901 bls.n 8004346 + { + return HAL_TIMEOUT; + 8004342: 2303 movs r3, #3 + 8004344: e234 b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + 8004346: 4b39 ldr r3, [pc, #228] ; (800442c ) + 8004348: 681a ldr r2, [r3, #0] + 800434a: 2380 movs r3, #128 ; 0x80 + 800434c: 00db lsls r3, r3, #3 + 800434e: 4013 ands r3, r2 + 8004350: d1f0 bne.n 8004334 + 8004352: e000 b.n 8004356 + if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + 8004354: 46c0 nop ; (mov r8, r8) + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8004356: 687b ldr r3, [r7, #4] + 8004358: 681b ldr r3, [r3, #0] + 800435a: 2208 movs r2, #8 + 800435c: 4013 ands r3, r2 + 800435e: d047 beq.n 80043f0 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check if LSI is used as system clock */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) + 8004360: 4b32 ldr r3, [pc, #200] ; (800442c ) + 8004362: 689b ldr r3, [r3, #8] + 8004364: 2238 movs r2, #56 ; 0x38 + 8004366: 4013 ands r3, r2 + 8004368: 2b18 cmp r3, #24 + 800436a: d10a bne.n 8004382 + { + /* When LSI is used as system clock it will not be disabled */ + if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) + 800436c: 4b2f ldr r3, [pc, #188] ; (800442c ) + 800436e: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004370: 2202 movs r2, #2 + 8004372: 4013 ands r3, r2 + 8004374: d03c beq.n 80043f0 + 8004376: 687b ldr r3, [r7, #4] + 8004378: 699b ldr r3, [r3, #24] + 800437a: 2b00 cmp r3, #0 + 800437c: d138 bne.n 80043f0 + { + return HAL_ERROR; + 800437e: 2301 movs r3, #1 + 8004380: e216 b.n 80047b0 + } + } + else + { + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8004382: 687b ldr r3, [r7, #4] + 8004384: 699b ldr r3, [r3, #24] + 8004386: 2b00 cmp r3, #0 + 8004388: d019 beq.n 80043be + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800438a: 4b28 ldr r3, [pc, #160] ; (800442c ) + 800438c: 6e1a ldr r2, [r3, #96] ; 0x60 + 800438e: 4b27 ldr r3, [pc, #156] ; (800442c ) + 8004390: 2101 movs r1, #1 + 8004392: 430a orrs r2, r1 + 8004394: 661a str r2, [r3, #96] ; 0x60 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8004396: f7fc fcc5 bl 8000d24 + 800439a: 0003 movs r3, r0 + 800439c: 613b str r3, [r7, #16] + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + 800439e: e008 b.n 80043b2 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 80043a0: f7fc fcc0 bl 8000d24 + 80043a4: 0002 movs r2, r0 + 80043a6: 693b ldr r3, [r7, #16] + 80043a8: 1ad3 subs r3, r2, r3 + 80043aa: 2b02 cmp r3, #2 + 80043ac: d901 bls.n 80043b2 + { + return HAL_TIMEOUT; + 80043ae: 2303 movs r3, #3 + 80043b0: e1fe b.n 80047b0 + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + 80043b2: 4b1e ldr r3, [pc, #120] ; (800442c ) + 80043b4: 6e1b ldr r3, [r3, #96] ; 0x60 + 80043b6: 2202 movs r2, #2 + 80043b8: 4013 ands r3, r2 + 80043ba: d0f1 beq.n 80043a0 + 80043bc: e018 b.n 80043f0 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 80043be: 4b1b ldr r3, [pc, #108] ; (800442c ) + 80043c0: 6e1a ldr r2, [r3, #96] ; 0x60 + 80043c2: 4b1a ldr r3, [pc, #104] ; (800442c ) + 80043c4: 2101 movs r1, #1 + 80043c6: 438a bics r2, r1 + 80043c8: 661a str r2, [r3, #96] ; 0x60 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80043ca: f7fc fcab bl 8000d24 + 80043ce: 0003 movs r3, r0 + 80043d0: 613b str r3, [r7, #16] + + /* Wait till LSI is disabled */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + 80043d2: e008 b.n 80043e6 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 80043d4: f7fc fca6 bl 8000d24 + 80043d8: 0002 movs r2, r0 + 80043da: 693b ldr r3, [r7, #16] + 80043dc: 1ad3 subs r3, r2, r3 + 80043de: 2b02 cmp r3, #2 + 80043e0: d901 bls.n 80043e6 + { + return HAL_TIMEOUT; + 80043e2: 2303 movs r3, #3 + 80043e4: e1e4 b.n 80047b0 + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + 80043e6: 4b11 ldr r3, [pc, #68] ; (800442c ) + 80043e8: 6e1b ldr r3, [r3, #96] ; 0x60 + 80043ea: 2202 movs r2, #2 + 80043ec: 4013 ands r3, r2 + 80043ee: d1f1 bne.n 80043d4 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 80043f0: 687b ldr r3, [r7, #4] + 80043f2: 681b ldr r3, [r3, #0] + 80043f4: 2204 movs r2, #4 + 80043f6: 4013 ands r3, r2 + 80043f8: d100 bne.n 80043fc + 80043fa: e0c7 b.n 800458c + { + FlagStatus pwrclkchanged = RESET; + 80043fc: 231f movs r3, #31 + 80043fe: 18fb adds r3, r7, r3 + 8004400: 2200 movs r2, #0 + 8004402: 701a strb r2, [r3, #0] + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* When the LSE is used as system clock, it is not allowed disable it */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) + 8004404: 4b09 ldr r3, [pc, #36] ; (800442c ) + 8004406: 689b ldr r3, [r3, #8] + 8004408: 2238 movs r2, #56 ; 0x38 + 800440a: 4013 ands r3, r2 + 800440c: 2b20 cmp r3, #32 + 800440e: d11f bne.n 8004450 + { + if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) + 8004410: 4b06 ldr r3, [pc, #24] ; (800442c ) + 8004412: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004414: 2202 movs r2, #2 + 8004416: 4013 ands r3, r2 + 8004418: d100 bne.n 800441c + 800441a: e0b7 b.n 800458c + 800441c: 687b ldr r3, [r7, #4] + 800441e: 689b ldr r3, [r3, #8] + 8004420: 2b00 cmp r3, #0 + 8004422: d000 beq.n 8004426 + 8004424: e0b2 b.n 800458c + { + return HAL_ERROR; + 8004426: 2301 movs r3, #1 + 8004428: e1c2 b.n 80047b0 + 800442a: 46c0 nop ; (mov r8, r8) + 800442c: 40021000 .word 0x40021000 + 8004430: fffeffff .word 0xfffeffff + 8004434: fffbffff .word 0xfffbffff + 8004438: ffff80ff .word 0xffff80ff + 800443c: ffffc7ff .word 0xffffc7ff + 8004440: 00f42400 .word 0x00f42400 + 8004444: 20000000 .word 0x20000000 + 8004448: 20000004 .word 0x20000004 + 800444c: fffffeff .word 0xfffffeff + } + else + { + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) + 8004450: 4bb5 ldr r3, [pc, #724] ; (8004728 ) + 8004452: 6bda ldr r2, [r3, #60] ; 0x3c + 8004454: 2380 movs r3, #128 ; 0x80 + 8004456: 055b lsls r3, r3, #21 + 8004458: 4013 ands r3, r2 + 800445a: d101 bne.n 8004460 + 800445c: 2301 movs r3, #1 + 800445e: e000 b.n 8004462 + 8004460: 2300 movs r3, #0 + 8004462: 2b00 cmp r3, #0 + 8004464: d011 beq.n 800448a + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8004466: 4bb0 ldr r3, [pc, #704] ; (8004728 ) + 8004468: 6bda ldr r2, [r3, #60] ; 0x3c + 800446a: 4baf ldr r3, [pc, #700] ; (8004728 ) + 800446c: 2180 movs r1, #128 ; 0x80 + 800446e: 0549 lsls r1, r1, #21 + 8004470: 430a orrs r2, r1 + 8004472: 63da str r2, [r3, #60] ; 0x3c + 8004474: 4bac ldr r3, [pc, #688] ; (8004728 ) + 8004476: 6bda ldr r2, [r3, #60] ; 0x3c + 8004478: 2380 movs r3, #128 ; 0x80 + 800447a: 055b lsls r3, r3, #21 + 800447c: 4013 ands r3, r2 + 800447e: 60fb str r3, [r7, #12] + 8004480: 68fb ldr r3, [r7, #12] + pwrclkchanged = SET; + 8004482: 231f movs r3, #31 + 8004484: 18fb adds r3, r7, r3 + 8004486: 2201 movs r2, #1 + 8004488: 701a strb r2, [r3, #0] + } + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 800448a: 4ba8 ldr r3, [pc, #672] ; (800472c ) + 800448c: 681a ldr r2, [r3, #0] + 800448e: 2380 movs r3, #128 ; 0x80 + 8004490: 005b lsls r3, r3, #1 + 8004492: 4013 ands r3, r2 + 8004494: d11a bne.n 80044cc + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 8004496: 4ba5 ldr r3, [pc, #660] ; (800472c ) + 8004498: 681a ldr r2, [r3, #0] + 800449a: 4ba4 ldr r3, [pc, #656] ; (800472c ) + 800449c: 2180 movs r1, #128 ; 0x80 + 800449e: 0049 lsls r1, r1, #1 + 80044a0: 430a orrs r2, r1 + 80044a2: 601a str r2, [r3, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80044a4: f7fc fc3e bl 8000d24 + 80044a8: 0003 movs r3, r0 + 80044aa: 613b str r3, [r7, #16] + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80044ac: e008 b.n 80044c0 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80044ae: f7fc fc39 bl 8000d24 + 80044b2: 0002 movs r2, r0 + 80044b4: 693b ldr r3, [r7, #16] + 80044b6: 1ad3 subs r3, r2, r3 + 80044b8: 2b02 cmp r3, #2 + 80044ba: d901 bls.n 80044c0 + { + return HAL_TIMEOUT; + 80044bc: 2303 movs r3, #3 + 80044be: e177 b.n 80047b0 + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80044c0: 4b9a ldr r3, [pc, #616] ; (800472c ) + 80044c2: 681a ldr r2, [r3, #0] + 80044c4: 2380 movs r3, #128 ; 0x80 + 80044c6: 005b lsls r3, r3, #1 + 80044c8: 4013 ands r3, r2 + 80044ca: d0f0 beq.n 80044ae + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80044cc: 687b ldr r3, [r7, #4] + 80044ce: 689b ldr r3, [r3, #8] + 80044d0: 2b01 cmp r3, #1 + 80044d2: d106 bne.n 80044e2 + 80044d4: 4b94 ldr r3, [pc, #592] ; (8004728 ) + 80044d6: 6dda ldr r2, [r3, #92] ; 0x5c + 80044d8: 4b93 ldr r3, [pc, #588] ; (8004728 ) + 80044da: 2101 movs r1, #1 + 80044dc: 430a orrs r2, r1 + 80044de: 65da str r2, [r3, #92] ; 0x5c + 80044e0: e01c b.n 800451c + 80044e2: 687b ldr r3, [r7, #4] + 80044e4: 689b ldr r3, [r3, #8] + 80044e6: 2b05 cmp r3, #5 + 80044e8: d10c bne.n 8004504 + 80044ea: 4b8f ldr r3, [pc, #572] ; (8004728 ) + 80044ec: 6dda ldr r2, [r3, #92] ; 0x5c + 80044ee: 4b8e ldr r3, [pc, #568] ; (8004728 ) + 80044f0: 2104 movs r1, #4 + 80044f2: 430a orrs r2, r1 + 80044f4: 65da str r2, [r3, #92] ; 0x5c + 80044f6: 4b8c ldr r3, [pc, #560] ; (8004728 ) + 80044f8: 6dda ldr r2, [r3, #92] ; 0x5c + 80044fa: 4b8b ldr r3, [pc, #556] ; (8004728 ) + 80044fc: 2101 movs r1, #1 + 80044fe: 430a orrs r2, r1 + 8004500: 65da str r2, [r3, #92] ; 0x5c + 8004502: e00b b.n 800451c + 8004504: 4b88 ldr r3, [pc, #544] ; (8004728 ) + 8004506: 6dda ldr r2, [r3, #92] ; 0x5c + 8004508: 4b87 ldr r3, [pc, #540] ; (8004728 ) + 800450a: 2101 movs r1, #1 + 800450c: 438a bics r2, r1 + 800450e: 65da str r2, [r3, #92] ; 0x5c + 8004510: 4b85 ldr r3, [pc, #532] ; (8004728 ) + 8004512: 6dda ldr r2, [r3, #92] ; 0x5c + 8004514: 4b84 ldr r3, [pc, #528] ; (8004728 ) + 8004516: 2104 movs r1, #4 + 8004518: 438a bics r2, r1 + 800451a: 65da str r2, [r3, #92] ; 0x5c + + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 800451c: 687b ldr r3, [r7, #4] + 800451e: 689b ldr r3, [r3, #8] + 8004520: 2b00 cmp r3, #0 + 8004522: d014 beq.n 800454e + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8004524: f7fc fbfe bl 8000d24 + 8004528: 0003 movs r3, r0 + 800452a: 613b str r3, [r7, #16] + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 800452c: e009 b.n 8004542 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800452e: f7fc fbf9 bl 8000d24 + 8004532: 0002 movs r2, r0 + 8004534: 693b ldr r3, [r7, #16] + 8004536: 1ad3 subs r3, r2, r3 + 8004538: 4a7d ldr r2, [pc, #500] ; (8004730 ) + 800453a: 4293 cmp r3, r2 + 800453c: d901 bls.n 8004542 + { + return HAL_TIMEOUT; + 800453e: 2303 movs r3, #3 + 8004540: e136 b.n 80047b0 + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 8004542: 4b79 ldr r3, [pc, #484] ; (8004728 ) + 8004544: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004546: 2202 movs r2, #2 + 8004548: 4013 ands r3, r2 + 800454a: d0f0 beq.n 800452e + 800454c: e013 b.n 8004576 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800454e: f7fc fbe9 bl 8000d24 + 8004552: 0003 movs r3, r0 + 8004554: 613b str r3, [r7, #16] + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + 8004556: e009 b.n 800456c + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8004558: f7fc fbe4 bl 8000d24 + 800455c: 0002 movs r2, r0 + 800455e: 693b ldr r3, [r7, #16] + 8004560: 1ad3 subs r3, r2, r3 + 8004562: 4a73 ldr r2, [pc, #460] ; (8004730 ) + 8004564: 4293 cmp r3, r2 + 8004566: d901 bls.n 800456c + { + return HAL_TIMEOUT; + 8004568: 2303 movs r3, #3 + 800456a: e121 b.n 80047b0 + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + 800456c: 4b6e ldr r3, [pc, #440] ; (8004728 ) + 800456e: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004570: 2202 movs r2, #2 + 8004572: 4013 ands r3, r2 + 8004574: d1f0 bne.n 8004558 + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + 8004576: 231f movs r3, #31 + 8004578: 18fb adds r3, r7, r3 + 800457a: 781b ldrb r3, [r3, #0] + 800457c: 2b01 cmp r3, #1 + 800457e: d105 bne.n 800458c + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8004580: 4b69 ldr r3, [pc, #420] ; (8004728 ) + 8004582: 6bda ldr r2, [r3, #60] ; 0x3c + 8004584: 4b68 ldr r3, [pc, #416] ; (8004728 ) + 8004586: 496b ldr r1, [pc, #428] ; (8004734 ) + 8004588: 400a ands r2, r1 + 800458a: 63da str r2, [r3, #60] ; 0x3c + } + } + } +#if defined(RCC_HSI48_SUPPORT) + /*------------------------------ HSI48 Configuration -----------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 800458c: 687b ldr r3, [r7, #4] + 800458e: 681b ldr r3, [r3, #0] + 8004590: 2220 movs r2, #32 + 8004592: 4013 ands r3, r2 + 8004594: d039 beq.n 800460a + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + 8004596: 687b ldr r3, [r7, #4] + 8004598: 69db ldr r3, [r3, #28] + 800459a: 2b00 cmp r3, #0 + 800459c: d01b beq.n 80045d6 + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + 800459e: 4b62 ldr r3, [pc, #392] ; (8004728 ) + 80045a0: 681a ldr r2, [r3, #0] + 80045a2: 4b61 ldr r3, [pc, #388] ; (8004728 ) + 80045a4: 2180 movs r1, #128 ; 0x80 + 80045a6: 03c9 lsls r1, r1, #15 + 80045a8: 430a orrs r2, r1 + 80045aa: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80045ac: f7fc fbba bl 8000d24 + 80045b0: 0003 movs r3, r0 + 80045b2: 613b str r3, [r7, #16] + + /* Wait till HSI48 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) + 80045b4: e008 b.n 80045c8 + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 80045b6: f7fc fbb5 bl 8000d24 + 80045ba: 0002 movs r2, r0 + 80045bc: 693b ldr r3, [r7, #16] + 80045be: 1ad3 subs r3, r2, r3 + 80045c0: 2b02 cmp r3, #2 + 80045c2: d901 bls.n 80045c8 + { + return HAL_TIMEOUT; + 80045c4: 2303 movs r3, #3 + 80045c6: e0f3 b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) + 80045c8: 4b57 ldr r3, [pc, #348] ; (8004728 ) + 80045ca: 681a ldr r2, [r3, #0] + 80045cc: 2380 movs r3, #128 ; 0x80 + 80045ce: 041b lsls r3, r3, #16 + 80045d0: 4013 ands r3, r2 + 80045d2: d0f0 beq.n 80045b6 + 80045d4: e019 b.n 800460a + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + 80045d6: 4b54 ldr r3, [pc, #336] ; (8004728 ) + 80045d8: 681a ldr r2, [r3, #0] + 80045da: 4b53 ldr r3, [pc, #332] ; (8004728 ) + 80045dc: 4956 ldr r1, [pc, #344] ; (8004738 ) + 80045de: 400a ands r2, r1 + 80045e0: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80045e2: f7fc fb9f bl 8000d24 + 80045e6: 0003 movs r3, r0 + 80045e8: 613b str r3, [r7, #16] + + /* Wait till HSI48 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + 80045ea: e008 b.n 80045fe + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 80045ec: f7fc fb9a bl 8000d24 + 80045f0: 0002 movs r2, r0 + 80045f2: 693b ldr r3, [r7, #16] + 80045f4: 1ad3 subs r3, r2, r3 + 80045f6: 2b02 cmp r3, #2 + 80045f8: d901 bls.n 80045fe + { + return HAL_TIMEOUT; + 80045fa: 2303 movs r3, #3 + 80045fc: e0d8 b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + 80045fe: 4b4a ldr r3, [pc, #296] ; (8004728 ) + 8004600: 681a ldr r2, [r3, #0] + 8004602: 2380 movs r3, #128 ; 0x80 + 8004604: 041b lsls r3, r3, #16 + 8004606: 4013 ands r3, r2 + 8004608: d1f0 bne.n 80045ec +#endif /* RCC_HSI48_SUPPORT */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + 800460a: 687b ldr r3, [r7, #4] + 800460c: 6a1b ldr r3, [r3, #32] + 800460e: 2b00 cmp r3, #0 + 8004610: d100 bne.n 8004614 + 8004612: e0cc b.n 80047ae + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8004614: 4b44 ldr r3, [pc, #272] ; (8004728 ) + 8004616: 689b ldr r3, [r3, #8] + 8004618: 2238 movs r2, #56 ; 0x38 + 800461a: 4013 ands r3, r2 + 800461c: 2b10 cmp r3, #16 + 800461e: d100 bne.n 8004622 + 8004620: e07b b.n 800471a + { + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + 8004622: 687b ldr r3, [r7, #4] + 8004624: 6a1b ldr r3, [r3, #32] + 8004626: 2b02 cmp r3, #2 + 8004628: d156 bne.n 80046d8 + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); +#endif /* RCC_PLLQ_SUPPORT */ + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 800462a: 4b3f ldr r3, [pc, #252] ; (8004728 ) + 800462c: 681a ldr r2, [r3, #0] + 800462e: 4b3e ldr r3, [pc, #248] ; (8004728 ) + 8004630: 4942 ldr r1, [pc, #264] ; (800473c ) + 8004632: 400a ands r2, r1 + 8004634: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8004636: f7fc fb75 bl 8000d24 + 800463a: 0003 movs r3, r0 + 800463c: 613b str r3, [r7, #16] + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 800463e: e008 b.n 8004652 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8004640: f7fc fb70 bl 8000d24 + 8004644: 0002 movs r2, r0 + 8004646: 693b ldr r3, [r7, #16] + 8004648: 1ad3 subs r3, r2, r3 + 800464a: 2b02 cmp r3, #2 + 800464c: d901 bls.n 8004652 + { + return HAL_TIMEOUT; + 800464e: 2303 movs r3, #3 + 8004650: e0ae b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8004652: 4b35 ldr r3, [pc, #212] ; (8004728 ) + 8004654: 681a ldr r2, [r3, #0] + 8004656: 2380 movs r3, #128 ; 0x80 + 8004658: 049b lsls r3, r3, #18 + 800465a: 4013 ands r3, r2 + 800465c: d1f0 bne.n 8004640 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined(RCC_PLLQ_SUPPORT) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 800465e: 4b32 ldr r3, [pc, #200] ; (8004728 ) + 8004660: 68db ldr r3, [r3, #12] + 8004662: 4a37 ldr r2, [pc, #220] ; (8004740 ) + 8004664: 4013 ands r3, r2 + 8004666: 0019 movs r1, r3 + 8004668: 687b ldr r3, [r7, #4] + 800466a: 6a5a ldr r2, [r3, #36] ; 0x24 + 800466c: 687b ldr r3, [r7, #4] + 800466e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004670: 431a orrs r2, r3 + 8004672: 687b ldr r3, [r7, #4] + 8004674: 6adb ldr r3, [r3, #44] ; 0x2c + 8004676: 021b lsls r3, r3, #8 + 8004678: 431a orrs r2, r3 + 800467a: 687b ldr r3, [r7, #4] + 800467c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800467e: 431a orrs r2, r3 + 8004680: 687b ldr r3, [r7, #4] + 8004682: 6b5b ldr r3, [r3, #52] ; 0x34 + 8004684: 431a orrs r2, r3 + 8004686: 687b ldr r3, [r7, #4] + 8004688: 6b9b ldr r3, [r3, #56] ; 0x38 + 800468a: 431a orrs r2, r3 + 800468c: 4b26 ldr r3, [pc, #152] ; (8004728 ) + 800468e: 430a orrs r2, r1 + 8004690: 60da str r2, [r3, #12] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLR); +#endif /* RCC_PLLQ_SUPPORT */ + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8004692: 4b25 ldr r3, [pc, #148] ; (8004728 ) + 8004694: 681a ldr r2, [r3, #0] + 8004696: 4b24 ldr r3, [pc, #144] ; (8004728 ) + 8004698: 2180 movs r1, #128 ; 0x80 + 800469a: 0449 lsls r1, r1, #17 + 800469c: 430a orrs r2, r1 + 800469e: 601a str r2, [r3, #0] + + /* Enable PLLR Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); + 80046a0: 4b21 ldr r3, [pc, #132] ; (8004728 ) + 80046a2: 68da ldr r2, [r3, #12] + 80046a4: 4b20 ldr r3, [pc, #128] ; (8004728 ) + 80046a6: 2180 movs r1, #128 ; 0x80 + 80046a8: 0549 lsls r1, r1, #21 + 80046aa: 430a orrs r2, r1 + 80046ac: 60da str r2, [r3, #12] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80046ae: f7fc fb39 bl 8000d24 + 80046b2: 0003 movs r3, r0 + 80046b4: 613b str r3, [r7, #16] + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 80046b6: e008 b.n 80046ca + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80046b8: f7fc fb34 bl 8000d24 + 80046bc: 0002 movs r2, r0 + 80046be: 693b ldr r3, [r7, #16] + 80046c0: 1ad3 subs r3, r2, r3 + 80046c2: 2b02 cmp r3, #2 + 80046c4: d901 bls.n 80046ca + { + return HAL_TIMEOUT; + 80046c6: 2303 movs r3, #3 + 80046c8: e072 b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 80046ca: 4b17 ldr r3, [pc, #92] ; (8004728 ) + 80046cc: 681a ldr r2, [r3, #0] + 80046ce: 2380 movs r3, #128 ; 0x80 + 80046d0: 049b lsls r3, r3, #18 + 80046d2: 4013 ands r3, r2 + 80046d4: d0f0 beq.n 80046b8 + 80046d6: e06a b.n 80047ae + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80046d8: 4b13 ldr r3, [pc, #76] ; (8004728 ) + 80046da: 681a ldr r2, [r3, #0] + 80046dc: 4b12 ldr r3, [pc, #72] ; (8004728 ) + 80046de: 4917 ldr r1, [pc, #92] ; (800473c ) + 80046e0: 400a ands r2, r1 + 80046e2: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80046e4: f7fc fb1e bl 8000d24 + 80046e8: 0003 movs r3, r0 + 80046ea: 613b str r3, [r7, #16] + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 80046ec: e008 b.n 8004700 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80046ee: f7fc fb19 bl 8000d24 + 80046f2: 0002 movs r2, r0 + 80046f4: 693b ldr r3, [r7, #16] + 80046f6: 1ad3 subs r3, r2, r3 + 80046f8: 2b02 cmp r3, #2 + 80046fa: d901 bls.n 8004700 + { + return HAL_TIMEOUT; + 80046fc: 2303 movs r3, #3 + 80046fe: e057 b.n 80047b0 + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8004700: 4b09 ldr r3, [pc, #36] ; (8004728 ) + 8004702: 681a ldr r2, [r3, #0] + 8004704: 2380 movs r3, #128 ; 0x80 + 8004706: 049b lsls r3, r3, #18 + 8004708: 4013 ands r3, r2 + 800470a: d1f0 bne.n 80046ee + } + } + /* Unselect main PLL clock source and disable main PLL outputs to save power */ +#if defined(RCC_PLLQ_SUPPORT) + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); + 800470c: 4b06 ldr r3, [pc, #24] ; (8004728 ) + 800470e: 68da ldr r2, [r3, #12] + 8004710: 4b05 ldr r3, [pc, #20] ; (8004728 ) + 8004712: 490c ldr r1, [pc, #48] ; (8004744 ) + 8004714: 400a ands r2, r1 + 8004716: 60da str r2, [r3, #12] + 8004718: e049 b.n 80047ae + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 800471a: 687b ldr r3, [r7, #4] + 800471c: 6a1b ldr r3, [r3, #32] + 800471e: 2b01 cmp r3, #1 + 8004720: d112 bne.n 8004748 + { + return HAL_ERROR; + 8004722: 2301 movs r3, #1 + 8004724: e044 b.n 80047b0 + 8004726: 46c0 nop ; (mov r8, r8) + 8004728: 40021000 .word 0x40021000 + 800472c: 40007000 .word 0x40007000 + 8004730: 00001388 .word 0x00001388 + 8004734: efffffff .word 0xefffffff + 8004738: ffbfffff .word 0xffbfffff + 800473c: feffffff .word 0xfeffffff + 8004740: 11c1808c .word 0x11c1808c + 8004744: eefefffc .word 0xeefefffc + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp_pllckcfg = RCC->PLLCFGR; + 8004748: 4b1b ldr r3, [pc, #108] ; (80047b8 ) + 800474a: 68db ldr r3, [r3, #12] + 800474c: 617b str r3, [r7, #20] + if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 800474e: 697b ldr r3, [r7, #20] + 8004750: 2203 movs r2, #3 + 8004752: 401a ands r2, r3 + 8004754: 687b ldr r3, [r7, #4] + 8004756: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004758: 429a cmp r2, r3 + 800475a: d126 bne.n 80047aa + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 800475c: 697b ldr r3, [r7, #20] + 800475e: 2270 movs r2, #112 ; 0x70 + 8004760: 401a ands r2, r3 + 8004762: 687b ldr r3, [r7, #4] + 8004764: 6a9b ldr r3, [r3, #40] ; 0x28 + if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8004766: 429a cmp r2, r3 + 8004768: d11f bne.n 80047aa + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + 800476a: 697a ldr r2, [r7, #20] + 800476c: 23fe movs r3, #254 ; 0xfe + 800476e: 01db lsls r3, r3, #7 + 8004770: 401a ands r2, r3 + 8004772: 687b ldr r3, [r7, #4] + 8004774: 6adb ldr r3, [r3, #44] ; 0x2c + 8004776: 021b lsls r3, r3, #8 + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 8004778: 429a cmp r2, r3 + 800477a: d116 bne.n 80047aa + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 800477c: 697a ldr r2, [r7, #20] + 800477e: 23f8 movs r3, #248 ; 0xf8 + 8004780: 039b lsls r3, r3, #14 + 8004782: 401a ands r2, r3 + 8004784: 687b ldr r3, [r7, #4] + 8004786: 6b1b ldr r3, [r3, #48] ; 0x30 + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + 8004788: 429a cmp r2, r3 + 800478a: d10e bne.n 80047aa +#if defined (RCC_PLLQ_SUPPORT) + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + 800478c: 697a ldr r2, [r7, #20] + 800478e: 23e0 movs r3, #224 ; 0xe0 + 8004790: 051b lsls r3, r3, #20 + 8004792: 401a ands r2, r3 + 8004794: 687b ldr r3, [r7, #4] + 8004796: 6b5b ldr r3, [r3, #52] ; 0x34 + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 8004798: 429a cmp r2, r3 + 800479a: d106 bne.n 80047aa +#endif /* RCC_PLLQ_SUPPORT */ + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + 800479c: 697b ldr r3, [r7, #20] + 800479e: 0f5b lsrs r3, r3, #29 + 80047a0: 075a lsls r2, r3, #29 + 80047a2: 687b ldr r3, [r7, #4] + 80047a4: 6b9b ldr r3, [r3, #56] ; 0x38 + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + 80047a6: 429a cmp r2, r3 + 80047a8: d001 beq.n 80047ae + { + return HAL_ERROR; + 80047aa: 2301 movs r3, #1 + 80047ac: e000 b.n 80047b0 + } + } + } + } + return HAL_OK; + 80047ae: 2300 movs r3, #0 +} + 80047b0: 0018 movs r0, r3 + 80047b2: 46bd mov sp, r7 + 80047b4: b008 add sp, #32 + 80047b6: bd80 pop {r7, pc} + 80047b8: 40021000 .word 0x40021000 + +080047bc : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80047bc: b580 push {r7, lr} + 80047be: b084 sub sp, #16 + 80047c0: af00 add r7, sp, #0 + 80047c2: 6078 str r0, [r7, #4] + 80047c4: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 80047c6: 687b ldr r3, [r7, #4] + 80047c8: 2b00 cmp r3, #0 + 80047ca: d101 bne.n 80047d0 + { + return HAL_ERROR; + 80047cc: 2301 movs r3, #1 + 80047ce: e0e9 b.n 80049a4 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 80047d0: 4b76 ldr r3, [pc, #472] ; (80049ac ) + 80047d2: 681b ldr r3, [r3, #0] + 80047d4: 2207 movs r2, #7 + 80047d6: 4013 ands r3, r2 + 80047d8: 683a ldr r2, [r7, #0] + 80047da: 429a cmp r2, r3 + 80047dc: d91e bls.n 800481c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80047de: 4b73 ldr r3, [pc, #460] ; (80049ac ) + 80047e0: 681b ldr r3, [r3, #0] + 80047e2: 2207 movs r2, #7 + 80047e4: 4393 bics r3, r2 + 80047e6: 0019 movs r1, r3 + 80047e8: 4b70 ldr r3, [pc, #448] ; (80049ac ) + 80047ea: 683a ldr r2, [r7, #0] + 80047ec: 430a orrs r2, r1 + 80047ee: 601a str r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + 80047f0: f7fc fa98 bl 8000d24 + 80047f4: 0003 movs r3, r0 + 80047f6: 60fb str r3, [r7, #12] + + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 80047f8: e009 b.n 800480e + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 80047fa: f7fc fa93 bl 8000d24 + 80047fe: 0002 movs r2, r0 + 8004800: 68fb ldr r3, [r7, #12] + 8004802: 1ad3 subs r3, r2, r3 + 8004804: 4a6a ldr r2, [pc, #424] ; (80049b0 ) + 8004806: 4293 cmp r3, r2 + 8004808: d901 bls.n 800480e + { + return HAL_TIMEOUT; + 800480a: 2303 movs r3, #3 + 800480c: e0ca b.n 80049a4 + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 800480e: 4b67 ldr r3, [pc, #412] ; (80049ac ) + 8004810: 681b ldr r3, [r3, #0] + 8004812: 2207 movs r2, #7 + 8004814: 4013 ands r3, r2 + 8004816: 683a ldr r2, [r7, #0] + 8004818: 429a cmp r2, r3 + 800481a: d1ee bne.n 80047fa + } + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800481c: 687b ldr r3, [r7, #4] + 800481e: 681b ldr r3, [r3, #0] + 8004820: 2202 movs r2, #2 + 8004822: 4013 ands r3, r2 + 8004824: d015 beq.n 8004852 + { + /* Set the highest APB divider in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8004826: 687b ldr r3, [r7, #4] + 8004828: 681b ldr r3, [r3, #0] + 800482a: 2204 movs r2, #4 + 800482c: 4013 ands r3, r2 + 800482e: d006 beq.n 800483e + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); + 8004830: 4b60 ldr r3, [pc, #384] ; (80049b4 ) + 8004832: 689a ldr r2, [r3, #8] + 8004834: 4b5f ldr r3, [pc, #380] ; (80049b4 ) + 8004836: 21e0 movs r1, #224 ; 0xe0 + 8004838: 01c9 lsls r1, r1, #7 + 800483a: 430a orrs r2, r1 + 800483c: 609a str r2, [r3, #8] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 800483e: 4b5d ldr r3, [pc, #372] ; (80049b4 ) + 8004840: 689b ldr r3, [r3, #8] + 8004842: 4a5d ldr r2, [pc, #372] ; (80049b8 ) + 8004844: 4013 ands r3, r2 + 8004846: 0019 movs r1, r3 + 8004848: 687b ldr r3, [r7, #4] + 800484a: 689a ldr r2, [r3, #8] + 800484c: 4b59 ldr r3, [pc, #356] ; (80049b4 ) + 800484e: 430a orrs r2, r1 + 8004850: 609a str r2, [r3, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8004852: 687b ldr r3, [r7, #4] + 8004854: 681b ldr r3, [r3, #0] + 8004856: 2201 movs r2, #1 + 8004858: 4013 ands r3, r2 + 800485a: d057 beq.n 800490c + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800485c: 687b ldr r3, [r7, #4] + 800485e: 685b ldr r3, [r3, #4] + 8004860: 2b01 cmp r3, #1 + 8004862: d107 bne.n 8004874 + { + /* Check the HSE ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 8004864: 4b53 ldr r3, [pc, #332] ; (80049b4 ) + 8004866: 681a ldr r2, [r3, #0] + 8004868: 2380 movs r3, #128 ; 0x80 + 800486a: 029b lsls r3, r3, #10 + 800486c: 4013 ands r3, r2 + 800486e: d12b bne.n 80048c8 + { + return HAL_ERROR; + 8004870: 2301 movs r3, #1 + 8004872: e097 b.n 80049a4 + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8004874: 687b ldr r3, [r7, #4] + 8004876: 685b ldr r3, [r3, #4] + 8004878: 2b02 cmp r3, #2 + 800487a: d107 bne.n 800488c + { + /* Check the PLL ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 800487c: 4b4d ldr r3, [pc, #308] ; (80049b4 ) + 800487e: 681a ldr r2, [r3, #0] + 8004880: 2380 movs r3, #128 ; 0x80 + 8004882: 049b lsls r3, r3, #18 + 8004884: 4013 ands r3, r2 + 8004886: d11f bne.n 80048c8 + { + return HAL_ERROR; + 8004888: 2301 movs r3, #1 + 800488a: e08b b.n 80049a4 + } + } + /* HSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 800488c: 687b ldr r3, [r7, #4] + 800488e: 685b ldr r3, [r3, #4] + 8004890: 2b00 cmp r3, #0 + 8004892: d107 bne.n 80048a4 + { + /* Check the HSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 8004894: 4b47 ldr r3, [pc, #284] ; (80049b4 ) + 8004896: 681a ldr r2, [r3, #0] + 8004898: 2380 movs r3, #128 ; 0x80 + 800489a: 00db lsls r3, r3, #3 + 800489c: 4013 ands r3, r2 + 800489e: d113 bne.n 80048c8 + { + return HAL_ERROR; + 80048a0: 2301 movs r3, #1 + 80048a2: e07f b.n 80049a4 + } + } + /* LSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) + 80048a4: 687b ldr r3, [r7, #4] + 80048a6: 685b ldr r3, [r3, #4] + 80048a8: 2b03 cmp r3, #3 + 80048aa: d106 bne.n 80048ba + { + /* Check the LSI ready flag */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + 80048ac: 4b41 ldr r3, [pc, #260] ; (80049b4 ) + 80048ae: 6e1b ldr r3, [r3, #96] ; 0x60 + 80048b0: 2202 movs r2, #2 + 80048b2: 4013 ands r3, r2 + 80048b4: d108 bne.n 80048c8 + { + return HAL_ERROR; + 80048b6: 2301 movs r3, #1 + 80048b8: e074 b.n 80049a4 + } + /* LSE is selected as System Clock Source */ + else + { + /* Check the LSE ready flag */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 80048ba: 4b3e ldr r3, [pc, #248] ; (80049b4 ) + 80048bc: 6ddb ldr r3, [r3, #92] ; 0x5c + 80048be: 2202 movs r2, #2 + 80048c0: 4013 ands r3, r2 + 80048c2: d101 bne.n 80048c8 + { + return HAL_ERROR; + 80048c4: 2301 movs r3, #1 + 80048c6: e06d b.n 80049a4 + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + 80048c8: 4b3a ldr r3, [pc, #232] ; (80049b4 ) + 80048ca: 689b ldr r3, [r3, #8] + 80048cc: 2207 movs r2, #7 + 80048ce: 4393 bics r3, r2 + 80048d0: 0019 movs r1, r3 + 80048d2: 687b ldr r3, [r7, #4] + 80048d4: 685a ldr r2, [r3, #4] + 80048d6: 4b37 ldr r3, [pc, #220] ; (80049b4 ) + 80048d8: 430a orrs r2, r1 + 80048da: 609a str r2, [r3, #8] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80048dc: f7fc fa22 bl 8000d24 + 80048e0: 0003 movs r3, r0 + 80048e2: 60fb str r3, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80048e4: e009 b.n 80048fa + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 80048e6: f7fc fa1d bl 8000d24 + 80048ea: 0002 movs r2, r0 + 80048ec: 68fb ldr r3, [r7, #12] + 80048ee: 1ad3 subs r3, r2, r3 + 80048f0: 4a2f ldr r2, [pc, #188] ; (80049b0 ) + 80048f2: 4293 cmp r3, r2 + 80048f4: d901 bls.n 80048fa + { + return HAL_TIMEOUT; + 80048f6: 2303 movs r3, #3 + 80048f8: e054 b.n 80049a4 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80048fa: 4b2e ldr r3, [pc, #184] ; (80049b4 ) + 80048fc: 689b ldr r3, [r3, #8] + 80048fe: 2238 movs r2, #56 ; 0x38 + 8004900: 401a ands r2, r3 + 8004902: 687b ldr r3, [r7, #4] + 8004904: 685b ldr r3, [r3, #4] + 8004906: 00db lsls r3, r3, #3 + 8004908: 429a cmp r2, r3 + 800490a: d1ec bne.n 80048e6 + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 800490c: 4b27 ldr r3, [pc, #156] ; (80049ac ) + 800490e: 681b ldr r3, [r3, #0] + 8004910: 2207 movs r2, #7 + 8004912: 4013 ands r3, r2 + 8004914: 683a ldr r2, [r7, #0] + 8004916: 429a cmp r2, r3 + 8004918: d21e bcs.n 8004958 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800491a: 4b24 ldr r3, [pc, #144] ; (80049ac ) + 800491c: 681b ldr r3, [r3, #0] + 800491e: 2207 movs r2, #7 + 8004920: 4393 bics r3, r2 + 8004922: 0019 movs r1, r3 + 8004924: 4b21 ldr r3, [pc, #132] ; (80049ac ) + 8004926: 683a ldr r2, [r7, #0] + 8004928: 430a orrs r2, r1 + 800492a: 601a str r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + 800492c: f7fc f9fa bl 8000d24 + 8004930: 0003 movs r3, r0 + 8004932: 60fb str r3, [r7, #12] + + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 8004934: e009 b.n 800494a + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8004936: f7fc f9f5 bl 8000d24 + 800493a: 0002 movs r2, r0 + 800493c: 68fb ldr r3, [r7, #12] + 800493e: 1ad3 subs r3, r2, r3 + 8004940: 4a1b ldr r2, [pc, #108] ; (80049b0 ) + 8004942: 4293 cmp r3, r2 + 8004944: d901 bls.n 800494a + { + return HAL_TIMEOUT; + 8004946: 2303 movs r3, #3 + 8004948: e02c b.n 80049a4 + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 800494a: 4b18 ldr r3, [pc, #96] ; (80049ac ) + 800494c: 681b ldr r3, [r3, #0] + 800494e: 2207 movs r2, #7 + 8004950: 4013 ands r3, r2 + 8004952: 683a ldr r2, [r7, #0] + 8004954: 429a cmp r2, r3 + 8004956: d1ee bne.n 8004936 + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8004958: 687b ldr r3, [r7, #4] + 800495a: 681b ldr r3, [r3, #0] + 800495c: 2204 movs r2, #4 + 800495e: 4013 ands r3, r2 + 8004960: d009 beq.n 8004976 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + 8004962: 4b14 ldr r3, [pc, #80] ; (80049b4 ) + 8004964: 689b ldr r3, [r3, #8] + 8004966: 4a15 ldr r2, [pc, #84] ; (80049bc ) + 8004968: 4013 ands r3, r2 + 800496a: 0019 movs r1, r3 + 800496c: 687b ldr r3, [r7, #4] + 800496e: 68da ldr r2, [r3, #12] + 8004970: 4b10 ldr r3, [pc, #64] ; (80049b4 ) + 8004972: 430a orrs r2, r1 + 8004974: 609a str r2, [r3, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); + 8004976: f000 f829 bl 80049cc + 800497a: 0001 movs r1, r0 + 800497c: 4b0d ldr r3, [pc, #52] ; (80049b4 ) + 800497e: 689b ldr r3, [r3, #8] + 8004980: 0a1b lsrs r3, r3, #8 + 8004982: 220f movs r2, #15 + 8004984: 401a ands r2, r3 + 8004986: 4b0e ldr r3, [pc, #56] ; (80049c0 ) + 8004988: 0092 lsls r2, r2, #2 + 800498a: 58d3 ldr r3, [r2, r3] + 800498c: 221f movs r2, #31 + 800498e: 4013 ands r3, r2 + 8004990: 000a movs r2, r1 + 8004992: 40da lsrs r2, r3 + 8004994: 4b0b ldr r3, [pc, #44] ; (80049c4 ) + 8004996: 601a str r2, [r3, #0] + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(uwTickPrio); + 8004998: 4b0b ldr r3, [pc, #44] ; (80049c8 ) + 800499a: 681b ldr r3, [r3, #0] + 800499c: 0018 movs r0, r3 + 800499e: f7fc f965 bl 8000c6c + 80049a2: 0003 movs r3, r0 +} + 80049a4: 0018 movs r0, r3 + 80049a6: 46bd mov sp, r7 + 80049a8: b004 add sp, #16 + 80049aa: bd80 pop {r7, pc} + 80049ac: 40022000 .word 0x40022000 + 80049b0: 00001388 .word 0x00001388 + 80049b4: 40021000 .word 0x40021000 + 80049b8: fffff0ff .word 0xfffff0ff + 80049bc: ffff8fff .word 0xffff8fff + 80049c0: 08005168 .word 0x08005168 + 80049c4: 20000000 .word 0x20000000 + 80049c8: 20000004 .word 0x20000004 + +080049cc : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 80049cc: b580 push {r7, lr} + 80049ce: b086 sub sp, #24 + 80049d0: af00 add r7, sp, #0 + uint32_t pllvco, pllsource, pllr, pllm, hsidiv; + uint32_t sysclockfreq; + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 80049d2: 4b3c ldr r3, [pc, #240] ; (8004ac4 ) + 80049d4: 689b ldr r3, [r3, #8] + 80049d6: 2238 movs r2, #56 ; 0x38 + 80049d8: 4013 ands r3, r2 + 80049da: d10f bne.n 80049fc + { + /* HSISYS can be derived for HSI16 */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + 80049dc: 4b39 ldr r3, [pc, #228] ; (8004ac4 ) + 80049de: 681b ldr r3, [r3, #0] + 80049e0: 0adb lsrs r3, r3, #11 + 80049e2: 2207 movs r2, #7 + 80049e4: 4013 ands r3, r2 + 80049e6: 2201 movs r2, #1 + 80049e8: 409a lsls r2, r3 + 80049ea: 0013 movs r3, r2 + 80049ec: 603b str r3, [r7, #0] + + /* HSI used as system clock source */ + sysclockfreq = (HSI_VALUE / hsidiv); + 80049ee: 6839 ldr r1, [r7, #0] + 80049f0: 4835 ldr r0, [pc, #212] ; (8004ac8 ) + 80049f2: f7fb fb87 bl 8000104 <__udivsi3> + 80049f6: 0003 movs r3, r0 + 80049f8: 613b str r3, [r7, #16] + 80049fa: e05d b.n 8004ab8 + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 80049fc: 4b31 ldr r3, [pc, #196] ; (8004ac4 ) + 80049fe: 689b ldr r3, [r3, #8] + 8004a00: 2238 movs r2, #56 ; 0x38 + 8004a02: 4013 ands r3, r2 + 8004a04: 2b08 cmp r3, #8 + 8004a06: d102 bne.n 8004a0e + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + 8004a08: 4b30 ldr r3, [pc, #192] ; (8004acc ) + 8004a0a: 613b str r3, [r7, #16] + 8004a0c: e054 b.n 8004ab8 + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8004a0e: 4b2d ldr r3, [pc, #180] ; (8004ac4 ) + 8004a10: 689b ldr r3, [r3, #8] + 8004a12: 2238 movs r2, #56 ; 0x38 + 8004a14: 4013 ands r3, r2 + 8004a16: 2b10 cmp r3, #16 + 8004a18: d138 bne.n 8004a8c + /* PLL used as system clock source */ + + /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + 8004a1a: 4b2a ldr r3, [pc, #168] ; (8004ac4 ) + 8004a1c: 68db ldr r3, [r3, #12] + 8004a1e: 2203 movs r2, #3 + 8004a20: 4013 ands r3, r2 + 8004a22: 60fb str r3, [r7, #12] + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + 8004a24: 4b27 ldr r3, [pc, #156] ; (8004ac4 ) + 8004a26: 68db ldr r3, [r3, #12] + 8004a28: 091b lsrs r3, r3, #4 + 8004a2a: 2207 movs r2, #7 + 8004a2c: 4013 ands r3, r2 + 8004a2e: 3301 adds r3, #1 + 8004a30: 60bb str r3, [r7, #8] + + switch (pllsource) + 8004a32: 68fb ldr r3, [r7, #12] + 8004a34: 2b03 cmp r3, #3 + 8004a36: d10d bne.n 8004a54 + { + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + 8004a38: 68b9 ldr r1, [r7, #8] + 8004a3a: 4824 ldr r0, [pc, #144] ; (8004acc ) + 8004a3c: f7fb fb62 bl 8000104 <__udivsi3> + 8004a40: 0003 movs r3, r0 + 8004a42: 0019 movs r1, r3 + 8004a44: 4b1f ldr r3, [pc, #124] ; (8004ac4 ) + 8004a46: 68db ldr r3, [r3, #12] + 8004a48: 0a1b lsrs r3, r3, #8 + 8004a4a: 227f movs r2, #127 ; 0x7f + 8004a4c: 4013 ands r3, r2 + 8004a4e: 434b muls r3, r1 + 8004a50: 617b str r3, [r7, #20] + break; + 8004a52: e00d b.n 8004a70 + + case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ + default: /* HSI16 used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; + 8004a54: 68b9 ldr r1, [r7, #8] + 8004a56: 481c ldr r0, [pc, #112] ; (8004ac8 ) + 8004a58: f7fb fb54 bl 8000104 <__udivsi3> + 8004a5c: 0003 movs r3, r0 + 8004a5e: 0019 movs r1, r3 + 8004a60: 4b18 ldr r3, [pc, #96] ; (8004ac4 ) + 8004a62: 68db ldr r3, [r3, #12] + 8004a64: 0a1b lsrs r3, r3, #8 + 8004a66: 227f movs r2, #127 ; 0x7f + 8004a68: 4013 ands r3, r2 + 8004a6a: 434b muls r3, r1 + 8004a6c: 617b str r3, [r7, #20] + break; + 8004a6e: 46c0 nop ; (mov r8, r8) + } + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); + 8004a70: 4b14 ldr r3, [pc, #80] ; (8004ac4 ) + 8004a72: 68db ldr r3, [r3, #12] + 8004a74: 0f5b lsrs r3, r3, #29 + 8004a76: 2207 movs r2, #7 + 8004a78: 4013 ands r3, r2 + 8004a7a: 3301 adds r3, #1 + 8004a7c: 607b str r3, [r7, #4] + sysclockfreq = pllvco / pllr; + 8004a7e: 6879 ldr r1, [r7, #4] + 8004a80: 6978 ldr r0, [r7, #20] + 8004a82: f7fb fb3f bl 8000104 <__udivsi3> + 8004a86: 0003 movs r3, r0 + 8004a88: 613b str r3, [r7, #16] + 8004a8a: e015 b.n 8004ab8 + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) + 8004a8c: 4b0d ldr r3, [pc, #52] ; (8004ac4 ) + 8004a8e: 689b ldr r3, [r3, #8] + 8004a90: 2238 movs r2, #56 ; 0x38 + 8004a92: 4013 ands r3, r2 + 8004a94: 2b20 cmp r3, #32 + 8004a96: d103 bne.n 8004aa0 + { + /* LSE used as system clock source */ + sysclockfreq = LSE_VALUE; + 8004a98: 2380 movs r3, #128 ; 0x80 + 8004a9a: 021b lsls r3, r3, #8 + 8004a9c: 613b str r3, [r7, #16] + 8004a9e: e00b b.n 8004ab8 + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) + 8004aa0: 4b08 ldr r3, [pc, #32] ; (8004ac4 ) + 8004aa2: 689b ldr r3, [r3, #8] + 8004aa4: 2238 movs r2, #56 ; 0x38 + 8004aa6: 4013 ands r3, r2 + 8004aa8: 2b18 cmp r3, #24 + 8004aaa: d103 bne.n 8004ab4 + { + /* LSI used as system clock source */ + sysclockfreq = LSI_VALUE; + 8004aac: 23fa movs r3, #250 ; 0xfa + 8004aae: 01db lsls r3, r3, #7 + 8004ab0: 613b str r3, [r7, #16] + 8004ab2: e001 b.n 8004ab8 + } + else + { + sysclockfreq = 0U; + 8004ab4: 2300 movs r3, #0 + 8004ab6: 613b str r3, [r7, #16] + } + + return sysclockfreq; + 8004ab8: 693b ldr r3, [r7, #16] +} + 8004aba: 0018 movs r0, r3 + 8004abc: 46bd mov sp, r7 + 8004abe: b006 add sp, #24 + 8004ac0: bd80 pop {r7, pc} + 8004ac2: 46c0 nop ; (mov r8, r8) + 8004ac4: 40021000 .word 0x40021000 + 8004ac8: 00f42400 .word 0x00f42400 + 8004acc: 007a1200 .word 0x007a1200 + +08004ad0 : + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8004ad0: b580 push {r7, lr} + 8004ad2: b086 sub sp, #24 + 8004ad4: af00 add r7, sp, #0 + 8004ad6: 6078 str r0, [r7, #4] + uint32_t tmpregister; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 8004ad8: 2313 movs r3, #19 + 8004ada: 18fb adds r3, r7, r3 + 8004adc: 2200 movs r2, #0 + 8004ade: 701a strb r2, [r3, #0] + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 8004ae0: 2312 movs r3, #18 + 8004ae2: 18fb adds r3, r7, r3 + 8004ae4: 2200 movs r2, #0 + 8004ae6: 701a strb r2, [r3, #0] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 8004ae8: 687b ldr r3, [r7, #4] + 8004aea: 681a ldr r2, [r3, #0] + 8004aec: 2380 movs r3, #128 ; 0x80 + 8004aee: 029b lsls r3, r3, #10 + 8004af0: 4013 ands r3, r2 + 8004af2: d100 bne.n 8004af6 + 8004af4: e0ad b.n 8004c52 + { + FlagStatus pwrclkchanged = RESET; + 8004af6: 2011 movs r0, #17 + 8004af8: 183b adds r3, r7, r0 + 8004afa: 2200 movs r2, #0 + 8004afc: 701a strb r2, [r3, #0] + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8004afe: 4b47 ldr r3, [pc, #284] ; (8004c1c ) + 8004b00: 6bda ldr r2, [r3, #60] ; 0x3c + 8004b02: 2380 movs r3, #128 ; 0x80 + 8004b04: 055b lsls r3, r3, #21 + 8004b06: 4013 ands r3, r2 + 8004b08: d110 bne.n 8004b2c + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8004b0a: 4b44 ldr r3, [pc, #272] ; (8004c1c ) + 8004b0c: 6bda ldr r2, [r3, #60] ; 0x3c + 8004b0e: 4b43 ldr r3, [pc, #268] ; (8004c1c ) + 8004b10: 2180 movs r1, #128 ; 0x80 + 8004b12: 0549 lsls r1, r1, #21 + 8004b14: 430a orrs r2, r1 + 8004b16: 63da str r2, [r3, #60] ; 0x3c + 8004b18: 4b40 ldr r3, [pc, #256] ; (8004c1c ) + 8004b1a: 6bda ldr r2, [r3, #60] ; 0x3c + 8004b1c: 2380 movs r3, #128 ; 0x80 + 8004b1e: 055b lsls r3, r3, #21 + 8004b20: 4013 ands r3, r2 + 8004b22: 60bb str r3, [r7, #8] + 8004b24: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8004b26: 183b adds r3, r7, r0 + 8004b28: 2201 movs r2, #1 + 8004b2a: 701a strb r2, [r3, #0] + } + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 8004b2c: 4b3c ldr r3, [pc, #240] ; (8004c20 ) + 8004b2e: 681a ldr r2, [r3, #0] + 8004b30: 4b3b ldr r3, [pc, #236] ; (8004c20 ) + 8004b32: 2180 movs r1, #128 ; 0x80 + 8004b34: 0049 lsls r1, r1, #1 + 8004b36: 430a orrs r2, r1 + 8004b38: 601a str r2, [r3, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8004b3a: f7fc f8f3 bl 8000d24 + 8004b3e: 0003 movs r3, r0 + 8004b40: 60fb str r3, [r7, #12] + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + 8004b42: e00b b.n 8004b5c + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8004b44: f7fc f8ee bl 8000d24 + 8004b48: 0002 movs r2, r0 + 8004b4a: 68fb ldr r3, [r7, #12] + 8004b4c: 1ad3 subs r3, r2, r3 + 8004b4e: 2b02 cmp r3, #2 + 8004b50: d904 bls.n 8004b5c + { + ret = HAL_TIMEOUT; + 8004b52: 2313 movs r3, #19 + 8004b54: 18fb adds r3, r7, r3 + 8004b56: 2203 movs r2, #3 + 8004b58: 701a strb r2, [r3, #0] + break; + 8004b5a: e005 b.n 8004b68 + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + 8004b5c: 4b30 ldr r3, [pc, #192] ; (8004c20 ) + 8004b5e: 681a ldr r2, [r3, #0] + 8004b60: 2380 movs r3, #128 ; 0x80 + 8004b62: 005b lsls r3, r3, #1 + 8004b64: 4013 ands r3, r2 + 8004b66: d0ed beq.n 8004b44 + } + } + + if (ret == HAL_OK) + 8004b68: 2313 movs r3, #19 + 8004b6a: 18fb adds r3, r7, r3 + 8004b6c: 781b ldrb r3, [r3, #0] + 8004b6e: 2b00 cmp r3, #0 + 8004b70: d15e bne.n 8004c30 + { + /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); + 8004b72: 4b2a ldr r3, [pc, #168] ; (8004c1c ) + 8004b74: 6dda ldr r2, [r3, #92] ; 0x5c + 8004b76: 23c0 movs r3, #192 ; 0xc0 + 8004b78: 009b lsls r3, r3, #2 + 8004b7a: 4013 ands r3, r2 + 8004b7c: 617b str r3, [r7, #20] + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) + 8004b7e: 697b ldr r3, [r7, #20] + 8004b80: 2b00 cmp r3, #0 + 8004b82: d019 beq.n 8004bb8 + 8004b84: 687b ldr r3, [r7, #4] + 8004b86: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004b88: 697a ldr r2, [r7, #20] + 8004b8a: 429a cmp r2, r3 + 8004b8c: d014 beq.n 8004bb8 + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + 8004b8e: 4b23 ldr r3, [pc, #140] ; (8004c1c ) + 8004b90: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004b92: 4a24 ldr r2, [pc, #144] ; (8004c24 ) + 8004b94: 4013 ands r3, r2 + 8004b96: 617b str r3, [r7, #20] + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 8004b98: 4b20 ldr r3, [pc, #128] ; (8004c1c ) + 8004b9a: 6dda ldr r2, [r3, #92] ; 0x5c + 8004b9c: 4b1f ldr r3, [pc, #124] ; (8004c1c ) + 8004b9e: 2180 movs r1, #128 ; 0x80 + 8004ba0: 0249 lsls r1, r1, #9 + 8004ba2: 430a orrs r2, r1 + 8004ba4: 65da str r2, [r3, #92] ; 0x5c + __HAL_RCC_BACKUPRESET_RELEASE(); + 8004ba6: 4b1d ldr r3, [pc, #116] ; (8004c1c ) + 8004ba8: 6dda ldr r2, [r3, #92] ; 0x5c + 8004baa: 4b1c ldr r3, [pc, #112] ; (8004c1c ) + 8004bac: 491e ldr r1, [pc, #120] ; (8004c28 ) + 8004bae: 400a ands r2, r1 + 8004bb0: 65da str r2, [r3, #92] ; 0x5c + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + 8004bb2: 4b1a ldr r3, [pc, #104] ; (8004c1c ) + 8004bb4: 697a ldr r2, [r7, #20] + 8004bb6: 65da str r2, [r3, #92] ; 0x5c + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) + 8004bb8: 697b ldr r3, [r7, #20] + 8004bba: 2201 movs r2, #1 + 8004bbc: 4013 ands r3, r2 + 8004bbe: d016 beq.n 8004bee + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8004bc0: f7fc f8b0 bl 8000d24 + 8004bc4: 0003 movs r3, r0 + 8004bc6: 60fb str r3, [r7, #12] + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 8004bc8: e00c b.n 8004be4 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8004bca: f7fc f8ab bl 8000d24 + 8004bce: 0002 movs r2, r0 + 8004bd0: 68fb ldr r3, [r7, #12] + 8004bd2: 1ad3 subs r3, r2, r3 + 8004bd4: 4a15 ldr r2, [pc, #84] ; (8004c2c ) + 8004bd6: 4293 cmp r3, r2 + 8004bd8: d904 bls.n 8004be4 + { + ret = HAL_TIMEOUT; + 8004bda: 2313 movs r3, #19 + 8004bdc: 18fb adds r3, r7, r3 + 8004bde: 2203 movs r2, #3 + 8004be0: 701a strb r2, [r3, #0] + break; + 8004be2: e004 b.n 8004bee + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 8004be4: 4b0d ldr r3, [pc, #52] ; (8004c1c ) + 8004be6: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004be8: 2202 movs r2, #2 + 8004bea: 4013 ands r3, r2 + 8004bec: d0ed beq.n 8004bca + } + } + } + + if (ret == HAL_OK) + 8004bee: 2313 movs r3, #19 + 8004bf0: 18fb adds r3, r7, r3 + 8004bf2: 781b ldrb r3, [r3, #0] + 8004bf4: 2b00 cmp r3, #0 + 8004bf6: d10a bne.n 8004c0e + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8004bf8: 4b08 ldr r3, [pc, #32] ; (8004c1c ) + 8004bfa: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004bfc: 4a09 ldr r2, [pc, #36] ; (8004c24 ) + 8004bfe: 4013 ands r3, r2 + 8004c00: 0019 movs r1, r3 + 8004c02: 687b ldr r3, [r7, #4] + 8004c04: 6c1a ldr r2, [r3, #64] ; 0x40 + 8004c06: 4b05 ldr r3, [pc, #20] ; (8004c1c ) + 8004c08: 430a orrs r2, r1 + 8004c0a: 65da str r2, [r3, #92] ; 0x5c + 8004c0c: e016 b.n 8004c3c + } + else + { + /* set overall return value */ + status = ret; + 8004c0e: 2312 movs r3, #18 + 8004c10: 18fb adds r3, r7, r3 + 8004c12: 2213 movs r2, #19 + 8004c14: 18ba adds r2, r7, r2 + 8004c16: 7812 ldrb r2, [r2, #0] + 8004c18: 701a strb r2, [r3, #0] + 8004c1a: e00f b.n 8004c3c + 8004c1c: 40021000 .word 0x40021000 + 8004c20: 40007000 .word 0x40007000 + 8004c24: fffffcff .word 0xfffffcff + 8004c28: fffeffff .word 0xfffeffff + 8004c2c: 00001388 .word 0x00001388 + } + } + else + { + /* set overall return value */ + status = ret; + 8004c30: 2312 movs r3, #18 + 8004c32: 18fb adds r3, r7, r3 + 8004c34: 2213 movs r2, #19 + 8004c36: 18ba adds r2, r7, r2 + 8004c38: 7812 ldrb r2, [r2, #0] + 8004c3a: 701a strb r2, [r3, #0] + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + 8004c3c: 2311 movs r3, #17 + 8004c3e: 18fb adds r3, r7, r3 + 8004c40: 781b ldrb r3, [r3, #0] + 8004c42: 2b01 cmp r3, #1 + 8004c44: d105 bne.n 8004c52 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8004c46: 4bb6 ldr r3, [pc, #728] ; (8004f20 ) + 8004c48: 6bda ldr r2, [r3, #60] ; 0x3c + 8004c4a: 4bb5 ldr r3, [pc, #724] ; (8004f20 ) + 8004c4c: 49b5 ldr r1, [pc, #724] ; (8004f24 ) + 8004c4e: 400a ands r2, r1 + 8004c50: 63da str r2, [r3, #60] ; 0x3c + } + } + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8004c52: 687b ldr r3, [r7, #4] + 8004c54: 681b ldr r3, [r3, #0] + 8004c56: 2201 movs r2, #1 + 8004c58: 4013 ands r3, r2 + 8004c5a: d009 beq.n 8004c70 + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8004c5c: 4bb0 ldr r3, [pc, #704] ; (8004f20 ) + 8004c5e: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004c60: 2203 movs r2, #3 + 8004c62: 4393 bics r3, r2 + 8004c64: 0019 movs r1, r3 + 8004c66: 687b ldr r3, [r7, #4] + 8004c68: 685a ldr r2, [r3, #4] + 8004c6a: 4bad ldr r3, [pc, #692] ; (8004f20 ) + 8004c6c: 430a orrs r2, r1 + 8004c6e: 655a str r2, [r3, #84] ; 0x54 + } + +#if defined(RCC_CCIPR_USART2SEL) + /*-------------------------- USART2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8004c70: 687b ldr r3, [r7, #4] + 8004c72: 681b ldr r3, [r3, #0] + 8004c74: 2202 movs r2, #2 + 8004c76: 4013 ands r3, r2 + 8004c78: d009 beq.n 8004c8e + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 8004c7a: 4ba9 ldr r3, [pc, #676] ; (8004f20 ) + 8004c7c: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004c7e: 220c movs r2, #12 + 8004c80: 4393 bics r3, r2 + 8004c82: 0019 movs r1, r3 + 8004c84: 687b ldr r3, [r7, #4] + 8004c86: 689a ldr r2, [r3, #8] + 8004c88: 4ba5 ldr r3, [pc, #660] ; (8004f20 ) + 8004c8a: 430a orrs r2, r1 + 8004c8c: 655a str r2, [r3, #84] ; 0x54 + } +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) + /*-------------------------- USART3 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 8004c8e: 687b ldr r3, [r7, #4] + 8004c90: 681b ldr r3, [r3, #0] + 8004c92: 2204 movs r2, #4 + 8004c94: 4013 ands r3, r2 + 8004c96: d009 beq.n 8004cac + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 8004c98: 4ba1 ldr r3, [pc, #644] ; (8004f20 ) + 8004c9a: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004c9c: 2230 movs r2, #48 ; 0x30 + 8004c9e: 4393 bics r3, r2 + 8004ca0: 0019 movs r1, r3 + 8004ca2: 687b ldr r3, [r7, #4] + 8004ca4: 68da ldr r2, [r3, #12] + 8004ca6: 4b9e ldr r3, [pc, #632] ; (8004f20 ) + 8004ca8: 430a orrs r2, r1 + 8004caa: 655a str r2, [r3, #84] ; 0x54 + } +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 8004cac: 687b ldr r3, [r7, #4] + 8004cae: 681b ldr r3, [r3, #0] + 8004cb0: 2210 movs r2, #16 + 8004cb2: 4013 ands r3, r2 + 8004cb4: d009 beq.n 8004cca + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUART1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 8004cb6: 4b9a ldr r3, [pc, #616] ; (8004f20 ) + 8004cb8: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004cba: 4a9b ldr r2, [pc, #620] ; (8004f28 ) + 8004cbc: 4013 ands r3, r2 + 8004cbe: 0019 movs r1, r3 + 8004cc0: 687b ldr r3, [r7, #4] + 8004cc2: 691a ldr r2, [r3, #16] + 8004cc4: 4b96 ldr r3, [pc, #600] ; (8004f20 ) + 8004cc6: 430a orrs r2, r1 + 8004cc8: 655a str r2, [r3, #84] ; 0x54 + } +#endif /* LPUART1 */ + +#if defined(LPUART2) + /*-------------------------- LPUART2 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) + 8004cca: 687b ldr r3, [r7, #4] + 8004ccc: 681a ldr r2, [r3, #0] + 8004cce: 2380 movs r3, #128 ; 0x80 + 8004cd0: 015b lsls r3, r3, #5 + 8004cd2: 4013 ands r3, r2 + 8004cd4: d009 beq.n 8004cea + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART2CLKSOURCE(PeriphClkInit->Lpuart2ClockSelection)); + + /* Configure the LPUART clock source */ + __HAL_RCC_LPUART2_CONFIG(PeriphClkInit->Lpuart2ClockSelection); + 8004cd6: 4b92 ldr r3, [pc, #584] ; (8004f20 ) + 8004cd8: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004cda: 4a94 ldr r2, [pc, #592] ; (8004f2c ) + 8004cdc: 4013 ands r3, r2 + 8004cde: 0019 movs r1, r3 + 8004ce0: 687b ldr r3, [r7, #4] + 8004ce2: 695a ldr r2, [r3, #20] + 8004ce4: 4b8e ldr r3, [pc, #568] ; (8004f20 ) + 8004ce6: 430a orrs r2, r1 + 8004ce8: 655a str r2, [r3, #84] ; 0x54 + } +#endif /* LPUART2 */ + +#if defined(RCC_CCIPR_LPTIM1SEL) + /*-------------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 8004cea: 687b ldr r3, [r7, #4] + 8004cec: 681a ldr r2, [r3, #0] + 8004cee: 2380 movs r3, #128 ; 0x80 + 8004cf0: 009b lsls r3, r3, #2 + 8004cf2: 4013 ands r3, r2 + 8004cf4: d009 beq.n 8004d0a + { + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 8004cf6: 4b8a ldr r3, [pc, #552] ; (8004f20 ) + 8004cf8: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004cfa: 4a8d ldr r2, [pc, #564] ; (8004f30 ) + 8004cfc: 4013 ands r3, r2 + 8004cfe: 0019 movs r1, r3 + 8004d00: 687b ldr r3, [r7, #4] + 8004d02: 6a9a ldr r2, [r3, #40] ; 0x28 + 8004d04: 4b86 ldr r3, [pc, #536] ; (8004f20 ) + 8004d06: 430a orrs r2, r1 + 8004d08: 655a str r2, [r3, #84] ; 0x54 + } +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) + /*-------------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + 8004d0a: 687b ldr r3, [r7, #4] + 8004d0c: 681a ldr r2, [r3, #0] + 8004d0e: 2380 movs r3, #128 ; 0x80 + 8004d10: 00db lsls r3, r3, #3 + 8004d12: 4013 ands r3, r2 + 8004d14: d009 beq.n 8004d2a + { + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + 8004d16: 4b82 ldr r3, [pc, #520] ; (8004f20 ) + 8004d18: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004d1a: 4a86 ldr r2, [pc, #536] ; (8004f34 ) + 8004d1c: 4013 ands r3, r2 + 8004d1e: 0019 movs r1, r3 + 8004d20: 687b ldr r3, [r7, #4] + 8004d22: 6ada ldr r2, [r3, #44] ; 0x2c + 8004d24: 4b7e ldr r3, [pc, #504] ; (8004f20 ) + 8004d26: 430a orrs r2, r1 + 8004d28: 655a str r2, [r3, #84] ; 0x54 + } +#endif /* RCC_CCIPR_LPTIM2SEL */ + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8004d2a: 687b ldr r3, [r7, #4] + 8004d2c: 681b ldr r3, [r3, #0] + 8004d2e: 2220 movs r2, #32 + 8004d30: 4013 ands r3, r2 + 8004d32: d009 beq.n 8004d48 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 8004d34: 4b7a ldr r3, [pc, #488] ; (8004f20 ) + 8004d36: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004d38: 4a7f ldr r2, [pc, #508] ; (8004f38 ) + 8004d3a: 4013 ands r3, r2 + 8004d3c: 0019 movs r1, r3 + 8004d3e: 687b ldr r3, [r7, #4] + 8004d40: 699a ldr r2, [r3, #24] + 8004d42: 4b77 ldr r3, [pc, #476] ; (8004f20 ) + 8004d44: 430a orrs r2, r1 + 8004d46: 655a str r2, [r3, #84] ; 0x54 + } + +#if defined(RCC_CCIPR_I2C2SEL) + /*-------------------------- I2C2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 8004d48: 687b ldr r3, [r7, #4] + 8004d4a: 681b ldr r3, [r3, #0] + 8004d4c: 2240 movs r2, #64 ; 0x40 + 8004d4e: 4013 ands r3, r2 + 8004d50: d009 beq.n 8004d66 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 8004d52: 4b73 ldr r3, [pc, #460] ; (8004f20 ) + 8004d54: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004d56: 4a79 ldr r2, [pc, #484] ; (8004f3c ) + 8004d58: 4013 ands r3, r2 + 8004d5a: 0019 movs r1, r3 + 8004d5c: 687b ldr r3, [r7, #4] + 8004d5e: 69da ldr r2, [r3, #28] + 8004d60: 4b6f ldr r3, [pc, #444] ; (8004f20 ) + 8004d62: 430a orrs r2, r1 + 8004d64: 655a str r2, [r3, #84] ; 0x54 + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* RNG */ + /*-------------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 8004d66: 687b ldr r3, [r7, #4] + 8004d68: 681a ldr r2, [r3, #0] + 8004d6a: 2380 movs r3, #128 ; 0x80 + 8004d6c: 01db lsls r3, r3, #7 + 8004d6e: 4013 ands r3, r2 + 8004d70: d015 beq.n 8004d9e + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 8004d72: 4b6b ldr r3, [pc, #428] ; (8004f20 ) + 8004d74: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004d76: 009b lsls r3, r3, #2 + 8004d78: 0899 lsrs r1, r3, #2 + 8004d7a: 687b ldr r3, [r7, #4] + 8004d7c: 6b1a ldr r2, [r3, #48] ; 0x30 + 8004d7e: 4b68 ldr r3, [pc, #416] ; (8004f20 ) + 8004d80: 430a orrs r2, r1 + 8004d82: 655a str r2, [r3, #84] ; 0x54 + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC) + 8004d84: 687b ldr r3, [r7, #4] + 8004d86: 6b1a ldr r2, [r3, #48] ; 0x30 + 8004d88: 2380 movs r3, #128 ; 0x80 + 8004d8a: 05db lsls r3, r3, #23 + 8004d8c: 429a cmp r2, r3 + 8004d8e: d106 bne.n 8004d9e + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + 8004d90: 4b63 ldr r3, [pc, #396] ; (8004f20 ) + 8004d92: 68da ldr r2, [r3, #12] + 8004d94: 4b62 ldr r3, [pc, #392] ; (8004f20 ) + 8004d96: 2180 movs r1, #128 ; 0x80 + 8004d98: 0249 lsls r1, r1, #9 + 8004d9a: 430a orrs r2, r1 + 8004d9c: 60da str r2, [r3, #12] + } + } + +#if defined(CEC) + /*-------------------------- CEC clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 8004d9e: 687b ldr r3, [r7, #4] + 8004da0: 681a ldr r2, [r3, #0] + 8004da2: 2380 movs r3, #128 ; 0x80 + 8004da4: 031b lsls r3, r3, #12 + 8004da6: 4013 ands r3, r2 + 8004da8: d009 beq.n 8004dbe + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 8004daa: 4b5d ldr r3, [pc, #372] ; (8004f20 ) + 8004dac: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004dae: 2240 movs r2, #64 ; 0x40 + 8004db0: 4393 bics r3, r2 + 8004db2: 0019 movs r1, r3 + 8004db4: 687b ldr r3, [r7, #4] + 8004db6: 6b5a ldr r2, [r3, #52] ; 0x34 + 8004db8: 4b59 ldr r3, [pc, #356] ; (8004f20 ) + 8004dba: 430a orrs r2, r1 + 8004dbc: 655a str r2, [r3, #84] ; 0x54 + } +#endif /* CEC */ + +#if defined(RCC_CCIPR_TIM1SEL) + /*-------------------------- TIM1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) + 8004dbe: 687b ldr r3, [r7, #4] + 8004dc0: 681a ldr r2, [r3, #0] + 8004dc2: 2380 movs r3, #128 ; 0x80 + 8004dc4: 039b lsls r3, r3, #14 + 8004dc6: 4013 ands r3, r2 + 8004dc8: d016 beq.n 8004df8 + { + /* Check the parameters */ + assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); + + /* Configure the TIM1 clock source */ + __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); + 8004dca: 4b55 ldr r3, [pc, #340] ; (8004f20 ) + 8004dcc: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004dce: 4a5c ldr r2, [pc, #368] ; (8004f40 ) + 8004dd0: 4013 ands r3, r2 + 8004dd2: 0019 movs r1, r3 + 8004dd4: 687b ldr r3, [r7, #4] + 8004dd6: 6b9a ldr r2, [r3, #56] ; 0x38 + 8004dd8: 4b51 ldr r3, [pc, #324] ; (8004f20 ) + 8004dda: 430a orrs r2, r1 + 8004ddc: 655a str r2, [r3, #84] ; 0x54 + + if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL) + 8004dde: 687b ldr r3, [r7, #4] + 8004de0: 6b9a ldr r2, [r3, #56] ; 0x38 + 8004de2: 2380 movs r3, #128 ; 0x80 + 8004de4: 03db lsls r3, r3, #15 + 8004de6: 429a cmp r2, r3 + 8004de8: d106 bne.n 8004df8 + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 8004dea: 4b4d ldr r3, [pc, #308] ; (8004f20 ) + 8004dec: 68da ldr r2, [r3, #12] + 8004dee: 4b4c ldr r3, [pc, #304] ; (8004f20 ) + 8004df0: 2180 movs r1, #128 ; 0x80 + 8004df2: 0449 lsls r1, r1, #17 + 8004df4: 430a orrs r2, r1 + 8004df6: 60da str r2, [r3, #12] + } +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) + /*-------------------------- TIM15 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + 8004df8: 687b ldr r3, [r7, #4] + 8004dfa: 681a ldr r2, [r3, #0] + 8004dfc: 2380 movs r3, #128 ; 0x80 + 8004dfe: 03db lsls r3, r3, #15 + 8004e00: 4013 ands r3, r2 + 8004e02: d016 beq.n 8004e32 + { + /* Check the parameters */ + assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + + /* Configure the TIM15 clock source */ + __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + 8004e04: 4b46 ldr r3, [pc, #280] ; (8004f20 ) + 8004e06: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004e08: 4a4e ldr r2, [pc, #312] ; (8004f44 ) + 8004e0a: 4013 ands r3, r2 + 8004e0c: 0019 movs r1, r3 + 8004e0e: 687b ldr r3, [r7, #4] + 8004e10: 6bda ldr r2, [r3, #60] ; 0x3c + 8004e12: 4b43 ldr r3, [pc, #268] ; (8004f20 ) + 8004e14: 430a orrs r2, r1 + 8004e16: 655a str r2, [r3, #84] ; 0x54 + + if (PeriphClkInit->Tim15ClockSelection == RCC_TIM15CLKSOURCE_PLL) + 8004e18: 687b ldr r3, [r7, #4] + 8004e1a: 6bda ldr r2, [r3, #60] ; 0x3c + 8004e1c: 2380 movs r3, #128 ; 0x80 + 8004e1e: 045b lsls r3, r3, #17 + 8004e20: 429a cmp r2, r3 + 8004e22: d106 bne.n 8004e32 + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 8004e24: 4b3e ldr r3, [pc, #248] ; (8004f20 ) + 8004e26: 68da ldr r2, [r3, #12] + 8004e28: 4b3d ldr r3, [pc, #244] ; (8004f20 ) + 8004e2a: 2180 movs r1, #128 ; 0x80 + 8004e2c: 0449 lsls r1, r1, #17 + 8004e2e: 430a orrs r2, r1 + 8004e30: 60da str r2, [r3, #12] + } + } +#endif /* RCC_CCIPR_TIM15SEL */ + + /*-------------------------- I2S1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) + 8004e32: 687b ldr r3, [r7, #4] + 8004e34: 681a ldr r2, [r3, #0] + 8004e36: 2380 movs r3, #128 ; 0x80 + 8004e38: 011b lsls r3, r3, #4 + 8004e3a: 4013 ands r3, r2 + 8004e3c: d014 beq.n 8004e68 + { + /* Check the parameters */ + assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); + + /* Configure the I2S1 clock source */ + __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); + 8004e3e: 4b38 ldr r3, [pc, #224] ; (8004f20 ) + 8004e40: 6d9b ldr r3, [r3, #88] ; 0x58 + 8004e42: 2203 movs r2, #3 + 8004e44: 4393 bics r3, r2 + 8004e46: 0019 movs r1, r3 + 8004e48: 687b ldr r3, [r7, #4] + 8004e4a: 6a1a ldr r2, [r3, #32] + 8004e4c: 4b34 ldr r3, [pc, #208] ; (8004f20 ) + 8004e4e: 430a orrs r2, r1 + 8004e50: 659a str r2, [r3, #88] ; 0x58 + + if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL) + 8004e52: 687b ldr r3, [r7, #4] + 8004e54: 6a1b ldr r3, [r3, #32] + 8004e56: 2b01 cmp r3, #1 + 8004e58: d106 bne.n 8004e68 + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + 8004e5a: 4b31 ldr r3, [pc, #196] ; (8004f20 ) + 8004e5c: 68da ldr r2, [r3, #12] + 8004e5e: 4b30 ldr r3, [pc, #192] ; (8004f20 ) + 8004e60: 2180 movs r1, #128 ; 0x80 + 8004e62: 0249 lsls r1, r1, #9 + 8004e64: 430a orrs r2, r1 + 8004e66: 60da str r2, [r3, #12] + } + } + +#if defined(RCC_CCIPR2_I2S2SEL) + /*-------------------------- I2S2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) + 8004e68: 687b ldr r3, [r7, #4] + 8004e6a: 681a ldr r2, [r3, #0] + 8004e6c: 2380 movs r3, #128 ; 0x80 + 8004e6e: 019b lsls r3, r3, #6 + 8004e70: 4013 ands r3, r2 + 8004e72: d014 beq.n 8004e9e + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + 8004e74: 4b2a ldr r3, [pc, #168] ; (8004f20 ) + 8004e76: 6d9b ldr r3, [r3, #88] ; 0x58 + 8004e78: 220c movs r2, #12 + 8004e7a: 4393 bics r3, r2 + 8004e7c: 0019 movs r1, r3 + 8004e7e: 687b ldr r3, [r7, #4] + 8004e80: 6a5a ldr r2, [r3, #36] ; 0x24 + 8004e82: 4b27 ldr r3, [pc, #156] ; (8004f20 ) + 8004e84: 430a orrs r2, r1 + 8004e86: 659a str r2, [r3, #88] ; 0x58 + + if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) + 8004e88: 687b ldr r3, [r7, #4] + 8004e8a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004e8c: 2b04 cmp r3, #4 + 8004e8e: d106 bne.n 8004e9e + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + 8004e90: 4b23 ldr r3, [pc, #140] ; (8004f20 ) + 8004e92: 68da ldr r2, [r3, #12] + 8004e94: 4b22 ldr r3, [pc, #136] ; (8004f20 ) + 8004e96: 2180 movs r1, #128 ; 0x80 + 8004e98: 0249 lsls r1, r1, #9 + 8004e9a: 430a orrs r2, r1 + 8004e9c: 60da str r2, [r3, #12] + } +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + /*-------------------------- USB clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + 8004e9e: 687b ldr r3, [r7, #4] + 8004ea0: 681a ldr r2, [r3, #0] + 8004ea2: 2380 movs r3, #128 ; 0x80 + 8004ea4: 045b lsls r3, r3, #17 + 8004ea6: 4013 ands r3, r2 + 8004ea8: d016 beq.n 8004ed8 + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 8004eaa: 4b1d ldr r3, [pc, #116] ; (8004f20 ) + 8004eac: 6d9b ldr r3, [r3, #88] ; 0x58 + 8004eae: 4a22 ldr r2, [pc, #136] ; (8004f38 ) + 8004eb0: 4013 ands r3, r2 + 8004eb2: 0019 movs r1, r3 + 8004eb4: 687b ldr r3, [r7, #4] + 8004eb6: 6c5a ldr r2, [r3, #68] ; 0x44 + 8004eb8: 4b19 ldr r3, [pc, #100] ; (8004f20 ) + 8004eba: 430a orrs r2, r1 + 8004ebc: 659a str r2, [r3, #88] ; 0x58 + + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) + 8004ebe: 687b ldr r3, [r7, #4] + 8004ec0: 6c5a ldr r2, [r3, #68] ; 0x44 + 8004ec2: 2380 movs r3, #128 ; 0x80 + 8004ec4: 019b lsls r3, r3, #6 + 8004ec6: 429a cmp r2, r3 + 8004ec8: d106 bne.n 8004ed8 + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 8004eca: 4b15 ldr r3, [pc, #84] ; (8004f20 ) + 8004ecc: 68da ldr r2, [r3, #12] + 8004ece: 4b14 ldr r3, [pc, #80] ; (8004f20 ) + 8004ed0: 2180 movs r1, #128 ; 0x80 + 8004ed2: 0449 lsls r1, r1, #17 + 8004ed4: 430a orrs r2, r1 + 8004ed6: 60da str r2, [r3, #12] + } +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(FDCAN1) || defined(FDCAN2) + /*-------------------------- FDCAN clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + 8004ed8: 687b ldr r3, [r7, #4] + 8004eda: 681a ldr r2, [r3, #0] + 8004edc: 2380 movs r3, #128 ; 0x80 + 8004ede: 049b lsls r3, r3, #18 + 8004ee0: 4013 ands r3, r2 + 8004ee2: d016 beq.n 8004f12 + { + /* Check the parameters */ + assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); + + /* Configure the FDCAN clock source */ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + 8004ee4: 4b0e ldr r3, [pc, #56] ; (8004f20 ) + 8004ee6: 6d9b ldr r3, [r3, #88] ; 0x58 + 8004ee8: 4a10 ldr r2, [pc, #64] ; (8004f2c ) + 8004eea: 4013 ands r3, r2 + 8004eec: 0019 movs r1, r3 + 8004eee: 687b ldr r3, [r7, #4] + 8004ef0: 6c9a ldr r2, [r3, #72] ; 0x48 + 8004ef2: 4b0b ldr r3, [pc, #44] ; (8004f20 ) + 8004ef4: 430a orrs r2, r1 + 8004ef6: 659a str r2, [r3, #88] ; 0x58 + + if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) + 8004ef8: 687b ldr r3, [r7, #4] + 8004efa: 6c9a ldr r2, [r3, #72] ; 0x48 + 8004efc: 2380 movs r3, #128 ; 0x80 + 8004efe: 005b lsls r3, r3, #1 + 8004f00: 429a cmp r2, r3 + 8004f02: d106 bne.n 8004f12 + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 8004f04: 4b06 ldr r3, [pc, #24] ; (8004f20 ) + 8004f06: 68da ldr r2, [r3, #12] + 8004f08: 4b05 ldr r3, [pc, #20] ; (8004f20 ) + 8004f0a: 2180 movs r1, #128 ; 0x80 + 8004f0c: 0449 lsls r1, r1, #17 + 8004f0e: 430a orrs r2, r1 + 8004f10: 60da str r2, [r3, #12] + } + } +#endif /* FDCAN1 || FDCAN2 */ + + return status; + 8004f12: 2312 movs r3, #18 + 8004f14: 18fb adds r3, r7, r3 + 8004f16: 781b ldrb r3, [r3, #0] +} + 8004f18: 0018 movs r0, r3 + 8004f1a: 46bd mov sp, r7 + 8004f1c: b006 add sp, #24 + 8004f1e: bd80 pop {r7, pc} + 8004f20: 40021000 .word 0x40021000 + 8004f24: efffffff .word 0xefffffff + 8004f28: fffff3ff .word 0xfffff3ff + 8004f2c: fffffcff .word 0xfffffcff + 8004f30: fff3ffff .word 0xfff3ffff + 8004f34: ffcfffff .word 0xffcfffff + 8004f38: ffffcfff .word 0xffffcfff + 8004f3c: ffff3fff .word 0xffff3fff + 8004f40: ffbfffff .word 0xffbfffff + 8004f44: feffffff .word 0xfeffffff + +08004f48 : + 8004f48: b510 push {r4, lr} + 8004f4a: 4b03 ldr r3, [pc, #12] ; (8004f58 ) + 8004f4c: 0001 movs r1, r0 + 8004f4e: 6818 ldr r0, [r3, #0] + 8004f50: f000 f826 bl 8004fa0 <_malloc_r> + 8004f54: bd10 pop {r4, pc} + 8004f56: 46c0 nop ; (mov r8, r8) + 8004f58: 20000058 .word 0x20000058 + +08004f5c : + 8004f5c: b570 push {r4, r5, r6, lr} + 8004f5e: 4e0f ldr r6, [pc, #60] ; (8004f9c ) + 8004f60: 000d movs r5, r1 + 8004f62: 6831 ldr r1, [r6, #0] + 8004f64: 0004 movs r4, r0 + 8004f66: 2900 cmp r1, #0 + 8004f68: d102 bne.n 8004f70 + 8004f6a: f000 f8b3 bl 80050d4 <_sbrk_r> + 8004f6e: 6030 str r0, [r6, #0] + 8004f70: 0029 movs r1, r5 + 8004f72: 0020 movs r0, r4 + 8004f74: f000 f8ae bl 80050d4 <_sbrk_r> + 8004f78: 1c43 adds r3, r0, #1 + 8004f7a: d00a beq.n 8004f92 + 8004f7c: 2303 movs r3, #3 + 8004f7e: 1cc5 adds r5, r0, #3 + 8004f80: 439d bics r5, r3 + 8004f82: 42a8 cmp r0, r5 + 8004f84: d007 beq.n 8004f96 + 8004f86: 1a29 subs r1, r5, r0 + 8004f88: 0020 movs r0, r4 + 8004f8a: f000 f8a3 bl 80050d4 <_sbrk_r> + 8004f8e: 3001 adds r0, #1 + 8004f90: d101 bne.n 8004f96 + 8004f92: 2501 movs r5, #1 + 8004f94: 426d negs r5, r5 + 8004f96: 0028 movs r0, r5 + 8004f98: bd70 pop {r4, r5, r6, pc} + 8004f9a: 46c0 nop ; (mov r8, r8) + 8004f9c: 200000ec .word 0x200000ec + +08004fa0 <_malloc_r>: + 8004fa0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8004fa2: 2203 movs r2, #3 + 8004fa4: 1ccb adds r3, r1, #3 + 8004fa6: 4393 bics r3, r2 + 8004fa8: 3308 adds r3, #8 + 8004faa: 0006 movs r6, r0 + 8004fac: 001f movs r7, r3 + 8004fae: 2b0c cmp r3, #12 + 8004fb0: d238 bcs.n 8005024 <_malloc_r+0x84> + 8004fb2: 270c movs r7, #12 + 8004fb4: 42b9 cmp r1, r7 + 8004fb6: d837 bhi.n 8005028 <_malloc_r+0x88> + 8004fb8: 0030 movs r0, r6 + 8004fba: f000 f873 bl 80050a4 <__malloc_lock> + 8004fbe: 4b38 ldr r3, [pc, #224] ; (80050a0 <_malloc_r+0x100>) + 8004fc0: 9300 str r3, [sp, #0] + 8004fc2: 681b ldr r3, [r3, #0] + 8004fc4: 001c movs r4, r3 + 8004fc6: 2c00 cmp r4, #0 + 8004fc8: d133 bne.n 8005032 <_malloc_r+0x92> + 8004fca: 0039 movs r1, r7 + 8004fcc: 0030 movs r0, r6 + 8004fce: f7ff ffc5 bl 8004f5c + 8004fd2: 0004 movs r4, r0 + 8004fd4: 1c43 adds r3, r0, #1 + 8004fd6: d15e bne.n 8005096 <_malloc_r+0xf6> + 8004fd8: 9b00 ldr r3, [sp, #0] + 8004fda: 681c ldr r4, [r3, #0] + 8004fdc: 0025 movs r5, r4 + 8004fde: 2d00 cmp r5, #0 + 8004fe0: d14e bne.n 8005080 <_malloc_r+0xe0> + 8004fe2: 2c00 cmp r4, #0 + 8004fe4: d051 beq.n 800508a <_malloc_r+0xea> + 8004fe6: 6823 ldr r3, [r4, #0] + 8004fe8: 0029 movs r1, r5 + 8004fea: 18e3 adds r3, r4, r3 + 8004fec: 0030 movs r0, r6 + 8004fee: 9301 str r3, [sp, #4] + 8004ff0: f000 f870 bl 80050d4 <_sbrk_r> + 8004ff4: 9b01 ldr r3, [sp, #4] + 8004ff6: 4283 cmp r3, r0 + 8004ff8: d147 bne.n 800508a <_malloc_r+0xea> + 8004ffa: 6823 ldr r3, [r4, #0] + 8004ffc: 0030 movs r0, r6 + 8004ffe: 1aff subs r7, r7, r3 + 8005000: 0039 movs r1, r7 + 8005002: f7ff ffab bl 8004f5c + 8005006: 3001 adds r0, #1 + 8005008: d03f beq.n 800508a <_malloc_r+0xea> + 800500a: 6823 ldr r3, [r4, #0] + 800500c: 19db adds r3, r3, r7 + 800500e: 6023 str r3, [r4, #0] + 8005010: 9b00 ldr r3, [sp, #0] + 8005012: 681b ldr r3, [r3, #0] + 8005014: 2b00 cmp r3, #0 + 8005016: d040 beq.n 800509a <_malloc_r+0xfa> + 8005018: 685a ldr r2, [r3, #4] + 800501a: 42a2 cmp r2, r4 + 800501c: d133 bne.n 8005086 <_malloc_r+0xe6> + 800501e: 2200 movs r2, #0 + 8005020: 605a str r2, [r3, #4] + 8005022: e014 b.n 800504e <_malloc_r+0xae> + 8005024: 2b00 cmp r3, #0 + 8005026: dac5 bge.n 8004fb4 <_malloc_r+0x14> + 8005028: 230c movs r3, #12 + 800502a: 2500 movs r5, #0 + 800502c: 6033 str r3, [r6, #0] + 800502e: 0028 movs r0, r5 + 8005030: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} + 8005032: 6821 ldr r1, [r4, #0] + 8005034: 1bc9 subs r1, r1, r7 + 8005036: d420 bmi.n 800507a <_malloc_r+0xda> + 8005038: 290b cmp r1, #11 + 800503a: d918 bls.n 800506e <_malloc_r+0xce> + 800503c: 19e2 adds r2, r4, r7 + 800503e: 6027 str r7, [r4, #0] + 8005040: 42a3 cmp r3, r4 + 8005042: d112 bne.n 800506a <_malloc_r+0xca> + 8005044: 9b00 ldr r3, [sp, #0] + 8005046: 601a str r2, [r3, #0] + 8005048: 6863 ldr r3, [r4, #4] + 800504a: 6011 str r1, [r2, #0] + 800504c: 6053 str r3, [r2, #4] + 800504e: 0030 movs r0, r6 + 8005050: 0025 movs r5, r4 + 8005052: f000 f82f bl 80050b4 <__malloc_unlock> + 8005056: 2207 movs r2, #7 + 8005058: 350b adds r5, #11 + 800505a: 1d23 adds r3, r4, #4 + 800505c: 4395 bics r5, r2 + 800505e: 1aea subs r2, r5, r3 + 8005060: 429d cmp r5, r3 + 8005062: d0e4 beq.n 800502e <_malloc_r+0x8e> + 8005064: 1b5b subs r3, r3, r5 + 8005066: 50a3 str r3, [r4, r2] + 8005068: e7e1 b.n 800502e <_malloc_r+0x8e> + 800506a: 605a str r2, [r3, #4] + 800506c: e7ec b.n 8005048 <_malloc_r+0xa8> + 800506e: 6862 ldr r2, [r4, #4] + 8005070: 42a3 cmp r3, r4 + 8005072: d1d5 bne.n 8005020 <_malloc_r+0x80> + 8005074: 9b00 ldr r3, [sp, #0] + 8005076: 601a str r2, [r3, #0] + 8005078: e7e9 b.n 800504e <_malloc_r+0xae> + 800507a: 0023 movs r3, r4 + 800507c: 6864 ldr r4, [r4, #4] + 800507e: e7a2 b.n 8004fc6 <_malloc_r+0x26> + 8005080: 002c movs r4, r5 + 8005082: 686d ldr r5, [r5, #4] + 8005084: e7ab b.n 8004fde <_malloc_r+0x3e> + 8005086: 0013 movs r3, r2 + 8005088: e7c4 b.n 8005014 <_malloc_r+0x74> + 800508a: 230c movs r3, #12 + 800508c: 0030 movs r0, r6 + 800508e: 6033 str r3, [r6, #0] + 8005090: f000 f810 bl 80050b4 <__malloc_unlock> + 8005094: e7cb b.n 800502e <_malloc_r+0x8e> + 8005096: 6027 str r7, [r4, #0] + 8005098: e7d9 b.n 800504e <_malloc_r+0xae> + 800509a: 605b str r3, [r3, #4] + 800509c: deff udf #255 ; 0xff + 800509e: 46c0 nop ; (mov r8, r8) + 80050a0: 200000e8 .word 0x200000e8 + +080050a4 <__malloc_lock>: + 80050a4: b510 push {r4, lr} + 80050a6: 4802 ldr r0, [pc, #8] ; (80050b0 <__malloc_lock+0xc>) + 80050a8: f000 f850 bl 800514c <__retarget_lock_acquire_recursive> + 80050ac: bd10 pop {r4, pc} + 80050ae: 46c0 nop ; (mov r8, r8) + 80050b0: 2000022c .word 0x2000022c + +080050b4 <__malloc_unlock>: + 80050b4: b510 push {r4, lr} + 80050b6: 4802 ldr r0, [pc, #8] ; (80050c0 <__malloc_unlock+0xc>) + 80050b8: f000 f849 bl 800514e <__retarget_lock_release_recursive> + 80050bc: bd10 pop {r4, pc} + 80050be: 46c0 nop ; (mov r8, r8) + 80050c0: 2000022c .word 0x2000022c + +080050c4 : + 80050c4: 0003 movs r3, r0 + 80050c6: 1882 adds r2, r0, r2 + 80050c8: 4293 cmp r3, r2 + 80050ca: d100 bne.n 80050ce + 80050cc: 4770 bx lr + 80050ce: 7019 strb r1, [r3, #0] + 80050d0: 3301 adds r3, #1 + 80050d2: e7f9 b.n 80050c8 + +080050d4 <_sbrk_r>: + 80050d4: 2300 movs r3, #0 + 80050d6: b570 push {r4, r5, r6, lr} + 80050d8: 4d06 ldr r5, [pc, #24] ; (80050f4 <_sbrk_r+0x20>) + 80050da: 0004 movs r4, r0 + 80050dc: 0008 movs r0, r1 + 80050de: 602b str r3, [r5, #0] + 80050e0: f7fb fd3e bl 8000b60 <_sbrk> + 80050e4: 1c43 adds r3, r0, #1 + 80050e6: d103 bne.n 80050f0 <_sbrk_r+0x1c> + 80050e8: 682b ldr r3, [r5, #0] + 80050ea: 2b00 cmp r3, #0 + 80050ec: d000 beq.n 80050f0 <_sbrk_r+0x1c> + 80050ee: 6023 str r3, [r4, #0] + 80050f0: bd70 pop {r4, r5, r6, pc} + 80050f2: 46c0 nop ; (mov r8, r8) + 80050f4: 20000228 .word 0x20000228 + +080050f8 <__errno>: + 80050f8: 4b01 ldr r3, [pc, #4] ; (8005100 <__errno+0x8>) + 80050fa: 6818 ldr r0, [r3, #0] + 80050fc: 4770 bx lr + 80050fe: 46c0 nop ; (mov r8, r8) + 8005100: 20000058 .word 0x20000058 + +08005104 <__libc_init_array>: + 8005104: b570 push {r4, r5, r6, lr} + 8005106: 2600 movs r6, #0 + 8005108: 4c0c ldr r4, [pc, #48] ; (800513c <__libc_init_array+0x38>) + 800510a: 4d0d ldr r5, [pc, #52] ; (8005140 <__libc_init_array+0x3c>) + 800510c: 1b64 subs r4, r4, r5 + 800510e: 10a4 asrs r4, r4, #2 + 8005110: 42a6 cmp r6, r4 + 8005112: d109 bne.n 8005128 <__libc_init_array+0x24> + 8005114: 2600 movs r6, #0 + 8005116: f000 f81b bl 8005150 <_init> + 800511a: 4c0a ldr r4, [pc, #40] ; (8005144 <__libc_init_array+0x40>) + 800511c: 4d0a ldr r5, [pc, #40] ; (8005148 <__libc_init_array+0x44>) + 800511e: 1b64 subs r4, r4, r5 + 8005120: 10a4 asrs r4, r4, #2 + 8005122: 42a6 cmp r6, r4 + 8005124: d105 bne.n 8005132 <__libc_init_array+0x2e> + 8005126: bd70 pop {r4, r5, r6, pc} + 8005128: 00b3 lsls r3, r6, #2 + 800512a: 58eb ldr r3, [r5, r3] + 800512c: 4798 blx r3 + 800512e: 3601 adds r6, #1 + 8005130: e7ee b.n 8005110 <__libc_init_array+0xc> + 8005132: 00b3 lsls r3, r6, #2 + 8005134: 58eb ldr r3, [r5, r3] + 8005136: 4798 blx r3 + 8005138: 3601 adds r6, #1 + 800513a: e7f2 b.n 8005122 <__libc_init_array+0x1e> + 800513c: 080051a8 .word 0x080051a8 + 8005140: 080051a8 .word 0x080051a8 + 8005144: 080051ac .word 0x080051ac + 8005148: 080051a8 .word 0x080051a8 + +0800514c <__retarget_lock_acquire_recursive>: + 800514c: 4770 bx lr + +0800514e <__retarget_lock_release_recursive>: + 800514e: 4770 bx lr + +08005150 <_init>: + 8005150: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005152: 46c0 nop ; (mov r8, r8) + 8005154: bcf8 pop {r3, r4, r5, r6, r7} + 8005156: bc08 pop {r3} + 8005158: 469e mov lr, r3 + 800515a: 4770 bx lr + +0800515c <_fini>: + 800515c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800515e: 46c0 nop ; (mov r8, r8) + 8005160: bcf8 pop {r3, r4, r5, r6, r7} + 8005162: bc08 pop {r3} + 8005164: 469e mov lr, r3 + 8005166: 4770 bx lr diff --git a/science-spectral/Debug/science-spectral.map b/science-spectral/Debug/science-spectral.map new file mode 100644 index 000000000..23bd6ea4e --- /dev/null +++ b/science-spectral/Debug/science-spectral.map @@ -0,0 +1,3968 @@ +Archive member included to satisfy reference by file (symbol) + +C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (exit) 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./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.o +LOAD ./Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.o +START GROUP +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libstdc++_nano.a +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libsupc++_nano.a +END GROUP +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libstdc++_nano.a +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +START GROUP +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v6-m/nofp/crtend.o +LOAD C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v6-m/nofp/crtn.o + 0x0000000020024000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0xbc + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0xbc ./Core/Startup/startup_stm32g0b1retx.o + 0x0000000008000000 g_pfnVectors + 0x00000000080000bc . = ALIGN (0x4) + +.text 0x00000000080000bc 0x50ac + 0x00000000080000bc . = ALIGN (0x4) + *(.text) + .text 0x00000000080000bc 0x48 C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x0000000008000104 0x114 C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + 0x0000000008000104 __aeabi_uidiv + 0x0000000008000104 __udivsi3 + 0x0000000008000210 __aeabi_uidivmod + .text 0x0000000008000218 0x4 C:/ST/STM32CubeIDE_1.13.2/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.1.202309131626/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + 0x0000000008000218 __aeabi_idiv0 + 0x0000000008000218 __aeabi_ldiv0 + *(.text*) + .text.main 0x000000000800021c 0xa4 ./Core/Src/main.o + 0x000000000800021c main + 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a/science-spectral/Debug/sources.mk b/science-spectral/Debug/sources.mk new file mode 100644 index 000000000..a788aa2d5 --- /dev/null +++ b/science-spectral/Debug/sources.mk @@ -0,0 +1,38 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +ELF_SRCS := +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +S_SRCS := +CC_SRCS := +C_SRCS := +CPP_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +OBJDUMP_LIST := +C_UPPER_DEPS := +S_DEPS := +C_DEPS := +CC_DEPS := +SIZE_OUTPUT := +C++_DEPS := +SU_FILES := +EXECUTABLES := +OBJS := +CXX_DEPS := +MAP_FILES := +S_UPPER_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32G0xx_HAL_Driver/Src \ + diff --git a/scripts/build_dawn.sh b/scripts/build_dawn.sh index 11b6fd517..0fdfefd49 100755 --- a/scripts/build_dawn.sh +++ b/scripts/build_dawn.sh @@ -16,5 +16,9 @@ CC=clang CXX=clang++ cmake \ -D TINT_BUILD_DOCS=OFF \ -D TINT_BUILD_TESTS=OFF \ -D DAWN_ENABLE_INSTALL=ON \ - -D BUILD_SHARED_LIBS=ON + -D BUILD_SHARED_LIBS=ON \ + -D DAWN_USE_GLFW=OFF \ + -D TINT_BUILD_CMD_TOOLS=OFF \ + -D TINT_BUILD_DOCS=OFF \ + -D TINT_BUILD_TESTS=OFF cmake --build out/Release diff --git a/scripts/build_teleop_stream_client.sh b/scripts/build_teleop_stream_client.sh new file mode 100755 index 000000000..8faa444fc --- /dev/null +++ b/scripts/build_teleop_stream_client.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +source deps/emsdk/emsdk_env.sh +emcmake cmake -B src/teleoperation/streaming/embuild -G Ninja -DCMAKE_BUILD_TYPE=Release src/teleoperation/streaming/ +cmake --build src/teleoperation/streaming/embuild diff --git a/scripts/debug_arm_ik.py b/scripts/debug_arm_ik.py index a72e0dafd..4757343cc 100755 --- a/scripts/debug_arm_ik.py +++ b/scripts/debug_arm_ik.py @@ -11,20 +11,24 @@ rospy.sleep(1.0) - pub.publish(IK(pose=Pose( - position=Point(x=0.5, y=0.5, z=0.5), - orientation=Quaternion(x=0.0, y=0.0, z=0.0, w=1.0), - ))) - + pub.publish( + IK( + pose=Pose( + position=Point(x=0.5, y=0.5, z=0.5), + orientation=Quaternion(x=0.0, y=0.0, z=0.0, w=1.0), + ) + ) + ) def on_clicked_point(clicked_point: PointStamped): - ik = IK(pose=Pose( - position=clicked_point.point, - orientation=Quaternion(x=0.0, y=0.0, z=0.0, w=1.0), - )) + ik = IK( + pose=Pose( + position=clicked_point.point, + orientation=Quaternion(x=0.0, y=0.0, z=0.0, w=1.0), + ) + ) pub.publish(ik) - sub = rospy.Subscriber("clicked_point", PointStamped, on_clicked_point) - rospy.spin() \ No newline at end of file + rospy.spin() diff --git a/scripts/debug_course_publisher.py b/scripts/debug_course_publisher.py index 42ad39e19..ff5b34384 100755 --- a/scripts/debug_course_publisher.py +++ b/scripts/debug_course_publisher.py @@ -16,18 +16,22 @@ if __name__ == "__main__": rospy.init_node("debug_course_publisher") - publish_waypoints([convert_waypoint_to_gps(waypoint) for waypoint in [ - ( - Waypoint(tag_id=0, type=WaypointType(val=WaypointType.NO_SEARCH)), - # SE3(position=np.array([-844.37, 10351.56, 0])), - SE3(position=np.array([-30, -15, 0])), - )#, - # ( - # Waypoint(tag_id=0, type=WaypointType(val=WaypointType.POST)), - # SE3(position=np.array([-2, -2, 0])), - # ), - # ( - # Waypoint(tag_id=1, type=WaypointType(val=WaypointType.POST)), - # SE3(position=np.array([11, -10, 0])), - # ) - ]]) + publish_waypoints( + [ + convert_waypoint_to_gps(waypoint) + for waypoint in [ + ( + Waypoint(tag_id=0, type=WaypointType(val=WaypointType.NO_SEARCH)), + SE3(position=np.array([4, 4, 0])), + ), + ( + Waypoint(tag_id=0, type=WaypointType(val=WaypointType.POST)), + SE3(position=np.array([-2, -2, 0])), + ), + ( + Waypoint(tag_id=1, type=WaypointType(val=WaypointType.POST)), + SE3(position=np.array([11, -10, 0])), + ), + ] + ] + ) diff --git a/scripts/debug_disable_auton.py b/scripts/debug_disable_auton.py index c8e76080d..84bb4ae2d 100755 --- a/scripts/debug_disable_auton.py +++ b/scripts/debug_disable_auton.py @@ -3,8 +3,7 @@ import numpy as np import rospy -from mrover.msg import EnableAuton -from mrover.srv import PublishEnableAuton +from mrover.srv import EnableAuton from util.course_publish_helpers import publish_waypoints @@ -19,8 +18,7 @@ rospy.init_node("debug_disable_auton") rospy.wait_for_service("enable_auton") try: - publish_enable = rospy.ServiceProxy("enable_auton", PublishEnableAuton) - msg = EnableAuton([], False) - publish_enable(msg) + publish_enable = rospy.ServiceProxy("enable_auton", EnableAuton) + publish_enable(False, []) except rospy.ServiceException as e: print(f"Service call failed: {e}") diff --git a/scripts/debug_service.py b/scripts/debug_service.py index 136329ac3..ce2b7d761 100755 --- a/scripts/debug_service.py +++ b/scripts/debug_service.py @@ -6,16 +6,16 @@ from typing import Any import rospy -from mrover.srv import EnableAuton, EnableAutonResponse +from std_srvs.srv import SetBool, SetBoolResponse # Change these values for the service name and type definition to test different values -SERVICE_NAME = "enable_auton" -SERVICE_TYPE = EnableAuton +SERVICE_NAME = "science_enable_heater_b1" +SERVICE_TYPE = SetBool def print_service_request(service_request: Any): rospy.loginfo(service_request) - return EnableAutonResponse(success=True) + return SetBoolResponse(success=True) def main(): diff --git a/scripts/plot_bdcmc_debug_messages.py b/scripts/plot_bdcmc_debug_messages.py new file mode 100644 index 000000000..72937d3c2 --- /dev/null +++ b/scripts/plot_bdcmc_debug_messages.py @@ -0,0 +1,57 @@ +import struct + +import can + +from math import * + +import can +import numpy as np +import pyqtgraph as pg +from pyqtgraph.Qt import QtCore + +if __name__ == "__main__": + app = pg.mkQApp() + + win = pg.GraphicsLayoutWidget(show=True, title="Basic plotting examples") + + win.setWindowTitle("Live Graph") + + pg.setConfigOptions(antialias=True) + + plot = win.addPlot() + curve1 = plot.plot(pen="b") + # curve2 = plot.plot(pen='g') + # curve3 = plot.plot(pen='r') + + plot.enableAutoRange("xy", True) + plot.setYRange(0, 1 << 14) + + xs = np.zeros(40) + ys = np.zeros((40, 4)) + + with can.interface.Bus(channel="vcan0", interface="socketcan", fd=True) as bus: + + def update(): + message = bus.recv() + # unpack message id as signed short + message_id = message.data[16] + + if message_id == 1: + global xs + global ys + + xs = np.roll(xs, -1) + ys = np.roll(ys, -1, axis=0) + + xs[-1] = message.timestamp + ys[-1] = np.array(struct.unpack("ffff", message.data[0:16])) + + curve1.setData(xs, ys[:, 0]) + # curve2.setData(xs, ys[:, 1]) + # curve3.setData(xs, ys[:, 2]) + + timer = QtCore.QTimer() + timer.timeout.connect(update) + timer.start(0) + + pg.exec() diff --git a/scripts/ros_env.sh b/scripts/ros_env.sh index 8254c7dda..5f1b262c3 100644 --- a/scripts/ros_env.sh +++ b/scripts/ros_env.sh @@ -1 +1 @@ -. /opt/ros/noetic/setup.sh && . ~/catkin_ws/devel/setup.sh \ No newline at end of file +source /opt/ros/noetic/setup.sh && source ~/catkin_ws/devel/setup.sh \ No newline at end of file diff --git a/scripts/toggle_basestation_networking b/scripts/toggle_basestation_networking new file mode 100755 index 000000000..e4f1447b0 --- /dev/null +++ b/scripts/toggle_basestation_networking @@ -0,0 +1,20 @@ +# !/usr/bin/env zsh + +# Script to add or remove ROS basestation networking script from bashrc +# TODO: make this work for bash and other catkin workspace locations + +CATKIN_WORKSPACE_PATH=~/catkin_ws +network_script_path="${CATKIN_WORKSPACE_PATH}/src/mrover/ansible/roles/basestation_networks/files/networking_setup_basestation" +enable_message="Basestation network setup enabled, disable with scripts/toggle_basestation_networking" + +if grep -q "source ${network_script_path}" ~/.zshrc; then + echo "Removing basestation networking script from .zshrc" + sed -i '/source ~\/catkin_ws\/src\/mrover\/ansible\/roles\/basestation_networks\/files\/networking_setup_basestation.sh/d' ~/.zshrc +else + echo "Adding basestation networking script to .zshrc" + if [[ $(tail -c1 ~/.zshrc | wc -l) -eq 0 ]]; then + echo "\n" >> ~/.zshrc + fi + echo "echo '${enable_message}'" >> ~/.zshrc + echo "source ${network_script_path}" >> ~/.zshrc +fi diff --git a/src/esw/arduino_led_hw_bridge.py b/src/esw/arduino_led_hw_bridge.py new file mode 100755 index 000000000..b8e456c0b --- /dev/null +++ b/src/esw/arduino_led_hw_bridge.py @@ -0,0 +1,145 @@ +#!/usr/bin/env python3 +import rospy +import serial +import threading + +from mrover.msg import LED + + +class LedBridge: + """ + A class that keeps track of the Auton LED color and updates as necessary over serial. + """ + + # Number of seconds for the entire flashing period. + BLINKING_PERIOD_S = 2 + + # Number of seconds the LED should be flashing for each period. + BLINKING_ON_S = 1 + + # Ideally, SLEEP_AMOUNT divides BLINKING_PERIOD_S and BLINKING_ON_S cleanly to avoid slop. + SLEEP_AMOUNT = 1 + + # The color of the LED. + _color: str + + # A counter for flashing, in seconds. + _blinking_counter_s: int + _is_blinking: bool + + # A serial connection to the Arduino. + _ser: serial.Serial + + _prev_color: LED + + def __init__(self, port: str, baud: int): + """ + :param port: port for the serial connection + :param baud: baud rate for the serial connection + """ + self._color = b"w" + self._prev_color = LED() + + self._blinking_counter_s = 0 + self._is_blinking = True + + self._ser = serial.Serial(port=port, baudrate=baud) + + def handle_message(self, color: LED) -> None: + if str(self._prev_color) == str(color): + return + + self._prev_color = color + + my_color = "" + + if color.red: + if color.green: + if color.blue: + my_color = b"w" # white - ALL COLORS + else: + my_color = b"n" # brown - n since not blue - red and green + else: + if color.blue: + my_color = b"p" # purple - red and blue + else: + my_color = b"r" + else: + if color.green: + if color.blue: + my_color = b"t" # teal - green and blue + else: + my_color = b"g" # green + else: + if color.blue: + my_color = b"b" # blue + else: + my_color = b"o" # off + + self._color = my_color + + self._is_blinking = color.is_blinking + + # If the desired color is red, blue, or off, then just update: + if not self._is_blinking: + self._update() + + # If the desired color is green, and we previously were not green, then update too. + elif self._is_blinking: + # Set to self.BLINKING_PERIOD_S instead of 0, + # so it just automatically resets at 0 once + # flash_if_blinking() is called. + self._blinking_counter_s = self.BLINKING_PERIOD_S + self._update() + + def _update(self): + """ + Writes to serial to change LED color. + Note: assumes self._color_lock is held! + """ + self._ser.write(self._color) + + def flash_if_blinking(self, event=None): + """ + Flash green if necessary. Function is expected to be called every self.SLEEP_AMOUNT seconds. + """ + if not self._is_blinking: + return + + # Copy the counter. + prev_counter = self._blinking_counter_s + + # Increment the counter however much was slept. + self._blinking_counter_s += self.SLEEP_AMOUNT + + # Switch to green at the end of a period. + if self._blinking_counter_s >= self.BLINKING_PERIOD_S: + self._blinking_counter_s = 0 + self._ser.write(self._color) + + # If we just passed the threshold of BLINKING_ON_S, turn off. + elif prev_counter < self.BLINKING_ON_S <= self._blinking_counter_s: + self._ser.write(b"o") + + +def main(): + rospy.init_node("arduino_led_hw_bridge") + + # read serial connection info from parameter server + port = rospy.get_param("auton_led_driver/port") + baud = rospy.get_param("auton_led_driver/baud") + + # Construct the bridge. + led_bridge = LedBridge(port, baud) + + # Configure subscriber. + rospy.Subscriber("led", LED, led_bridge.handle_message) + + # Sleep indefinitely, flashing if necessary. + rospy.Timer(rospy.Duration(led_bridge.SLEEP_AMOUNT), led_bridge.flash_if_blinking) + + rospy.spin() + + +if __name__ == "__main__": + main() diff --git a/src/esw/arm_hw_bridge/main.cpp b/src/esw/arm_hw_bridge/main.cpp index c8a0c7d8f..7a3762427 100644 --- a/src/esw/arm_hw_bridge/main.cpp +++ b/src/esw/arm_hw_bridge/main.cpp @@ -5,14 +5,14 @@ std::unique_ptr armLaserCanDevice; -bool armLaserCallback(std_srvs::SetBool::Request& req, std_srvs::SetBool::Response& res) { +auto armLaserCallback(std_srvs::SetBool::Request& req, std_srvs::SetBool::Response& res) -> bool { armLaserCanDevice->publish_message(mrover::InBoundPDLBMessage{mrover::ArmLaserCommand{.enable = static_cast(req.data)}}); res.success = true; res.message = "DONE"; return true; } -int main(int argc, char** argv) { +auto main(int argc, char** argv) -> int { // Initialize the ROS node ros::init(argc, argv, "arm_hw_bridge"); ros::NodeHandle nh; diff --git a/src/esw/arm_position_test_bridge/arm_position.cpp b/src/esw/arm_position_test_bridge/arm_position.cpp new file mode 100644 index 000000000..32dc61d23 --- /dev/null +++ b/src/esw/arm_position_test_bridge/arm_position.cpp @@ -0,0 +1,154 @@ +#include "messaging.hpp" +#include "ros/ros.h" +#include "std_srvs/SetBool.h" +#include +#include +#include + +#include +#include +#include + +void sleep(int ms); +void set_arm_position(ros::Publisher& publisher, std::vector positions, int delay); + +std::vector position_data; + +auto arm_position_callback(sensor_msgs::JointState::ConstPtr const& msg) { + ROS_INFO(";)"); + position_data = msg->position; + ROS_INFO("hey"); +} + +void reset_pos(ros::Publisher armPublisher, int delay) { + set_arm_position(armPublisher, {0, 0, 0, 0, 0, 0, 0}, delay); +} + +void de_roll(float position, ros::Publisher armPublisher, int delay = 5000) { + set_arm_position(armPublisher, {0, 0, 0, 0, 0, position, 0}, delay); + ROS_INFO("Joint_DE_ROLL: %f", position_data[4]); + reset_pos(armPublisher, delay); +} + +void de_pitch(float position, ros::Publisher armPublisher, int delay = 5000) { + set_arm_position(armPublisher, {0, 0, 0, position, 0, 0, 0}, delay); + ROS_INFO("Joint_DE_PITCH: %f", position_data[3]); + reset_pos(armPublisher, delay); +} + +auto main(int argc, char** argv) -> int { + // Delay between operations + int delay = 5000; + position_data.resize(7); + + ros::init(argc, argv, "arm_position_test_bridge"); + ros::NodeHandle nh; + ros::Rate rate(10); + + ros::Publisher armPublisher = nh.advertise("arm_position_cmd", 1); + ros::Subscriber armSubscriber = nh.subscribe("arm_joint_data", 10, arm_position_callback); + + while (ros::ok()) { + /* Arm Position Test */ + ROS_INFO("****BEGIN BASIC AUTON ARM POSITION TEST****"); + + + // ROS_INFO("MOVE A"); + + // set_arm_position(armPublisher, {0.4, 0, 0, 0, 0, 0, 0}, delay); + // ROS_INFO("Joint_A: %f", position_data[0]); + //reset_pos(armPublisher, delay); + + // Test forwards limit switch + //set_arm_position(armPublisher, {1, 0, 0, 0, 0, 0, 0}, delay); + //ROS_INFO("Joint_A: %f", position_data[0]); + //reset_pos(armPublisher, delay); + + // Test backwards limit switch + //set_arm_position(armPublisher, {-0.4, 0, 0, 0, 0, 0, 0}, delay); + //ROS_INFO("Joint_A: %f", position_data[0]); + //reset_pos(armPublisher, delay); + + + // ROS_INFO("MOVE B"); + // set_arm_position(armPublisher, {0, -0.70, 0, 0, 0, 0, 0}, delay); + // ROS_INFO("Joint_B: %f", position_data[1]); + // reset_pos(armPublisher, delay); + + ROS_INFO("MOVE C"); + set_arm_position(armPublisher, {0, 0, 2, 0, 0, 0, 0}, delay); + ROS_INFO("Joint_C: %f", position_data[2]); + reset_pos(armPublisher, delay); + + // set_arm_position(armPublisher, {0, 0, 1.7, 0, 0, 0, 0}, delay); + // ROS_INFO("Joint_C: %f", position_data[2]); + // reset_pos(armPublisher, delay); + + // ROS_INFO("MOVE DE PITCH"); + // float test_de_pitch_positions[4] = {2.35, -2.35, 1.17, -1.17}; + // for(float value : test_de_pitch_positions) { + // de_pitch(value, armPublisher); + // } + + // ROS_INFO("MOVE DE ROLL"); + // float test_de_roll_positions[4] = {6.28, -6.28, 3.14, -3.14}; + // for(float value : test_de_roll_positions){ + // de_roll(value, armPublisher); + // } + ROS_INFO("****END BASIC ARM POSITION TEST****"); + // ROS_INFO("****BEGIN COMPLEX AUTON ARM POSITION TEST****"); + + // ROS_INFO("BOTH DE"); + // for(int i = 0; i < 4; i++){ + // set_arm_position(armPublisher, {0,0,0,0,test_de_pitch_positions[i],test_de_roll_positions[i],0}, delay); + // ROS_INFO("Joint_DE_ROLL: %f", position_data[4]); + // ROS_INFO("Joint_DE_PITCH: %f", position_data[3]); + // reset_pos(armPublisher, delay); + // } + + // // Joint A: [0.0, 1.0] + // // Joint B: [-0.78540, 0.0] + // // Joint C: [-2.094, 1.745] 220 degrees of motion + // // Joint DE-Pitch: [-2.268, 2.268] + // // Joint DE-Roll: [-inf,inf] + // ROS_INFO("A,B,C"); + // //min position + // set_arm_position(armPublisher, {0,-0.78,-2.0,0,0,0,0}, delay); + // ROS_INFO("Joint_A: %f", position_data[0]); + // ROS_INFO("Joint_B: %f", position_data[1]); + // ROS_INFO("Joint_C: %f", position_data[2]); + // reset_pos(armPublisher, delay); + + // // max position + // set_arm_position(armPublisher, {0.9,0.0,1.7,0,0,0,0}, delay); + // ROS_INFO("Joint_A: %f", position_data[0]); + // ROS_INFO("Joint_B: %f", position_data[1]); + // ROS_INFO("Joint_C: %f", position_data[2]); + // reset_pos(armPublisher, delay); + + // set_arm_position(armPublisher, {0.3,-0.32,-1.2,0,0,0,0}, delay); + // ROS_INFO("Joint_A: %f", position_data[0]); + // ROS_INFO("Joint_B: %f", position_data[1]); + // ROS_INFO("Joint_C: %f", position_data[2]); + // ROS_INFO("****END COMPLEX AUTON ARM POSITION TEST****"); + } + + return 0; +} + +void sleep(int ms) { + std::this_thread::sleep_for(std::chrono::milliseconds(ms)); +} + +void set_arm_position(ros::Publisher& publisher, std::vector positions, int delay) { + mrover::Position armMsg; + // TODO: figure out how to set allen_key and gripper to nan + armMsg.names = {"joint_a", "joint_b", "joint_c", "joint_de_pitch", "joint_de_roll", "allen_key", "gripper"}; + armMsg.positions = std::move(positions); + ROS_INFO("[0]: %f, [1]: %f, [2]: %f", armMsg.positions[0], armMsg.positions[1], armMsg.positions[2]); + + for (int i = 0; i < delay; i += 50) { + sleep(50); + publisher.publish(armMsg); + } +} diff --git a/src/esw/arm_translator_bridge/arm_translator.cpp b/src/esw/arm_translator_bridge/arm_translator.cpp index 80827be54..058ac7128 100644 --- a/src/esw/arm_translator_bridge/arm_translator.cpp +++ b/src/esw/arm_translator_bridge/arm_translator.cpp @@ -1,28 +1,47 @@ #include "arm_translator.hpp" +#include "joint_de_translation.hpp" +#include "linear_joint_translation.hpp" + +#include +#include + namespace mrover { ArmTranslator::ArmTranslator(ros::NodeHandle& nh) { assert(mJointDEPitchIndex == mJointDE0Index); assert(mJointDERollIndex == mJointDE1Index); assert(mArmHWNames.size() == mRawArmNames.size()); - for (size_t i = 0; i < mRawArmNames.size(); ++i) { + ROS_INFO("hi"); + for (std::size_t i = 0; i < mRawArmNames.size(); ++i) { if (i != mJointDEPitchIndex && i != mJointDERollIndex) { assert(mArmHWNames.at(i) == mRawArmNames.at(i)); } + { + auto rawName = static_cast(mRawArmNames[i]); + [[maybe_unused]] auto [_, was_inserted] = mAdjustServersByRawArmNames.try_emplace(rawName, nh.advertiseService(std::format("{}_adjust", rawName), &ArmTranslator::adjustServiceCallback, this)); + assert(was_inserted); + } + { + auto hwName = static_cast(mArmHWNames[i]); + [[maybe_unused]] auto [_, was_inserted] = mAdjustClientsByArmHWNames.try_emplace(hwName, nh.serviceClient(std::format("{}_adjust", hwName))); + assert(was_inserted); + } } - mJointDEPitchOffset = Radians{getFloatFromRosParam(nh, "joint_de/pitch_offset")}; - mJointDERollOffset = Radians{getFloatFromRosParam(nh, "joint_de/roll_offset")}; + mJointDEPitchOffset = requireParamAsUnit(nh, "joint_de/pitch_offset"); + mJointDERollOffset = requireParamAsUnit(nh, "joint_de/roll_offset"); - mMinRadPerSecDE0 = RadiansPerSecond{getFloatFromRosParam(nh, "brushless_motors/controllers/joint_de_0/min_velocity")}; - mMaxRadPerSecDE0 = RadiansPerSecond{getFloatFromRosParam(nh, "brushless_motors/controllers/joint_de_0/max_velocity")}; - mMinRadPerSecDE1 = RadiansPerSecond{getFloatFromRosParam(nh, "brushless_motors/controllers/joint_de_1/min_velocity")}; - mMaxRadPerSecDE1 = RadiansPerSecond{getFloatFromRosParam(nh, "brushless_motors/controllers/joint_de_1/max_velocity")}; + mMinRadPerSecDE0 = requireParamAsUnit(nh, "brushless_motors/controllers/joint_de_0/min_velocity"); + mMaxRadPerSecDE0 = requireParamAsUnit(nh, "brushless_motors/controllers/joint_de_0/max_velocity"); + mMinRadPerSecDE1 = requireParamAsUnit(nh, "brushless_motors/controllers/joint_de_1/min_velocity"); + mMaxRadPerSecDE1 = requireParamAsUnit(nh, "brushless_motors/controllers/joint_de_1/max_velocity"); mJointDEPitchPosSub = nh.subscribe("joint_de_pitch_raw_position_data", 1, &ArmTranslator::processPitchRawPositionData, this); mJointDERollPosSub = nh.subscribe("joint_de_roll_raw_position_data", 1, &ArmTranslator::processRollRawPositionData, this); + mJointALinMult = requireParamAsUnit(nh, "brushless_motors/controllers/joint_a/rad_to_meters_ratio"); + mThrottleSub = nh.subscribe("arm_throttle_cmd", 1, &ArmTranslator::processThrottleCmd, this); mVelocitySub = nh.subscribe("arm_velocity_cmd", 1, &ArmTranslator::processVelocityCmd, this); mPositionSub = nh.subscribe("arm_position_cmd", 1, &ArmTranslator::processPositionCmd, this); @@ -34,46 +53,60 @@ namespace mrover { mJointDataPub = std::make_unique(nh.advertise("arm_joint_data", 1)); } - void ArmTranslator::clampValues(float& val1, float& val2, float minValue1, float maxValue1, float minValue2, float maxValue2) { - if (val1 < minValue1) { - float const ratio = minValue1 / val1; - val1 *= ratio; - val2 *= ratio; - } - if (maxValue1 < val1) { - float const ratio = maxValue1 / val1; - val1 *= ratio; - val2 *= ratio; - } - if (val2 < minValue2) { - float const ratio = minValue2 / val2; - val1 *= ratio; - val2 *= ratio; - } - if (maxValue2 < val2) { - float const ratio = maxValue2 / val2; - val1 *= ratio; - val2 *= ratio; - } + // void ArmTranslator::clampValues(float& val1, float& val2, float minValue1, float maxValue1, float minValue2, float maxValue2) { + // val1 = (val1 - (-80)) / (maxValue1 - minValue1) * (); + // val2 if (val1 < minValue1) { + // float const ratio = minValue1 / val1; + // val1 *= ratio; + // val2 *= ratio; + // } + // if (maxValue1 < val1) { + // float const ratio = maxValue1 / val1; + // val1 *= ratio; + // val2 *= ratio; + // } + // if (val2 < minValue2) { + // float const ratio = minValue2 / val2; + // val1 *= ratio; + // val2 *= ratio; + // } + // if (maxValue2 < val2) { + // float const ratio = maxValue2 / val2; + // val1 *= ratio; + // val2 *= ratio; + // } + // } + + auto ArmTranslator::mapValue(float& val, float inputMinValue, float inputMaxValue, float outputMinValue, float outputMaxValue) -> void { + val = (val - inputMinValue) / (inputMaxValue - inputMinValue) * (outputMaxValue - outputMinValue) + outputMinValue; } - void ArmTranslator::processThrottleCmd(Throttle::ConstPtr const& msg) { + auto ArmTranslator::processThrottleCmd(Throttle::ConstPtr const& msg) const -> void { if (mRawArmNames != msg->names || mRawArmNames.size() != msg->throttles.size()) { ROS_ERROR("Throttle requests for arm is ignored!"); return; } Throttle throttle = *msg; + ROS_INFO("pitch throttle: %f roll throttle: %f", msg->throttles.at(mJointDEPitchIndex), msg->throttles.at(mJointDERollIndex)); auto [joint_de_0_throttle, joint_de_1_throttle] = transformPitchRollToMotorOutputs( msg->throttles.at(mJointDEPitchIndex), msg->throttles.at(mJointDERollIndex)); - clampValues( + ROS_INFO("pre-mapped values: de_0 %f de_1 %f", joint_de_0_throttle, joint_de_1_throttle); + + mapValue( joint_de_0_throttle, - joint_de_1_throttle, + -80.0f, + 80.0f, -1.0f, - 1.0f, + 1.0f); + + mapValue( + joint_de_1_throttle, + -80.0f, + 80.0f, -1.0f, 1.0f); @@ -82,14 +115,16 @@ namespace mrover { throttle.throttles.at(mJointDEPitchIndex) = joint_de_0_throttle; throttle.throttles.at(mJointDERollIndex) = joint_de_1_throttle; + ROS_INFO("post-mapped values: de_0 %f de_1 %f", joint_de_0_throttle, joint_de_1_throttle); + mThrottlePub->publish(throttle); } - bool ArmTranslator::jointDEIsCalibrated() { + auto ArmTranslator::jointDEIsCalibrated() const -> bool { return mJointDE0PosOffset.has_value() && mJointDE1PosOffset.has_value(); } - void ArmTranslator::updatePositionOffsets() { + auto ArmTranslator::updatePositionOffsets() -> void { if (!mCurrentRawJointDEPitch.has_value() || !mCurrentRawJointDERoll.has_value() || !mCurrentRawJointDE0Position.has_value() || !mCurrentRawJointDE1Position.has_value()) { return; } @@ -103,17 +138,17 @@ namespace mrover { } } - void ArmTranslator::processPitchRawPositionData(std_msgs::Float32::ConstPtr const& msg) { + auto ArmTranslator::processPitchRawPositionData(std_msgs::Float32::ConstPtr const& msg) -> void { mCurrentRawJointDEPitch = Radians{msg->data}; updatePositionOffsets(); } - void ArmTranslator::processRollRawPositionData(std_msgs::Float32::ConstPtr const& msg) { + auto ArmTranslator::processRollRawPositionData(std_msgs::Float32::ConstPtr const& msg) -> void { mCurrentRawJointDERoll = Radians{msg->data}; updatePositionOffsets(); } - void ArmTranslator::processVelocityCmd(Velocity::ConstPtr const& msg) { + auto ArmTranslator::processVelocityCmd(Velocity::ConstPtr const& msg) -> void { if (mRawArmNames != msg->names || mRawArmNames.size() != msg->velocities.size()) { ROS_ERROR("Velocity requests for arm is ignored!"); return; @@ -125,11 +160,17 @@ namespace mrover { msg->velocities.at(mJointDEPitchIndex), msg->velocities.at(mJointDERollIndex)); - clampValues( + mapValue( joint_de_0_vel, + -800.0, + 800.0, + mMinRadPerSecDE1.get(), + mMaxRadPerSecDE1.get()); + + mapValue( joint_de_1_vel, - mMinRadPerSecDE0.get(), - mMaxRadPerSecDE0.get(), + -800.0, + 800.0, mMinRadPerSecDE1.get(), mMaxRadPerSecDE1.get()); @@ -138,11 +179,16 @@ namespace mrover { velocity.velocities.at(mJointDEPitchIndex) = joint_de_0_vel; velocity.velocities.at(mJointDERollIndex) = joint_de_1_vel; + // joint a convert linear velocity (meters/s) to revolution/s + auto joint_a_vel = convertLinVel(msg->velocities.at(mJointAIndex), static_cast(mJointALinMult.get())); + velocity.velocities.at(mJointAIndex) = joint_a_vel; + ROS_INFO("joint a velocity after conversion: %f", joint_a_vel); + mVelocityPub->publish(velocity); } - - void ArmTranslator::processPositionCmd(Position::ConstPtr const& msg) { + auto ArmTranslator::processPositionCmd(Position::ConstPtr const& msg) -> void { + ROS_INFO("msg: %f", msg->positions[0]); if (mRawArmNames != msg->names || mRawArmNames.size() != msg->positions.size()) { ROS_ERROR("Position requests for arm is ignored!"); return; @@ -167,22 +213,31 @@ namespace mrover { position.positions.at(mJointDEPitchIndex) = joint_de_0_pos; position.positions.at(mJointDERollIndex) = joint_de_1_pos; + // joint a convert linear position (meters) to radians + auto joint_a_pos = convertLinPos(msg->positions.at(mJointAIndex), mJointALinMult.get()); + position.positions.at(mJointAIndex) = joint_a_pos; + mPositionPub->publish(position); } - void ArmTranslator::processArmHWJointData(sensor_msgs::JointState::ConstPtr const& msg) { + auto ArmTranslator::processArmHWJointData(sensor_msgs::JointState::ConstPtr const& msg) -> void { if (mArmHWNames != msg->name || mArmHWNames.size() != msg->position.size() || mArmHWNames.size() != msg->velocity.size() || mArmHWNames.size() != msg->effort.size()) { ROS_ERROR("Forwarding joint data for arm is ignored!"); return; } + // Convert joint state of joint a from radians/revolutions to meters + auto jointALinVel = convertLinVel(static_cast(msg->velocity.at(mJointAIndex)), mJointALinMult.get()); + auto jointALinPos = convertLinPos(static_cast(msg->position.at(mJointAIndex)), mJointALinMult.get()); + + sensor_msgs::JointState jointState = *msg; auto [jointDEPitchVel, jointDERollVel] = transformMotorOutputsToPitchRoll( static_cast(msg->velocity.at(mJointDE0Index)), static_cast(msg->velocity.at(mJointDE1Index))); - auto [jointDEPitchPos, jointDERollPos] = transformMotorOutputsToPitchRoll( + [[maybe_unused]] auto [jointDEPitchPos, jointDERollPos] = transformMotorOutputsToPitchRoll( static_cast(msg->position.at(mJointDE0Index)), static_cast(msg->position.at(mJointDE1Index))); @@ -202,8 +257,62 @@ namespace mrover { jointState.effort.at(mJointDE0Index) = jointDEPitchEff; jointState.effort.at(mJointDE1Index) = jointDERollEff; + jointState.velocity.at(mJointAIndex) = jointALinVel; + jointState.position.at(mJointAIndex) = jointALinPos; + mJointDataPub->publish(jointState); } + auto ArmTranslator::adjustServiceCallback(AdjustMotor::Request& req, AdjustMotor::Response& res) -> bool { + + if (req.name == "joint_de_roll") { + mJointDERollAdjust = req.value; + } else if (req.name == "joint_de_pitch") { + mJointDEPitchAdjust = req.value; + } else if (req.name == "joint_a") { + AdjustMotor::Request controllerReq; + AdjustMotor::Response controllerRes = res; + controllerReq.value = convertLinPos(static_cast(req.value), mJointALinMult.get()); + + mAdjustClientsByArmHWNames[req.name].call(controllerReq, controllerRes); + res.success = controllerRes.success; + } else { + AdjustMotor::Request controllerReq = req; + AdjustMotor::Response controllerRes = res; + mAdjustClientsByArmHWNames[req.name].call(controllerReq, controllerRes); + res.success = controllerRes.success; + } + + if (mJointDEPitchAdjust && mJointDERollAdjust) { + // convert DE_roll and DE_pitch into DE_0 and DE_1 (outgoing message to arm_hw_bridge) + auto [joint_de_0_raw_value, joint_de_1_raw_value] = transformPitchRollToMotorOutputs( + mJointDEPitchAdjust.value(), + mJointDERollAdjust.value()); + mJointDEPitchAdjust = std::nullopt; + mJointDERollAdjust = std::nullopt; + + float joint_de_0_value = joint_de_0_raw_value + mJointDE0PosOffset->get(); + float joint_de_1_value = joint_de_1_raw_value + mJointDE1PosOffset->get(); + + AdjustMotor::Response controllerResDE0; + AdjustMotor::Request controllerReqDE0; + controllerReqDE0.name = "joint_de_0"; + controllerReqDE0.value = joint_de_0_value; + mAdjustClientsByArmHWNames[controllerReqDE0.name].call(controllerResDE0, controllerReqDE0); + + AdjustMotor::Response controllerResDE1; + AdjustMotor::Request controllerReqDE1; + controllerReqDE1.name = "joint_de_1"; + controllerReqDE1.value = joint_de_1_value; + mAdjustClientsByArmHWNames[controllerReqDE1.name].call(controllerReqDE1, controllerResDE1); + + res.success = controllerResDE0.success && controllerResDE1.success; + } else { + // adjust service was for de, but both de joints have not adjusted yet + res.success = false; + } + return true; + } + -} // namespace mrover +} // namespace mrover \ No newline at end of file diff --git a/src/esw/arm_translator_bridge/arm_translator.hpp b/src/esw/arm_translator_bridge/arm_translator.hpp index d69d6d1b5..14beae37e 100644 --- a/src/esw/arm_translator_bridge/arm_translator.hpp +++ b/src/esw/arm_translator_bridge/arm_translator.hpp @@ -1,13 +1,15 @@ #pragma once +#include "joint_de_translation.hpp" +#include "matrix_helper.hpp" + +#include +#include + #include #include -#include "units/units.hpp" - -#include "joint_de_translation.hpp" -#include "matrix_helper.hpp" -#include "read_from_ros_param.hpp" +#include #include #include #include @@ -15,44 +17,52 @@ #include #include +#include +#include + namespace mrover { class ArmTranslator { public: ArmTranslator() = default; - ArmTranslator(ros::NodeHandle& nh); + explicit ArmTranslator(ros::NodeHandle& nh); - void processPitchRawPositionData(std_msgs::Float32::ConstPtr const& msg); + auto processPitchRawPositionData(std_msgs::Float32::ConstPtr const& msg) -> void; - void processRollRawPositionData(std_msgs::Float32::ConstPtr const& msg); + auto processRollRawPositionData(std_msgs::Float32::ConstPtr const& msg) -> void; - void processVelocityCmd(Velocity::ConstPtr const& msg); + auto processVelocityCmd(Velocity::ConstPtr const& msg) -> void; - void processPositionCmd(Position::ConstPtr const& msg); + auto processPositionCmd(Position::ConstPtr const& msg) -> void; - void processArmHWJointData(sensor_msgs::JointState::ConstPtr const& msg); + auto processThrottleCmd(Throttle::ConstPtr const& msg) const -> void; - private: - void processThrottleCmd(Throttle::ConstPtr const& msg); + auto processArmHWJointData(sensor_msgs::JointState::ConstPtr const& msg) -> void; + + auto adjustServiceCallback(AdjustMotor::Request& req, AdjustMotor::Response& res) -> bool; - static void clampValues(float& val1, float& val2, float minValue1, float maxValue1, float minValue2, float maxValue2); + private: + // static void clampValues(float& val1, float& val2, float minValue1, float maxValue1, float minValue2, float maxValue2); + + static void mapValue(float& val, float inputMinValue, float inputMaxValue, float outputMinValue, float outputMaxValue); - bool jointDEIsCalibrated(); + [[nodiscard]] auto jointDEIsCalibrated() const -> bool; - void updatePositionOffsets(); + auto updatePositionOffsets() -> void; - const std::vector mRawArmNames = {"joint_a", "joint_b", "joint_c", "joint_de_pitch", "joint_de_roll", "allen_key", "gripper"}; - const std::vector mArmHWNames = {"joint_a", "joint_b", "joint_c", "joint_de_0", "joint_de_1", "allen_key", "gripper"}; + const std::vector mRawArmNames{"joint_a", "joint_b", "joint_c", "joint_de_pitch", "joint_de_roll", "allen_key", "gripper"}; + const std::vector mArmHWNames{"joint_a", "joint_b", "joint_c", "joint_de_0", "joint_de_1", "allen_key", "gripper"}; std::unique_ptr mThrottlePub; std::unique_ptr mVelocityPub; std::unique_ptr mPositionPub; std::unique_ptr mJointDataPub; - const size_t mJointDEPitchIndex = std::find(mRawArmNames.begin(), mRawArmNames.end(), "joint_de_pitch") - mRawArmNames.begin(); - const size_t mJointDERollIndex = std::find(mRawArmNames.begin(), mRawArmNames.end(), "joint_de_roll") - mRawArmNames.begin(); - const size_t mJointDE0Index = std::find(mArmHWNames.begin(), mArmHWNames.end(), "joint_de_0") - mArmHWNames.begin(); - const size_t mJointDE1Index = std::find(mArmHWNames.begin(), mArmHWNames.end(), "joint_de_1") - mArmHWNames.begin(); + size_t const mJointDEPitchIndex = std::find(mRawArmNames.begin(), mRawArmNames.end(), "joint_de_pitch") - mRawArmNames.begin(); + size_t const mJointDERollIndex = std::find(mRawArmNames.begin(), mRawArmNames.end(), "joint_de_roll") - mRawArmNames.begin(); + size_t const mJointDE0Index = std::find(mArmHWNames.begin(), mArmHWNames.end(), "joint_de_0") - mArmHWNames.begin(); + size_t const mJointDE1Index = std::find(mArmHWNames.begin(), mArmHWNames.end(), "joint_de_1") - mArmHWNames.begin(); + size_t const mJointAIndex = std::find(mArmHWNames.begin(), mArmHWNames.end(), "joint_a") - mArmHWNames.begin(); std::optional mJointDE0PosOffset = Radians{0}; std::optional mJointDE1PosOffset = Radians{0}; @@ -69,6 +79,8 @@ namespace mrover { RadiansPerSecond mMaxRadPerSecDE0{}; RadiansPerSecond mMaxRadPerSecDE1{}; + RadiansPerMeter mJointALinMult{}; // TODO: need to be rev/meter for velocity.... + ros::Subscriber mJointDEPitchPosSub; ros::Subscriber mJointDERollPosSub; @@ -76,6 +88,16 @@ namespace mrover { ros::Subscriber mVelocitySub; ros::Subscriber mPositionSub; ros::Subscriber mArmHWJointDataSub; + + // TODO:(owen) unique_ptr servers? unique_ptr clients? Both? Neither? The world may never know. (try to learn) + std::unordered_map mAdjustServersByRawArmNames; + // std::unordered_map > mCalibrateServer; + + std::unordered_map mAdjustClientsByArmHWNames; + // std::unique_ptr mCalibrateClient; + + std::optional mJointDEPitchAdjust; + std::optional mJointDERollAdjust; }; } // namespace mrover diff --git a/src/esw/arm_translator_bridge/joint_de_translation.hpp b/src/esw/arm_translator_bridge/joint_de_translation.hpp index 12fca6f02..3108c321d 100644 --- a/src/esw/arm_translator_bridge/joint_de_translation.hpp +++ b/src/esw/arm_translator_bridge/joint_de_translation.hpp @@ -10,7 +10,7 @@ namespace mrover { constexpr std::array, 2> CONVERT_MOTORS_TO_PITCH_ROLL_MATRIX = inverseMatrix(CONVERT_PITCH_ROLL_TO_MOTORS_MATRIX); - static std::pair transformMotorOutputsToPitchRoll(float motor_0, float motor_1) { + [[maybe_unused]] static auto transformMotorOutputsToPitchRoll(float motor_0, float motor_1) -> std::pair { std::array motorsVector = {motor_0, motor_1}; @@ -21,7 +21,7 @@ namespace mrover { } // Function to transform coordinates - static std::pair transformPitchRollToMotorOutputs(float pitch, float roll) { + [[maybe_unused]] static auto transformPitchRollToMotorOutputs(float pitch, float roll) -> std::pair { // Create the input vector std::array pitchRollVector = {pitch, roll}; diff --git a/src/esw/arm_translator_bridge/main.cpp b/src/esw/arm_translator_bridge/main.cpp index 442e6fa45..12510baf7 100644 --- a/src/esw/arm_translator_bridge/main.cpp +++ b/src/esw/arm_translator_bridge/main.cpp @@ -1,9 +1,8 @@ #include #include "arm_translator.hpp" -#include -int main(int argc, char** argv) { +auto main(int argc, char** argv) -> int { // Initialize the ROS node ros::init(argc, argv, "arm_translator_bridge"); ros::NodeHandle nh; diff --git a/src/esw/arm_translator_bridge/read_from_ros_param.hpp b/src/esw/arm_translator_bridge/read_from_ros_param.hpp deleted file mode 100644 index 0d45db98d..000000000 --- a/src/esw/arm_translator_bridge/read_from_ros_param.hpp +++ /dev/null @@ -1,17 +0,0 @@ -#pragma once - -#include -#include - -namespace mrover { - - static float getFloatFromRosParam(ros::NodeHandle const& nh, std::string const& paramName) { - XmlRpc::XmlRpcValue rpcValue; - assert(nh.hasParam(paramName)); - nh.getParam(paramName, rpcValue); - assert(rpcValue.getType() == XmlRpc::XmlRpcValue::TypeDouble); - auto value = (float) static_cast(rpcValue); - return value; - } - -} // namespace mrover \ No newline at end of file diff --git a/src/esw/brushed_test_bridge/brushed_test_bridge.cpp b/src/esw/brushed_test_bridge/brushed_test_bridge.cpp index 67b083e3a..5db22b3c2 100644 --- a/src/esw/brushed_test_bridge/brushed_test_bridge.cpp +++ b/src/esw/brushed_test_bridge/brushed_test_bridge.cpp @@ -1,19 +1,33 @@ -#include - #include #include #include +#include + +using namespace mrover; -int main(int argc, char** argv) { +auto main(int argc, char** argv) -> int { ros::init(argc, argv, "brushed_test_bridge"); ros::NodeHandle nh; - auto brushlessController = std::make_unique(nh, "jetson", "devboard"); + auto brushlessController = std::make_unique(nh, "jetson", "joint_b"); + + auto targetPosition = 10_rad; + auto targetVelocity = RadiansPerSecond{0.8}; + Dimensionless targetThrottle = 0.5; + + ros::Timer timer = nh.createTimer(ros::Duration{5}, [&](ros::TimerEvent const&) { + targetPosition *= -1; + targetVelocity *= -1; + targetThrottle *= -1; + ROS_INFO_STREAM(std::format("Target: {}", targetPosition.get())); + }); - ros::Rate rate(1); + ros::Rate rate(100); while (ros::ok()) { - brushlessController->setDesiredThrottle(0.8); + // brushlessController->setDesiredPosition(targetPosition); + // brushlessController->setDesiredVelocity(targetVelocity); + brushlessController->setDesiredThrottle(targetThrottle); rate.sleep(); ros::spinOnce(); } diff --git a/src/esw/brushless_test_bridge/brushless_test_bridge.cpp b/src/esw/brushless_test_bridge/brushless_test_bridge.cpp index 8ce9a7b03..74eabdcfd 100644 --- a/src/esw/brushless_test_bridge/brushless_test_bridge.cpp +++ b/src/esw/brushless_test_bridge/brushless_test_bridge.cpp @@ -1,10 +1,11 @@ +#include #include #include #include #include -int main(int argc, char** argv) { +auto main(int argc, char** argv) -> int { // Initialize the ROS node ros::init(argc, argv, "brushless_test_bridge"); ros::NodeHandle nh; @@ -21,20 +22,46 @@ int main(int argc, char** argv) { // - rosrun mrover can_driver_node _interface:=can0 // - roslaunch brushless_test.launch - auto brushlessController = std::make_unique(nh, "jetson", "devboard"); + // auto brushlessController_de0 = std::make_unique(nh, "jetson", "joint_de_0"); + // auto brushlessController_de1 = std::make_unique(nh, "jetson", "joint_de_1"); + + // fake DE publisher: + + auto DEPub = std::make_unique(nh.advertise("arm_velocity_cmd", 1)); + auto SAPub = std::make_unique(nh.advertise("sa_velocity_cmd", 1)); + + + mrover::Velocity armMsg; + mrover::Velocity saMsg; + armMsg.names = {"joint_a", "joint_b", "joint_c", "joint_de_pitch", "joint_de_roll", "allen_key", "gripper"}; + armMsg.velocities = {0, 0, 0, 20, 20, 0, 0}; + + saMsg.names = {"sa_x", "sa_y", "sa_z", "sampler", "sensor_actuator"}; + saMsg.velocities = {0, 0, 0.07,0, 0}; + + // brushlessController_de0->setStop(); + // brushlessController_de1->setStop(); + + ros::Rate rate{15}; int count = 0; - ros::Rate rate{100}; - std::array positions = {1.0, 2.0, 3.0, 4.0}; - while (ros::ok()) { - // Throttle test - //brushlessController->setDesiredThrottle(mrover::Percent{((float) count) / 500.0}); - //brushlessController->setDesiredVelocity(mrover::RadiansPerSecond{10.0}); - brushlessController->setDesiredPosition(mrover::Radians{positions.at(count / 400)}); + + while(ros::ok()){ + // publish DE velocity: + DEPub->publish(armMsg); + SAPub->publish(saMsg); count++; + + if(count > 100) { + armMsg.velocities[3] *= -1; + armMsg.velocities[4] *= -1; + count = 0; + } + ros::spinOnce(); rate.sleep(); } return EXIT_SUCCESS; } + diff --git a/src/esw/brushless_test_bridge/running_the_test_bridge.md b/src/esw/brushless_test_bridge/running_the_test_bridge.md new file mode 100644 index 000000000..31307c7fc --- /dev/null +++ b/src/esw/brushless_test_bridge/running_the_test_bridge.md @@ -0,0 +1,36 @@ +# Running the test bridge +## Running on your laptop (not on the jetson) + +### Step 1: FDCANUSB configuration +Clone the `fdcanusb` GitHub repo (do this outside of the mrover directory, perhaps in `~/Desktop`):
+`git clone https://github.com/mjbots/fdcanusb.git`
+`cd fdcanusb`
+Build the `fdcanusb_daemon`:
+`cd sw/`
+`g++ -Wall -g -O2 fdcanusb_daemon.cc -o fdcanusb_daemon`
+This step above needs to be done only once. When running the test bridge again (e.g. after reboot of laptop), you only need to do steps 2 onwards.
+### Step 2: CAN interface +Create a new can interface:
+`sudo ip link add dev vcan0 type vcan`
+Set the interface `vcan0` to '`up`'
+`sudo ip link set vcan0 up` +### Step 3: Plug in the moteus +Set up, turn on and plug the moteus in via USB. Wait a few seconds for the fdcanusb to turn on and register, then continue.
+### Step 4: Start the fdcanusb daemon +Run in one terminal window (in the directory `fdcanusb/sw`):
+`./fdcanusb_daemon -F -v /dev/fdcanusb vcan0` + +### Step 5: ROS services +In another terminal window, run:
+`roscore`
+In another terminal window, run:
+`mrover`
+`rosparam load config/esw_devboard.yaml`
+`rosrun mrover can_driver_node _interface:=vcan0`
+ +### Step 6: Test bridge +Make sure all of the other processes are running. Open another window, and run:
+`mrover`
+`catkin build` <-- Re-run this command after making changes, to rebuild the code
+`rosrun mrover brushless_test_bridge`
+^^ Once you have all of the previous set up, you only need to re-run this command. diff --git a/src/esw/cache_bridge/main.cpp b/src/esw/cache_bridge/main.cpp index 69c70d5c2..3e91fa5c4 100644 --- a/src/esw/cache_bridge/main.cpp +++ b/src/esw/cache_bridge/main.cpp @@ -2,7 +2,7 @@ #include -int main(int argc, char** argv) { +auto main(int argc, char** argv) -> int { // Initialize the ROS node ros::init(argc, argv, "cache_bridge"); ros::NodeHandle nh; diff --git a/src/esw/cameras/cameras.cpp b/src/esw/cameras/cameras.cpp deleted file mode 100644 index 0836ba162..000000000 --- a/src/esw/cameras/cameras.cpp +++ /dev/null @@ -1,99 +0,0 @@ -#include -#include - -#include -#include -#include - -#include -#include -#include - -//#include - -int main() { - StreamServer streamServer{"0.0.0.0", 8080}; - - cv::Size size{1280, 720}; - - NvEncoder nvEncoder{size}; - - cv::VideoCapture cap{std::format("v4l2src ! videoconvert ! video/x-raw,width={},height={},format=I420,framerate=10/1 ! appsink", size.width, size.height), cv::CAP_GSTREAMER}; - - // cv::VideoCapture cap{std::format("videotestsrc ! video/x-raw,width={},height={},format=I420,framerate=30/1 ! appsink", size.width, size.height), cv::CAP_GSTREAMER}; - - if (!cap.isOpened()) throw std::runtime_error{"Failed to open capture"}; - - size_t totalSent = 0; - size_t totalFrames = 0; - auto now = std::chrono::high_resolution_clock::now(); - - cv::Mat frameI420; - while (streamServer.m_client->is_open() && cap.read(frameI420)) { - assert(frameI420.type() == CV_8UC1); - - cv::imshow("USB", frameI420); - cv::waitKey(1); - - NvEncoder::BitstreamView view = nvEncoder.feed(frameI420); - std::span span{static_cast(view.lockParams.bitstreamBufferPtr), view.lockParams.bitstreamSizeInBytes}; - streamServer.feed(span); - - totalSent += span.size_bytes(); - totalFrames++; - double MB = totalSent / 1024.0 / 1024.0; - auto elapsed = std::chrono::duration(std::chrono::high_resolution_clock::now() - now); - double MBps = MB / elapsed.count(); - double fps = totalFrames / elapsed.count(); - - std::cout << std::format("MBps: {} FPS: {}\n", MBps, fps); - } - - // static de265_decoder_context* decoder = de265_new_decoder(); - // if (!decoder) return EXIT_FAILURE; - // if (de265_error error = de265_start_worker_threads(decoder, 0); error != DE265_OK) throw std::runtime_error{"Errored starting worker threads"}; - // - // int more = 1; - // while (more) { - // de265_error status = de265_decode(decoder, &more); - // - // if (status == DE265_ERROR_WAITING_FOR_INPUT_DATA) { - // cv::Mat frame; - // cap.read(frame); - // assert(frame.type() == CV_8UC1); - // - // cv::imshow("F", frame); - // cv::waitKey(0); - // - // NvEncoder::BitstreamView view = nvEncoder.feed(frame); - // if (de265_error error = de265_push_data(decoder, view.lockParams.bitstreamBufferPtr, view.lockParams.bitstreamSizeInBytes, clock(), nullptr); error != DE265_OK) { - // throw std::runtime_error{"Errored pushing encoder data"}; - // } - // } - // - // const de265_image* image; - // do { - // image = de265_peek_next_picture(decoder); - // if (image) { - // int width = de265_get_image_width(image, 0); - // int height = de265_get_image_height(image, 0); - // int format = de265_get_chroma_format(image); - // int bpp = de265_get_bits_per_pixel(image, 0); - // - // if (cv::Size{width, height} != size) throw std::runtime_error{"Unexpected image size"}; - // if (format != de265_chroma_420) throw std::runtime_error{"Unsupported chroma format"}; - // if (bpp != 8) throw std::runtime_error{"Unsupported bits per pixel"}; - // - // int ystride; - // auto* y = de265_get_image_plane(image, 0, &ystride); - // cv::Mat Y{height, width, CV_8UC1, (void*) y, static_cast(ystride)}; - // cv::imshow("Y", Y); - // cv::waitKey(1); - // - // de265_release_next_picture(decoder); - // } - // } while (image); - // } - - return EXIT_SUCCESS; -} \ No newline at end of file diff --git a/src/esw/can_driver/can_driver.cpp b/src/esw/can_driver/can_driver.cpp index 8ebd5009a..7b9aa81c2 100644 --- a/src/esw/can_driver/can_driver.cpp +++ b/src/esw/can_driver/can_driver.cpp @@ -2,19 +2,19 @@ namespace mrover { - static int checkSyscallResult(int result) { + static auto checkSyscallResult(int result) -> int { if (result < 0) throw std::system_error{errno, std::generic_category()}; return result; } - static void checkErrorCode(boost::system::error_code const& ec) { + static auto checkErrorCode(boost::system::error_code const& ec) -> void { if (ec.value() == boost::system::errc::success) return; throw std::runtime_error(std::format("Boost failure: {} {}", ec.value(), ec.message())); } - static std::uint8_t nearestFittingFdcanFrameSize(std::size_t size) { + static auto nearestFittingFdcanFrameSize(std::size_t size) -> std::uint8_t { if (size <= 8) return size; if (size <= 12) return 12; if (size <= 16) return 16; @@ -26,7 +26,7 @@ namespace mrover { throw std::runtime_error("Too large!"); } - void CanNodelet::onInit() { + auto CanNodelet::onInit() -> void { try { NODELET_INFO("CAN Node starting..."); @@ -35,8 +35,6 @@ namespace mrover { mInterface = mPnh.param("interface", "can0"); mIsExtendedFrame = mPnh.param("is_extended_frame", true); - mBitrate = static_cast(mPnh.param("bitrate", 500000)); - mBitratePrescaler = static_cast(mPnh.param("bitrate_prescaler", 2)); XmlRpc::XmlRpcValue canDevices; mNh.getParam("can/devices", canDevices); @@ -46,9 +44,8 @@ namespace mrover { auto bus = xmlRpcValueToTypeOrDefault(canDevice, "bus"); - if (std::uint8_t interfaceNumber = mInterface.back() - '0'; bus != interfaceNumber) { - continue; - } + mBus = mInterface.back() - '0'; + if (bus != mBus) continue; assert(canDevice.getType() == XmlRpc::XmlRpcValue::TypeStruct); @@ -75,7 +72,7 @@ namespace mrover { NODELET_WARN("For example before testing the devboard run: \"rosparam load config/esw_devboard.yml\""); } - mCanNetLink = {mInterface, mBitrate, mBitratePrescaler}; + mCanNetLink = CanNetLink{mInterface}; int socketFileDescriptor = setupSocket(); mStream.emplace(mIoService); @@ -94,7 +91,7 @@ namespace mrover { } } - int CanNodelet::setupSocket() const { + auto CanNodelet::setupSocket() const -> int { int socketFd = checkSyscallResult(socket(PF_CAN, SOCK_RAW, CAN_RAW)); NODELET_INFO_STREAM("Opened CAN socket with file descriptor: " << socketFd); @@ -115,7 +112,7 @@ namespace mrover { return socketFd; } - void CanNodelet::readFrameAsync() { // NOLINT(*-no-recursion) + auto CanNodelet::readFrameAsync() -> void { // NOLINT(*-no-recursion) // You would think we would have to read the header first to find the data length (which is not always 64 bytes) and THEN read the data // However socketcan is nice and just requires we read the max length // It then puts the actual length in the header @@ -136,25 +133,25 @@ namespace mrover { }); } - void CanNodelet::frameReadCallback() { // NOLINT(*-no-recursion) - auto rawId = std::bit_cast(mReadFrame.can_id); - auto messageId = std::bit_cast(static_cast(rawId.identifier)); + auto CanNodelet::frameReadCallback() -> void { // NOLINT(*-no-recursion) + auto [identifier, isErrorFrame, isRemoteTransmissionRequest, isExtendedFrame] = std::bit_cast(mReadFrame.can_id); + auto [destination, source, isReplyRequired] = std::bit_cast(static_cast(identifier)); optional_ref sourceDeviceName = mDevices.backward(CanFdAddress{ - .bus = 0, // TODO set correct bus - .id = messageId.source, + .bus = mBus, + .id = source, }); if (!sourceDeviceName) { - NODELET_WARN_STREAM(std::format("Received CAN message on interface {} that had an unknown source ID: {}", mInterface, std::uint8_t{messageId.source})); + NODELET_WARN_STREAM(std::format("Received CAN message on interface {} that had an unknown source ID: {}", mInterface, std::uint8_t{source})); return; } optional_ref destinationDeviceName = mDevices.backward(CanFdAddress{ - .bus = 0, // TODO set correct bus - .id = messageId.destination, + .bus = mBus, + .id = destination, }); if (!destinationDeviceName) { - NODELET_WARN_STREAM(std::format("Received CAN message on interface {} that had an unknown destination ID: {}", mInterface, std::uint8_t{messageId.destination})); + NODELET_WARN_STREAM(std::format("Received CAN message on interface {} that had an unknown destination ID: {}", mInterface, std::uint8_t{destination})); return; } @@ -163,16 +160,10 @@ namespace mrover { msg.destination = destinationDeviceName.value(); msg.data.assign(mReadFrame.data, mReadFrame.data + mReadFrame.len); - ROS_DEBUG_STREAM("Received CAN message:\n" - << msg); - mDevicesPubSub.at(sourceDeviceName.value()).publisher.publish(msg); } - void CanNodelet::frameSendRequestCallback(CAN::ConstPtr const& msg) { - ROS_DEBUG_STREAM("Received request to send CAN message:\n" - << *msg); - + auto CanNodelet::frameSendRequestCallback(CAN::ConstPtr const& msg) -> void { optional_ref source = mDevices.forward(msg->source); if (!source) { NODELET_WARN_STREAM(std::format("Sending CAN message on interface {} that had an unknown source: {}", mInterface, msg->source)); @@ -206,19 +197,15 @@ namespace mrover { written != sizeof(frame)) { NODELET_FATAL_STREAM(std::format("Failed to write CAN frame to socket! Expected to write {} bytes, but only wrote {} bytes", sizeof(frame), written)); ros::shutdown(); - return; } } catch (boost::system::system_error const& error) { // check if ran out of buffer space if (error.code() == boost::asio::error::no_buffer_space) { - NODELET_WARN_STREAM("No buffer space available to send CAN message"); + NODELET_WARN_STREAM_THROTTLE(1, "No buffer space available to send CAN message"); return; - } else { - throw; } + ros::shutdown(); } - - ROS_DEBUG_STREAM("Sent CAN message"); } CanNodelet::~CanNodelet() { diff --git a/src/esw/can_driver/can_driver.hpp b/src/esw/can_driver/can_driver.hpp index 79b557c80..d63d073c4 100644 --- a/src/esw/can_driver/can_driver.hpp +++ b/src/esw/can_driver/can_driver.hpp @@ -53,9 +53,8 @@ namespace mrover { ros::NodeHandle mNh, mPnh; std::string mInterface; + std::uint8_t mBus{}; bool mIsExtendedFrame{}; - std::uint32_t mBitrate{}; - std::uint32_t mBitratePrescaler{}; canfd_frame mReadFrame{}; CanNetLink mCanNetLink; @@ -70,7 +69,7 @@ namespace mrover { mDevices; std::unordered_map mDevicesPubSub; - [[nodiscard]] int setupSocket() const; + [[nodiscard]] auto setupSocket() const -> int; void onInit() override; diff --git a/src/esw/can_driver/can_net_link.cpp b/src/esw/can_driver/can_net_link.cpp index a41c889d6..f85075912 100644 --- a/src/esw/can_driver/can_net_link.cpp +++ b/src/esw/can_driver/can_net_link.cpp @@ -3,7 +3,7 @@ namespace mrover { // TODO(quintin): Either remove bitrate settings or make it work - CanNetLink::CanNetLink(std::string interface, [[maybe_unused]] std::uint32_t bitrate, [[maybe_unused]] std::uint32_t bitrate_prescaler) + CanNetLink::CanNetLink(std::string interface) : mInterface{std::move(interface)} { try { diff --git a/src/esw/can_driver/can_net_link.hpp b/src/esw/can_driver/can_net_link.hpp index d8b990e5d..0630596ac 100644 --- a/src/esw/can_driver/can_net_link.hpp +++ b/src/esw/can_driver/can_net_link.hpp @@ -8,7 +8,7 @@ namespace mrover { CanNetLink() = default; - CanNetLink(std::string, std::uint32_t bitrate, std::uint32_t bitrate_prescaler); + explicit CanNetLink(std::string); CanNetLink(CanNetLink const&) = delete; CanNetLink& operator=(CanNetLink const&) = delete; diff --git a/src/esw/can_driver/main.cpp b/src/esw/can_driver/main.cpp index 42ad6340d..638bc269a 100644 --- a/src/esw/can_driver/main.cpp +++ b/src/esw/can_driver/main.cpp @@ -7,7 +7,7 @@ PLUGINLIB_EXPORT_CLASS(mrover::CanNodelet, nodelet::Nodelet) #else -int main(int argc, char** argv) { +auto main(int argc, char** argv) -> int { ros::init(argc, argv, "can_driver"); // Start the CAN Nodelet diff --git a/src/esw/drive_bridge/main.cpp b/src/esw/drive_bridge/main.cpp index 11ff0c0c9..7a895dd21 100644 --- a/src/esw/drive_bridge/main.cpp +++ b/src/esw/drive_bridge/main.cpp @@ -3,6 +3,7 @@ #include #include +#include using namespace mrover; @@ -11,29 +12,16 @@ void moveDrive(geometry_msgs::Twist::ConstPtr const& msg); std::unique_ptr driveManager; std::vector driveNames{"front_left", "front_right", "middle_left", "middle_right", "back_left", "back_right"}; -std::unordered_map motorMultipliers; // Store the multipliers for each motor - Meters WHEEL_DISTANCE_INNER; Meters WHEEL_DISTANCE_OUTER; compound_unit> WHEEL_LINEAR_TO_ANGULAR; RadiansPerSecond MAX_MOTOR_SPEED; -int main(int argc, char** argv) { +auto main(int argc, char** argv) -> int { // Initialize the ROS node ros::init(argc, argv, "drive_bridge"); ros::NodeHandle nh; - // Load motor multipliers from the ROS parameter server - XmlRpc::XmlRpcValue driveControllers; - assert(nh.hasParam("drive/controllers")); - nh.getParam("drive/controllers", driveControllers); - assert(driveControllers.getType() == XmlRpc::XmlRpcValue::TypeStruct); - for (auto const& driveName: driveNames) { - assert(driveControllers.hasMember(driveName)); - assert(driveControllers[driveName].getType() == XmlRpc::XmlRpcValue::TypeStruct); - motorMultipliers[driveName] = Dimensionless{xmlRpcValueToTypeOrDefault(driveControllers[driveName], "multiplier", 1.0)}; - } - // Load rover dimensions and other parameters from the ROS parameter server auto roverWidth = requireParamAsUnit(nh, "rover/width"); auto roverLength = requireParamAsUnit(nh, "rover/length"); @@ -67,9 +55,9 @@ void moveDrive(geometry_msgs::Twist::ConstPtr const& msg) { auto turn = RadiansPerSecond{msg->angular.z}; // TODO(quintin) Don't ask me to explain perfectly why we need to cancel out a meters unit in the numerator // I think it comes from the fact that there is a unit vector in the denominator of the equation - auto delta = (turn/Radians{1}) * WHEEL_DISTANCE_INNER; // should be in m/s - RadiansPerSecond left = (forward-delta) * WHEEL_LINEAR_TO_ANGULAR; - RadiansPerSecond right = (forward+delta) * WHEEL_LINEAR_TO_ANGULAR; + auto delta = turn / Radians{1} * WHEEL_DISTANCE_INNER; // should be in m/s + RadiansPerSecond left = (forward - delta) * WHEEL_LINEAR_TO_ANGULAR; + RadiansPerSecond right = (forward + delta) * WHEEL_LINEAR_TO_ANGULAR; std::unordered_map driveCommandVelocities{ {"front_left", left}, @@ -80,13 +68,7 @@ void moveDrive(geometry_msgs::Twist::ConstPtr const& msg) { {"back_right", right}, }; - ROS_INFO("m/s %f", forward.get()); - for (auto [name, angularVelocity]: driveCommandVelocities) { - // Set the desired speed for the motor - Dimensionless multiplier = motorMultipliers[name]; - RadiansPerSecond scaledAngularVelocity = angularVelocity * multiplier; // currently in rad/s - - driveManager->getController(name).setDesiredVelocity(scaledAngularVelocity); + driveManager->getController(name).setDesiredVelocity(angularVelocity); } } diff --git a/src/esw/fw/auton_led/auton_led.ino b/src/esw/fw/auton_led/auton_led.ino new file mode 100644 index 000000000..1ee854035 --- /dev/null +++ b/src/esw/fw/auton_led/auton_led.ino @@ -0,0 +1,64 @@ +int red_led = 12; +int green_led = 10; +int blue_led = 11; + +void led_control(char led_ID) { + if (led_ID == 'r') { + digitalWrite(red_led, LOW); + digitalWrite(green_led, HIGH); + digitalWrite(blue_led, HIGH); + } else if (led_ID == 'g') { + digitalWrite(green_led, LOW); + digitalWrite(blue_led, HIGH); + digitalWrite(red_led, HIGH); + } + else if (led_ID == 'b') { + digitalWrite(blue_led, LOW); + digitalWrite(red_led, HIGH); + digitalWrite(green_led, HIGH); + } + else if (led_ID == 'o') { + digitalWrite(blue_led, HIGH); + digitalWrite(red_led, HIGH); + digitalWrite(green_led, HIGH); + } + else if (led_ID == 'w') { + digitalWrite(blue_led, LOW); + digitalWrite(red_led, LOW); + digitalWrite(green_led, LOW); + } + else if (led_ID == "n") { + digitalWrite(blue_led, HIGH); + digitalWrite(red_led, LOW); + digitalWrite(green_led, LOW); + } + else if (led_ID == "p") { + digitalWrite(blue_led, LOW); + digitalWrite(red_led, LOW); + digitalWrite(green_led, HIGH); + } + else if (led_ID == "p") { + digitalWrite(blue_led, LOW); + digitalWrite(red_led, HIGH); + digitalWrite(green_led, LOW); + } +} + +void setup() { + // put your setup code here, to run once: + pinMode(red_led, OUTPUT); // red led + pinMode(green_led, OUTPUT); // green led + pinMode(blue_led, OUTPUT); // blue led + digitalWrite(blue_led, LOW); + digitalWrite(red_led, LOW); + digitalWrite(green_led, LOW); + Serial.begin(115200); +} + +void loop() { + + if (Serial.available()) { + char input = Serial.read(); + led_control(input); + } +} \ No newline at end of file diff --git a/src/esw/fw/bdcmc/.cproject b/src/esw/fw/bdcmc/.cproject index 8654174d6..5d1d5e7d6 100644 --- a/src/esw/fw/bdcmc/.cproject +++ b/src/esw/fw/bdcmc/.cproject @@ -24,7 +24,7 @@