From 705a21035bddc856c1e434d5502f69758e82c7e9 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Tue, 12 Nov 2024 07:05:02 -0700 Subject: [PATCH] [RISC-V] Drop undesirable two instruction macc alternatives So I was looking at sub_dct a little while ago and was surprised to see us emit two instructions out of a single pattern. We generally try to avoid that -- it's not always possible, but as a general rule of thumb it should be avoided. Specifically I saw: > vmv1r.v v4,v2 # 138 [c=4 l=4] *pred_mul_plusrvvm1hi_undef/5 > vmacc.vv v4,v8,v1 When we emit multiple instructions out of a single pattern we can't build a good schedule as we can't really describe the two instructions well and we can't split them up -- they move as an atomic unit. These cases can also raise correctness issues if the pattern doesn't properly account for both instructions in its length computation. Note the length, 4 bytes. So this is both a performance and latent correctness issue. It appears that these alternatives are meant to deal with the case when we have three source inputs and a non-matching output. The author did put in "?" to slightly disparage these alternatives, but a "!" would have been better. The best solution is to just remove those alternatives and let the allocator manage the matching operand issue. That's precisely what this patch does. For the various integer multiply-add/multiply-accumulate patterns we drop the alternatives which don't require a match between the output and one of the inputs. That fixes the correctness issue and should shave a cycle or two off our sub_dct code. Essentially the move bubbles up into an empty slot and we can schedule around the vmacc sensibly. Interestingly enough this fixes a scan-assembler test in my tester for both rv32 and rv64. > Tests that now work, but didn't before (10 tests): > > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 > unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 My BPI is already in a bootstrap test, so this patch won't hit the BPI for bootstrapping until Wednesday, meaning no data until Thursday. Will wait for the pre-commit tester though. gcc/ * config/riscv/vector.md (pred_mul_plus_undef): Drop alternatives where output doesn't have to match input. (pred_madd, pred_macc): Likewise. (pred_madd_scalar, pred_macc_scalar): Likewise. (pred_madd_exended_scalar): Likewise. (pred_macc_exended_scalar): Likewise. (pred_minus_mul_undef): Likewise. (pred_nmsub, pred_nmsac): Likewise. (pred_nmsub_scalar, pred_nmsac_scalar): Likewise. (pred_nmsub_exended_scalar): Likewise. (pred_nmsac_exended_scalar): Likewise. --- gcc/config/riscv/vector.md | 310 +++++++++++++++++-------------------- 1 file changed, 140 insertions(+), 170 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index a21288f7af2a2..8bbae41c9f324 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -5218,56 +5218,52 @@ }) (define_insn "*pred_mul_plus_undef" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") - (match_operand 9 "const_int_operand" " i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm, Wc1,Wc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:V_VLSI (mult:V_VLSI - (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr") - (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr")) - (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr")) + (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr") + (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, 0")) (match_operand:V_VLSI 2 "vector_undef_operand")))] "TARGET_VECTOR" "@ vmadd.vv\t%0,%4,%5%p1 vmacc.vv\t%0,%3,%4%p1 - vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1 vmadd.vv\t%0,%4,%5%p1 - vmacc.vv\t%0,%3,%4%p1 - vmv%m5r.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1" + vmacc.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "")]) (define_insn "*pred_madd" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:V_VLSI (mult:V_VLSI - (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr") - (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSI 2 "register_operand" " 0, 0") + (match_operand:V_VLSI 3 "register_operand" " vr, vr")) + (match_operand:V_VLSI 4 "register_operand" " vr, vr")) (match_dup 2)))] "TARGET_VECTOR" "@ vmadd.vv\t%0,%3,%4%p1 - vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1 - vmadd.vv\t%0,%3,%4%p1 - vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1" + vmadd.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5277,28 +5273,24 @@ (set (attr "avl_type_idx") (const_int 8))]) (define_insn "*pred_macc" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:V_VLSI (mult:V_VLSI - (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr") - (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")) + (match_operand:V_VLSI 2 "register_operand" " vr, vr") + (match_operand:V_VLSI 3 "register_operand" " vr, vr")) + (match_operand:V_VLSI 4 "register_operand" " 0, 0")) (match_dup 4)))] "TARGET_VECTOR" - "@ - vmacc.vv\t%0,%2,%3%p1 - vmv%m4r.v\t%0,%4;vmacc.vv\t%0,%2,%3%p1 - vmacc.vv\t%0,%2,%3%p1 - vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1" + "vmacc.vv\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5329,29 +5321,27 @@ {}) (define_insn "*pred_madd_scalar" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:V_VLSI (mult:V_VLSI (vec_duplicate:V_VLSI - (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) - (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")) - (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ")) + (match_operand:V_VLSI 3 "register_operand" " 0, 0")) + (match_operand:V_VLSI 4 "register_operand" " vr, vr")) (match_dup 3)))] "TARGET_VECTOR" "@ vmadd.vx\t%0,%z2,%4%p1 - vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%z2,%4%p1 - vmadd.vx\t%0,%z2,%4%p1 - vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%z2,%4%p1" + vmadd.vx\t%0,%z2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5361,29 +5351,27 @@ (set (attr "avl_type_idx") (const_int 8))]) (define_insn "*pred_macc_scalar" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:V_VLSI (mult:V_VLSI (vec_duplicate:V_VLSI - (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) - (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ")) + (match_operand:V_VLSI 3 "register_operand" " vr, vr")) + (match_operand:V_VLSI 4 "register_operand" " 0, 0")) (match_dup 4)))] "TARGET_VECTOR" "@ vmacc.vx\t%0,%z2,%3%p1 - vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1 - vmacc.vx\t%0,%z2,%3%p1 - vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1" + vmacc.vx\t%0,%z2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5428,30 +5416,28 @@ }) (define_insn "*pred_madd_extended_scalar" - [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI_D (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:V_VLSI_D (mult:V_VLSI_D (vec_duplicate:V_VLSI_D (sign_extend: - (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) - (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ"))) + (match_operand:V_VLSI_D 3 "register_operand" " 0, 0")) + (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")) (match_dup 3)))] "TARGET_VECTOR && !TARGET_64BIT" "@ vmadd.vx\t%0,%z2,%4%p1 - vmv%m2r.v\t%0,%z2\;vmadd.vx\t%0,%z2,%4%p1 - vmadd.vx\t%0,%z2,%4%p1 - vmv%m2r.v\t%0,%z2\;vmadd.vx\t%0,%z2,%4%p1" + vmadd.vx\t%0,%z2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5461,30 +5447,28 @@ (set (attr "avl_type_idx") (const_int 8))]) (define_insn "*pred_macc_extended_scalar" - [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI_D (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:V_VLSI_D (mult:V_VLSI_D (vec_duplicate:V_VLSI_D (sign_extend: - (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) - (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ"))) + (match_operand:V_VLSI_D 3 "register_operand" " vr, vr")) + (match_operand:V_VLSI_D 4 "register_operand" " 0, 0")) (match_dup 4)))] "TARGET_VECTOR && !TARGET_64BIT" "@ vmacc.vx\t%0,%z2,%3%p1 - vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1 - vmacc.vx\t%0,%z2,%3%p1 - vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1" + vmacc.vx\t%0,%z2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5516,56 +5500,52 @@ }) (define_insn "*pred_minus_mul_undef" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") - (match_operand 9 "const_int_operand" " i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (minus:V_VLSI - (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr") + (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, 0") (mult:V_VLSI - (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr") - (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))) + (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr") + (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))) (match_operand:V_VLSI 2 "vector_undef_operand")))] "TARGET_VECTOR" "@ vnmsub.vv\t%0,%4,%5%p1 vnmsac.vv\t%0,%3,%4%p1 - vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1 vnmsub.vv\t%0,%4,%5%p1 - vnmsac.vv\t%0,%3,%4%p1 - vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1" + vnmsac.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "")]) (define_insn "*pred_nmsub" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (minus:V_VLSI - (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSI 4 "register_operand" " vr, vr") (mult:V_VLSI - (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr") - (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))) + (match_operand:V_VLSI 2 "register_operand" " 0, 0") + (match_operand:V_VLSI 3 "register_operand" " vr, vr"))) (match_dup 2)))] "TARGET_VECTOR" "@ vnmsub.vv\t%0,%3,%4%p1 - vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1 - vnmsub.vv\t%0,%3,%4%p1 - vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1" + vnmsub.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5575,28 +5555,26 @@ (set (attr "avl_type_idx") (const_int 8))]) (define_insn "*pred_nmsac" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (minus:V_VLSI - (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr") + (match_operand:V_VLSI 4 "register_operand" " 0, 0") (mult:V_VLSI - (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr") - (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))) + (match_operand:V_VLSI 2 "register_operand" " vr, vr") + (match_operand:V_VLSI 3 "register_operand" " vr, vr"))) (match_dup 4)))] "TARGET_VECTOR" "@ vnmsac.vv\t%0,%2,%3%p1 - vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1 - vnmsac.vv\t%0,%2,%3%p1 - vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1" + vnmsac.vv\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5627,29 +5605,27 @@ {}) (define_insn "*pred_nmsub_scalar" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (minus:V_VLSI - (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSI 4 "register_operand" " vr, vr") (mult:V_VLSI (vec_duplicate:V_VLSI - (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) - (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ")) + (match_operand:V_VLSI 3 "register_operand" " 0, 0"))) (match_dup 3)))] "TARGET_VECTOR" "@ vnmsub.vx\t%0,%z2,%4%p1 - vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1 - vnmsub.vx\t%0,%z2,%4%p1 - vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1" + vnmsub.vx\t%0,%z2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5659,29 +5635,27 @@ (set (attr "avl_type_idx") (const_int 8))]) (define_insn "*pred_nmsac_scalar" - [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (minus:V_VLSI - (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr") + (match_operand:V_VLSI 4 "register_operand" " 0, 0") (mult:V_VLSI (vec_duplicate:V_VLSI - (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) - (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ")) + (match_operand:V_VLSI 3 "register_operand" " vr, vr"))) (match_dup 4)))] "TARGET_VECTOR" "@ vnmsac.vx\t%0,%z2,%3%p1 - vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1 - vnmsac.vx\t%0,%z2,%3%p1 - vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1" + vnmsac.vx\t%0,%z2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5726,30 +5700,28 @@ }) (define_insn "*pred_nmsub_extended_scalar" - [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI_D (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (minus:V_VLSI_D - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSI_D 4 "register_operand" " vr, vr") (mult:V_VLSI_D (vec_duplicate:V_VLSI_D (sign_extend: - (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) - (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ"))) + (match_operand:V_VLSI_D 3 "register_operand" " 0, 0"))) (match_dup 3)))] "TARGET_VECTOR && !TARGET_64BIT" "@ vnmsub.vx\t%0,%z2,%4%p1 - vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1 - vnmsub.vx\t%0,%z2,%4%p1 - vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1" + vnmsub.vx\t%0,%z2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5759,30 +5731,28 @@ (set (attr "avl_type_idx") (const_int 8))]) (define_insn "*pred_nmsac_extended_scalar" - [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr") + [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr") (if_then_else:V_VLSI_D (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (minus:V_VLSI_D - (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr") + (match_operand:V_VLSI_D 4 "register_operand" " 0, 0") (mult:V_VLSI_D (vec_duplicate:V_VLSI_D (sign_extend: - (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) - (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ"))) + (match_operand:V_VLSI_D 3 "register_operand" " vr, vr"))) (match_dup 4)))] "TARGET_VECTOR && !TARGET_64BIT" "@ vnmsac.vx\t%0,%z2,%3%p1 - vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1 - vnmsac.vx\t%0,%z2,%3%p1 - vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1" + vnmsac.vx\t%0,%z2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4")