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README~
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README~
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This file will help you understand what's going on in the folder 'slicing' -- vineeshvs (21/05/15)
-------------------------------------------------------------------------------------------------------------------------------------
22/05/15:
---------
* The original 'slicing' folder is moved to ../backups/slicing_removing_MUT_also
26/05/15:
---------
* Restricitons on Verilog code:
*
// Module instantiation <-- (Comment is necessary)
half_adder u2_half_adder ( <--(Upto this bracket should be in the same line. Next line onwards port mapping should start)
// Inputs <--(Comment is necessary)
.in_x(s0),
.in_y(c0),
// End of inputs <--(Comment is necessary)
// Outputs <--(Comment is necessary)
.out_sum(s1),
.out_carry(c2)
// End of outputs <--(Comment is necessary)
);
*
26/05/15:
---------
* Writing function to find inputs of top module
* Restricitons on Verilog code (Contd.):
* For extracting the inputs of the top module, the following conditions are to be satisfied
* input a0; <-- Each input should be separately declared (& NOT as 'input a0,b0;')
input b0; <-- 'input[SPACE][INPUT_NAME];'
29/05/15:
---------
* Restricitons on Verilog code (Contd.):
// Inputs_top <- The word 'Inputs_top' is necessary in the comment before the inputs of top module
// Outputs_top <- The word 'Outputs_top' is necessary in the comment before the outputs of top module
// End of inputs_top <-This string is necessary at the end of all input declarations of top module
// End of outputs_top <-This string is necessary at the end of all output declarations of top module
* Slicing is done (Sample console output on running slice.py is given below)
* Configurations:
* MUT: u2_half_adder
* Console output:
=====================================================================================================================
Removing modules_to_be_sliced
---------------------------------------------------------------------------------------------------------------------
Reassigning the signals affected by slicing into potential_PO,potential_PI,inputs_to_be_deleted,outputs_to_be_deleted
---------------------------------------------------------------------------------------------------------------------
inputs_modules_to_be_sliced = ['s1', 's0', 'a1', 'b1', 'd1', 'c3']
s1 is an input of the modules_to_be_sliced
s1 is not the input of any other module -> potential_PO
s0 is an input of the modules_to_be_sliced
s0 is the input of some module -> NOP
a1 is an input of the modules_to_be_sliced
b1 is an input of the modules_to_be_sliced
d1 is an input of the modules_to_be_sliced
c3 is an input of the modules_to_be_sliced
potential_PO=['s1']
inputs_to_be_deleted=['a1', 'b1', 'd1', 'c3']
s2 is an output of the modules_to_be_sliced
s2 is not an input of any module -> delete it
d1 is an output of the modules_to_be_sliced
d1 is not an input of any module -> delete it
c3 is an output of the modules_to_be_sliced
c3 is not an input of any module -> delete it
s3 is an output of the modules_to_be_sliced
s3 is not an input of any module -> delete it
potential_PI=[]
outputs_to_be_deleted=['s2', 'd1', 'c3', 's3']
-----------------------------------------------------------------------------------------
Adding potential_PO & potential_PI, deleting inputs_to_be_deleted & outputs_to_be_deleted
-----------------------------------------------------------------------------------------
match found
input a1 is deleted1
match found
input b1 is deleted1
output s1 written
match found
output s2 is deleted1
match found
output d1 is deleted1
match found
output s3 is deleted1
=====================================================================================================================
30/05/15:
---------
* file name changed from slice.py to slicing.py due to import problem in the gui with the name import
> Change the location of 'output_files' later. Now it is kept in the working directory