From dd720cae57979dc858f1162f0044b13d1ceb5495 Mon Sep 17 00:00:00 2001 From: Tang Haojin Date: Sat, 3 Aug 2024 00:32:10 +0800 Subject: [PATCH 01/11] ci: do not consider procname with ssh (#3335) --- scripts/xiangshan.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/xiangshan.py b/scripts/xiangshan.py index e83a3d6a8be..a41946323e5 100644 --- a/scripts/xiangshan.py +++ b/scripts/xiangshan.py @@ -526,7 +526,7 @@ def get_free_cores(n): try: joint = ' '.join(proc.cmdline()) numa_match = numa_re.match(joint) - if numa_match: + if numa_match and 'ssh' not in proc.name(): disable_cores.extend(range(int(numa_match.group(1)), int(numa_match.group(2)) + 1)) except (psutil.NoSuchProcess, psutil.AccessDenied, psutil.ZombieProcess): pass From c15f982f49c3608a64e9b7d24d3d8c326d286767 Mon Sep 17 00:00:00 2001 From: zhanglinjuan Date: Sat, 3 Aug 2024 00:33:01 +0800 Subject: [PATCH 02/11] Bump CoupledL2 and OpenLLC (#3332) This commit includes the following commits in CoupledL2: * https://github.com/OpenXiangShan/CoupledL2/pull/215 * https://github.com/OpenXiangShan/CoupledL2/pull/212 and the following commits in OpenLLC: * https://github.com/OpenXiangShan/OpenLLC/pull/9 --- coupledL2 | 2 +- openLLC | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/coupledL2 b/coupledL2 index 79a2971e9e0..b59fb143fd1 160000 --- a/coupledL2 +++ b/coupledL2 @@ -1 +1 @@ -Subproject commit 79a2971e9e07f6417675c21f784543aaf556cf3f +Subproject commit b59fb143fd12c938f6c3570aa8ba1d9a23ba246f diff --git a/openLLC b/openLLC index 2a33569b22d..7ff91e2c5c2 160000 --- a/openLLC +++ b/openLLC @@ -1 +1 @@ -Subproject commit 2a33569b22d7223ee4dd5d4ad128f0a378ff24e0 +Subproject commit 7ff91e2c5c29b0f79c8da58ea76942198e9987e1 From a061b23e782d765edb3bd0f84158b8066175334d Mon Sep 17 00:00:00 2001 From: Anzo <126764519+Anzooooo@users.noreply.github.com> Date: Sat, 3 Aug 2024 00:34:04 +0800 Subject: [PATCH 03/11] MemBlock: fix segment blocking logic (#3328) --- src/main/scala/xiangshan/backend/MemBlock.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala index 5662f132268..198ce0b4a3b 100644 --- a/src/main/scala/xiangshan/backend/MemBlock.scala +++ b/src/main/scala/xiangshan/backend/MemBlock.scala @@ -1332,8 +1332,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer) val vlsuCanAccept = (0 until VlduCnt).map( i => vsSplit(i).io.in.ready && vlSplit(i).io.in.ready ) - val isSegment = (io.ooo_to_mem.issueVldu.head.bits.uop.vpu.nf =/= 0.U) && - !(io.ooo_to_mem.issueVldu.head.bits.uop.fuOpType === VlduType.vlr || io.ooo_to_mem.issueVldu.head.bits.uop.fuOpType === VstuType.vsr) + val isSegment = io.ooo_to_mem.issueVldu.head.valid && isVsegls(io.ooo_to_mem.issueVldu.head.bits.uop.fuType) // init port /** From ff6715878e93faee95e237d8ac88370479702e34 Mon Sep 17 00:00:00 2001 From: xiaofeibao <1441675923@qq.com> Date: Thu, 1 Aug 2024 14:23:07 +0800 Subject: [PATCH 04/11] IssueQueue: enqReady remove deqSuccess and flushed for fix timing --- src/main/scala/xiangshan/backend/issue/EntryBundles.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/issue/EntryBundles.scala b/src/main/scala/xiangshan/backend/issue/EntryBundles.scala index a2a420ff088..50f9e5b4df8 100644 --- a/src/main/scala/xiangshan/backend/issue/EntryBundles.scala +++ b/src/main/scala/xiangshan/backend/issue/EntryBundles.scala @@ -182,7 +182,7 @@ object EntryBundles extends HasCircularQueuePtrHelper { bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq common.canIssue := validReg && status.canIssue - common.enqReady := !validReg || common.clear + common.enqReady := !validReg || commonIn.transSel common.clear := common.flushed || common.deqSuccess || commonIn.transSel common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B From a75acccc5056b49c5823708ce77a2b09b865a5d0 Mon Sep 17 00:00:00 2001 From: chengguanghui Date: Mon, 29 Jul 2024 14:46:47 +0800 Subject: [PATCH 05/11] NewCSR: fix bug, shouldn't handle traping to other Mode anymore when hart traps to DebugMode --- .../scala/xiangshan/backend/fu/NewCSR/NewCSR.scala | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala index 36544c84460..f41ec05af04 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala @@ -310,6 +310,7 @@ class NewCSR(implicit val p: Parameters) extends Module trapHandleMod.io.in.vstvec := vstvec.regOut val entryPrivState = trapHandleMod.io.out.entryPrivState + val entryDebugMode = Wire(Bool()) // PMP val pmpEntryMod = Module(new PMPEntryHandleModule) @@ -587,9 +588,9 @@ class NewCSR(implicit val p: Parameters) extends Module println(mod.dumpFields) } - trapEntryMEvent .valid := hasTrap && entryPrivState.isModeM - trapEntryHSEvent.valid := hasTrap && entryPrivState.isModeHS - trapEntryVSEvent.valid := hasTrap && entryPrivState.isModeVS + trapEntryMEvent .valid := hasTrap && entryPrivState.isModeM && !entryDebugMode + trapEntryHSEvent.valid := hasTrap && entryPrivState.isModeHS && !entryDebugMode + trapEntryVSEvent.valid := hasTrap && entryPrivState.isModeVS && !entryDebugMode Seq(trapEntryMEvent, trapEntryHSEvent, trapEntryVSEvent, trapEntryDEvent).foreach { eMod => eMod.in match { @@ -862,7 +863,9 @@ class NewCSR(implicit val p: Parameters) extends Module debugMod.io.in.tdata2Update := tdata2Update debugMod.io.in.tdata1Wdata := wdata - trapEntryDEvent.valid := debugMod.io.out.hasDebugTrap && !debugMode + entryDebugMode := debugMod.io.out.hasDebugTrap && !debugMode + + trapEntryDEvent.valid := entryDebugMode trapEntryDEvent.in.hasDebugIntr := debugMod.io.out.hasDebugIntr trapEntryDEvent.in.debugMode := debugMode trapEntryDEvent.in.hasTrap := hasTrap From 72f5170339a10140c01db8103e44b1dedac8487a Mon Sep 17 00:00:00 2001 From: sinceforYy <1017657683@qq.com> Date: Thu, 1 Aug 2024 12:16:13 +0800 Subject: [PATCH 06/11] NewCSR: fix select condition of candidates --- .../xiangshan/backend/fu/NewCSR/InterruptFilter.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala index e895f8d07f2..0fd20f48ad4 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala @@ -50,6 +50,8 @@ class InterruptFilter extends Module { val sieFields = sie.asTypeOf(new SieBundle) val hipFields = hip.asTypeOf(new HipBundle) val hieFields = hie.asTypeOf(new HieBundle) + val vsipFields = vsip.asTypeOf(new VSipBundle) + val vsieFields = vsie.asTypeOf(new VSieBundle) val hidelegFields = hideleg.asTypeOf(new HidelegBundle) private val hsip = hip.asUInt | sip.asUInt @@ -180,10 +182,10 @@ class InterruptFilter extends Module { ) // refactor this code & has some problem - val Candidate1: Bool = hidelegFields.VSEI && hipFields.VSEIP && hieFields.VSEIE.asBool && (hstatus.VGEIN.asUInt =/= 0.U) && (vstopei.asUInt =/= 0.U) - val Candidate2: Bool = hidelegFields.VSEI && hipFields.VSEIP && hieFields.VSEIE.asBool && (hstatus.VGEIN.asUInt === 0.U) && (hvictl.IID.asUInt === 9.U) && (hvictl.IPRIO.asUInt =/= 0.U) - val Candidate3: Bool = hidelegFields.VSEI && hipFields.VSEIP && hieFields.VSEIE.asBool && !Candidate1 && !Candidate2 - val Candidate4: Bool = hvictl.VTI.asUInt === 0.U + val Candidate1: Bool = vsipFields.VSEIP.asBool && vsieFields.VSEIE.asBool && (hstatus.VGEIN.asUInt =/= 0.U) && (vstopei.asUInt =/= 0.U) + val Candidate2: Bool = vsipFields.VSEIP.asBool && vsieFields.VSEIE.asBool && (hstatus.VGEIN.asUInt === 0.U) && (hvictl.IID.asUInt === 9.U) && (hvictl.IPRIO.asUInt =/= 0.U) + val Candidate3: Bool = vsipFields.VSEIP.asBool && vsieFields.VSEIE.asBool && !Candidate1 && !Candidate2 + val Candidate4: Bool = (hvictl.VTI.asUInt === 0.U) && (vsie & vsip & "hfffffffffffffdff".U).orR val Candidate5: Bool = (hvictl.VTI.asUInt === 1.U) && (hvictl.IID.asUInt =/= 9.U) val CandidateNoValid: Bool = !Candidate1 && !Candidate2 && !Candidate3 && !Candidate4 && !Candidate5 From c24406020f47d8578ae01c991ec5a0c302bc0d5b Mon Sep 17 00:00:00 2001 From: sinceforYy <1017657683@qq.com> Date: Fri, 2 Aug 2024 16:38:19 +0800 Subject: [PATCH 07/11] vset: select min value from oldVL and vlmax in vsetrvfwvf --- src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala b/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala index e549ebc1708..f8f2a673b3d 100644 --- a/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala +++ b/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala @@ -109,7 +109,8 @@ class VSetRvfWvf(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) { out.res.data := Mux(isReadVl, oldVL, Mux(vsetModule.io.out.vconfig.vtype.illegal, 0.U, - Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType), oldVL, vsetModule.io.out.vconfig.vl))) + Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType), + Mux(oldVL < vlmax, oldVL, vlmax), vsetModule.io.out.vconfig.vl))) if (cfg.writeVlRf) io.vtype.get.bits := vsetModule.io.out.vconfig.vtype if (cfg.writeVlRf) io.vtype.get.valid := isVsetvl && io.out.valid From 1d4845431c2d5719de54b413e65af48e7902c2d6 Mon Sep 17 00:00:00 2001 From: xiaofeibao <1441675923@qq.com> Date: Sun, 4 Aug 2024 13:18:12 +0800 Subject: [PATCH 08/11] VFALU and VFMA: fix bug of vlmul when outWiden is 1 --- src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala | 6 ++++-- src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala b/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala index 13661a01895..acb2d771b61 100644 --- a/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala +++ b/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala @@ -304,10 +304,12 @@ class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) val outCtrl_s0 = ctrlVec.head val outVecCtrl_s0 = ctrlVec.head.vpu.get val outEew_s0 = Mux(resWiden, outVecCtrl_s0.vsew + 1.U, outVecCtrl_s0.vsew) - val outEew = Mux(RegEnable(resWiden, io.in.fire), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) + val outWiden = RegEnable(resWiden, io.in.fire) + val outEew = Mux(outWiden, outVecCtrl.vsew + 1.U, outVecCtrl.vsew) val vlMax_s0 = ((VLEN/8).U >> outEew_s0).asUInt val vlMax = ((VLEN/8).U >> outEew).asUInt - val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1,0)).asUInt + 1.U, outVecCtrl.vlmul(1,0)) + val outVlmulFix = Mux(outWiden, outVecCtrl.vlmul - 1.U, outVecCtrl.vlmul) + val lmulAbs = Mux(outVlmulFix(2), (~outVlmulFix(1,0)).asUInt + 1.U, outVlmulFix(1,0)) // vfmv_f_s need vl=1, reduction last uop need vl=1, other uop need vl=vlmax numOfUopVFRED := { // addTime include add frs1 diff --git a/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala b/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala index c795bcac0bd..efa5b831154 100644 --- a/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala +++ b/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala @@ -94,7 +94,8 @@ class VFMA(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) val outEew = Mux(outWiden, outVecCtrl.vsew + 1.U, outVecCtrl.vsew) val outVuopidx = outVecCtrl.vuopIdx(2, 0) val vlMax = ((VLEN / 8).U >> outEew).asUInt - val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1, 0)).asUInt + 1.U, outVecCtrl.vlmul(1, 0)) + val outVlmulFix = Mux(outWiden, outVecCtrl.vlmul - 1.U, outVecCtrl.vlmul) + val lmulAbs = Mux(outVlmulFix(2), (~outVlmulFix(1, 0)).asUInt + 1.U, outVlmulFix(1, 0)) val outVlFix = Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) val vlMaxAllUop = Wire(outVl.cloneType) vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt From 7c24a7e1231b9286804d7e5198990539ee617035 Mon Sep 17 00:00:00 2001 From: xiaofeibao <1441675923@qq.com> Date: Thu, 1 Aug 2024 17:43:57 +0800 Subject: [PATCH 09/11] Rob: fix bug of deqHasFlushed when redirect and flushout valid at the same time --- src/main/scala/xiangshan/backend/rob/Rob.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala index d310d026e92..39a3b5e56b6 100644 --- a/src/main/scala/xiangshan/backend/rob/Rob.scala +++ b/src/main/scala/xiangshan/backend/rob/Rob.scala @@ -600,19 +600,20 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP val misPredBlock = misPredBlockCounter(0) val deqFlushBlockCounter = Reg(UInt(3.W)) val deqFlushBlock = deqFlushBlockCounter(0) - val deqHasFlushed = Reg(Bool()) + val deqHasFlushed = RegInit(false.B) + val deqHasCommitted = io.commits.isCommit && io.commits.commitValid(0) val deqHitRedirectReg = RegNext(io.redirect.valid && io.redirect.bits.robIdx === deqPtr) when(deqNeedFlush && deqHitRedirectReg){ deqFlushBlockCounter := "b111".U }.otherwise{ deqFlushBlockCounter := deqFlushBlockCounter >> 1.U } - when(deqNeedFlush && io.flushOut.valid){ - deqHasFlushed := true.B - }.elsewhen(!deqNeedFlush){ + when(deqHasCommitted){ deqHasFlushed := false.B + }.elsewhen(deqNeedFlush && io.flushOut.valid){ + deqHasFlushed := true.B } - val blockCommit = misPredBlock || lastCycleFlush || hasWFI || io.redirect.valid || (deqNeedFlush && !deqHasFlushed && !deqHasFlushPipe) || deqFlushBlock + val blockCommit = misPredBlock || lastCycleFlush || hasWFI || io.redirect.valid || (deqNeedFlush && !deqHasFlushed) || deqFlushBlock io.commits.isWalk := state === s_walk io.commits.isCommit := state === s_idle && !blockCommit From bb03ab5dfd0f0f1a2537bcc5a6a15932858c4ff7 Mon Sep 17 00:00:00 2001 From: xiaofeibao <1441675923@qq.com> Date: Sun, 4 Aug 2024 15:47:00 +0800 Subject: [PATCH 10/11] Rob: fix bug of fence instraction's interrupt_safe is 1 --- src/main/scala/xiangshan/backend/rob/Rob.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala index 39a3b5e56b6..3a42237b684 100644 --- a/src/main/scala/xiangshan/backend/rob/Rob.scala +++ b/src/main/scala/xiangshan/backend/rob/Rob.scala @@ -997,7 +997,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP // However, we cannot determine whether a load/store instruction is MMIO. // Thus, we don't allow load/store instructions to trigger an interrupt. // TODO: support non-MMIO load-store instructions to trigger interrupts - val allow_interrupts = !CommitType.isLoadStore(io.enq.req(i).bits.commitType) + val allow_interrupts = !CommitType.isLoadStore(io.enq.req(i).bits.commitType) && !FuType.isFence(io.enq.req(i).bits.fuType) robEntries(RegEnable(allocatePtrVec(i).value, canEnqueue(i))).interrupt_safe := RegEnable(allow_interrupts, canEnqueue(i)) } } From f55cdaab615c13ad82256ecd9e8e4a84def2f8f9 Mon Sep 17 00:00:00 2001 From: zhanglinjuan Date: Mon, 5 Aug 2024 11:48:58 +0800 Subject: [PATCH 11/11] L2Top, MemBlock, Backend: reconstruct reset tree (#3333) Modules in XSTile are reset in the order of L2, MemBlock, Backend and Frontend. --- src/main/scala/xiangshan/L2Top.scala | 8 +++ src/main/scala/xiangshan/XSCore.scala | 19 +---- src/main/scala/xiangshan/XSTile.scala | 12 +--- .../scala/xiangshan/backend/Backend.scala | 35 ++++++++- .../scala/xiangshan/backend/MemBlock.scala | 71 +++++++++++-------- 5 files changed, 87 insertions(+), 58 deletions(-) diff --git a/src/main/scala/xiangshan/L2Top.scala b/src/main/scala/xiangshan/L2Top.scala index 14309448226..dfbfe6fa4fa 100644 --- a/src/main/scala/xiangshan/L2Top.scala +++ b/src/main/scala/xiangshan/L2Top.scala @@ -157,6 +157,7 @@ class L2Top()(implicit p: Parameters) extends LazyModule val l2_tlb_req = IO(new TlbRequestIO(nRespDups = 2)) val l2_pmp_resp = IO(Flipped(new PMPRespBundle)) val l2_hint = IO(ValidIO(new L2ToL1Hint())) + val reset_core = IO(Output(Reset())) val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5)) @@ -214,6 +215,13 @@ class L2Top()(implicit p: Parameters) extends LazyModule l2_tlb_req.req_kill := DontCare l2_tlb_req.resp.ready := true.B } + + if (debugOpts.ResetGen) { + val resetTree = ResetGenNode(Seq(CellNode(reset_core))) + ResetGen(resetTree, reset, sim = false) + } else { + reset_core := DontCare + } } lazy val module = new L2TopImp(this) diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala index a096ea21da1..0e6b24ce247 100644 --- a/src/main/scala/xiangshan/XSCore.scala +++ b/src/main/scala/xiangshan/XSCore.scala @@ -237,24 +237,9 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) io.beu_errors.l2 <> DontCare io.l2_pf_enable := memBlock.io.outer_l2_pf_enable - // Modules are reset one by one - val resetTree = ResetGenNode( - Seq( - ModuleNode(memBlock), - ResetGenNode(Seq( - ModuleNode(backend), - ResetGenNode(Seq( - ResetGenNode(Seq( - ModuleNode(frontend) - )) - )) - )) - ) - ) - // ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) if (debugOpts.ResetGen) { - frontend.reset := memBlock.reset_io_frontend - backend.reset := memBlock.reset_io_backend + backend.reset := memBlock.reset_backend + frontend.reset := backend.io.frontendReset } } diff --git a/src/main/scala/xiangshan/XSTile.scala b/src/main/scala/xiangshan/XSTile.scala index f43d26c0c82..30b019315ca 100644 --- a/src/main/scala/xiangshan/XSTile.scala +++ b/src/main/scala/xiangshan/XSTile.scala @@ -160,15 +160,9 @@ class XSTile()(implicit p: Parameters) extends LazyModule io.chi.foreach(_ <> l2top.module.chi.get) l2top.module.nodeID.foreach(_ := io.nodeID.get) - // Modules are reset one by one - // io_reset ---- - // | - // v - // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores} - // val resetChain = Seq( - // Seq(l2top.module, core.module) - // ) - // ResetGen(resetChain, reset, !debugOpts.FPGAPlatform) + if (debugOpts.ResetGen && enableL2) { + core.module.reset := l2top.module.reset_core + } } lazy val module = new XSTileImp(this) diff --git a/src/main/scala/xiangshan/backend/Backend.scala b/src/main/scala/xiangshan/backend/Backend.scala index 19332450024..d5efec6dc6c 100644 --- a/src/main/scala/xiangshan/backend/Backend.scala +++ b/src/main/scala/xiangshan/backend/Backend.scala @@ -22,7 +22,7 @@ import chisel3.util._ import device.MsiInfoBundle import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import system.HasSoCParameter -import utility.{Constantin, ZeroExt} +import utility._ import utils.{HPerfMonitor, HasPerfEvents, PerfEvent} import xiangshan._ import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} @@ -679,6 +679,38 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends dontTouch(wbDataPath.io.fromMemExu) } + // reset tree + if (p(DebugOptionsKey).ResetGen) { + val rightResetTree = ResetGenNode(Seq( + ModuleNode(dataPath), + ModuleNode(intExuBlock), + ModuleNode(fpExuBlock), + ModuleNode(vfExuBlock), + ModuleNode(bypassNetwork), + ModuleNode(wbDataPath) + )) + val leftResetTree = ResetGenNode(Seq( + ModuleNode(pcTargetMem), + ModuleNode(intScheduler), + ModuleNode(fpScheduler), + ModuleNode(vfScheduler), + ModuleNode(memScheduler), + ModuleNode(og2ForVector), + ModuleNode(wbFuBusyTable), + ResetGenNode(Seq( + ModuleNode(ctrlBlock), + ResetGenNode(Seq( + CellNode(io.frontendReset) + )) + )) + )) + ResetGen(leftResetTree, reset, sim = false) + ResetGen(rightResetTree, reset, sim = false) + } else { + io.frontendReset := DontCare + } + + // perf events val pfevent = Module(new PFEvent) pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) val csrevents = pfevent.io.hpmevent.slice(8,16) @@ -811,6 +843,7 @@ class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle val frontendSfence = Output(new SfenceBundle) val frontendCsrCtrl = Output(new CustomCSRCtrlIO) val frontendTlbCsr = Output(new TlbCsrBundle) + val frontendReset = Output(Reset()) val mem = new BackendMemIO diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala index 198ce0b4a3b..82933c59dbb 100644 --- a/src/main/scala/xiangshan/backend/MemBlock.scala +++ b/src/main/scala/xiangshan/backend/MemBlock.scala @@ -295,8 +295,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer) }) // reset signals of frontend & backend are generated in memblock - val reset_io_frontend = IO(Output(Reset())) - val reset_io_backend = IO(Output(Reset())) + val reset_backend = IO(Output(Reset())) dontTouch(io.externalInterrupt) dontTouch(io.inner_hartId) @@ -540,6 +539,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer) val tlbcsr = RegNext(RegNext(io.ooo_to_mem.tlbCsr)) private val ptw = outer.ptw.module private val ptw_to_l2_buffer = outer.ptw_to_l2_buffer.module + private val l1d_to_l2_buffer = outer.l1d_to_l2_buffer.module ptw.io.hartId := io.hartId ptw.io.sfence <> sfence ptw.io.csr.tlb <> tlbcsr @@ -553,18 +553,12 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer) } // dtlb - val dtlb_ld = VecInit(Seq.fill(1){ - val tlb_ld = Module(new TLBNonBlock(LduCnt + HyuCnt + 1, 2, ldtlbParams)) - tlb_ld.io // let the module have name in waveform - }) - val dtlb_st = VecInit(Seq.fill(1){ - val tlb_st = Module(new TLBNonBlock(StaCnt, 1, sttlbParams)) - tlb_st.io // let the module have name in waveform - }) - val dtlb_prefetch = VecInit(Seq.fill(1){ - val tlb_prefetch = Module(new TLBNonBlock(2, 2, pftlbParams)) - tlb_prefetch.io // let the module have name in waveform - }) + val dtlb_ld_tlb_ld = Module(new TLBNonBlock(LduCnt + HyuCnt + 1, 2, ldtlbParams)) + val dtlb_st_tlb_st = Module(new TLBNonBlock(StaCnt, 1, sttlbParams)) + val dtlb_prefetch_tlb_prefetch = Module(new TLBNonBlock(2, 2, pftlbParams)) + val dtlb_ld = Seq(dtlb_ld_tlb_ld.io) + val dtlb_st = Seq(dtlb_st_tlb_st.io) + val dtlb_prefetch = Seq(dtlb_prefetch_tlb_prefetch.io) /* tlb vec && constant variable */ val dtlb = dtlb_ld ++ dtlb_st ++ dtlb_prefetch val (dtlb_ld_idx, dtlb_st_idx, dtlb_pf_idx) = (0, 1, 2) @@ -654,7 +648,8 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer) val pmp = Module(new PMP()) pmp.io.distribute_csr <> csrCtrl.distribute_csr - val pmp_check = VecInit(Seq.fill(DTlbSize)(Module(new PMPChecker(4, leaveHitMux = true)).io)) + val pmp_checkers = Seq.fill(DTlbSize)(Module(new PMPChecker(4, leaveHitMux = true))) + val pmp_check = pmp_checkers.map(_.io) for ((p,d) <- pmp_check zip dtlb_pmps) { p.apply(tlbcsr.priv.dmode, pmp.io.pmp, pmp.io.pma, d) require(p.req.bits.size.getWidth == d.bits.size.getWidth) @@ -1611,22 +1606,6 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer) io.outer_l2_pf_enable := io.inner_l2_pf_enable // io.inner_hc_perfEvents <> io.outer_hc_perfEvents - if (p(DebugOptionsKey).ResetGen) { - val resetTree = ResetGenNode( - Seq( - CellNode(reset_io_frontend), - CellNode(reset_io_backend), - ModuleNode(itlbRepeater3), - ModuleNode(dtlbRepeater), - ModuleNode(ptw), - ModuleNode(ptw_to_l2_buffer) - ) - ) - ResetGen(resetTree, reset, !p(DebugOptionsKey).ResetGen) - } else { - reset_io_frontend := DontCare - reset_io_backend := DontCare - } // vector segmentUnit vSegmentUnit.io.in.bits <> io.ooo_to_mem.issueVldu.head.bits vSegmentUnit.io.in.valid := isSegment && io.ooo_to_mem.issueVldu.head.valid// is segment instruction @@ -1639,6 +1618,36 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer) vSegmentUnit.io.rdcache.resp.valid := dcache.io.lsu.load(0).resp.valid vSegmentUnit.io.rdcache.s2_bank_conflict := dcache.io.lsu.load(0).s2_bank_conflict + // reset tree of MemBlock + if (p(DebugOptionsKey).ResetGen) { + val leftResetTree = ResetGenNode( + Seq( + ModuleNode(ptw), + ModuleNode(ptw_to_l2_buffer), + ModuleNode(lsq), + ModuleNode(dtlb_st_tlb_st), + ModuleNode(dtlb_prefetch_tlb_prefetch), + ModuleNode(pmp) + ) + ++ pmp_checkers.map(ModuleNode(_)) + ++ (if (prefetcherOpt.isDefined) Seq(ModuleNode(prefetcherOpt.get)) else Nil) + ++ (if (l1PrefetcherOpt.isDefined) Seq(ModuleNode(l1PrefetcherOpt.get)) else Nil) + ) + val rightResetTree = ResetGenNode( + Seq( + ModuleNode(sbuffer), + ModuleNode(dtlb_ld_tlb_ld), + ModuleNode(dcache), + ModuleNode(l1d_to_l2_buffer), + CellNode(reset_backend) + ) + ) + ResetGen(leftResetTree, reset, sim = false) + ResetGen(rightResetTree, reset, sim = false) + } else { + reset_backend := DontCare + } + // top-down info dcache.io.debugTopDown.robHeadVaddr := io.debugTopDown.robHeadVaddr dtlbRepeater.io.debugTopDown.robHeadVaddr := io.debugTopDown.robHeadVaddr