Add aarch64a_soft_nofp variant #523
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For the LLVM changes, we're trying to minimise the side of our downstream patch, so we'd prefer to wait until these have been committed to LLVM itself.
For the testing, have you checked if QEMU correctly models the undefined instruction exception if a floating-point instruction is executed in this library variant? I did some testing a while ago and couldn't get that to happen, which is why I'm trying to make FVPs usable for testing, since they can accurately model a lot of less-common architectures like this.
| - ldp x10,x11, [x0, #0x050] | ||
| - ldp x12,x13, [x0, #0x060] | ||
| - ldp x14,x15, [x0, #0x070] | ||
| + LDP(x2, x3, x0, #0x010, #0x018) |
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The LDP instructions with X registers should be available without the FPU, is this part of the change needed?
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Nope. I'm not sure why I thought that was necessary. I'll be updating the upstream PR once I've finish testing.
Build a soft float multilib variant for aarch64 supporting targets without an FPU. This contains a couple of minor fixes for llvm to enable this; I'll be submitting those upstream. Signed-off-by: Keith Packard <[email protected]>
Makes sense. I'm working on getting those upstream.
I don't think QEMU has a model for aarch64 without an FPU, so all of my testing uses the full machine. However, my test harness leaves the FPU disabled when testing the nofp code. When it hits an instruction using the FPU, qemu traps. |
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It would be good to have these changes tested on FVP; I haven't figured out how to do that yet. |
Build a soft float multilib variant for aarch64 supporting targets without an FPU.
This contains a couple of minor fixes for llvm to enable this; I'll be submitting those upstream.