[RCFC] LPC4322 SWD-SGPIO.

records/board/mimxrt1170_evk_qspi.yaml

@@ -3,6 +3,7 @@ common:
         - DAPLINK_MIMXRT_TARGET
         - SOFT_RESET=VECTRESET
         - SWO_UART=1
+        - SWDP_SGPIO=1
     sources:
         board:
             - source/board/mimxrt1170_evk.c

source/hic_hal/nxp/lpc4322/DAP_config.h

@@ -300,11 +300,13 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT(uint32_t bit)
 {
+#ifndef SWDP_SGPIO
     if (bit & 0x1) {
         X_SET(SWDIO);
     } else {
         X_CLR(SWDIO);
     }
+#endif
 }
 
 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
@@ -313,8 +315,10 @@ called prior \ref PIN_SWDIO_OUT function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE(void)
 {
+#ifndef SWDP_SGPIO
     X_SET(SWDIO_TXE);
     X_DIR_OUT(SWDIO);
+#endif
 }
 
 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -323,8 +327,10 @@ called prior \ref PIN_SWDIO_IN function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE(void)
 {
+#ifndef SWDP_SGPIO
     X_DIR_IN(SWDIO);
     X_CLR(SWDIO_TXE);
+#endif
 }
 
 
@@ -506,11 +512,36 @@ __STATIC_INLINE void DAP_SETUP(void)
 
     while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
 
+#ifdef SWDP_SGPIO
+    // Normal-drive and high-speed pins support a programmable slew rate (bit EHS).
+    // The typical frequencies supported are 50 MHz/80 MHz for normal-drive pins
+    // and 75 MHz/204 MHz for high-speed pins.
+    // See "Programmable slew rate" and "Pin configuration registers for normal-drive pins" UM10503.
+    //
+    // The clock pins CLK0 to CLK3 and P3_3 support a programmable high-speed
+    // output with typical frequencies of 75 MHz or 204 MHz depending on the slew rate setting
+    // See "High-speed pins" and "Pin configuration registers for high-speed pins" UM10503.
+    //
+    // High-drive pins support the programmable glitch filter
+    // but not the programmable slew rate.
+    // See "High-drive pins" and "Pin configuration registers for high-drive pins" UM10503.
+
+    // SWCLK/TCK: SGPIO11. P1_17 is a High-drive pin.
+    // FILTER_DISABLE: The filter has to be disabled for frequencies greater than 30 MHz.
+    scu_pinmux(1, 17, PUP_DISABLE | PDN_DISABLE | INBUF_ENABLE | FILTER_DISABLE | DRIVE_20MA, FUNC6);
+
+    // SWDIO/TMS: SGPIO14. P1_6 is a Normal-drive pin.
+    scu_pinmux(1,  6, PUP_DISABLE | PDN_DISABLE | INBUF_ENABLE | FILTER_DISABLE | SLEWRATE_FAST, FUNC6);
+
+    // SWDIO/TXEN: SGPIO15. P1_5 is a Normal-drive pin.
+    scu_pinmux(1,  5, PUP_DISABLE | PDN_DISABLE | INBUF_ENABLE | FILTER_DISABLE | SLEWRATE_FAST, FUNC6);
+#else
     /* Configure I/O pins: function number, input buffer enabled,    */
     /*                     no pull-up/down                           */
     scu_pinmux(1, 17, GPIO_NOPULL, FUNC0);   /* SWCLK/TCK: GPIO0[12] */
     scu_pinmux(1,  6, GPIO_NOPULL, FUNC0);   /* SWDIO/TMS: GPIO1[9]  */
     scu_pinmux(1,  5, GPIO_NOPULL, FUNC0);   /* SWDIO_OE:  GPIO1[8]  */
+#endif
 }
 
 /** Reset Target Device with custom specific I/O pin or command sequence.

source/hic_hal/nxp/lpc4322/gpio.c

@@ -89,6 +89,11 @@ void gpio_init(void)
     X_DIR_IN(SWO);
 #endif
 
+#ifdef SWDP_SGPIO
+    extern void sgpio_init(void);
+    sgpio_init();
+#endif
+
     busy_wait(10000);
 }
 

source/hic_hal/nxp/lpc4322/lpc43xx_scu.c

@@ -80,7 +80,7 @@
  * 					- FUNC7		:Function 7
  * @return		None
  **********************************************************************/
-void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)
+void scu_pinmux(uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
 {
     uint32_t *scu_base = (uint32_t *)(LPC_SCU_BASE);
     scu_base[(PORT_OFFSET * port + PIN_OFFSET * pin) / 4] = mode + func;

source/hic_hal/nxp/lpc4322/lpc43xx_scu.h

@@ -69,9 +69,10 @@ extern "C"
 #define INBUF_DISABLE	  (0 << 6)	// Input buffer
 #define FILTER_ENABLE	  (0 << 7)	// Glitch filter (for signals below 30MHz)
 #define FILTER_DISABLE	  (1 << 7)	// No glitch filter (for signals above 30MHz)
-#define DRIVE_8MA         (1 << 8)	// Drive strength of 8mA
-#define DRIVE_14MA        (1 << 9)	// Drive strength of 14mA
-#define DRIVE_20MA        (3 << 8)	// Drive strength of 20mA
+#define DRIVE_4MA         (0 << 8)	// Normal-drive: drive strength of 4mA (default)
+#define DRIVE_8MA         (1 << 8)	// Medium-drive: drive strength of 8mA
+#define DRIVE_14MA        (2 << 8)	// High-drive: drive strength of 14mA
+#define DRIVE_20MA        (3 << 8)	// Ultra high-drive: drive strength of 20mA
 
 
 /* Configuration examples for various I/O pins */
@@ -107,7 +108,7 @@ extern "C"
  * @{
  */
 
-void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
+void scu_pinmux(uint8_t port, uint8_t pin, uint16_t mode, uint8_t func);
 
 /**
  * @}