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Add: Tle5012b encoder #383
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from edg.abstract_parts import * | ||||||||||||||
from edg.parts.JlcPart import JlcPart | ||||||||||||||
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class Tle5012b_Device(InternalSubcircuit, FootprintBlock, JlcPart): | ||||||||||||||
def __init__(self) -> None: | ||||||||||||||
super().__init__() | ||||||||||||||
self.vdd = self.Port(VoltageSink( | ||||||||||||||
voltage_limits=(3.0, 5.5) * Volt, | ||||||||||||||
current_draw=(5 * uAmp, 16 * mAmp) | ||||||||||||||
)) | ||||||||||||||
self.gnd = self.Port(Ground()) | ||||||||||||||
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dio_model = DigitalBidir.from_supply( | ||||||||||||||
self.gnd, self.vdd, | ||||||||||||||
voltage_limit_tolerance=(-0.3, 0.3) * Volt, | ||||||||||||||
input_threshold_factor=(0.3, 0.7), | ||||||||||||||
current_limits=(5 * uAmp, 25 * mAmp) | ||||||||||||||
) | ||||||||||||||
dio_model_sck = DigitalSink.from_supply(self.gnd, self.vdd, | ||||||||||||||
voltage_limit_tolerance=(-0.3, 0.3) * Volt) | ||||||||||||||
self.sck = self.Port(dio_model_sck) | ||||||||||||||
self.csq = self.Port(dio_model_sck) | ||||||||||||||
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Suggested change
I think most of the pindefs can be reused? |
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self.data = self.Port(DigitalSink.from_bidir(dio_model)) | ||||||||||||||
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if_dio_model = DigitalBidir.from_supply( | ||||||||||||||
self.gnd, self.vdd, | ||||||||||||||
voltage_limit_tolerance=(-0.3, 0.3) * Volt, | ||||||||||||||
input_threshold_factor=(0.3, 0.7), | ||||||||||||||
current_limits=(5 * uAmp, 15 * mAmp) | ||||||||||||||
) | ||||||||||||||
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self.ifa = self.Port(DigitalSource.from_bidir(if_dio_model), optional=True) | ||||||||||||||
self.ifb = self.Port(DigitalSource.from_bidir(if_dio_model), optional=True) | ||||||||||||||
self.ifc = self.Port(DigitalSource.from_bidir(if_dio_model), optional=True) | ||||||||||||||
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def contents(self) -> None: | ||||||||||||||
self.footprint( | ||||||||||||||
'U', 'fp:SO8_PG-DSO-8_INF', | ||||||||||||||
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Suggested change
Can a standard KiCad footprint be used? This one should be compatible, though the pads stretch more on the inside |
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{ | ||||||||||||||
'1': self.ifc, | ||||||||||||||
'2': self.sck, | ||||||||||||||
'3': self.csq, | ||||||||||||||
'4': self.data, | ||||||||||||||
'5': self.ifa, | ||||||||||||||
'6': self.vdd, | ||||||||||||||
'7': self.gnd, | ||||||||||||||
'8': self.ifb | ||||||||||||||
}, | ||||||||||||||
mfr='Infineon', part='Tle5012b', | ||||||||||||||
datasheet='https://www.infineon.com/cms/en/product/sensor/magnetic-sensors/magnetic-position-sensors/angle-sensors/tle5012b-e1000/' | ||||||||||||||
) | ||||||||||||||
self.assign(self.lcsc_part, 'C123083') | ||||||||||||||
self.assign(self.actual_basic_part, False) | ||||||||||||||
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class Tle5012b(Magnetometer, DefaultExportBlock): | ||||||||||||||
"""Angle sensor based on Giant Magneto Resistance (GMR) for precise angular position sensing.""" | ||||||||||||||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Consider quantifying the precision. I think it's a 15-bit angle output? |
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def __init__(self): | ||||||||||||||
super().__init__() | ||||||||||||||
self.ic = self.Block(Tle5012b_Device()) | ||||||||||||||
self.gnd = self.Export(self.ic.gnd, [Common]) | ||||||||||||||
self.pwr = self.Export(self.ic.vdd, [Power]) | ||||||||||||||
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self.sck = self.Export(self.ic.sck, optional=True) | ||||||||||||||
self.csq = self.Export(self.ic.csq, optional=True) | ||||||||||||||
self.data = self.Export(self.ic.data, optional=True) | ||||||||||||||
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self.ifa = self.Export(self.ic.ifa, optional=True, | ||||||||||||||
doc="IIF Phase A / Hall Switch Signal 1 / PWM / SPC output (input for SPC trigger only)") | ||||||||||||||
self.ifb = self.Export(self.ic.ifb, optional=True, doc="IIF Phase B / Hall Switch Signal 2") | ||||||||||||||
self.ifc = self.Export(self.ic.ifc, optional=True, doc="External Clock / IIF Index / Hall Switch Signal 3") | ||||||||||||||
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Do you use these? If not, I'd consider leaving these out for simplicity, for now. Part of the reason is that design-side, I'd like the application circuit to provide high-level interfaces, and the application circuit could figure out how to map like PWM to device pins and enforce constraints (such as only one of the IO options can be active) |
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def contents(self): | ||||||||||||||
super().contents() | ||||||||||||||
self.vdd_cap = self.Block(DecouplingCapacitor(100 * nFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) |
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Where'd this come from?
It seems that it can sink up to -25mA and has a pull-up rating of 3uA? I don't see a source current limit even though there's a section on the SSC interface in push-pull configuration.