This repository contains data collected from 50 chips. We designed and fabricated a 65nm CMOS chip with eleven SRAM macros. These macros exercise different memory and chip-level parameters. Several parameters are passed to the SRAM compiler at the memory level, including the number of addresses, words, aspect ratio, and the chosen bitcell. During the floorplan, chip-level decisions are considered, such as the location and rotation of each SRAM macro in the test chip.
These measurements were conducted at the Centre for Hardware Security, Tallinn University of Technology (TalTech), Estonia. The measurement aimed to analyze the impact of design-time decisions and their effect on robustness. The analysis of SRAM-based PUFs can be found in the accompanying paper.
How to cite this work: 1- Z. U. Abideen, R. Wang, T. D. Perez, G. -J. Schrijen and S. Pagliarini, "Impact of Orientation on the Bias of SRAM-Based PUFs," in IEEE Design & Test, doi: 10.1109/MDAT.2023.3322621. 2- @ARTICLE{ZAIN_PUF, author={Abideen, Zain Ul and Wang, Rui and Perez, Tiago Diadami and Schrijen, Geert-Jan and Pagliarini, Samuel}, journal={IEEE Design & Test}, title={Impact of Orientation on the Bias of SRAM-Based PUFs}, year={2023}, volume={}, number={}, pages={1-1}, doi={10.1109/MDAT.2023.3322621}}
The published paper is available on the following link: https://ieeexplore.ieee.org/document/10273403
This work has been partially conducted in the project “ICT programme” which was supported by the European Union through the ESF. It was also supported by EU’s Horizon 2020 R&I programme under Grant Agreement No 872614 (SMART4ALL).