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In this collection you will find the logic gates. Use these blocks in your digital circuits for opensource FPGAs created with icestudio. All the components of this collection are combinational
These are examples of some blocks in this collection:
Find information about collections and how to install them on this link: Installing the iceK collection in Icestudio. It was written for the iceK collection as an example. Use the repo of the icegates collection instead
- Download the ZIP file from the latest release
- ...or get the ZIP file with the latest changes from the main branch: iceGates-main.zip
All the blocks are logic gates with different inputs
There are different types of And Gates: Standard, Bus, Bus enable and Operator
The standard AND gate has 2 inputs. But there are AND gates with more inputs. In this figure, AND gates with 2,3 and 4 inputs are shown:
This example is available on the File/Examples/01-AND-gate/Alhmabra-II/01-AND-gate-buttons-LED menu. It is an example of manually testing a 2-inputs AND gate with two buttons and one LED, for the Alhambra-II ICE40 FPGA board. The LED is only ON when both buttons, SW1 and SW2 are pressed
As the logic gates are foundamental, all the blocks are implemented in Verilog. This is the implementation of the 2-inputs AND gate
//-- AND gate
//-- Verilog implementation
assign c = a & b;You can double click on the block for displaying its implementation:
The AND gates can also have the inputs as a BUS, instead of isolated wires. In this picture AND gates of 2, 4 and 8 bits input buses are shown:
In this example a 2-bit bus input AND is shown. It is equivalent to the example 1: The LED is only turned on when the two buttons are pressed. But this time all the wires used are inside a 2-bit BUS, so the circuit is more compact and easy to read
All the BUS inpt ANDs are implemented using standard ANDs and split blocks. For example, this is the implementation of the BUS-AND2 gate:
This type of ANDs are used for enabling/disabling a BUS. When the en input is 1, the BUS is enable and is shown as the output. When en is 0, the output is 0 (Bus disabled)
In this picture, three Bus-enable ANDs are shown: for 2, 4 and 8 bits Buses:
In this example an AND-Busen4 gate is used for enabling a 4-bits bus. The 4-bits number 0xF (1111 in binary) go throug the AND gate only if the enable input is 1. When the pushbutton SW1 is pressed, the AND is enabled and the 0xF value is shown on the LEDs. When the button is not pressed, all the LEDs are off
Then AND Bus enable gates are implemented using standard AND gates and split blocks. The input bus is split into its individual wires. Each wire is ANDed with the enable input. In this figure it can be seen the implementation of the AND-Busen4 gate:
The AND gate can be used as an operator between two numbers of equal size in bits. The AND operation is performed between each bit of the two input number. For example, given this 4-bits numbers: 0101 and 0011, the result of the AND operation between them is the following 4-bits number: 0001:
0101
0011
----
0001
In this figure the AND-op4 gate is shown:
In this example the AND-OP4 gate is used for doing and AND operation between two 4-bits number: a and b. The b operator is 0000. When the button SW1 is pressed, the operator b is 0011. The operator a is alwais 1010
The AND-opN is implemented by spliting the two operators in their N wires, performing N AND operation between the bits and
joining the results into an output bus
In this picture it is shown the implementation of the AND-op4 gate. It is implemented by means of two AND-op2 gates
The AND-op2 gate is implemented by means of two standard AND gates, as shown in this figure:
There are different types of Or Gates: Standard, Bus and Operator
The standard OR gate has 2 inputs. But there are OR gates with more inputs. In this figure, OR gates with 2,3 and 4 inputs are shown:
This example is available on the File/Examples/05-OR-gate/Alhmabra-II/05-OR-gate-buttons-LED menu. It is an example of manually testing a 2-inputs OR gate with two buttons and one LED, for the Alhambra-II ICE40 FPGA board. The LED is ON when any of the buttons (or both) are pressed
As the logic gates are foundamental, all the blocks are implemented in Verilog. This is the implementation of the 2-inputs OR gate
//-- OR Gate
//-- Verilog implementation
assign c = a | b;You can double click on the block for displaying its implementation:
The OR gates can also have the inputs as a BUS, instead of isolated wires. In this picture OR gates of 2, 4 and 8 bits input buses are shown:
In this example a 2-bit bus input OR is shown. It is equivalent to the example 5: The LED is ON when any of the buttons (or both) are pressed. But this time all the wires used are inside a 2-bit BUS, so the circuit is more compact and easy to read
All the BUS inpt ORs are implemented using standard ORs and split blocks. For example, this is the implementation of the BUS-OR2 gate:
The OR gate can be used as an operator between two numbers of equal size in bits. The OR operation is performed between each bit of the two input number. For example, given this 4-bits numbers: 0101 and 0011, the result of the OR operation between them is the following 4-bits number: 0111:
0101
0011
----
0111
In this figure the OR-op4 gate is shown:
In this example the OR-OP4 gate is used for doing and OR operation between two 4-bits number: a and b. The b operator is 0000. When the button SW1 is pressed, the operator b is 0011. The operator a is always 1010
The OR-opN is implemented by spliting the two operators in their N wires, performing N OR operations between the bits and
joining the results into an output bus
In this picture it is shown the implementation of the OR-op4 gate. It is implemented by means of two OR-op2 gates
The OR-op2 gate is implemented by means of two standard OR gates, as shown in this figure:
There are two types of NOT Gates: Standard and Operator
The standard NOT gate has only 1 input:
This example is available on the File/Examples/08-NOT-gate/Alhmabra-II/08-NOT-button-LED menu. It is an example of manually testing a NOT gate with one button and one LED, for the Alhambra-II ICE40 FPGA board. When the button is not pressed, LED is ON. When the button SW1 is pressed, the LED turns OFF
As the NOT gate is foundamental, it is implemented in Verilog:
//-- NOT Gate
assign q = ~a;You can double click on the block for displaying its implementation:
The NOT gate can be used as an unary operator. What it does it to invert all the bits of the input number. For example, given this 4-bits number 0101, the result of the NOT operation the following 4-bits number: 1010
0101
---- NOT
1010
In this figure the NOT-4 gate is shown:
In this example the NOT-4 gate is used for inverting the bits of a 4-bits number. If the buton is not pressed, the operand a is 0000, so that all the LEDs are ON. When the button is pressed the operand is 0101. The result is the number1010 that is shown on the LEDS
The NOT-N is implemented by spliting the input number into their N wires, and inverting each bit. Then, the N results are joined into an output bus
In this picture it is shown the implementation of the NOT-4 gate. It is implemented by means of four standard NOT gates
There are two types of Xor Gates: Standard and Operator
The standard XOR gate has 2 inputs:
This example is available on the File/Examples/10-XOR-gate/Alhmabra-II/10-XOR-gate-buttons-LED menu. It is an example of manually testing a 2-inputs XOR gate with two buttons and one LED, for the Alhambra-II ICE40 FPGA board
The XOR gate can be constructed from previous gates (AND, OR, NOT). But it can also be implemented using Verilog:
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;You can double click on the block for displaying its implementation:
The XOR gate can be used as an operator between two numbers of equal size in bits. The XOR operation is performed between each bit of the two input number. For example, given this 4-bits numbers: 0101 and 0011, the result of the XOR operation between them is the following 4-bits number: 0110:
0101
0011
----
0110
In this figure the XOR-op4 gate is shown:
In this example the XOR-OP4 gate is used for doing and XOR operation between two 4-bits number: a and b. The b operator is 0000. When the button SW1 is pressed, the operator b is 0011. The operator a is always 1010
The XOR-opN is implemented by spliting the two operators in their N wires, performing N XOR operations between the bits and
joining the results into an output bus
In this picture it is shown the implementation of the XOR-op4 gate. It is implemented by means of two XOR-op2 gates
The XOR-op2 gate is implemented by means of two standard XOR gates, as shown in this figure:
There are two types of Xnor Gates: Standard and Operator
The standard XNOR gate has 2 inputs:
This example is available on the File/Examples/12-XNOR-gate/Alhmabra-II/12-XNOR-gate-buttons-LED menu. It is an example of manually testing a 2-inputs XNOR gate with two buttons and one LED, for the Alhambra-II ICE40 FPGA board
The XNOR gate is implemented using other blocks: the XOR and NOT
You can double click on the block for displaying its implementation:
The XNOR gate can be used as an operator between two numbers of equal size in bits. The XNOR operation is performed between each bit of the two input number. For example, given this 4-bits numbers: 0101 and 0011, the result of the XNOR operation between them is the following 4-bits number: 1001. The meaning of the XNOR is equal. The corresponding bit is 1 if the two bits are equal. It is 0 if the bits are different
0101
0011
----
1001
In this figure the XNOR-op4 gate is shown:
In this example the XNOR-OP4 gate is used for doing and XNOR operation between two 4-bits number: a and b. The b operator is 0000. When the button SW1 is pressed, the operator b is 0011. The operator a is always 1010
The XNOR-opN is implemented by spliting the two operators in their N wires, performing N XNOR operations between the bits and
joining the results into an output bus
In this picture it is shown the implementation of the XNOR-op4 gate. It is implemented by means of two XNOR-op2 gates
The XNOR-op2 gate is implemented by means of two standard XNOR gates, as shown in this figure:
The NAND Gate is an AND gate connected to a NOT gate. This gate is important because all the other can be implemented by connecting only NANDs gates. This is a 2 inputs NAND gate:
This example is available on the File/Examples/14-NAND-gate/Alhmabra-II/14-NAND-gate-buttons-LED menu. It is an example of manually testing a 2-inputs NAND gate with two buttons and one LED, for the Alhambra-II ICE40 FPGA board. The LED is only OFF when both buttons, SW1 and SW2 are pressed
The NAND gate is implemented by connecting the AND and NOT gates
The NOR Gate is an OR gate connected to a NOT gate. This gate is important because all the other can be implemented by connecting only NOR gates. This is a 2 inputs NOR gate:
This example is available on the File/Examples/15-NOR-gate/Alhmabra-II/15-NOR-gate-buttons-LED menu. It is an example of manually testing a 2-inputs NOR gate with two buttons and one LED, for the Alhambra-II ICE40 FPGA board. The LED is OFF when any button (or both) are pressed
The NOR gate is implemented by connecting the OR and NOT gates
The collection can be translated to any language. Any translation is very welcome!! 😀️ If you want to translate it to your native languaje please follow these instructions: Translating the collection into your language. This instructions are for the iceK collection, but the translation procedure is the same for any other collection
The Organization of this collections is exactly the same than all the other collections. It consist of the following folders:
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blocks: This is were the icestudio blocks are located, with all the elements of the collection, organized by subfolders -
examples: Circuit examples ready to use in Icestudio. Inside this examples there are some special elements:-
00-Index.ice: Collection indexe. Here you will see some of the more important blocks that the collection contains -
TESTs: This is used by the collection developer for testing the different blocks. Everytime a block is added, it should be tested somehow. That tests are in that folder. This is not likely for the standar user, so you can skip it
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icons: Here you will find the SVG files for the icons used in the collection blocks. You can edit them or create new icons from them-
block+icon: Some of the blocks in SVG, for using them in your documentations. These are some examples:
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locale: Folder with the English texts and their translation into other languages -
wiki: Images used in this wiki
This is the Index file:
- 00-Index.ice:
Contributions are welcome! 😀️
You can contribute in different manners:
- Adding new blocks
- Translating the collection to your language
- Migrating the examples to more boards
These are the steps to follow for contributing:
- Fork the icegates repo into your github account
- Clone it to your computer
- Install the collection as an external collection, so that you can access it from icestudio (See: Other uses: External collection)
- Create your own block (See Creating new blocks)
- Save it and click on Tools/Collection/Reload for using it and testing it
- Commit and push to your repo
- Emit a pull request
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The main language is English: Create all your blocks and examples in English (the English text should be inside de .ice files). Then translate it to your local language (if you like), following the instructions mentioned here: Translating the collection into your language
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The icegate collection is ONLY FOR LOGIC GATES. If you want to contribute with other type of blocks, do it in its corresponding collection (iceMux, iceRegs, iceFF....)
