KTU_MLAB_Digital_Chip

KTU_MLAB_chip/design_data/sdc/top_square.sdc

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+# GLOBAL PARAMS
+
+set CYCLE 10
+set INPUT_DLY [expr 0.5*$CYCLE]
+set OUTPUT_DLY [expr 0.5*$CYCLE]
+
+
+# CLOCK CONSTRAINTS
+
+# Create 100MHz clock
+create_clock -name clk_100m -period $CYCLE  [get_ports clk_100m]
+
+#Create 25MHz clock
+create_generated_clock -name clk_pix -source [get_port clk_100m] -divide_by 4 [get_pins divider_inst/clk_pix]
+
+# Rising clock edge for each DFF will be 0.2ns
+set_clock_transition 0.2  [get_clocks clk_100m]
+
+# Clock jitter
+set_clock_uncertainty 0.2 [get_clocks clk_100m]
+
+
+# IO CONSTRAINTS
+# Delays outside the chip
+
+# Starting with rising edge of the clk how long it takes the signal to get to the INPUT PORT
+set_input_delay -max $INPUT_DLY -clock clk_100m [remove_from_collection [all_inputs] [get_ports clk_100m]] ;# setup time check
+set_input_delay -min 0 -clock clk_100m [remove_from_collection [all_inputs] [get_ports clk_100m]] ;# hold time check
+# remove_from_collection to skip this delay on the clk input
+
+# Starting with the rising edge of the clk how long it takes the signal to get from the OUTPUT PORT to the EXTERNAL DFF input
+set_output_delay -max $OUTPUT_DLY -clock clk_100m [all_outputs] ;# setup time check
+set_output_delay -min 0 -clock clk_100m [all_outputs] ;# hold time check
+
+# Set a cell that will drive chip input can also set input transition instead
+# set_driving_cell -cell [get_lib_cells MYLIB/INV4] -pin Z [remove_from_collection [all_inputs] [get_ports clk_100m]]
+# Alternatively set transition manually
+set_input_transition 0.5 [all_inputs]
+
+# And set the capacitance on chip outputs
+set_load 0.05 [all_outputs]
+
+
+# DRV (DESIGN RULE VIOLATION) CONSTRAINTS
+
+# Tools should read the following two command values from .lib automatically
+# Maximum allowed transition time through a net (to fit inside the delay table in .lib)
+#set_max_transition 3 [all_inputs]
+# Maximum capacitive load of a net (to fit inside the delay table in .lib)
+#set_max_capacitance 0.15 [all_inputs]
+
+#set_max_fanout 10 [all_inputs]
+
+set_wireload 0.05
+
+
+

KTU_MLAB_chip/design_data/verilog/clock_divider.v

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+module clock_divider(
+	input clk_100m,
+	input btn_rst,
+	output clk_pix
+);
+
+// Turn 100MHz clock to 25MHz for pixel output
+
+	reg clk_pix_reg;
+    reg [15:0] cnt;
+
+	assign clk_pix = clk_pix_reg;
+/*
+    always @(posedge clk_100m or posedge btn_rst) begin// For every four posedge clk we get one posedge pix_stb
+        cnt <= !cnt;
+        clk_pix_reg <= clk_pix_reg;
+        if(btn_rst)begin
+            clk_pix_reg <= 0;
+            cnt <= 0;
+        end
+        else if(cnt)
+            clk_pix_reg <= !clk_pix_reg;
+    end
+*/
+	always @(posedge clk_100m or posedge btn_rst) begin// For every four posedge clk we get one posedge pix_stb
+        if(btn_rst)begin
+            clk_pix_reg <= 0;
+            cnt <= 0;
+		end
+		else begin
+			cnt <= !cnt;
+			if(cnt)
+				clk_pix_reg <= !clk_pix_reg;
+			else
+        		clk_pix_reg <= clk_pix_reg;
+		end
+    end
+endmodule

KTU_MLAB_chip/design_data/verilog/simple_480p.v

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+module simple_480p (
+    input  wire clk_pix,   // pixel clock
+    input  wire rst_pix,   // reset in pixel clock domain
+    output reg [9:0] sx,  // horizontal screen position
+    output reg [9:0] sy,  // vertical screen position
+    output reg hsync,     // horizontal sync
+    output reg vsync,     // vertical sync
+    output reg de         // data enable (low in blanking interval)
+    );
+
+    // horizontal timings
+    parameter HA_END = 639;           // end of active pixels
+    parameter HS_STA = HA_END + 16;   // sync starts after front porch
+    parameter HS_END = HS_STA + 96;   // sync ends
+    parameter LINE   = 799;           // last pixel on line (after back porch)
+
+    // vertical timings
+    parameter VA_END = 479;           // end of active pixels
+    parameter VS_STA = VA_END + 10;   // sync starts after front porch
+    parameter VS_END = VS_STA + 2;    // sync ends
+    parameter SCREEN = 524;           // last line on screen (after back porch)
+
+    always @(*) begin
+        hsync = ~(sx >= HS_STA && sx < HS_END);  // invert: negative polarity
+        vsync = ~(sy >= VS_STA && sy < VS_END);  // invert: negative polarity
+        de = (sx <= HA_END && sy <= VA_END);
+    end
+
+    // calculate horizontal and vertical screen position
+    always @(posedge clk_pix or posedge rst_pix) begin
+        if(rst_pix)begin
+            sx <= 0;
+            sy <= 0;
+        end
+        else if (sx == LINE) begin  // last pixel on line?
+            sx <= 0;
+            sy <= (sy == SCREEN) ? 0 : sy + 1;  // last line on screen?
+        end else
+            sx <= sx + 1;
+    end
+endmodule

KTU_MLAB_chip/design_data/verilog/top_square.v

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+module top_square (
+    input  wire clk_100m,     // 100 MHz clock
+    input  wire btn_rst,      // reset button
+    output reg vga_hsync,    // VGA horizontal sync
+    output reg vga_vsync,    // VGA vertical sync
+    output reg [3:0] vga_r,  // 4-bit VGA red
+    output reg [3:0] vga_g,  // 4-bit VGA green
+    output reg [3:0] vga_b   // 4-bit VGA blue
+);
+    // Sync signals and coordinates
+    localparam CORDW = 10;  // screen coordinate width in bits
+    wire [CORDW-1:0] sx, sy;
+    wire hsync, vsync, de;
+
+	wire clk_pix;
+
+	clock_divider divider_inst(
+		.clk_100m(clk_100m),
+		.btn_rst(btn_rst),
+		.clk_pix(clk_pix)
+	);
+
+    simple_480p display_inst (
+        .clk_pix(clk_pix),
+        .rst_pix(btn_rst),   // reset logic
+        .sx(sx),
+        .sy(sy),
+        .hsync(hsync),
+        .vsync(vsync),
+        .de(de)
+    );
+
+    // Define a square with screen coordinates
+    reg square;
+    always @(*) begin
+        // Square only
+        //square = (sx > 220 && sx < 420) && (sy > 140 && sy < 340);
+        // Square with line around screen border
+        square = (sx > 220 && sx < 420) && (sy > 140 && sy < 340)
+                 || (sy==0) || (sx==0) || (sy==479) || (sx==639);
+    end
+
+    // Paint color: white inside square, blue outside
+    reg [3:0] paint_r, paint_g, paint_b;
+    always @(*) begin
+        paint_r = (square) ? 4'hF : 4'h1;
+        paint_g = (square) ? 4'hF : 4'h3;
+        paint_b = (square) ? 4'hF : 4'h7;
+    end
+
+    // Display color: paint color but black in blanking interval
+    reg [3:0] display_r, display_g, display_b;
+    always @(*) begin
+        display_r = (de) ? paint_r : 4'h0;
+        display_g = (de) ? paint_g : 4'h0;
+        display_b = (de) ? paint_b : 4'h0;
+    end
+
+    // VGA Pmod output
+    always @(posedge clk_pix) begin
+        vga_hsync <= hsync;
+        vga_vsync <= vsync;
+        vga_r <= display_r;
+        vga_g <= display_g;
+        vga_b <= display_b;
+    end
+endmodule

KTU_MLAB_chip/doc/.gitignore

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+build/
+build.log

KTU_MLAB_chip/doc/Makefile

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+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS     ?= -j auto -w build.log
+SPHINXBUILD   ?= sphinx-build
+SOURCEDIR     = source
+BUILDDIR      = build
+
+.DEFAULT_GOAL := docs
+
+#docs: clean setup build display
+docs: clean  build display
+
+
+.ONESHELL:
+clean:
+	@rm -rf $(BUILDDIR)
+	@rm -rf build.log
+
+build:
+	@$(SPHINXBUILD) -M "html" "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+# Put it first so that "make" without argument is like "make help".
+help:
+	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+
+.ONESHELL:
+display:
+	@cd $(BUILDDIR)/html
+	@xdg-open index.html

KTU_MLAB_chip/doc/requirements.txt

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+sphinx==7.1.2
+sphinx-rtd-theme==1.3.0rc1

KTU_MLAB_chip/doc/source/conf.py

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+# Configuration file for the Sphinx documentation builder.
+
+# -- Project information
+
+project = 'Amazing Design'
+copyright = '2024, IHP Open PDK'
+author = 'Amazing Design Authors'
+
+release = '0.1'
+version = '0.1.0'
+
+# -- General configuration
+
+extensions = [
+    'sphinx.ext.duration',
+    'sphinx.ext.doctest',
+    'sphinx.ext.autodoc',
+    'sphinx.ext.autosummary',
+    'sphinx.ext.intersphinx',
+]
+
+intersphinx_mapping = {
+    'python': ('https://docs.python.org/3/', None),
+    'sphinx': ('https://www.sphinx-doc.org/en/master/', None),
+}
+intersphinx_disabled_domains = ['std']
+
+templates_path = ['_templates']
+
+# -- Options for HTML output
+
+html_theme = 'sphinx_rtd_theme'
+
+# -- Options for EPUB output
+epub_show_urls = 'footnote'

KTU_MLAB_chip/doc/source/designdata.rst

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+Design data and design process description
+############################################
+
+
+Document the design process here and comment on the design data. 
+

KTU_MLAB_chip/doc/source/index.rst

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+
+********************************************************
+Welcome to Amazing Design Open Source PDK documentation!
+********************************************************
+
+
+.. toctree::
+    :hidden:
+
+    specification
+    designdata
+    validation
+
+.. warning::
+    This documentation is currently a **work in progress**.
+
+.. image:: _static/IHP_logo.png
+    :align: center
+    :alt: IHP Logo Image.
+    :width: 400
+

KTU_MLAB_chip/doc/source/specification.rst

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+Specification of the Amazing Design
+###################################
+
+
+Provide your specification here. Consider comparison with other stat of an art designs. 
+

KTU_MLAB_chip/doc/source/validation.rst

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+Validation  of the Amazing Design
+#################################
+
+
+Document the measurement results here.
+

KTU_MLAB_chip/val/readme.md

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+VGA driver on SG13G2 PDK