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Merge pull request #68 from arturum1/master
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Update IOBSOC submodule and make necessary changes; Fix compatibility with subclasses of this SoC.
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@jjts
jjts authored Dec 22, 2023
2 parents bbb7a1d + d134d7b commit 113f8de
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Showing 20 changed files with 185 additions and 240 deletions.
21 changes: 17 additions & 4 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,19 @@ on:

jobs:

uart16550:
runs-on: self-hosted
timeout-minutes: 5
# run even if previous job failed
if: ${{ !cancelled() }}

steps:
- uses: actions/checkout@v3
with:
submodules: 'recursive'
- name: run uart16550 test
run: nix-shell --run "make -C submodules/UART16550/ clean build-setup && make -C submodules/iob_uart16550_V0.10/ sim-run"

iverilog-baremetal:
runs-on: self-hosted
timeout-minutes: 30
Expand All @@ -36,8 +49,8 @@ jobs:
- name: clean
run: nix-shell --run "make clean"
- name: setup init_mem ext_mem
run: nix-shell --run "make setup INIT_MEM=1"
- name: verilator test
run: nix-shell --run "make setup INIT_MEM=1 RUN_LINUX=0"
- name: icarus test
run: nix-shell --run "make -C ../iob_soc_o* sim-run"

verilator-baremetal:
Expand All @@ -52,8 +65,8 @@ jobs:
submodules: 'recursive'
- name: clean
run: nix-shell --run "make clean"
- name: setup init_mem ext_mem
run: nix-shell --run "make setup INIT_MEM=0"
- name: setup no_init_mem ext_mem
run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0"
- name: verilator test
run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator"

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10 changes: 3 additions & 7 deletions hardware/simulation/sim_build.mk
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Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
# Add iob_soc_opencryptolinux software as a build dependency
HEX+=iob_soc_opencryptolinux_boot.hex iob_soc_opencryptolinux_firmware.hex

ROOT_DIR :=../..
include ../../software/sw_build.mk
include $(ROOT_DIR)/software/sw_build.mk

VTOP:=iob_soc_opencryptolinux_tb

Expand All @@ -13,15 +14,10 @@ VTOP:=iob_soc_opencryptolinux_sim_wrapper

endif

CONSOLE_CMD=../../scripts/console.py -L
CONSOLE_CMD ?=../../scripts/console.py -L

GRAB_TIMEOUT ?= 3600

TEST_LIST+=test1
test1:
make -C ../../ fw-clean SIMULATOR=$(SIMULATOR) && make -C ../../ sim-clean SIMULATOR=$(SIMULATOR) && make run SIMULATOR=$(SIMULATOR)

# Include the UUT configuration if iob-soc is used as a Tester
ifneq ($(wildcard uut_build_for_iob_soc_opencryptolinux.mk),)
include uut_build_for_iob_soc_opencryptolinux.mk
endif
208 changes: 124 additions & 84 deletions hardware/simulation/src/iob_soc_opencryptolinux_sim_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -8,32 +8,42 @@
//Peripherals _swreg_def.vh file includes.
`include "iob_soc_opencryptolinux_periphs_swreg_def.vs"

`ifndef IOB_ETH_SWREG_ADDR_W
`define IOB_ETH_SWREG_ADDR_W 12
`endif

module iob_soc_opencryptolinux_sim_wrapper (
output trap_o,
//tester uart
input uart_avalid,
input [`IOB_UART_SWREG_ADDR_W-1:0] uart_addr,
input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_wdata,
input [3:0] uart_wstrb,
output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_rdata,
output uart_ready,
output uart_rvalid,
input [1-1:0] clk_i, //V2TEX_IO System clock input.
input [1-1:0] rst_i //V2TEX_IO System reset, asynchronous and active high.
`include "clk_rst_s_port.vs"
output trap_o,

`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_ETHERNET
// Ethernet for testbench
input ethernet_valid_i,
input [`IOB_ETH_SWREG_ADDR_W-1:0] ethernet_addr_i,
input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_wdata_i,
input [3:0] ethernet_wstrb_i,
output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_rdata_o,
output ethernet_ready_o,
output ethernet_rvalid_o,
`endif

// UART for testbench
input uart_valid_i,
input [`IOB_UART_SWREG_ADDR_W-1:0] uart_addr_i,
input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_wdata_i,
input [3:0] uart_wstrb_i,
output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_rdata_o,
output uart_ready_o,
output uart_rvalid_o
);

localparam AXI_ID_W = 4;
localparam AXI_LEN_W = 8;
localparam AXI_ADDR_W = `DDR_ADDR_W;
localparam AXI_DATA_W = `DDR_DATA_W;

wire clk = clk_i;
wire cke = 1'b1;
wire arst = rst_i;

`include "iob_soc_opencryptolinux_wrapper_pwires.vs"


/////////////////////////////////////////////
// TEST PROCEDURE
//
Expand All @@ -58,12 +68,19 @@ module iob_soc_opencryptolinux_sim_wrapper (
.AXI_DATA_W(AXI_DATA_W)
) soc0 (
`include "iob_soc_opencryptolinux_pportmaps.vs"
.clk_i (clk),
.cke_i (cke),
.arst_i(arst),
.clk_i (clk_i),
.cke_i (1'b1),
.arst_i(arst_i),
.trap_o(trap_o)
);


// interconnect clk and arst
wire clk_interconnect;
wire arst_interconnect;
assign clk_interconnect = clk_i;
assign arst_interconnect = arst_i;

`include "iob_soc_opencryptolinux_interconnect.vs"

//instantiate the axi memory
Expand All @@ -78,57 +95,25 @@ module iob_soc_opencryptolinux_sim_wrapper (
) ddr_model_mem (
`include "iob_memory_axi_s_portmap.vs"

.clk_i(clk),
.rst_i(arst)
.clk_i(clk_i),
.rst_i(arst_i)
);

//finish simulation on trap
/* //Sut
always @(posedge trap[0]) begin
#10 $display("Found SUT CPU trap condition");
$finish;
end
//IOb-SoC
always @(posedge trap[1]) begin
#10 $display("Found iob_soc CPU trap condition");
$finish;
end */

//sram monitor - use for debugging programs
/*
wire [`IOB_SOC_SRAM_ADDR_W-1:0] sram_daddr = uut.int_mem0.int_sram.d_addr;
wire sram_dwstrb = |uut.int_mem0.int_sram.d_wstrb & uut.int_mem0.int_sram.d_valid;
wire sram_drdstrb = !uut.int_mem0.int_sram.d_wstrb & uut.int_mem0.int_sram.d_valid;
wire [`IOB_SOC_DATA_W-1:0] sram_dwdata = uut.int_mem0.int_sram.d_wdata;
wire sram_iwstrb = |uut.int_mem0.int_sram.i_wstrb & uut.int_mem0.int_sram.i_valid;
wire sram_irdstrb = !uut.int_mem0.int_sram.i_wstrb & uut.int_mem0.int_sram.i_valid;
wire [`IOB_SOC_SRAM_ADDR_W-1:0] sram_iaddr = uut.int_mem0.int_sram.i_addr;
wire [`IOB_SOC_DATA_W-1:0] sram_irdata = uut.int_mem0.int_sram.i_rdata;
always @(posedge sram_dwstrb)
if(sram_daddr == 13'h090d) begin
#10 $display("Found CPU memory condition at %f : %x : %x", $time, sram_daddr, sram_dwdata );
//$finish;
end
*/
//Manually added testbench uart core. RS232 pins attached to the same pins
//of the iob_soc UART0 instance to communicate with it
// The interface of iob_soc UART0 is assumed to be the first portmapped interface (UART_*)
iob_uart uart_tb (
.clk_i (clk),
.cke_i (cke),
.arst_i(arst),

.iob_avalid_i(uart_avalid),
.iob_addr_i (uart_addr),
.iob_wdata_i (uart_wdata),
.iob_wstrb_i (uart_wstrb),
.iob_rdata_o (uart_rdata),
.iob_rvalid_o(uart_rvalid),
.iob_ready_o (uart_ready),
.clk_i (clk_i),
.cke_i (1'b1),
.arst_i(arst_i),

.iob_valid_i(uart_valid_i),
.iob_addr_i (uart_addr_i),
.iob_wdata_i (uart_wdata_i),
.iob_wstrb_i (uart_wstrb_i),
.iob_rdata_o (uart_rdata_o),
.iob_rvalid_o(uart_rvalid_o),
.iob_ready_o (uart_ready_o),

.txd_o(uart_rxd_i),
.rxd_i(uart_txd_o),
Expand All @@ -142,31 +127,86 @@ always @(posedge trap[1]) begin
reg [1:0] eth_cnt = 2'b0;
reg eth_clk;

always @(posedge clk) begin
always @(posedge clk_i) begin
eth_cnt <= eth_cnt + 1'b1;
eth_clk <= eth_cnt[1];
end

// Ethernet Interface signals
assign ETHERNET0_RX_CLK = eth_clk;
assign ETHERNET0_TX_CLK = eth_clk;
assign ETHERNET0_PLL_LOCKED = 1'b1;

//add core test module in testbench
iob_eth_tb_gen eth_tb (
.clk (clk),
.reset(arst),

// This module acts like a loopback
.RX_CLK (ETHERNET0_TX_CLK),
.RX_DATA(ETHERNET0_TX_DATA),
.RX_DV (ETHERNET0_TX_EN),

// The wires are thus reversed
.TX_CLK (ETHERNET0_RX_CLK),
.TX_DATA(ETHERNET0_RX_DATA),
.TX_EN (ETHERNET0_RX_DV)
);
assign ETH0_MRxClk = eth_clk;
assign ETH0_MTxClk = eth_clk;

//Manually added testbench ethernet core. MII pins attached to the same pins
//of the iob_soc ETH0 instance to communicate with it
// The interface of iob_soc ETH0 is assumed to be the first portmapped interface (ETH_*)
iob_eth
#(
.AXI_ID_W(AXI_ID_W),
.AXI_ADDR_W(AXI_ADDR_W),
.AXI_DATA_W(AXI_DATA_W),
.AXI_LEN_W(AXI_LEN_W)
) eth_tb (
.inta_o(),
.MTxClk(eth_clk),
.MTxD(ETH0_MRxD),
.MTxEn(ETH0_MRxDv),
.MTxErr(ETH0_MRxErr),
.MRxClk(eth_clk),
.MRxDv(ETH0_MTxEn),
.MRxD(ETH0_MTxD),
.MRxErr(ETH0_MTxErr),
.MColl(1'b0),
.MCrS(1'b0),
.MDC(),
.MDIO(),
.iob_valid_i(ethernet_valid_i),
.iob_addr_i (ethernet_addr_i),
.iob_wdata_i (ethernet_wdata_i),
.iob_wstrb_i (ethernet_wstrb_i),
.iob_rvalid_o(ethernet_rvalid_o),
.iob_rdata_o (ethernet_rdata_o),
.iob_ready_o (ethernet_ready_o),
.axi_awid_o (),
.axi_awaddr_o (),
.axi_awlen_o (),
.axi_awsize_o (),
.axi_awburst_o (),
.axi_awlock_o (),
.axi_awcache_o (),
.axi_awprot_o (),
.axi_awqos_o (),
.axi_awvalid_o (),
.axi_awready_i (1'b0),
.axi_wdata_o (),
.axi_wstrb_o (),
.axi_wlast_o (),
.axi_wvalid_o (),
.axi_wready_i (1'b0),
.axi_bid_i ({AXI_ID_W{1'b0}}),
.axi_bresp_i (2'b0),
.axi_bvalid_i (1'b0),
.axi_bready_o (),
.axi_arid_o (),
.axi_araddr_o (),
.axi_arlen_o (),
.axi_arsize_o (),
.axi_arburst_o (),
.axi_arlock_o (),
.axi_arcache_o (),
.axi_arprot_o (),
.axi_arqos_o (),
.axi_arvalid_o (),
.axi_arready_i (1'b0),
.axi_rid_i ({AXI_ID_W{1'b0}}),
.axi_rdata_i ({AXI_DATA_W{1'b0}}),
.axi_rresp_i (2'b0),
.axi_rlast_i (1'b0),
.axi_rvalid_i (1'b0),
.axi_rready_o (),
.clk_i(clk_i),
.arst_i(arst_i),
.cke_i(1'b1)
);
`endif

endmodule
1 change: 0 additions & 1 deletion hardware/src/arbiter.v
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This file was deleted.

8 changes: 4 additions & 4 deletions hardware/src/iob2axil.v
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ module iob2axil #(
input wire [ 1:0] axil_rresp_i,

// IOb slave interface
input wire iob_avalid_i,
input wire iob_valid_i,
input wire [ ADDR_W-1:0] iob_addr_i,
input wire [ DATA_W-1:0] iob_wdata_i,
input wire [DATA_W/8-1:0] iob_wstrb_i,
Expand All @@ -51,20 +51,20 @@ module iob2axil #(
//

// write address
assign axil_awvalid_o = iob_avalid_i & |iob_wstrb_i;
assign axil_awvalid_o = iob_valid_i & |iob_wstrb_i;
assign axil_awaddr_o = iob_addr_i;
assign axil_awprot_o = 3'd2;

// write
assign axil_wvalid_o = iob_avalid_i & |iob_wstrb_i;
assign axil_wvalid_o = iob_valid_i & |iob_wstrb_i;
assign axil_wdata_o = iob_wdata_i;
assign axil_wstrb_o = iob_wstrb_i;

// write response
assign axil_bready_o = 1'b1;

// read address
assign axil_arvalid_o = iob_avalid_i & ~|iob_wstrb_i;
assign axil_arvalid_o = iob_valid_i & ~|iob_wstrb_i;
assign axil_araddr_o = iob_addr_i;
assign axil_arprot_o = 3'd2;

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