Merge pull request #64 from PedroAntunes178/master

SoC:  Run in Cyclone V; Console enters Non-Canonical mode when necessary; BootLoader is generic and can load any firmware.

.github/workflows/ci.yml

@@ -36,7 +36,7 @@ jobs:
       - name: clean
         run: nix-shell --run "make clean"
       - name: setup init_mem ext_mem
-        run: nix-shell --run "make setup RUN_LINUX=0 INIT_MEM=1"
+        run: nix-shell --run "make setup INIT_MEM=1"
       - name: verilator test
         run: nix-shell --run "make -C ../iob_soc_o* sim-run"
 
@@ -53,25 +53,25 @@ jobs:
       - name: clean
         run: nix-shell --run "make clean"
       - name: setup init_mem ext_mem
-        run: nix-shell --run "make setup RUN_LINUX=0 INIT_MEM=0"
+        run: nix-shell --run "make setup INIT_MEM=0"
       - name: verilator test
         run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator"
 
 
-##  cyclonev-baremetal:
-##    runs-on: self-hosted
-##    timeout-minutes: 60
-##    # run even if previous job failed
-##    if: ${{ !cancelled() }}
-##    # run after indicated job
-##    needs: [ verilator-baremetal ]
-##  
-##    steps:
-##      - uses: actions/checkout@v3
-##        with:
-##          submodules: 'recursive'
-##      - name: cyclonev test
-##        run: make fpga-run RUN_LINUX=0 INIT_MEM=0 BOARD=CYCLONEV-GT-DK
+  cyclonev-baremetal:
+    runs-on: self-hosted
+    timeout-minutes: 60
+    # run even if previous job failed
+    if: ${{ !cancelled() }}
+    # run after indicated job
+    needs: [ verilator-baremetal ]
+
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          submodules: 'recursive'
+      - name: cyclonev test
+        run: make fpga-run RUN_LINUX=0 INIT_MEM=0 BOARD=CYCLONEV-GT-DK
 
   aes-ku040-baremetal:
     runs-on: self-hosted

Makefile

@@ -2,6 +2,7 @@ CORE := iob_soc_opencryptolinux
 
 SIMULATOR ?= icarus
 BOARD ?= AES-KU040-DB-G
+GRAB_TIMEOUT ?= 1800
 
 DISABLE_LINT:=1
 
@@ -23,30 +24,29 @@ endif
 setup:
 	make build-setup SETUP_ARGS="$(SETUP_ARGS)"
 
-test-linux:
+sim-test-linux:
 	nix-shell --run "make clean"
-	nix-shell --run "make setup INIT_MEM=1 RUN_LINUX=1"
-	nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator"
+	nix-shell --run "make setup INIT_MEM=1"
+	nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator RUN_LINUX=1"
 
 sim-test:
-	# IOb-SoC-Opencryptolinux only supports USE_EXTMEM=1
-	#make clean && make setup && make -C ../iob_soc_opencryptolinux_V*/ sim-test
-	#make clean && make setup INIT_MEM=0 && make -C ../iob_soc_opencryptolinux_V*/ sim-test
-	make clean && make setup USE_EXTMEM=1 && make -C ../iob_soc_opencryptolinux_V*/ sim-test
-	make clean && make setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../iob_soc_opencryptolinux_V*/ sim-test
+	nix-shell --run "make clean"
+	nix-shell --run "make setup INIT_MEM=1"
+	nix-shell --run "make -C ../iob_soc_o* sim-run"
+	nix-shell --run "make clean"
+	nix-shell --run "make setup INIT_MEM=0"
+	nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator"
 
 fpga-run:
-	nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) RUN_LINUX=$(RUN_LINUX) && make -C ../$(CORE)_V*/ fpga-fw-build BOARD=$(BOARD)'
-	make -C ../$(CORE)_V*/ fpga-run BOARD=$(BOARD)
+	nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) && make -C ../$(CORE)_V*/ fpga-fw-build BOARD=$(BOARD) RUN_LINUX=$(RUN_LINUX)'
+	make -C ../$(CORE)_V*/ fpga-run BOARD=$(BOARD) GRAB_TIMEOUT=$(GRAB_TIMEOUT) RUN_LINUX=$(RUN_LINUX)
 
 fpga-test:
-	# IOb-SoC-Opencryptolinux only supports USE_EXTMEM=1
-	make clean setup fpga-run INIT_MEM=0 USE_EXTMEM=1
+	# IOb-SoC-Opencryptolinux always uses external memory
+	make clean setup fpga-run INIT_MEM=0
 
 test-all:
-	make clean && make setup && make -C ../iob_soc_opencryptolinux_V*/ pc-emul-test
-	#make sim-test SIMULATOR=icarus
-	make sim-test SIMULATOR=verilator
+	make sim-test
 	make fpga-test BOARD=CYCLONEV-GT-DK
 	make fpga-test BOARD=AES-KU040-DB-G
 	make clean && make setup && make -C ../iob_soc_opencryptolinux_V*/ doc-test

hardware/simulation/src/iob_soc_opencryptolinux_sim_wrapper.v

@@ -70,7 +70,7 @@ module iob_soc_opencryptolinux_sim_wrapper (
    //IOb-SoC-OpenCryptoLinux and SUT access the same memory.
    axi_ram #(
 `ifdef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM
-      .FILE      ("init_ddr_contents.hex"),  //This file contains firmware for both systems
+      .FILE      ("init_ddr_contents"),  //This file contains firmware for both systems
 `endif
       .ID_WIDTH  (AXI_ID_W),
       .DATA_WIDTH(AXI_DATA_W),

hardware/src/axi_ram.v

@@ -166,33 +166,47 @@ module axi_ram #(
   assign axi_rlast_o   = PIPELINE_OUTPUT ? axi_rlast_pipe_reg : axi_rlast_reg;
   assign axi_rvalid_o  = PIPELINE_OUTPUT ? axi_rvalid_pipe_reg : axi_rvalid_reg;
 
-  localparam mem_init_file_int = FILE;
-
-  initial begin
-    if (mem_init_file_int != "none") begin
-      $readmemh(mem_init_file_int, mem, 0, 2 ** VALID_ADDR_WIDTH - 1);
-    end
-  end
-
   generate
     genvar i;
-    for (i = 0; i < WORD_WIDTH; i = i + 1) begin : g_Bytes_in_word
-      if (READ_ON_WRITE) begin : g_always_read
-        always @(posedge clk_i) begin
-          if (mem_wr_en & axi_wstrb_i[i]) begin
-            mem[write_addr_valid][WORD_SIZE*i+:WORD_SIZE] <= axi_wdata_i[WORD_SIZE*i+:WORD_SIZE];
-          end
-          axi_rdata_reg[WORD_SIZE*i+:WORD_SIZE] <= mem[read_addr_valid][WORD_SIZE*i+:WORD_SIZE];
+    if (READ_ON_WRITE) begin : g_always_read
+      localparam mem_init_file_int = {FILE, ".hex"};
+      initial begin
+        if (FILE != "none") begin
+          $readmemh(mem_init_file_int, mem, 0, 2 ** VALID_ADDR_WIDTH - 1);
         end
-      end else begin : g_no_read_on_write
+      end
+      for (i = 0; i < WORD_WIDTH; i = i + 1) begin : g_Bytes_in_word
         always @(posedge clk_i) begin
           if (mem_wr_en & axi_wstrb_i[i]) begin
             mem[write_addr_valid][WORD_SIZE*i+:WORD_SIZE] <= axi_wdata_i[WORD_SIZE*i+:WORD_SIZE];
-          end else begin
-            axi_rdata_reg[WORD_SIZE*i+:WORD_SIZE] <= mem[read_addr_valid][WORD_SIZE*i+:WORD_SIZE];
           end
+          axi_rdata_reg[WORD_SIZE*i+:WORD_SIZE] <= mem[read_addr_valid][WORD_SIZE*i+:WORD_SIZE];
         end
       end
+    end else begin : g_no_read_on_write
+      localparam file_suffix = {"7", "6", "5", "4", "3", "2", "1", "0"};
+      wire [VALID_ADDR_WIDTH-1:0] ram_addr_valid;
+      wire [WORD_WIDTH-1:0] ram_en;
+      assign ram_addr_valid = mem_wr_en ? write_addr_valid : read_addr_valid;
+      for (i = 0; i < WORD_WIDTH; i = i + 1) begin : g_Bytes_in_word
+        localparam mem_init_file_int = (FILE != "none") ?
+             {FILE, "_", file_suffix[8*(i+1)-1-:8], ".hex"} : "none";
+        assign ram_en[i] = mem_wr_en ? axi_wstrb_i[i] : 1'b1;
+
+        iob_ram_sp #(
+            .HEXFILE(mem_init_file_int),
+            .ADDR_W (VALID_ADDR_WIDTH),
+            .DATA_W (WORD_SIZE)
+        ) ram (
+            .clk_i(clk_i),
+
+            .en_i  (ram_en[i]),
+            .addr_i(ram_addr_valid),
+            .d_i   (axi_wdata_i[WORD_SIZE*i+:WORD_SIZE]),
+            .we_i  (mem_wr_en),
+            .d_o   (axi_rdata_reg[WORD_SIZE*i+:WORD_SIZE])
+        );
+      end
     end
   endgenerate
 

hardware/src/iob_soc_opencryptolinux.v

@@ -228,7 +228,7 @@ module iob_soc_opencryptolinux #(
       .READ_ON_WRITE(1),
 `endif
       .PIPELINE_OUTPUT(2),
-      .FILE("iob_soc_opencryptolinux_boot.hex")
+      .FILE("iob_soc_opencryptolinux_boot")
   ) boot_ram (
       .clk_i(clk_i),
       .rst_i(arst_i),

iob_soc_opencryptolinux.py

@@ -15,6 +15,7 @@
 from iob_spi_master import iob_spi_master
 from axil2iob import axil2iob
 from iob_reset_sync import iob_reset_sync
+from iob_ram_sp import iob_ram_sp
 
 
 class iob_soc_opencryptolinux(iob_soc):
@@ -82,6 +83,7 @@ def _create_submodules_list(cls, extra_submodules=[]):
                 iob_uart16550,
                 axil2iob,
                 iob_reset_sync,
+                iob_ram_sp,
                 # iob_spi_master,
                 (iob_uart, {"purpose": "simulation"}),
             ]
@@ -110,14 +112,12 @@ def _post_setup(cls):
             if os.path.isfile(src_file):
                 shutil.copy2(src_file, dst)
 
-        # If RUN_LINUX is not set, use 3000000 baud in simulation
-        for arg in sys.argv[1:]:
-            if arg == "RUN_LINUX":
-                inplace_change(
-                    os.path.join(cls.build_dir, "hardware/simulation/src/bsp.vh"),
-                    "define BAUD 3000000",
-                    "define BAUD 115200",
-                )
+        # Copy NonCanonical script to scripts build directory
+        dst = f"{cls.build_dir}/scripts"
+        src_file = f"{__class__.setup_dir}/submodules/IOBSOC/submodules/LIB/scripts/noncanonical.py"
+        shutil.copy2(src_file, dst)
+        src_file = f"{__class__.setup_dir}/scripts/check_if_run_linux.py"
+        shutil.copy2(src_file, dst)
 
         # Override periphs_tmp.h of iob-soc with one specific for opencryptolinux
         create_periphs_tmp(

scripts/check_if_run_linux.py

@@ -0,0 +1,53 @@
+#!/usr/bin/env python3
+
+import sys
+
+ROOT_DIR = sys.argv[1]
+if len(sys.argv) > 2:
+    RUN_LINUX = sys.argv[2]
+else:
+    RUN_LINUX = "0"
+
+# Generate "iob_mem.txt" according to which binary firmware the SoC should load to RAM
+
+iob_mem_file = f"{ROOT_DIR}/hardware/iob_mem.txt"
+with open(iob_mem_file, "w") as file:
+    if RUN_LINUX == "1":
+        file.write(
+            "fw_jump.bin 0\nImage 400000\niob_soc.dtb F80000\nrootfs.cpio.gz 1000000"
+        )
+    else:
+        file.write("iob_soc_opencryptolinux_firmware.bin 0")
+
+
+# Fixes existing bsp.h and bsp.vh for Simulation
+
+bsp_file = f"{ROOT_DIR}/software/src/bsp.h"
+with open(bsp_file, "r") as file:
+    content = file.read()
+
+if "define SIMULATION 1" in content:
+    if RUN_LINUX == "1":
+        bsp_file = f"{ROOT_DIR}/hardware/simulation/src/bsp.vh"
+        with open(bsp_file, "w") as file:
+            file.write(
+                "`define BAUD 115200\n`define FREQ 100000000\n`define DDR_DATA_W 32\n`define DDR_ADDR_W 26\n`define SIMULATION 1"
+            )
+
+        bsp_file = f"{ROOT_DIR}/software/src/bsp.h"
+        with open(bsp_file, "w") as file:
+            file.write(
+                "#define BAUD 115200\n#define FREQ 100000000\n#define DDR_DATA_W 32\n#define DDR_ADDR_W 26\n#define SIMULATION 1"
+            )
+    else:
+        bsp_file = f"{ROOT_DIR}/hardware/simulation/src/bsp.vh"
+        with open(bsp_file, "w") as file:
+            file.write(
+                "`define BAUD 3000000\n`define FREQ 100000000\n`define DDR_DATA_W 32\n`define DDR_ADDR_W 26\n`define SIMULATION 1"
+            )
+
+        bsp_file = f"{ROOT_DIR}/software/src/bsp.h"
+        with open(bsp_file, "w") as file:
+            file.write(
+                "#define BAUD 3000000\n#define FREQ 100000000\n#define DDR_DATA_W 32\n#define DDR_ADDR_W 26\n#define SIMULATION 1"
+            )

software/src/iob_soc_opencryptolinux_boot.c

@@ -1,8 +1,8 @@
 #include "bsp.h"
+#include "clint.h"
 #include "iob-uart16550.h"
 #include "iob_soc_opencryptolinux_conf.h"
 #include "iob_soc_opencryptolinux_system.h"
-#include "clint.h"
 
 // defined here (and not in periphs.h) because it is the only peripheral used
 // by the bootloader
@@ -17,6 +17,8 @@
 #define EXT_MEM 0x80000000
 
 int main() {
+  int file_size;
+  char *prog_start_addr;
 
   // init uart
   uart16550_init(UART0_BASE, FREQ / (16 * BAUD));
@@ -35,7 +37,6 @@ int main() {
   uart16550_puts(": DDR in use and program runs from DDR\n");
 
   // address to copy firmware to
-  char *prog_start_addr;
   prog_start_addr = (char *)(EXT_MEM);
 
   while (uart16550_getc() != ACK) {
@@ -44,47 +45,58 @@ int main() {
   }
 
 #ifndef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM
-#ifdef IOB_SOC_OPENCRYPTOLINUX_RUN_LINUX
-
-  // receive firmware from host
-  int file_size = 0;
-  char opensbi[] = "fw_jump.bin";
-  char kernel[] = "Image";
-  char dtb[] = "iob_soc.dtb";
-  char rootfs[] = "rootfs.cpio.gz";
-  file_size = uart16550_recvfile(opensbi, prog_start_addr);
-  prog_start_addr = (char *)(EXT_MEM + 0x00400000);
-  file_size = uart16550_recvfile(kernel, prog_start_addr);
-  prog_start_addr = (char *)(EXT_MEM + 0x00F80000);
-  file_size = uart16550_recvfile(dtb, prog_start_addr);
-  prog_start_addr = (char *)(EXT_MEM + 0x01000000);
-  file_size = uart16550_recvfile(rootfs, prog_start_addr);
-  uart16550_puts(PROGNAME);
-  uart16550_puts(": Loading firmware...\n");
-
-#else
-
-  // receive firmware from host
-  int file_size = 0;
-  char r_fw[] = "iob_soc_opencryptolinux_firmware.bin";
-  file_size = uart16550_recvfile(r_fw, prog_start_addr);
-  uart16550_puts(PROGNAME);
-  uart16550_puts(": Loading firmware...\n");
-
-  // sending firmware back for debug
-  if (file_size)
-    uart16550_sendfile(r_fw, file_size, prog_start_addr);
-  else {
-    uart16550_puts(PROGNAME);
-    uart16550_puts(": ERROR loading firmware\n");
+  file_size = uart16550_recvfile("../iob_mem.txt", prog_start_addr);
+  // compute_mem_load_txt
+  int state = 0;
+  int file_name_count = 0;
+  int file_count = 0;
+  char file_name_array[4][50];
+  long int file_address_array[4];
+  char hexChar = 0;
+  int hexDecimal = 0;
+  int i = 0;
+  for (i = 0; i < file_size; i++) {
+    hexChar = *(prog_start_addr + i);
+    //uart16550_puts(&hexChar); /* Used for debugging. */
+    if (state == 0) {
+      if (hexChar == ' ') {
+        file_name_array[file_count][file_name_count] = '\0';
+        file_name_count = 0;
+        file_address_array[file_count] = 0;
+        file_count = file_count + 1;
+        state = 1;
+      } else {
+        file_name_array[file_count][file_name_count] = hexChar;
+        file_name_count = file_name_count + 1;
+      }
+    } else if (state == 1) {
+      if (hexChar == '\n') {
+        state = 0;
+      } else {
+        if ('0' <= hexChar && hexChar <= '9') {
+          hexDecimal = hexChar - '0';
+        } else if ('a' <= hexChar && hexChar <= 'f') {
+          hexDecimal = 10 + hexChar - 'a';
+        } else if ('A' <= hexChar && hexChar <= 'F') {
+          hexDecimal = 10 + hexChar - 'A';
+        } else {
+          uart16550_puts(PROGNAME);
+          uart16550_puts(": invalid hexadecimal character.\n");
+        }
+        file_address_array[file_count-1] =
+            file_address_array[file_count-1] * 16 + hexDecimal;
+      }
+    }
   }
 
-#endif
+  for (i = 0; i < file_count; i++) {
+    prog_start_addr = (char *)(EXT_MEM + file_address_array[i]);
+    file_size = uart16550_recvfile(file_name_array[i], prog_start_addr);
+  }
 #endif
 
-#ifdef RUN_LINUX
+  uart16550_sendfile("test.log", 12, "Test passed!");
   uart16550_putc((char)DC1);
-#endif
 
   // Clear CPU registers, to not pass arguments to the next
   asm volatile("li a0,0");