Merge pull request #53 from arturum1/master

Fix ci.yml; Rename sources; Update submodules.

.github/workflows/ci.yml

@@ -15,7 +15,6 @@ on:
   push:
     branches:
       - master
-      - python-setup
   # Don't forget to require approval for all outside collaborators
   pull_request:
     branches: '*'
@@ -29,7 +28,6 @@ jobs:
     timeout-minutes: 30
     # run even if previous job failed
     if: ${{ !cancelled() }}
-    # run after indicated job
 
     steps:
       - uses: actions/checkout@v3
@@ -47,7 +45,6 @@ jobs:
     timeout-minutes: 30
     # run even if previous job failed
     if: ${{ !cancelled() }}
-    # run after indicated job
 
     steps:
       - uses: actions/checkout@v3
@@ -73,12 +70,8 @@ jobs:
       - uses: actions/checkout@v3
         with:
           submodules: 'recursive'
-      - name: clean
-        run: nix-shell --run "make clean"
-      - name: setup ext_mem
-        run: nix-shell --run "make setup RUN_LINUX=0 INIT_MEM=0"
       - name: cyclonev test
-        run: make -C ../iob_soc_o* fpga-test BOARD=CYCLONEV-GT-DK
+        run: make fpga-run RUN_LINUX=0 INIT_MEM=0 BOARD=CYCLONEV-GT-DK
 
   aes-ku040-baremetal:
     runs-on: self-hosted
@@ -92,18 +85,14 @@ jobs:
       - uses: actions/checkout@v3
         with:
           submodules: 'recursive'
-      - name: clean
-        run: nix-shell --run "make clean"
-      - name: setup ext_mem
-        run: nix-shell --run "make setup RUN_LINUX=0 INIT_MEM=0"
       - name: ku040 test
-        run: make -C ../iob_soc_o* fpga-test BOARD=AES-KU040-DB-G
+        run: make fpga-run RUN_LINUX=0 INIT_MEM=0 BOARD=AES-KU040-DB-G
 
   doc:
     runs-on: self-hosted
     timeout-minutes: 60
     if: ${{ !cancelled() }}
-    needs: [ cyclonev-baremetal, aes-ku040-baremetal, cyclonev-linux, aes-ku040-linux ]
+    needs: [ cyclonev-baremetal, aes-ku040-baremetal ]
 
     steps:
       - uses: actions/checkout@v3

.gitmodules

@@ -1,6 +1,3 @@
-[submodule "submodules/LIB"]
-	path = submodules/LIB
-	url = [email protected]:IObundle/iob-lib.git
 [submodule "submodules/VEXRISCV"]
 	path = submodules/VEXRISCV
 	url = [email protected]:IObundle/iob-vexriscv.git

Makefile

@@ -1,8 +1,12 @@
 CORE := iob_soc_opencryptolinux
 
+SIMULATOR ?= icarus
+BOARD ?= CYCLONEV-GT-DK
+
 DISABLE_LINT:=1
 
-include submodules/LIB/setup.mk
+LIB_DIR:=submodules/IOBSOC/submodules/LIB
+include $(LIB_DIR)/setup.mk
 
 INIT_MEM ?= 1
 RUN_LINUX ?= 1
@@ -15,18 +19,23 @@ ifeq ($(RUN_LINUX),1)
 SETUP_ARGS += RUN_LINUX
 endif
 
+setup:
+	make build-setup SETUP_ARGS="$(SETUP_ARGS)"
+
 sim-test:
 	# IOb-SoC-Opencryptolinux only supports USE_EXTMEM=1
 	#make clean && make setup && make -C ../iob_soc_opencryptolinux_V*/ sim-test
 	#make clean && make setup INIT_MEM=0 && make -C ../iob_soc_opencryptolinux_V*/ sim-test
 	make clean && make setup USE_EXTMEM=1 && make -C ../iob_soc_opencryptolinux_V*/ sim-test
 	make clean && make setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../iob_soc_opencryptolinux_V*/ sim-test
 
+fpga-run:
+	nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) RUN_LINUX=$(RUN_LINUX) && make -C ../$(CORE)_V*/ fpga-fw-build BOARD=$(BOARD)'
+	make -C ../$(CORE)_V*/ fpga-run BOARD=$(BOARD)
+
 fpga-test:
 	# IOb-SoC-Opencryptolinux only supports USE_EXTMEM=1
-	#make clean && make setup && make -C ../iob_soc_opencryptolinux_V*/ fpga-test
-	#make clean && make setup INIT_MEM=0 && make -C ../iob_soc_opencryptolinux_V*/ fpga-test
-	make clean && make setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../iob_soc_opencryptolinux_V*/ fpga-test
+	make clean setup fpga-run INIT_MEM=0 USE_EXTMEM=1
 
 test-all:
 	make clean && make setup && make -C ../iob_soc_opencryptolinux_V*/ pc-emul-test

default.nix

@@ -0,0 +1 @@
+submodules/IOBSOC/submodules/LIB/scripts/default.nix

hardware/src/arbiter.v

@@ -0,0 +1 @@
+../../submodules/IOBSOC/submodules/AXI/rtl/arbiter.v

hardware/src/iob_soc_opencryptolinux.v

@@ -326,7 +326,7 @@ module iob_soc_opencryptolinux #(
 
 
 
-  boot_ctr #(
+  iob_soc_opencryptolinux_boot_ctr #(
       .DATA_W(UART0_DATA_W),
       .ADDR_W(UART0_ADDR_W)
   ) boot_ctr (

hardware/src/boot_ctr.v → hardware/src/iob_soc_opencryptolinux_boot_ctr.v

@@ -1,6 +1,6 @@
 `timescale 1 ns / 1 ps
 
-module boot_ctr #(
+module iob_soc_opencryptolinux_boot_ctr #(
     parameter ADDR_W = 0,
     parameter DATA_W = 0,
     parameter STRB_W = (DATA_W / 8)

hardware/src/priority_encoder.v

@@ -0,0 +1 @@
+../../submodules/IOBSOC/submodules/AXI/rtl/priority_encoder.v

iob_soc_opencryptolinux.py

@@ -4,14 +4,15 @@
 import shutil
 
 from mk_configuration import update_define
+from verilog_tools import inplace_change
 
 from iob_soc import iob_soc
 from iob_vexriscv import iob_vexriscv
 from iob_uart16550 import iob_uart16550
 from iob_plic import iob_plic
 from iob_clint import iob_clint
 from iob_uart import iob_uart
-from iob_spi import iob_spi
+from iob_spi_master import iob_spi_master
 from axil2iob import axil2iob
 from iob_reset_sync import iob_reset_sync
 
@@ -41,8 +42,8 @@ def _create_instances(cls):
                     parameters={"N_SOURCES": "32", "N_TARGETS": "2"},
                 )
             )
-        if iob_spi in cls.submodule_list:
-            cls.peripherals.append(iob_spi("SPI0", "SPI master peripheral"))
+        if iob_spi_master in cls.submodule_list:
+            cls.peripherals.append(iob_spi_master("SPI0", "SPI master peripheral"))
 
     @classmethod
     def _create_submodules_list(cls, extra_submodules=[]):
@@ -89,9 +90,16 @@ def _post_setup(cls):
             if os.path.isfile(src_file):
                 shutil.copy2(src_file, dst)
 
-        dst = f"{cls.build_dir}/hardware/src"
-        src_file = f"{__class__.setup_dir}/hardware/src/axi_interconnect.v"
-        shutil.copy2(src_file, dst)
+        # If RUN_LINUX is not set, use 3000000 baud in simulation
+        for arg in sys.argv[1:]:
+            if arg == "RUN_LINUX":
+                break
+        else:
+            inplace_change(
+                os.path.join(cls.build_dir, "hardware/simulation/bsp.vh"),
+                "define BAUD 115200",
+                "define BAUD 3000000",
+            )
 
     @classmethod
     def _setup_confs(cls, extra_confs=[]):