Merge pull request #95 from P-Miranda/merge-eth

[WIP] merge: eth-simulation branch into master

.github/workflows/ci.yml

@@ -66,22 +66,22 @@ jobs:
       - name: icarus test
         run: nix-shell --run "make -C ../iob_soc_o* sim-run"
 
-  verilator-baremetal:
-    runs-on: self-hosted
-    timeout-minutes: 90
-    # run even if previous job failed
-    if: ${{ !cancelled() }}
-
-    steps:
-      - uses: actions/checkout@v4
-        with:
-          submodules: 'recursive'
-      - name: clean
-        run: nix-shell --run "make clean"
-      - name: setup no_init_mem ext_mem
-        run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0"
-      - name: verilator test
-        run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator"
+  # verilator-baremetal:
+  #   runs-on: self-hosted
+  #   timeout-minutes: 90
+  #   # run even if previous job failed
+  #   if: ${{ !cancelled() }}
+  #
+  #   steps:
+  #     - uses: actions/checkout@v4
+  #       with:
+  #         submodules: 'recursive'
+  #     - name: clean
+  #       run: nix-shell --run "make clean"
+  #     - name: setup no_init_mem ext_mem
+  #       run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0"
+  #     - name: verilator test
+  #       run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator"
 
 
   cyclonev:
@@ -90,7 +90,7 @@ jobs:
     # run even if previous job failed
     if: ${{ !cancelled() }}
     # run after indicated job
-    needs: [ verilator-baremetal ]
+    needs: [ iverilog-baremetal ]
 
     steps:
       - uses: actions/checkout@v4
@@ -107,7 +107,7 @@ jobs:
     # run even if previous job failed
     if: ${{ !cancelled() }}
     # run after indicated job
-    needs: [ verilator-baremetal ]
+    needs: [ iverilog-baremetal ]
 
     steps:
       - uses: actions/checkout@v4

Makefile

@@ -20,6 +20,9 @@ endif
 setup:
 	make build-setup SETUP_ARGS="$(SETUP_ARGS)"
 
+sim-run:
+	nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) && make -C ../$(CORE)_V*/ sim-run SIMULATOR=$(SIMULATOR)'
+
 sim-test-linux:
 	nix-shell --run "make clean"
 	nix-shell --run "make setup INIT_MEM=1"
@@ -66,4 +69,4 @@ test-linux-fpga-connect: build_dir_name
 	-ln -s minicom_test1.txt $(BUILD_DIR)/hardware/fpga/minicom_linux_script.txt
 	make fpga-connect RUN_LINUX=1 BOOT_FLOW=$(BOOT_FLOW)
 
-.PHONY: sim-test fpga-test test-all test-linux-fpga-connect
+.PHONY: setup sim-run sim-test fpga-test test-all test-linux-fpga-connect

README.md

@@ -46,6 +46,49 @@ make setup
 
 The first time it runs, `nix-shell` will automatically install all the required dependencies. This can take a couple of hours, but after that, you can enjoy IOb-SoC-OpenCryptoLinux and not worry about installing software tools.
 
+## Ethernet simulation
+The ethernet simulation requires setting up dummy interfaces with
+`eth-[SIMULATOR]` that require `sudo`:
+Setup the following interfaces with the commands:
+```bash
+sudo modprobe dummy
+sudo ip link add eth-icarus type dummy
+sudo ifconfig eth-icarus up
+sudo ip link add eth-verilator type dummy
+sudo ifconfig eth-verilator up
+```
+
+#### Make dummy interfaces permanent:
+1. Add `dummy` to `/etc/modules`
+2. Create `/etc/network/if-pre-up.d/dummy-eth-interfaces` with:
+```bash
+#!/usr/bin/env bash
+
+# Create eth-SIMULATOR dummy interfaces
+ip link add eth-icarus type dummy
+ifconfig eth-icarus up
+ip link add eth-verilator type dummy
+ifconfig eth-verilator up
+```
+3. Set script as executable:
+```bash
+# Set script as executable
+sudo chmod +x /etc/network/if-pre-up.d/dummy-eth-interfaces
+```
+
+## Ethernet Receiver MAC Address
+The current ethernet setup uses a fake receiver MAC address (RMAC_ADDR) common
+for all simulators and boards. To receive ethernet packets for any destination
+address, the interface connected to the board needs to be in premiscuous mode.
+Check premiscuous mode with the command:
+```bash
+ip -d link
+# check for promiscuity 1
+```
+Set promiscuity to 1 with the command:
+```bash
+sudo ip link set [interface] promisc on
+```
 
 ## Dependencies
 

hardware/common_src/iob_soc_opencryptolinux_mwrap.v

@@ -0,0 +1,183 @@
+`timescale 1 ns / 1 ps
+
+`include "bsp.vh"
+`include "iob_soc_opencryptolinux_conf.vh"
+`include "iob_utils.vh"
+
+//Peripherals _swreg_def.vh file includes.
+`include "iob_soc_opencryptolinux_periphs_swreg_def.vs"
+
+module iob_soc_opencryptolinux_mwrap #(
+
+`ifdef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM
+    parameter HEXFILE  = "iob_soc_opencryptolinux_firmware",
+`else
+    parameter HEXFILE  = "none",
+`endif
+    parameter BOOT_HEXFILE = "iob_soc_opencryptolinux_boot",
+    parameter MEM_NO_READ_ON_WRITE = 1,        //no simultaneous read/write
+   `include "iob_soc_opencryptolinux_params.vs"
+) (
+   `include "iob_soc_opencryptolinux_io.vs"
+);
+
+`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_EXTMEM
+
+    `include "iob_mwrap_extmem_wires.vs"
+
+    assign axi_awid_o = axi_awid;
+    assign axi_awaddr_o = axi_awaddr;
+    assign axi_awlen_o = axi_awlen;
+    assign axi_awsize_o = axi_awsize;
+    assign axi_awburst_o = axi_awburst;
+    assign axi_awlock_o = axi_awlock;
+    assign axi_awcache_o = axi_awcache;
+    assign axi_awprot_o = axi_awprot;
+    assign axi_awqos_o = axi_awqos;
+    assign axi_awvalid_o = axi_awvalid;
+    assign axi_awready = axi_awready_i;    
+    assign axi_wdata_o = axi_wdata;
+    assign axi_wstrb_o = axi_wstrb;
+    assign axi_wlast_o = axi_wlast;
+    assign axi_wvalid_o = axi_wvalid;
+    assign  axi_wready = axi_wready_i;
+    assign axi_bid = axi_bid_i;   
+    assign axi_bresp = axi_bresp_i;
+    assign axi_bvalid = axi_bvalid_i;
+    assign axi_bready_o = axi_bready;
+    assign axi_arid_o = axi_arid;
+    assign axi_araddr_o = axi_araddr;
+    assign axi_arlen_o = axi_arlen;
+    assign axi_arsize_o = axi_arsize;
+    assign axi_arburst_o = axi_arburst;
+    assign axi_arlock_o = axi_arlock;
+    assign axi_arcache_o = axi_arcache;
+    assign axi_arprot_o = axi_arprot;
+    assign axi_arqos_o = axi_arqos;
+    assign axi_arvalid_o = axi_arvalid;
+    assign axi_arready = axi_arready_i;
+    assign  axi_rid = axi_rid_i;
+    assign  axi_rdata = axi_rdata_i;
+    assign  axi_rresp = axi_rresp_i;
+    assign  axi_rlast = axi_rlast_i;
+    assign  axi_rvalid = axi_rvalid_i;
+    assign axi_rready_o = axi_rready;
+
+
+`endif
+
+
+
+//rom wires
+wire rom_r_valid;
+wire [BOOTROM_ADDR_W-3:0] rom_r_addr;
+wire [DATA_W-1:0] rom_r_rdata;
+
+
+//ram wires
+wire                               i_valid;
+wire          [SRAM_ADDR_W-3:0]    i_addr;
+wire          [     DATA_W-1:0]    i_wdata;
+wire          [   DATA_W/8-1:0]    i_wstrb;
+wire          [     DATA_W-1:0]    i_rdata;
+wire                               d_valid;
+wire          [SRAM_ADDR_W-3:0]    d_addr;
+wire          [     DATA_W-1:0]    d_wdata;
+wire          [   DATA_W/8-1:0]    d_wstrb;
+wire          [     DATA_W-1:0]    d_rdata;
+//
+
+`ifdef USE_SPRAM
+    wire                       spram_en;
+    wire     [SRAM_ADDR_W-3:0] spram_addr;
+    wire     [DATA_W/8-1:0]    spram_we;
+    wire     [DATA_W-1:0]      spram_di;
+    wire     [DATA_W-1:0]      spram_do;
+`endif
+
+iob_soc_opencryptolinux #(
+    `include "iob_soc_opencryptolinux_inst_params.vs"
+)iob_soc_opencryptolinux(
+    `include "iob_soc_opencryptolinux_pportmaps.vs"
+    .clk_i(                             clk_i),
+    .cke_i(                             cke_i),
+    .arst_i(                           arst_i),
+    .trap_o(                           trap_o)
+);
+
+
+
+    `ifdef USE_SPRAM
+        iob_ram_sp_be #(
+            .HEXFILE(HEXFILE),
+            .ADDR_W (SRAM_ADDR_W - 2),
+            .DATA_W (DATA_W)
+        ) main_mem_byte (
+            .clk_i(clk_i),
+            // data port
+            .en_i  (spram_en),
+            .addr_i(spram_addr),
+            .we_i  (spram_we),
+            .d_i   (spram_di),
+            .dt_o  (spram_do)
+        );
+    `else
+        `ifdef IOB_MEM_NO_READ_ON_WRITE
+            iob_ram_dp_be #(
+            .HEXFILE             (HEXFILE),
+            .ADDR_W              (SRAM_ADDR_W - 2),
+            .DATA_W              (DATA_W),
+            .MEM_NO_READ_ON_WRITE(1)
+            ) main_mem_byte (
+            .clk_i(clk_i),
+            // data port
+            .enA_i  (d_valid),
+            .addrA_i(d_addr),
+            .weA_i  (d_wstrb),
+            .dA_i   (d_wdata),
+            .dA_o   (d_rdata),
+
+            // instruction port
+            .enB_i  (i_valid),
+            .addrB_i(i_addr),
+            .weB_i  (i_wstrb),
+            .dB_i   (i_wdata),
+            .dB_o   (i_rdata)
+        );
+        `else  // !`ifdef IOB_MEM_NO_READ_ON_WRITE
+            iob_ram_dp_be_xil #(
+                .HEXFILE(HEXFILE),
+                .ADDR_W (SRAM_ADDR_W - 2),
+                .DATA_W (DATA_W)
+            ) main_mem_byte (
+                .clk_i(clk_i),
+
+                // data port
+                .enA_i  (d_valid),
+                .addrA_i(d_addr),
+                .weA_i  (d_wstrb),
+                .dA_i   (d_wdata),
+                .dA_o   (d_rdata),
+                // instruction port
+                .enB_i  (i_valid),
+                .addrB_i(i_addr),
+                .weB_i  (i_wstrb),
+                .dB_i   (i_wdata),
+                .dB_o   (i_rdata)
+            );
+        `endif
+    `endif 
+
+
+    //rom instatiation
+    iob_rom_sp #(
+        .DATA_W (DATA_W),
+        .ADDR_W (BOOTROM_ADDR_W - 2),
+        .HEXFILE({BOOT_HEXFILE, ".hex"})
+    ) sp_rom0 (
+        .clk_i   (clk_i),
+        .r_en_i  (rom_r_valid),
+        .addr_i  (rom_r_addr),
+        .r_data_o(rom_r_rdata)
+    );
+endmodule

hardware/fpga/Makefile

@@ -35,6 +35,7 @@ include $(FPGA_TOOL)/build.mk
 #include the module's headers and sources
 VHDR += $(wildcard ../src/*.vh) $(wildcard ./src/*.vh)
 VSRC += $(wildcard ../src/*.v) $(wildcard ./src/*.v)
+VSRC += $(wildcard ../common_src/*.v)
 
 ifneq ($(wildcard $(FPGA_TOOL)/$(BOARD)/$(NAME)_fpga_wrapper.v),)
 VSRC+=$(FPGA_TOOL)/$(BOARD)/$(NAME)_fpga_wrapper.v

hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_opencryptolinux_fpga_wrapper_dev.sdc

@@ -0,0 +1,2 @@
+create_clock -name "clk" -period 20.0 [get_ports {clk}]
+create_clock -period 40 [get_ports {ENET_RX_CLK}]

iob_soc_opencryptolinux.py

@@ -254,24 +254,42 @@ def _post_setup(cls):
             with open(cls.build_dir + "/hardware/fpga/fpga_build.mk", "w") as file:
                 file.writelines(contents)
 
+            # Set ETH_IF in sim_build.mk
+            with open(cls.build_dir + "/hardware/simulation/sim_build.mk", "r") as file:
+                contents = file.readlines()
+
+            contents.insert(0, "\n")
+            contents.insert(
+                0,
+                """
+#Lines below were auto generated by iob_soc_opencryptolinux.py
+ETH_IF ?= eth-$(SIMULATOR)
+""",
+            )
+            with open(cls.build_dir + "/hardware/simulation/sim_build.mk", "w") as file:
+                file.writelines(contents)
+
         if cls.is_top_module:
             # Set ethernet MAC address
             append_str_config_build_mk(
-                """
+                f"""
 ### Set Ethernet environment variables
-#Mac address of pc interface connected to ethernet peripheral (based on board name)
+#Eth interface address of pc connected to ethernet peripheral (based on board name)
 $(if $(findstring sim,$(MAKECMDGOALS))$(SIMULATOR),$(eval BOARD=))
 ifeq ($(BOARD),AES-KU040-DB-G)
-RMAC_ADDR ?=989096c0632c
+ETH_IF ?=eno1
 endif
 ifeq ($(BOARD),CYCLONEV-GT-DK)
-RMAC_ADDR ?=309c231e624b
+ETH_IF ?= enp0s31f6
 endif
-RMAC_ADDR ?=000000000000
+# Set a MAC address for console (randomly generated)
+RMAC_ADDR ?=88431eafa897
 export RMAC_ADDR
 #Set correct environment if running on IObundle machines
-ifneq ($(filter pudim-flan sericaia,$(shell hostname)),)
+ifneq ($(filter feynman pudim-flan sericaia,$(shell hostname)),)
 IOB_CONSOLE_PYTHON_ENV ?= /opt/pyeth3/bin/python
+else
+IOB_CONSOLE_PYTHON_ENV ?= {__class__.setup_dir}/submodules/ETHERNET/scripts/pyRawWrapper/pyRawWrapper
 endif
                     """,
                 cls.build_dir,

software/src/iob_soc_opencryptolinux_boot.c

@@ -115,12 +115,8 @@ void console_get_files(int file_count, long int file_address_array[4],
   for (i = 0; i < file_count; i++) {
     file_addr = (char *)(file_start_addr + file_address_array[i]);
     // Receive data from console via Ethernet
-#ifndef SIMULATION
     file_sizes[i] = uart_recvfile_ethernet(file_name_array[i]);
     eth_rcv_file(file_addr, file_sizes[i]);
-#else
-    file_sizes[i] = uart16550_recvfile(file_name_array[i], file_addr);
-#endif
   }
 }
 

software/src/iob_soc_opencryptolinux_firmware.c

@@ -115,15 +115,13 @@ int main() {
   eth_init(ETH0_BASE, &clear_cache);
   eth_wait_phy_rst();
 
-#ifndef SIMULATION
   char buffer[5096];
   // Receive data from console via Ethernet
   uint32_t file_size = uart_recvfile_ethernet("../src/eth_example.txt");
   eth_rcv_file(buffer, file_size);
   uart16550_puts("\nFile received from console via ethernet:\n");
   for (i = 0; i < file_size; i++)
     uart16550_putc(buffer[i]);
-#endif
 
   InitializeCryptoSide(VERSAT0_BASE);