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*: new CPU with AXI interface, CLINT and PLIC; internal interfaces are now AXI as well. #55

Merged
merged 31 commits into from
Oct 18, 2023
Merged

*: new CPU with AXI interface, CLINT and PLIC; internal interfaces are now AXI as well. #55

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e3aba49
_boot.c, OS, ext_mem.v: alteration to make it simillar to how it was …
PedroAntunes178 Aug 9, 2023
b7f7155
Merge remote-tracking branch 'origin/master'
PedroAntunes178 Aug 9, 2023
d6b6129
ext_mem.v: fix merge conflits.
PedroAntunes178 Aug 9, 2023
9ef5455
submodules/SPI: added.
PedroAntunes178 Aug 10, 2023
13e6463
iob_soc_opencryptolinux.py: add SPI peripheral to SoC.
PedroAntunes178 Aug 10, 2023
8344eb8
iob_soc_opencryptolinux.v: change CPU used.
PedroAntunes178 Sep 5, 2023
bb1e904
Merge remote-tracking branch 'origin/master' into new_cpu
PedroAntunes178 Sep 5, 2023
d41f00a
submodules/*: update.
PedroAntunes178 Sep 5, 2023
f0465cf
Merge branch 'IObundle:master' into master
PedroAntunes178 Sep 6, 2023
19a7d62
iob_soc_opencryptolinux.v: aparently cke_i is no longer an input; fix…
PedroAntunes178 Sep 8, 2023
b91cb9e
*: simulation executes until Waiting for Console ACK.
PedroAntunes178 Sep 11, 2023
ba31c22
software/*: iverilog runs bootloader; set custom peripheral addresses.
PedroAntunes178 Sep 12, 2023
193241c
iob2axi.v: create and add to extmem.
PedroAntunes178 Sep 13, 2023
cdac4b9
iob2axi.v: read FSM made (not tested).
PedroAntunes178 Sep 14, 2023
c37f11a
iob2axi.v: write FSM made (not tested).
PedroAntunes178 Sep 14, 2023
df209cd
iob2axi.v: fix errors detected by simulators.
PedroAntunes178 Sep 14, 2023
23d22b1
iob2axi.v, ext_mem.v: small fixes to interface converter.
PedroAntunes178 Sep 15, 2023
71678b6
*: runs part of the firmware.
PedroAntunes178 Sep 15, 2023
f88de02
opencryptolinux.py: add axi interfaces.
PedroAntunes178 Sep 18, 2023
fb72c8c
*: baremetal simulation runs.
PedroAntunes178 Sep 18, 2023
23a09d1
software/*: testing interrupts in baremetal.
PedroAntunes178 Sep 18, 2023
25135bd
iob_soc_opencryptolinux.v: pass PLIC and CLINT slave bus to CPU.
PedroAntunes178 Sep 18, 2023
84a5c02
*: test CLINT firmware.
PedroAntunes178 Sep 21, 2023
0b7f393
software/src/*: use SpinalHDL PLIC and CLINT firmware.
PedroAntunes178 Oct 10, 2023
97ea48c
software/*: firmware is compiled corectly.
PedroAntunes178 Oct 13, 2023
e8fbaf0
int_mem.v: use axi_ram.
PedroAntunes178 Oct 13, 2023
9d2575e
hardware: compiles without errors.
PedroAntunes178 Oct 14, 2023
3cb47fc
iob_soc_opencryptolinux.v: simplify code.
PedroAntunes178 Oct 17, 2023
29a887a
*: SoC runs baremetal firmware.
PedroAntunes178 Oct 18, 2023
eb6988c
submodules/*: update.
PedroAntunes178 Oct 18, 2023
ccce12e
Merge branch 'new_cpu'
PedroAntunes178 Oct 18, 2023
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3 changes: 3 additions & 0 deletions .gitmodules
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Original file line number Diff line number Diff line change
Expand Up @@ -19,3 +19,6 @@
[submodule "submodules/IOBSOC"]
path = submodules/IOBSOC
url = [email protected]:IObundle/iob-soc.git
[submodule "submodules/SPI"]
path = submodules/SPI
url = [email protected]:IObundle/iob-spi.git
3 changes: 2 additions & 1 deletion hardware/simulation/bsp.vh
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
`define BAUD 115200
//`define BAUD 115200
`define BAUD 2000000
`define FREQ 100000000
`define DDR_DATA_W 32
`define DDR_ADDR_W 26
Expand Down
10 changes: 5 additions & 5 deletions hardware/simulation/src/iob_soc_opencryptolinux_sim_wrapper.v
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Expand Up @@ -29,7 +29,7 @@ module iob_soc_opencryptolinux_sim_wrapper (

wire clk = clk_i;
wire cke = 1'b1;
wire rst = rst_i;
wire arst = rst_i;

`include "iob_soc_opencryptolinux_wrapper_pwires.vs"

Expand Down Expand Up @@ -60,7 +60,7 @@ module iob_soc_opencryptolinux_sim_wrapper (
`include "iob_soc_opencryptolinux_pportmaps.vs"
.clk_i (clk),
.cke_i (cke),
.arst_i(rst),
.arst_i(arst),
.trap_o(trap_o)
);

Expand All @@ -80,7 +80,7 @@ module iob_soc_opencryptolinux_sim_wrapper (
`include "iob_memory_axi_s_portmap.vs"

.clk_i(clk),
.rst_i(rst)
.rst_i(arst)
);

//finish simulation on trap
Expand Down Expand Up @@ -121,7 +121,7 @@ always @(posedge trap[1]) begin
iob_uart uart_tb (
.clk_i (clk),
.cke_i (cke),
.arst_i(rst),
.arst_i(arst),

.iob_avalid_i(uart_avalid),
.iob_addr_i (uart_addr),
Expand Down Expand Up @@ -156,7 +156,7 @@ always @(posedge trap[1]) begin
//add core test module in testbench
iob_eth_tb_gen eth_tb (
.clk (clk),
.reset(rst),
.reset(arst),

// This module acts like a loopback
.RX_CLK (ETHERNET0_TX_CLK),
Expand Down
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