Added Versat, crypto software implementations and versat implementations as well. Added tests and they all pass

.github/workflows/ci.yml

@@ -73,7 +73,7 @@ jobs:
 
   cyclonev:
     runs-on: self-hosted
-    timeout-minutes: 60
+    timeout-minutes: 90
     # run even if previous job failed
     if: ${{ !cancelled() }}
     # run after indicated job

.gitmodules

@@ -13,6 +13,9 @@
 [submodule "submodules/SPI"]
 	path = submodules/SPI
 	url = [email protected]:IObundle/iob-spi.git
+[submodule "submodules/VERSAT"]
+	path = submodules/VERSAT
+	url = [email protected]:IObundle/iob-versat.git
 [submodule "submodules/ETHERNET"]
 	path = submodules/ETHERNET
 	url = [email protected]:IObundle/iob-eth.git

default.nix

@@ -0,0 +1,34 @@
+{ pkgs ? import (builtins.fetchTarball {
+  # Descriptive name to make the store path easier to identify
+  name = "nixos-22.11";
+  # Commit hash for nixos-22.11
+  url = "https://github.com/NixOS/nixpkgs/archive/refs/tags/22.11.tar.gz";
+  # Hash obtained using `nix-prefetch-url --unpack <url>`
+  sha256 = "11w3wn2yjhaa5pv20gbfbirvjq6i3m7pqrq2msf0g7cv44vijwgw";
+}) {}}:
+pkgs.mkShell {
+  name = "iob-shell";
+  buildInputs = with pkgs; [     
+    bash
+    gnumake
+    verilog
+    verilator
+    gtkwave
+    python3
+    python3Packages.black
+    python3Packages.parse
+    python3Packages.numpy
+    python3Packages.wavedrom
+    python3Packages.matplotlib
+    python3Packages.scipy
+    python3Packages.pyserial
+    (texlive.combine { inherit (texlive) scheme-medium multirow lipsum catchfile nowidow enumitem placeins xltabular ltablex titlesec makecell datetime fmtcount comment textpos csquotes amsmath cancel listings hyperref biblatex; })
+    (callPackage ./submodules/IOBSOC/submodules/LIB/scripts/riscv-gnu-toolchain.nix { })
+    (callPackage ./submodules/VERSAT/versat.nix { })
+    verible
+    black
+    llvmPackages_14.clangUseLLVM
+    librsvg
+    libreoffice
+  ];
+}

hardware/fpga/quartus/CYCLONEV-GT-DK/linux_build_macros.txt

@@ -1,7 +1,8 @@
 TIMER0_ADDR f2000000
 UART0_ADDR f4000000
-ETH0_ADDR f6000000
-CLINT0_ADDR f8000000
-PLIC0_ADDR fa000000
+VERSAT0_ADDR f6000000
+ETH0_ADDR f8000000
+CLINT0_ADDR fa000000
+PLIC0_ADDR fc000000
 FREQ 50000000
 BAUD 115200

hardware/fpga/vivado/AES-KU040-DB-G/linux_build_macros.txt

@@ -1,7 +1,8 @@
 TIMER0_ADDR f2000000
 UART0_ADDR f4000000
-ETH0_ADDR f6000000
-CLINT0_ADDR f8000000
-PLIC0_ADDR fa000000
+VERSAT0_ADDR f6000000
+ETH0_ADDR f8000000
+CLINT0_ADDR fa000000
+PLIC0_ADDR fc000000
 FREQ 100000000
 BAUD 115200

hardware/simulation/linux_build_macros.txt

@@ -1,7 +1,8 @@
 TIMER0_ADDR f2000000
 UART0_ADDR f4000000
-ETH0_ADDR f6000000
-CLINT0_ADDR f8000000
-PLIC0_ADDR fa000000
+VERSAT0_ADDR f6000000
+ETH0_ADDR f8000000
+CLINT0_ADDR fa000000
+PLIC0_ADDR fc000000
 FREQ 100000000
 BAUD 3000000

hardware/src/units/xunitF.v

@@ -0,0 +1,145 @@
+`timescale 1ns / 1ps
+
+module xunitF #(
+         parameter DELAY_W = 32,
+         parameter DATA_W = 32
+              )
+    (
+    //control
+    input               clk,
+    input               rst,
+
+    input               running,
+    input               run,
+    output              done,
+
+    //input / output data
+    input [DATA_W-1:0]  in0,
+    input [DATA_W-1:0]  in1,
+    input [DATA_W-1:0]  in2,
+    input [DATA_W-1:0]  in3,
+    input [DATA_W-1:0]  in4,
+    input [DATA_W-1:0]  in5,
+    input [DATA_W-1:0]  in6,
+    input [DATA_W-1:0]  in7,
+
+    input [DATA_W-1:0]  in8,
+    input [DATA_W-1:0]  in9,
+
+    (* versat_latency = 16 *) output [DATA_W-1:0] out0,
+    (* versat_latency = 16 *) output [DATA_W-1:0] out1,
+    (* versat_latency = 16 *) output [DATA_W-1:0] out2,
+    (* versat_latency = 16 *) output [DATA_W-1:0] out3,
+    (* versat_latency = 16 *) output [DATA_W-1:0] out4,
+    (* versat_latency = 16 *) output [DATA_W-1:0] out5,
+    (* versat_latency = 16 *) output [DATA_W-1:0] out6,
+    (* versat_latency = 16 *) output [DATA_W-1:0] out7,
+
+    //configurations
+    input [DELAY_W-1:0]         delay0 // Encodes delay
+    );
+
+reg [DELAY_W-1:0] delay;
+reg [31:0] a,b,c,d,e,f,g,h;
+
+assign out0 = a;
+assign out1 = b;
+assign out2 = c;
+assign out3 = d;
+assign out4 = e;
+assign out5 = f;
+assign out6 = g;
+assign out7 = h;
+
+assign done = (delay == 0);
+
+wire [31:0] w = in8;
+wire [31:0] k = in9;
+
+function [31:0] ROTR_32(input [31:0] x,input [4:0] c);
+begin
+   ROTR_32 = (((x) >> (c)) | ((x) << (32 - (c))));
+end
+endfunction
+
+function [31:0] SHR(input [31:0] x,input [4:0] c); 
+begin
+   SHR = ((x) >> (c));
+end
+endfunction
+
+function [31:0] Ch(input [31:0] x,y,z);
+begin
+   Ch = (((x) & (y)) ^ (~(x) & (z)));
+end
+endfunction
+
+function [31:0] Maj(input [31:0] x,y,z); 
+begin 
+   Maj = (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)));
+end
+endfunction
+
+function [31:0] Sigma0_32(input [31:0] x);
+begin
+   Sigma0_32 = (ROTR_32(x, 2) ^ ROTR_32(x,13) ^ ROTR_32(x,22));
+end
+endfunction
+
+function [31:0] Sigma1_32(input [31:0] x);
+begin
+   Sigma1_32 = (ROTR_32(x, 6) ^ ROTR_32(x,11) ^ ROTR_32(x,25));
+end
+endfunction
+
+wire [31:0] T1 = h + Sigma1_32(e) + Ch(e,f,g) + k + w;
+wire [31:0] T2 = Sigma0_32(a) + Maj(a,b,c);
+
+wire [31:0] T1_init = in7 + Sigma1_32(in4) + Ch(in4,in5,in6) + k + w;
+wire [31:0] T2_init = Sigma0_32(in0) + Maj(in0,in1,in2);
+
+reg working;
+
+always @(posedge clk,posedge rst)
+begin
+   if(rst) begin
+      delay <= 0;
+      working <= 0;
+      a <= 0;
+      b <= 0;
+      c <= 0;
+      d <= 0;
+      e <= 0;
+      f <= 0;
+      g <= 0;
+      h <= 0;
+   end else if(run) begin
+      delay <= delay0;
+      working <= 0;
+   end else if(!working) begin
+      if(delay == 0) begin
+         a <= T1_init + T2_init;
+         b <= in0;
+         c <= in1;
+         d <= in2;
+         e <= in3 + T1_init;
+         f <= in4;
+         g <= in5;
+         h <= in6;
+         working <= 1'b1;
+      end else begin
+         delay <= delay - 1;
+      end
+   end else begin
+      a <= T1 + T2;
+      b <= a;
+      c <= b;
+      d <= c;
+      e <= d + T1;
+      f <= e;
+      g <= f;
+      h <= g;
+   end
+end
+
+endmodule

hardware/src/units/xunitM.v

@@ -0,0 +1,108 @@
+`timescale 1ns / 1ps
+
+module xunitM #(
+         parameter DELAY_W = 32,
+         parameter DATA_W = 32
+              )
+    (
+    //control
+    input               clk,
+    input               rst,
+
+    input               running,
+    input               run,
+    output              done,
+
+    //input / output data
+    input [DATA_W-1:0]  in0,
+
+    (* versat_latency = 17 *) output reg [DATA_W-1:0] out0,
+
+    //configurations
+    input [DELAY_W-1:0]         delay0 // Encodes delay
+    );
+
+assign done = 1'b1;
+
+reg [DELAY_W-1:0] delay;
+reg [4:0] latency;
+reg [31:0] w[15:0];
+
+// Extract from array to view on gtkwave
+wire [31:0] w0 = w[0];
+wire [31:0] w1 = w[1];
+wire [31:0] w2 = w[2];
+wire [31:0] w3 = w[3];
+wire [31:0] w4 = w[4];
+wire [31:0] w5 = w[5];
+wire [31:0] w6 = w[6];
+wire [31:0] w7 = w[7];
+wire [31:0] w8 = w[8];
+wire [31:0] w9 = w[9];
+wire [31:0] w10 = w[10];
+wire [31:0] w11 = w[11];
+wire [31:0] w12 = w[12];
+wire [31:0] w13 = w[13];
+wire [31:0] w14 = w[14];
+wire [31:0] w15 = w[15];
+
+function [31:0] ROTR_32(input [31:0] x,input [4:0] c);
+begin
+   ROTR_32 = (((x) >> (c)) | ((x) << (32 - (c))));
+end
+endfunction
+
+function [31:0] SHR(input [31:0] x,input [4:0] c); 
+begin
+   SHR = ((x) >> (c));
+end
+endfunction
+
+function [31:0] sigma0_32(input [31:0] x);
+begin
+   sigma0_32 = (ROTR_32(x, 7) ^ ROTR_32(x,18) ^ SHR(x, 3));
+end
+endfunction
+
+function [31:0] sigma1_32(input [31:0] x);
+begin
+   sigma1_32 = (ROTR_32(x,17) ^ ROTR_32(x,19) ^ SHR(x,10));
+end
+endfunction
+
+wire [31:0] val = (sigma1_32(w[14]) + (w[9]) + sigma0_32(w[1]) + (w[0]));
+
+integer i;
+always @(posedge clk,posedge rst)
+begin
+   if(rst) begin
+      delay <= 0;
+      for(i = 0; i < 16; i = i + 1) 
+         w[i] <= 0;
+   end else if(run) begin
+      delay <= delay0; // wait delay0 cycles for valid input data
+      latency <= 5'h11; // cycles from valid input to valid output
+   end else if (|delay) begin
+     delay <= delay - 1;
+   end else begin
+      if(|latency) begin
+         latency <= latency - 1;
+      end
+
+      out0 <= w[0];
+
+      for(i = 0; i < 15; i = i + 1) begin
+         w[i] <= w[i+1];
+      end
+
+      if(latency[4:1] != 0) begin // latency > 1
+         w[15] <= in0;
+      end else begin
+         w[15] <= val;
+      end
+
+      out0 <= val;
+   end
+end
+
+endmodule