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BOOT and ext_mem partially connected together
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Compilation works but nothing runs again because of the changes.

Corrected input ports of iob_soc_boot and they're now on the Python
of itself and iob-soc's for auto-mapping.
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@Edw590
Edw590 committed Aug 21, 2023
1 parent ff64ccb commit 126e588
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Showing 9 changed files with 233 additions and 119 deletions.
0 hardware/src/iob_soc_ext_mem_if.v → hardware/iob_soc_ext_mem_if.v
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135 changes: 59 additions & 76 deletions hardware/src/iob_soc.v
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Original file line number Diff line number Diff line change
Expand Up @@ -84,21 +84,21 @@ module iob_soc #(
`ifdef IOB_SOC_USE_EXTMEM

// INSTRUCTION BUS
iob_split #(
.ADDR_W (ADDR_W),
.DATA_W (DATA_W),
.N_SLAVES(2),
.P_SLAVES(AddrMsb)
) ibus_split (
.clk_i (clk_i),
.arst_i (cpu_reset),
// master interface
.m_req_i (cpu_i_req),
.m_resp_o(cpu_i_resp),
// slaves interface
.s_req_o ({ext_mem_i_req, int_mem_i_req}),
.s_resp_i({ext_mem_i_resp, int_mem_i_resp})
);
//iob_split #(
// .ADDR_W (ADDR_W),
// .DATA_W (DATA_W),
// .N_SLAVES(2),
// .P_SLAVES(AddrMsb)
//) ibus_split (
// .clk_i (clk_i),
// .arst_i (cpu_reset),
// // master interface
// .m_req_i (cpu_i_req),
// .m_resp_o(cpu_i_resp),
// // slaves interface
// .s_req_o ({ext_mem_i_req, int_mem_i_req}),
// .s_resp_i({ext_mem_i_resp, int_mem_i_resp})
//);
`else
assign int_mem_i_req = cpu_i_req;
assign cpu_i_resp = int_mem_i_resp;
Expand All @@ -115,21 +115,24 @@ module iob_soc #(
wire [`RESP_W-1:0] ext_mem_d_resp;
`ifdef IOB_SOC_USE_EXTMEM

iob_split #(
.ADDR_W (ADDR_W),
.DATA_W (DATA_W),
.N_SLAVES(2), //E,{P,I}
.P_SLAVES(AddrMsb)
) dbus_split (
.clk_i (clk_i),
.arst_i (cpu_reset),
// master interface
.m_req_i (cpu_d_req),
.m_resp_o(cpu_d_resp),
// slaves interface
.s_req_o ({ext_mem_d_req, int_d_req}),
.s_resp_i({ext_mem_d_resp, int_d_resp})
);
//iob_split #(
// .ADDR_W (ADDR_W),
// .DATA_W (DATA_W),
// .N_SLAVES(2), //E,{P,I}
// .P_SLAVES(AddrMsb)
//) dbus_split (
// .clk_i (clk_i),
// .arst_i (cpu_reset),
// // master interface
// .m_req_i (cpu_d_req),
// .m_resp_o(cpu_d_resp),
// // slaves interface
// .s_req_o ({ext_mem_d_req, int_d_req}),
// .s_resp_i({ext_mem_d_resp, int_d_resp})

assign ext_mem_d_req = cpu_d_req;
assign cpu_d_resp = ext_mem_d_resp;
//);
`else
assign int_d_req = cpu_d_req;
assign cpu_d_resp = int_d_resp;
Expand All @@ -139,58 +142,38 @@ module iob_soc #(



wire [`IOB_SOC_BOOT_CTR_W-1:0] BOOT_CTR;

wire [ `REQ_W-1:0] boot_ctr_i_req;
wire [`RESP_W-1:0] boot_ctr_i_resp;
assign cpu_reset = boot_cpu_rst_o;
assign boot_cpu_i_req_i = cpu_i_req;
assign cpu_i_resp = boot_cpu_i_resp_o;
assign boot_ext_mem_i_resp_i = ext_mem_i_resp;
assign ext_mem_i_req = boot_ext_mem_i_req_o;

iob_soc_boot #(
.ADDR_W (ADDR_W),
.DATA_W (DATA_W)
/*iob_soc_boot #(
.ADDR_W(ADDR_W),
.DATA_W(DATA_W)
) soc_boot (
.clk_i (clk_i),
.cke_i (cke_i),
.arst_i(arst_i),
.clk_i (clk_i),
.cke_i (cke_i),
.arst_i (arst_i),
.cpu_rst_o(cpu_reset),
.iob_avalid_i (cpu_d_req[`AVALID(0)]),
.iob_addr_i (cpu_d_req[`ADDRESS(0, ADDR_W)]),
.iob_wdata_i (cpu_d_req[`WDATA(0)]),
.iob_wstrb_i (cpu_d_req[`WSTRB(0)]),
.iob_avalid_i(cpu_d_req[`AVALID(0)]),
.iob_addr_i (cpu_d_req[`ADDRESS(0, ADDR_W)]),
.iob_wdata_i (cpu_d_req[`WDATA(0)]),
.iob_wstrb_i (cpu_d_req[`WSTRB(0)]),
// These below are empty. They're not used by the module and anyway cpu_d_resp is an output.
// Can't be driven by multiple drivers.
.iob_rvalid_o (),
.iob_rdata_o (),
.iob_ready_o (),

//boot_ctr_i_req_i (boot_ctr_i_req),
//boot_ctr_i_resp_o(boot_ctr_i_resp),
.iob_rvalid_o(),
.iob_rdata_o (),
.iob_ready_o (),
.CTR_o(BOOT_CTR)
);
.cpu_i_req_i (cpu_i_req),
.cpu_i_resp_o(cpu_i_resp),
.ext_mem_i_req_o (ext_mem_i_req),
.ext_mem_i_resp_i(ext_mem_i_resp)
);*/

//// SPLIT INSTUCTION BUS TO ACCESS MEMORY OR BOOT ROM

//external memory instruction bus
//wire [ `REQ_W-1:0] boot_ctr_i_req;
//wire [`RESP_W-1:0] boot_ctr_i_resp;

//iob_split2 #(
// .ADDR_W (ADDR_W),
// .DATA_W (DATA_W),
// .N_SLAVES(3)
//) boot_ibus_split (
// .clk_i (clk_i),
// .arst_i (cpu_reset),
// .s_sel_i (BOOT_CTR),
// // master interface
// .m_req_i (cpu_i_req),
// .m_resp_o(cpu_i_resp),
// // slaves interface
// .s_req_o ({boot_ctr_i_req, ext_mem_i_req, ext_mem_i_req}),
// .s_resp_i({boot_ctr_i_resp, ext_mem_i_resp, ext_mem_i_resp})
//);
//
////assign ext_mem_i_req = cpu_i_req;
////assign cpu_i_resp = ext_mem_i_resp;
//assign ext_mem_d_req = cpu_d_req;
Expand Down Expand Up @@ -225,8 +208,8 @@ module iob_soc #(
.clk_i (clk_i),
.arst_i (cpu_reset),
// master interface
.m_req_i (int_d_req),
.m_resp_o(int_d_resp),
.m_req_i (cpu_d_req),
.m_resp_o(cpu_d_resp),
// slaves interface
.s_req_o (slaves_req),
.s_resp_i(slaves_resp)
Expand Down
72 changes: 72 additions & 0 deletions iob_soc.py
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Original file line number Diff line number Diff line change
Expand Up @@ -131,6 +131,7 @@ def _create_submodules_list(cls, extra_submodules=[]):
@classmethod
def _setup_portmap(cls):
cls.peripheral_portmap += [
# UART0
(
{"corename": "UART0", "if_name": "rs232", "port": "txd_o", "bits": []},
{
Expand Down Expand Up @@ -167,6 +168,77 @@ def _setup_portmap(cls):
"bits": [],
},
),
# BOOT0
(
{
"corename": "BOOT0",
"if_name": "general",
"port": "cpu_rst_o",
"bits": [],
},
{
"corename": "internal",
"if_name": "boot",
"port": "cpu_reset",
"bits": [],
},
),
(
{
"corename": "BOOT0",
"if_name": "general",
"port": "cpu_i_req_i",
"bits": [],
},
{
"corename": "internal",
"if_name": "boot",
"port": "cpu_i_req",
"bits": [],
},
),
(
{
"corename": "BOOT0",
"if_name": "general",
"port": "cpu_i_resp_o",
"bits": [],
},
{
"corename": "internal",
"if_name": "boot",
"port": "cpu_i_resp",
"bits": [],
},
),
(
{
"corename": "BOOT0",
"if_name": "general",
"port": "ext_mem_i_resp_i",
"bits": [],
},
{
"corename": "internal",
"if_name": "boot",
"port": "ext_mem_i_resp",
"bits": [],
},
),
(
{
"corename": "BOOT0",
"if_name": "general",
"port": "ext_mem_i_req_o",
"bits": [],
},
{
"corename": "internal",
"if_name": "boot",
"port": "ext_mem_i_req",
"bits": [],
},
),
]

@classmethod
Expand Down
2 changes: 1 addition & 1 deletion software/src/iob_soc_firmware.S
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ addi sp, sp, %lo(1<<IOB_SOC_SRAM_ADDR_W)
//call main
jal ra, main

li s5, 6 //cpu_rst=1, boot=1, preboot=0
li s5, 0b110
li s6, CTR_ADDR
sw s5, 0(s6)

Expand Down
65 changes: 49 additions & 16 deletions submodules/BOOT/hardware/src/iob_soc_boot.v
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Original file line number Diff line number Diff line change
Expand Up @@ -8,17 +8,29 @@
module iob_soc_boot #(
`include "iob_soc_boot_params.vs"
) (
input [ `REQ_W-1:0] boot_ctr_i_req_i,

output [`RESP_W-1:0] boot_ctr_i_resp_o,
output [`IOB_SOC_BOOT_CTR_W-1:0] CTR_o,

`include "iob_soc_boot_io.vs"
);

`include "iob_soc_boot_swreg_inst.vs"

wire [ REQ_W_PARAM-1:0] boot_ctr_i_req;
wire [RESP_W_PARAM-1:0] boot_ctr_i_resp;

assign CTR_o = CTR;

//create CPU reset pulse
wire cpu_rst_req;
assign cpu_rst_req = (iob_avalid_i & (|iob_wstrb_i) & iob_wdata_i[2]) | arst_i;

iob_pulse_gen #(
.START (0),
.DURATION(100)
) reset_pulse (
.clk_i (clk_i),
.arst_i (arst_i),
.cke_i (cke_i),
.start_i(cpu_rst_req),
.pulse_o(cpu_rst_o)
);

//
//INSTANTIATE BOOT ROM
Expand All @@ -43,21 +55,21 @@ module iob_soc_boot #(
.clk_i(clk_i),

// instruction memory interface
.r_en_a_i (boot_ctr_i_req_i[`AVALID(0)]),
.addr_a_i (boot_ctr_i_req_i[`ADDRESS(0, FULL_ROM_ADDR_W)][FULL_ROM_ADDR_W-1:0] >> 2),
.r_data_a_o(boot_ctr_i_resp_o[`RDATA(0)]),
.r_en_a_i (boot_ctr_i_req[`AVALID(0)]),
.addr_a_i (boot_ctr_i_req[`ADDRESS(0, FULL_ROM_ADDR_W)]),
.r_data_a_o(boot_ctr_i_resp[`RDATA(0)]),

// data memory interface
.r_en_b_i (ROM_ren),
.addr_b_i (iob_addr_i[FULL_ROM_ADDR_W-1:0] >> 2),
.r_data_b_o(ROM)
);
assign ROM_ready = 1'b1;
assign boot_ctr_i_resp_o[`READY(0)] = 1'b1;
assign boot_ctr_i_resp[`READY(0)] = 1'b1;

iob_reg #(
.DATA_W (1),
.RST_VAL(1'd0)
.DATA_W (`VALID_W),
.RST_VAL(0)
) data_rvalid_reg (
.clk_i (clk_i),
.cke_i (cke_i),
Expand All @@ -67,19 +79,40 @@ module iob_soc_boot #(
);

iob_reg #(
.DATA_W (1),
.RST_VAL(1'd0)
.DATA_W (`VALID_W),
.RST_VAL(0)
) instruc_rvalid_reg (
.clk_i (clk_i),
.cke_i (cke_i),
.arst_i(arst_i),
.data_i(boot_ctr_i_req_i[`AVALID(0)]),
.data_o(boot_ctr_i_resp_o[`RVALID(0)])
.data_i(boot_ctr_i_req[`AVALID(0)]),
.data_o(boot_ctr_i_resp[`RVALID(0)])
);




// SPLIT INSTUCTION BUS TO ACCESS MEMORY OR BOOT ROM

iob_split2 #(
.ADDR_W (ADDR_W),
.DATA_W (DATA_W),
.N_SLAVES(3)
) boot_ibus_split (
.clk_i (clk_i),
.arst_i (cpu_rst_o),

.s_sel_i (CTR[2-1:0]),

// master interface
.m_req_i (cpu_i_req_i),
.m_resp_o(cpu_i_resp_o),
// slaves interface
.s_req_o ({boot_ctr_i_req, ext_mem_i_req_o, ext_mem_i_req_o}),
.s_resp_i({boot_ctr_i_resp, ext_mem_i_resp_i, ext_mem_i_resp_i})
);





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