Merge remote-tracking branch 'origin/if_gen2' into revamp2

.github/workflows/ci.yml

@@ -63,9 +63,9 @@ jobs:
       - name: Clean untracked files and directories (like old submodules)
         run: git clean -ffdx
       - name: init mem and no ext mem
-        run: make fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=1 USE_EXTMEM=0
+        run: make fpga-run BOARD=cyclonev_gt_dk INIT_MEM=1 USE_EXTMEM=0
       - name: no init mem and ext mem
-        run: make fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=0 USE_EXTMEM=1
+        run: make fpga-run BOARD=cyclonev_gt_dk INIT_MEM=0 USE_EXTMEM=1
 
   ku040:
     runs-on: self-hosted
@@ -80,9 +80,9 @@ jobs:
       - name: Clean untracked files and directories (like old submodules)
         run: git clean -ffdx
       - name: init mem and no ext mem
-        run: make fpga-run BOARD=AES-KU040-DB-G INIT_MEM=1 USE_EXTMEM=0
+        run: make fpga-run BOARD=aes_ku040_db_g INIT_MEM=1 USE_EXTMEM=0
       - name: no init mem and ext mem
-        run: make fpga-run BOARD=AES-KU040-DB-G INIT_MEM=0 USE_EXTMEM=1
+        run: make fpga-run BOARD=aes_ku040_db_g INIT_MEM=0 USE_EXTMEM=1
 
   lib:
     runs-on: self-hosted

Makefile

@@ -2,15 +2,19 @@ CORE := iob_soc
 
 SIMULATOR ?= icarus
 SYNTHESIZER ?= yosys
-BOARD ?= CYCLONEV-GT-DK
+BOARD ?= cyclonev_gt_dk
 
 BUILD_DIR ?= $(shell nix-shell --run "py2hwsw $(CORE) print_build_dir")
 
 INIT_MEM ?= 1
 USE_EXTMEM ?= 0
 
+ifneq ($(DEBUG),)
+EXTRA_ARGS +=--debug_level $(DEBUG)
+endif
+
 setup:
-	nix-shell --run "py2hwsw $(CORE) setup --no_verilog_lint --py_params 'init_mem=$(INIT_MEM):use_extmem=$(USE_EXTMEM)'"
+	nix-shell --run "py2hwsw $(CORE) setup --no_verilog_lint --py_params 'init_mem=$(INIT_MEM):use_extmem=$(USE_EXTMEM)' $(EXTRA_ARGS)"
 
 pc-emul-run:
 	nix-shell --run "make clean setup && make -C ../$(CORE)_V*/ pc-emul-run"
@@ -65,7 +69,7 @@ board_server_status:
 
 clean:
 	nix-shell --run "py2hwsw $(CORE) clean --build_dir '$(BUILD_DIR)'"
-	@rm -rf ../*.summary ../*.rpt 
+	@rm -rf ../*.summary ../*.rpt
 	@find . -name \*~ -delete
 
 # Remove all __pycache__ folders with python bytecode

README.md

@@ -97,8 +97,8 @@ When you start the simulation, IOb-SoC's simulation Makefile will log you on to
 
 ### Set up the remote FPGA toolchain and board servers
 
-Using the CYCLONEV-GT-DK board as an example, note that in
-`hardware/fpga/quartus/CYCLONEV-GT-DK/Makefile,` the variable for the FPGA tool
+Using the cyclonev_gt_dk board as an example, note that in
+`hardware/fpga/quartus/cyclonev_gt_dk/Makefile,` the variable for the FPGA tool
 server logical name, `FPGA_SERVER,` is set to `QUARTUS_SERVER,` and the
 variable for the user name, `FPGA_USER`, is set to `QUARTUS_USER`; the
 variable for the board server, `BOARD_SERVER,` is set to `CYC5_SERVER`, and

document/doc_build.mk

@@ -10,7 +10,7 @@ ASICSYNTH?=0
 #default is 0 as EDA tools may not be accessible
 RESULTS ?= 1
 #results for intel FPGA
-INT_FAMILY ?=CYCLONEV-GT-DK
+INT_FAMILY ?=cyclonev_gt_dk
 #results for xilinx fpga
-XIL_FAMILY ?=AES-KU040-DB-G
+XIL_FAMILY ?=aes_ku040_db_g
 

hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_fpga_wrapper_dev.sdc → hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.sdc

@@ -57,10 +57,10 @@ set_property IOSTANDARD LVCMOS18 [get_ports {rxd_i}]
 #set_property IOSTANDARD LVCMOS18 [get_ports {trap}]
 
 ####### User PUSH Switches
-#set_property PACKAGE_PIN N24 [get_ports {reset_i}]
-#set_property IOSTANDARD LVCMOS12 [get_ports {reset_i}]
-set_property PACKAGE_PIN K20 [get_ports {reset_i}]
-set_property IOSTANDARD LVCMOS12 [get_ports {reset_i}]
+#set_property PACKAGE_PIN N24 [get_ports {areset_i}]
+#set_property IOSTANDARD LVCMOS12 [get_ports {areset_i}]
+set_property PACKAGE_PIN K20 [get_ports {areset_i}]
+set_property IOSTANDARD LVCMOS12 [get_ports {areset_i}]
 
 #set_property PACKAGE_PIN K18 [get_ports {gpio_push_sw_tri_i[0]}]
 #set_property IOSTANDARD LVCMOS12 [get_ports {gpio_push_sw_tri_i[0]}]