feature: counter and sipo to support clock negedge operation

IObundle · Nov 1, 2023 · 6171c2e · 6171c2e
1 parent 8dd3cd9
commit 6171c2e
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Showing 2 changed files with 6 additions and 4 deletions.
diff --git a/submodules/LIB/hardware/modules/counter/iob_counter/hardware/src/iob_counter.v b/submodules/LIB/hardware/modules/counter/iob_counter/hardware/src/iob_counter.v
@@ -2,7 +2,8 @@
 
 module iob_counter #(
    parameter DATA_W  = 21,
-   parameter RST_VAL = {DATA_W{1'b0}}
+   parameter RST_VAL = {DATA_W{1'b0}},
+   parameter CLKEDGE = "posedge"
 ) (
    `include "clk_en_rst_s_port.vs"
 
@@ -17,7 +18,7 @@ module iob_counter #(
    iob_reg_re #(
       .DATA_W (DATA_W),
       .RST_VAL(RST_VAL),
-      .CLKEDGE("posedge")
+      .CLKEDGE("CLKEDGE")
    ) reg0 (
       `include "clk_en_rst_s_s_portmap.vs"
       .rst_i (rst_i),

diff --git a/submodules/LIB/hardware/modules/iob_sipo_reg/hardware/src/iob_sipo_reg.v b/submodules/LIB/hardware/modules/iob_sipo_reg/hardware/src/iob_sipo_reg.v
@@ -1,7 +1,8 @@
 `timescale 1ns / 1ps
 
 module iob_sipo_reg #(
-   parameter DATA_W = 21
+   parameter DATA_W = 21,
+   parameter CLKEDGE = "pos"
 ) (
 
    `include "clk_en_rst_s_port.vs"
@@ -19,7 +20,7 @@ module iob_sipo_reg #(
    iob_reg #(
       .DATA_W (DATA_W),
       .RST_VAL(0),
-      .CLKEDGE("posedge")
+      .CLKEDGE("CLKEDGE")
    ) reg0 (
       `include "clk_en_rst_s_s_portmap.vs"