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fix build env after using nix-shell
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jjts committed Oct 23, 2023
1 parent 2ff8cfd commit 96819fa
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Showing 6 changed files with 13 additions and 12 deletions.
4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@ jobs:
- name: test-clean
run: make test-clean
- name: test-cyclonev
run: nix-shell --run "make fpga-test BOARD=CYCLONEV-GT-DK"
run: make fpga-test BOARD=CYCLONEV-GT-DK

aes-ku040:
runs-on: self-hosted
Expand All @@ -90,7 +90,7 @@ jobs:
- name: test-clean
run: make test-clean
- name: test-aes-ku040
run: nix-shell --run "make fpga-test BOARD=AES-KU040-DB-G"
run: make fpga-test BOARD=AES-KU040-DB-G

doc:
runs-on: self-hosted
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11 changes: 6 additions & 5 deletions hardware/fpga/fpga.mk
Original file line number Diff line number Diff line change
Expand Up @@ -48,18 +48,19 @@ endif
endif
endif

build: $(FPGA_OBJ)

#make the FPGA programming file either locally or remotely
ifeq ($(INIT_MEM),1)
$(FPGA_OBJ): $(wildcard *.sdc) $(VSRC) $(VHDR) boot.hex firmware.hex
build: $(wildcard *.sdc) $(VSRC) $(VHDR) boot.hex $(FPGA_OBJ)
else
$(FPGA_OBJ): $(wildcard *.sdc) $(VSRC) $(VHDR) boot.hex
build: $(wildcard *.sdc) $(VSRC) $(VHDR) boot.hex firmware.hex $(FPGA_OBJ)
endif
export
#make the FPGA programming file either locally or remotely
$(FPGA_OBJ):
ifeq ($(NORUN),0)
ifeq ($(FPGA_SERVER),)
@rm -f $(FPGA_LOG)
make local-build
# ../build.sh "$(INCLUDE)" "$(DEFINE)" "$(VSRC)"
else
ssh $(FPGA_USER)@$(FPGA_SERVER) "if [ ! -d $(REMOTE_ROOT_DIR) ]; then mkdir -p $(REMOTE_ROOT_DIR); fi"
rsync -avz --delete --force --exclude .git $(ROOT_DIR) $(FPGA_USER)@$(FPGA_SERVER):$(REMOTE_ROOT_DIR)
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2 changes: 1 addition & 1 deletion hardware/fpga/quartus/build.sh
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
#!/bin/bash
set -e
nios=$QUARTUSPATH/nios2eds/nios2_command_shell.sh
nios=nios2_command_shell.sh
$nios quartus_sh -t ../top_system.tcl "$1" "$2" "$3"
#$nios quartus_map top_system
#$nios quartus_sh -t qsys/alt_ddr3/synthesis/submodules/alt_ddr3_mem_if_ddr3_emif_1_p0_pin_assignments.tcl
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2 changes: 1 addition & 1 deletion hardware/fpga/quartus/prog.sh
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
#!/bin/bash
set -e
nios=$QUARTUSPATH/nios2eds/nios2_command_shell.sh
nios=nios2_command_shell.sh
$nios quartus_pgm -m jtag -c 1 -o "p;top_system.sof"
4 changes: 2 additions & 2 deletions hardware/fpga/quartus/quartus.mk
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,8 @@ FPGA_USER=$(QUARTUS_USER)

include ../../fpga.mk

local-build: $(QIP_FILE)
$(QUARTUSPATH)/nios2eds/nios2_command_shell.sh quartus_sh -t ../top_system.tcl "$(INCLUDE)" "$(DEFINE)" "$(VSRC)"
local-build:
nios2_command_shell.sh quartus_sh -t ../top_system.tcl "$(INCLUDE)" "$(DEFINE)" "$(VSRC)"
mv output_files/top_system.sof $(FPGA_OBJ)
mv output_files/top_system.fit.summary $(FPGA_LOG)

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2 changes: 1 addition & 1 deletion submodules/LIB
Submodule LIB updated 1 files
+1 −1 hardware/fpga/quartus.mk

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