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refactor(wrapper): Rename rst signal to arst in wrappers.
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@arturum1
arturum1 committed Aug 29, 2023
1 parent 02731ff commit a3594ac
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Showing 6 changed files with 43 additions and 25 deletions.
8 changes: 4 additions & 4 deletions hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ module iob_soc_fpga_wrapper (
// Clocking / Reset
//-----------------------------------------------------------------

wire rst;
wire arst;

//
// Logic to contatenate data pins and ethernet clock
Expand Down Expand Up @@ -125,7 +125,7 @@ module iob_soc_fpga_wrapper (
`include "iob_soc_pportmaps.vs"
.clk_i (clk),
.cke_i (1'b1),
.arst_i(rst),
.arst_i(arst),
.trap_o(trap)
);

Expand All @@ -150,7 +150,7 @@ module iob_soc_fpga_wrapper (
iob_reset_sync rst_sync (
.clk_i (clk),
.arst_i(rst_int),
.arst_o(rst)
.arst_o(arst)
);

alt_ddr3 ddr3_ctrl (
Expand Down Expand Up @@ -229,7 +229,7 @@ module iob_soc_fpga_wrapper (
iob_reset_sync rst_sync (
.clk_i (clk),
.arst_i(~resetn),
.arst_o(rst)
.arst_o(arst)
);
`endif

Expand Down
6 changes: 3 additions & 3 deletions hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_fpga_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,7 @@ module iob_soc_fpga_wrapper (
`include "iob_soc_wrapper_pwires.vs"

wire clk;
wire rst;
wire arst;


//
Expand Down Expand Up @@ -121,7 +121,7 @@ module iob_soc_fpga_wrapper (
`include "iob_soc_pportmaps.vs"
.clk_i (clk),
.cke_i (1'b1),
.arst_i(rst),
.arst_i(arst),
.trap_o(trap)
);

Expand Down Expand Up @@ -330,7 +330,7 @@ module iob_soc_fpga_wrapper (
.arst_i (reset),
.cke_i (1'b1),
.start_i(start),
.pulse_o(rst)
.pulse_o(arst)
);
`endif

Expand Down
10 changes: 5 additions & 5 deletions hardware/simulation/src/iob_soc_sim_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ module iob_soc_sim_wrapper (
localparam AXI_DATA_W = `DDR_DATA_W;

wire clk = clk_i;
wire rst = rst_i;
wire arst = rst_i;

`include "iob_soc_wrapper_pwires.vs"

Expand Down Expand Up @@ -64,7 +64,7 @@ module iob_soc_sim_wrapper (
`include "iob_soc_pportmaps.vs"
.clk_i (clk),
.cke_i (1'b1),
.arst_i(rst),
.arst_i(arst),
.trap_o(trap_o)
);

Expand All @@ -85,7 +85,7 @@ module iob_soc_sim_wrapper (
`include "iob_memory_axi_s_portmap.vs"

.clk_i(clk),
.rst_i(rst)
.rst_i(arst)
);
`endif

Expand Down Expand Up @@ -128,7 +128,7 @@ always @(posedge trap[1]) begin
iob_uart uart_tb (
.clk_i (clk),
.cke_i (cke),
.arst_i(rst),
.arst_i(arst),

.iob_avalid_i(uart_avalid),
.iob_addr_i (uart_addr),
Expand Down Expand Up @@ -163,7 +163,7 @@ always @(posedge trap[1]) begin
//add core test module in testbench
iob_eth_tb_gen eth_tb (
.clk (clk),
.reset(rst),
.reset(arst),

// This module acts like a loopback
.RX_CLK (ETHERNET0_TX_CLK),
Expand Down
6 changes: 4 additions & 2 deletions scripts/iob_soc_create_system.py
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Original file line number Diff line number Diff line change
Expand Up @@ -77,13 +77,15 @@ def create_systemv(build_dir, top, peripherals_list, internal_wires=None):
# Insert peripheral instance name
periphs_inst_str += " {} (\n".format(instance.name)
# Insert io signals
#print(f"Debug: {instance.name} {instance.io} {port_list[instance.__class__.name]}\n") # DEBUG
# print(f"Debug: {instance.name} {instance.io} {port_list[instance.__class__.name]}\n") # DEBUG
for signal in get_pio_signals(port_list[instance.__class__.name]):
if "if_defined" in signal.keys():
periphs_inst_str += f"`ifdef {top.upper()}_{signal['if_defined']}\n"
periphs_inst_str += " .{}({}),\n".format(
signal["name"],
get_peripheral_port_mapping(instance, signal["if_name"], signal["name"]),
get_peripheral_port_mapping(
instance, signal["if_name"], signal["name"]
),
)
if "if_defined" in signal.keys():
periphs_inst_str += "`endif\n"
Expand Down
2 changes: 1 addition & 1 deletion scripts/iob_soc_create_wrapper_files.py
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ def create_interconnect_instance(out_dir, name, num_extmem_connections):
.M_COUNT (1)
) system_axi_interconnect (
.clk(clk),
.rst(rst),
.rst(arst),
// Need to use manually defined connections because awlock and arlock of interconnect is only on bit for each slave
.s_axi_awid (axi_awid), //Address write channel ID.
Expand Down
36 changes: 26 additions & 10 deletions scripts/iob_soc_utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -410,9 +410,9 @@ def peripheral_portmap(python_module):
"descr": f"IOs for peripherals based on portmap index {map_idx}",
"ports": mapping_ios,
# Only set `ios_table_prefix` if user has not specified a value in the portmap entry
#"ios_table_prefix": True
#if "ios_table_prefix" not in mapping[mapping_external_interface]
#else mapping[mapping_external_interface]["ios_table_prefix"],
# "ios_table_prefix": True
# if "ios_table_prefix" not in mapping[mapping_external_interface]
# else mapping[mapping_external_interface]["ios_table_prefix"],
}
)

Expand Down Expand Up @@ -490,7 +490,11 @@ def peripheral_portmap(python_module):
)
)
# Append if_name as a prefix of signal
mapping_ios[-1]["name"] = mapping[mapping_external_interface]["if_name"] + "_" + port["name"]
mapping_ios[-1]["name"] = (
mapping[mapping_external_interface]["if_name"]
+ "_"
+ port["name"]
)
# Dont add `if_name` prefix if `iob_table_prefix` is set to False
if (
"ios_table_prefix" in mapping[mapping_external_interface]
Expand Down Expand Up @@ -521,12 +525,22 @@ def peripheral_portmap(python_module):

# Insert mapping between IO and wire for mapping[0] (if its not internal/external interface)
if mapping_internal_interface != 0 and mapping_external_interface != 0:
map_IO_to_wire(mapping_items[0].io, mapping[0]["if_name"]+'_'+port["name"], 0, [], wire_name)
map_IO_to_wire(
mapping_items[0].io,
mapping[0]["if_name"] + "_" + port["name"],
0,
[],
wire_name,
)

# Insert mapping between IO and wire for mapping[1] (if its not internal/external interface)
if mapping_internal_interface != 1 and mapping_external_interface != 1:
map_IO_to_wire(
mapping_items[1].io, mapping[1]["if_name"]+'_'+if_mapping[port["name"]], 0, [], wire_name
mapping_items[1].io,
mapping[1]["if_name"] + "_" + if_mapping[port["name"]],
0,
[],
wire_name,
)

else:
Expand Down Expand Up @@ -601,7 +615,9 @@ def peripheral_portmap(python_module):
)
)
# Append if_name as a prefix of signal
mapping_ios[-1]["name"] = mapping[mapping_external_interface]["if_name"] + "_" + port["name"] # FIXME
mapping_ios[-1]["name"] = (
mapping[mapping_external_interface]["if_name"] + "_" + port["name"]
) # FIXME
# Dont add `if_name` prefix if `iob_table_prefix` is set to False
if (
"ios_table_prefix" in mapping[mapping_external_interface]
Expand Down Expand Up @@ -630,10 +646,10 @@ def peripheral_portmap(python_module):

# Insert mapping between IO and wire for mapping[0] (if its not internal/external interface)
if mapping_internal_interface != 0 and mapping_external_interface != 0:
#print(f"Debug: {mapping_items[0].name} {mapping_items[0].ios} {mapping_items[0].io}\n") # DEBUG
# print(f"Debug: {mapping_items[0].name} {mapping_items[0].ios} {mapping_items[0].io}\n") # DEBUG
map_IO_to_wire(
mapping_items[0].io,
mapping[0]["if_name"]+"_"+mapping[0]["port"],
mapping[0]["if_name"] + "_" + mapping[0]["port"],
eval_param_expression_from_config(
port["n_bits"], mapping_items[0].confs, "max"
),
Expand All @@ -645,7 +661,7 @@ def peripheral_portmap(python_module):
if mapping_internal_interface != 1 and mapping_external_interface != 1:
map_IO_to_wire(
mapping_items[1].io,
mapping[1]["if_name"]+"_"+mapping[1]["port"],
mapping[1]["if_name"] + "_" + mapping[1]["port"],
eval_param_expression_from_config(
port2["n_bits"], mapping_items[1].confs, "max"
),
Expand Down

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