Merge pull request #608 from arturum1/python-setup

Fix `axi_m_port` interface; Fix iob_soc_create_system.py; Update submodules.
IObundle · Oct 26, 2023 · a6e3ca7 · a6e3ca7
2 parents ddc4770 + 3322989
commit a6e3ca7
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Showing 14 changed files with 156 additions and 111 deletions.
diff --git a/hardware/src/iob_soc.v b/hardware/src/iob_soc.v
@@ -159,7 +159,7 @@ module iob_soc #(
    // INTERNAL SRAM MEMORY
    //
 
-   int_mem #(
+   iob_soc_int_mem #(
       .ADDR_W        (ADDR_W),
       .DATA_W        (DATA_W),
       .HEXFILE       ("iob_soc_firmware"),
@@ -205,7 +205,7 @@ module iob_soc #(
    wire [AXI_ADDR_W-1:0] internal_axi_awaddr_o;
    wire [AXI_ADDR_W-1:0] internal_axi_araddr_o;
 
-   ext_mem #(
+   iob_soc_ext_mem #(
       .ADDR_W     (ADDR_W),
       .DATA_W     (DATA_W),
       .FIRM_ADDR_W(SRAM_ADDR_W),
@@ -236,19 +236,19 @@ module iob_soc #(
       .axi_awcache_o(axi_awcache_o[0+:4]),
       .axi_awprot_o (axi_awprot_o[0+:3]),
       .axi_awqos_o  (axi_awqos_o[0+:4]),
-      .axi_awvalid_o(axi_awvalid_o),
-      .axi_awready_i(axi_awready_i),
+      .axi_awvalid_o(axi_awvalid_o[0+:1]),
+      .axi_awready_i(axi_awready_i[0+:1]),
       //write
       .axi_wdata_o  (axi_wdata_o[0+:AXI_DATA_W]),
       .axi_wstrb_o  (axi_wstrb_o[0+:(AXI_DATA_W/8)]),
-      .axi_wlast_o  (axi_wlast_o),
-      .axi_wvalid_o (axi_wvalid_o),
-      .axi_wready_i (axi_wready_i),
+      .axi_wlast_o  (axi_wlast_o[0+:1]),
+      .axi_wvalid_o (axi_wvalid_o[0+:1]),
+      .axi_wready_i (axi_wready_i[0+:1]),
       //write response
       .axi_bid_i    (axi_bid_i[0+:AXI_ID_W]),
       .axi_bresp_i  (axi_bresp_i[0+:2]),
-      .axi_bvalid_i (axi_bvalid_i),
-      .axi_bready_o (axi_bready_o),
+      .axi_bvalid_i (axi_bvalid_i[0+:1]),
+      .axi_bready_o (axi_bready_o[0+:1]),
       //address read
       .axi_arid_o   (axi_arid_o[0+:AXI_ID_W]),
       .axi_araddr_o (internal_axi_araddr_o[0+:AXI_ADDR_W]),
@@ -259,15 +259,15 @@ module iob_soc #(
       .axi_arcache_o(axi_arcache_o[0+:4]),
       .axi_arprot_o (axi_arprot_o[0+:3]),
       .axi_arqos_o  (axi_arqos_o[0+:4]),
-      .axi_arvalid_o(axi_arvalid_o),
-      .axi_arready_i(axi_arready_i),
+      .axi_arvalid_o(axi_arvalid_o[0+:1]),
+      .axi_arready_i(axi_arready_i[0+:1]),
       //read
       .axi_rid_i    (axi_rid_i[0+:AXI_ID_W]),
       .axi_rdata_i  (axi_rdata_i[0+:AXI_DATA_W]),
       .axi_rresp_i  (axi_rresp_i[0+:2]),
-      .axi_rlast_i  (axi_rlast_i),
-      .axi_rvalid_i (axi_rvalid_i),
-      .axi_rready_o (axi_rready_o),
+      .axi_rlast_i  (axi_rlast_i[0+:1]),
+      .axi_rvalid_i (axi_rvalid_i[0+:1]),
+      .axi_rready_o (axi_rready_o[0+:1]),
 
       .clk_i (clk_i),
       .cke_i (cke_i),

diff --git a/hardware/src/boot_ctr.v → hardware/src/iob_soc_boot_ctr.v b/hardware/src/boot_ctr.v → hardware/src/iob_soc_boot_ctr.v
@@ -1,6 +1,6 @@
 `timescale 1 ns / 1 ps
 
-module boot_ctr #(
+module iob_soc_boot_ctr #(
    parameter HEXFILE        = "boot.hex",
    parameter DATA_W         = 0,
    parameter ADDR_W         = 0,

diff --git a/hardware/src/ext_mem.v → hardware/src/iob_soc_ext_mem.v b/hardware/src/ext_mem.v → hardware/src/iob_soc_ext_mem.v
@@ -2,7 +2,7 @@
 
 `include "iob_utils.vh"
 
-module ext_mem #(
+module iob_soc_ext_mem #(
    parameter ADDR_W      = 0,
    parameter DATA_W      = 0,
    parameter FIRM_ADDR_W = 0,

diff --git a/hardware/src/int_mem.v → hardware/src/iob_soc_int_mem.v b/hardware/src/int_mem.v → hardware/src/iob_soc_int_mem.v
@@ -3,7 +3,7 @@
 `include "iob_soc_conf.vh"
 `include "iob_utils.vh"
 
-module int_mem #(
+module iob_soc_int_mem #(
    parameter ADDR_W         = 0,
    parameter DATA_W         = 0,
    parameter HEXFILE        = "firmware",
@@ -70,7 +70,7 @@ module int_mem #(
    wire [ `REQ_W-1:0] ram_w_req;
    wire [`RESP_W-1:0] ram_w_resp;
 
-   boot_ctr #(
+   iob_soc_boot_ctr #(
       .HEXFILE       ({BOOT_HEXFILE, ".hex"}),
       .DATA_W        (DATA_W),
       .ADDR_W        (ADDR_W),
@@ -158,7 +158,7 @@ module int_mem #(
    //
    // INSTANTIATE RAM
    //
-   sram #(
+   iob_soc_sram #(
 `ifndef IOB_SOC_USE_EXTMEM
 `ifdef IOB_SOC_INIT_MEM
       .HEXFILE    (HEXFILE),

diff --git a/hardware/src/sram.v → hardware/src/iob_soc_sram.v b/hardware/src/sram.v → hardware/src/iob_soc_sram.v
@@ -2,7 +2,7 @@
 `include "iob_soc_conf.vh"
 `include "bsp.vh"
 
-module sram #(
+module iob_soc_sram #(
    parameter DATA_W      = `IOB_SOC_DATA_W,
    parameter SRAM_ADDR_W = `IOB_SOC_SRAM_ADDR_W,
    parameter HEXFILE     = "none"

diff --git a/iob_soc.py b/iob_soc.py
@@ -7,6 +7,7 @@
 from iob_block_group import iob_block_group
 from iob_soc_utils import pre_setup_iob_soc, post_setup_iob_soc
 from mk_configuration import update_define
+from verilog_tools import inplace_change
 
 # Submodules
 from iob_picorv32 import iob_picorv32
@@ -56,6 +57,13 @@ def _generate_files(cls):
         """Setup this system using specialized iob-soc functions"""
         # Pre-setup specialized IOb-SoC functions
         num_extmem_connections = pre_setup_iob_soc(cls)
+        # Remove `[0+:1]` part select in AXI connections of ext_mem0 in iob_soc.v template
+        if num_extmem_connections == 1:
+            inplace_change(
+                os.path.join(cls.build_dir, "hardware/src", cls.name + ".v"),
+                "[0+:1])",
+                ")",
+            )
         # Generate hw, sw, doc files
         super()._generate_files()
         # Post-setup specialized IOb-SoC functions

diff --git a/scripts/iob_soc_create_system.py b/scripts/iob_soc_create_system.py
@@ -149,7 +149,7 @@ def create_systemv(build_dir, top, peripherals_list, internal_wires=None):
 # axi_awid_width: String representing the width of the axi_awid signal.
 def get_extmem_bus_size(axi_awid_width: str):
     # Parse the size of the ext_mem bus, it should be something like "N*AXI_ID_W", where N is the size of the bus
-    bus_size = re.findall("^(?:(\d+)\*)?AXI_ID_W$", axi_awid_width)
+    bus_size = re.findall("^(?:\((\d+)\*)?AXI_ID_W\)?$", axi_awid_width)
     # Make sure parse of with was successful
     assert (
         bus_size != []

diff --git a/scripts/iob_soc_utils.py b/scripts/iob_soc_utils.py
@@ -241,7 +241,7 @@ def post_setup_iob_soc(python_module, num_extmem_connections):
             )
         # Copy joinHexFiles.py from LIB
         build_srcs.copy_files(
-            "submodules/LIB", f"{build_dir}/scripts", ["joinHexFiles.py"], "*.py"
+            build_srcs.LIB_DIR, f"{build_dir}/scripts", ["joinHexFiles.py"], "*.py"
         )
 
 

diff --git a/submodules/CACHE b/submodules/CACHE
diff --git a/submodules/LIB/scripts/iob_module.py b/submodules/LIB/scripts/iob_module.py
@@ -363,7 +363,7 @@ def _build_regs_table(cls):
                         "rst_val": build_srcs.version_str_to_digits(cls.version),
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": True,
+                        "autoreg": True,
                         "descr": "Product version.  This 16-bit register uses nibbles to represent decimal numbers using their binary values. The two most significant nibbles represent the integral part of the version, and the two least significant nibbles represent the decimal part. For example V12.34 is represented by 0x1234.",
                     }
                 )