Add SPDX license headers; Refactor iob_soc; Remove unneeded original_name and name attributes; Fix append of lists from iob_system child cores.
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master. New verilog parameters allow setting an ADDR_W smaller than the address range of each master. This suppresses verilog warnings when widths do not match. For example, iob_system allocates an address range of 30 bits for the memory. However, the memory bus only has `AXI_ADDR_W` bits (24 bits in simulation). New parameter sets output of that master interface to match `AXI_ADDR_W` bits, and ignores unused bits internally.
Add MIT license to xilinx clock_wizard.v
…he default values. Refactor `iob_soc.py`; Update py2hwsw.
…_snippets lists. Update py2hwsw. Add `basys3` board to iob-soc.
arturum1
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original_name and name attributes; Fix append of lists from iob_system child cores.original_name and name attributes; Fix append of lists from iob_system child cores.
agrevin
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Oct 8, 2024
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