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If gen2 #974

Merged
merged 1,580 commits into from
Nov 12, 2024
Merged

If gen2 #974

merged 1,580 commits into from
Nov 12, 2024

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jjts
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@jjts jjts commented Nov 12, 2024

Merging the long-due if_gen2 branch, which already absorbed the hardware revamp branch.

P-Miranda and others added 30 commits August 21, 2024 16:11
feat(nco): nco improvements
Update py2 to fix state number bug
fix(axis-in): remove DATA register from axis in
This fix cleans submodules that remain from old job runs.
fix(ci): Clean submodules after checkout
New Makefile no longer uses workaround to override py2hwsw based on: https://stackoverflow.com/a/26518222
Now, to use a custom py2hwsw version, comment the one from the `default.nix` file temporarily, and add your own version to PATH.

Note: Since the py2hwsw script has the .py extension, you need to
create a symlink without the .py extension, and add it to PATH.
Currently has an issue with fixed `_param.vs` file generated by `csrs`
module.

To generate regfileif as a top module for testing, use the following
command:
py2hwsw iob_regfileif setup --py_params 'test=True'

Partially related to issue: IObundle/py2hwsw#33
- Currently, regfileif always has 2 interfaces.
- From the perspective of the internal interface, the registers have their
direction inverted.
- Interfaces may be of different types (iob, axi, ...).
- Planned support for interfaces with different widths.
  Need to add support for this in `csrs.py` module as well.
  Should the widths be configured via verilog or python parameters?
arturum1 and others added 29 commits October 10, 2024 05:34
Improve `default.nix` to import the one from py2hwsw
Update py2 version; Add `README.md`.
Merge branch 'main' of IObundle/iob-soc into if_gen2; Update py2hwsw version.
Merge branch 'main' of github.com:IObundle/iob-soc into if_gen2
@jjts jjts merged commit 619ea69 into main Nov 12, 2024
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6 participants