Update README; Rename PY2HWSW_PATH to PY2HWSW_ROOT.
#975
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| @@ -119,7 +70,9 @@ You can *emulate* IOb-SoC's on a PC to develop and debug your embedded system. T | |||
| ```Bash | |||
| make pc-emul-run | |||
| ``` | |||
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| <!-- | |||
| # TODO: iob-soc repo no longer has sw_build.mk (it comes from iob-system). Should we add it back? | |||
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No, but we need a way to pull the examples out of lib for user inspection.
py2hwsw --lib-ls <=> ls PY2HWSW_ROOT/lib (root may be in nix-store or wherever
py2hwsw --lib-ls relative/path/to/lib <=> ls PY2HWSW_ROOT/lib/relative/path/to/lib
py2hwsw --lip-cp relative/path/to/lib destdir <=> cp -r PY2HWSW_ROOT/lib/relative/path/to/lib destdir
This allows the user to study the lib examples
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| The host machine must run an access server, a Python program in [`./scripts/board_server.py`](https://github.com/IObundle/py2hwsw/blob/main/py2hwsw/scripts/board_server.py), set up to run as a service. The client connects to the host using the SSH protocol and runs the board client program [`./scripts/board_client.py`](https://github.com/IObundle/py2hwsw/blob/main/py2hwsw/scripts/board_client.py). Note that the term *board* is used instead of *simulator* because the same server/client programs control the access to the board and FPGA compilers. The client requests the simulator for GRAB_TIMEOUT seconds, which is 300 seconds by default. Its value can be specified in the `./hardware/fpga/fpga_build.mk` Makefile segment, for example, as | ||
| The simulator will timeout after GRAB_TIMEOUT seconds, which is 300 seconds by default. Its value can be specified in the `../iob_soc_Vx.y/hardware/simulation/sim_build.mk` Makefile segment, for example, as |
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make sim GRAB_TIMEOUT = x
Ok?
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Yes, that also works.
Should I add that command to the README.md?
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maybe not , if simulation gets stuck they have to do ctr-c
| ```Bash | ||
| make sim-test | ||
| ``` | ||
| The simulation test contents can be edited in IOb-SoC's top Makefile. | ||
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| Each simulator must be described in the [`./hardware/simulation/<simulator>.mk`](https://github.com/IObundle/py2hwsw/tree/main/py2hwsw/hardware/simulation) file. For example, the file `vcs.mk` describes the VCS simulator. | ||
| Each simulator must be described in the [`../iob_soc_Vx.y/hardware/simulation/<simulator>.mk`](https://github.com/IObundle/py2hwsw/tree/main/py2hwsw/hardware/simulation) file. For example, the file `vcs.mk` describes the VCS simulator. |
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The supported simulators can be listed with
py2hwsw sim-ls <=> ls PY2HWSW_ROOT/hardware/simulation/*.mk
bla bla
py2hwsw sim-cat simulator <=> cat PY2HWSW_ROOT/hardware/simulation/simulator.mk
To support a new simulator or change the makefile segment of supported simulator place simulator.mk into iob-soc/hardware/simulation/simulator.mk
| installed locally. The FPGA board must also be attached to the local host. | ||
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| Each board must be described under the [`../iob_soc_Vx.y/hardware/fpga/<tool>/<board_dir>`](https://github.com/IObundle/py2hwsw/tree/main/py2hwsw/hardware/fpga) directory. | ||
| For example, the [`../iob_soc_Vx.y/hardware/fpga/vivado/basys3`](https://github.com/IObundle/py2hwsw/tree/main/py2hwsw/hardware/fpga/vivado/basys3) directory contents describe the board BASYS3, which has an FPGA device that can be programmed by the Xilinx/AMD Vivado design tool. | ||
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| <!-- | ||
| # TODO: Explain the `board_client`/`board_server` program. It is also used in local machines. | ||
| # Maybe remove the script that uses them in local machines. | ||
| --> | ||
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do not explain
If server not present it just runs
No description provided.