FPGA based SDR platform
Codec: AD9963 FPGA: Spartan 6 LX9, clock 48MHz Host interface: USB 2.0, CY7C68013A in FIFO mode, clock 24MHz
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JacekGreniger/fpga-sdr-platform
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FPGA SDR platform: AD9963 + XC6SLX9 + CY7C68013
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