restore allowlist for AMD 19_21_B0

LLNL · Nov 3, 2023 · f5b5ce9 · f5b5ce9
1 parent 8f8b747
commit f5b5ce9
Showing 1 changed file with 311 additions and 0 deletions.
diff --git a/allowlists/al_19_21 b/allowlists/al_19_21
@@ -0,0 +1,311 @@
+# Based on "Processor Programming Reference (PPR) for AMD Family
+# 19h Model 21h, Revision B0 Processors", Rev 3.05 - Apr 22, 2021,
+# pages 96-194.
+# https://www.amd.com/system/files/TechDocs/56214-B0-PUB.zip
+# NOTE:  The r/w notes are a gross simplification.
+# Please consult the actual manual before doing stuff that matters.
+#
+#   register          writemask comments
+0x00000010 0x0000000000000000 # Time Stamp Counter, r/w, volatile, inc at P0 freq.
+#0x0000001B 0x0000000000000000 # APIC Base Address, r/w
+#0x0000002A 0x0000000000000000 # Cluster ID, r/o
+#0x00000048 0x0000000000000000 # Speculative Control, r/w
+#0x00000049 0x0000000000000000 # Prediction Command, w/o
+#0x0000008B 0x0000000000000000 # Patch Level, r/o
+0x000000E7 0x0000000000000000 # Max Performance Frequency Clock Count, r/w, volatile, inc at P0 clock
+0x000000E8 0x0000000000000000 # Actual Performance Frequency Clock Count, r/w, volatile, inc per clock
+#0x000000FE 0x0000000000000000 # MTRR Capabilities, r/o
+#0x00000174 0x0000000000000000 # SYSENTER_CS, r/w
+#0x00000175 0x0000000000000000 # SYSENTER_ESP, r/w
+#0x00000176 0x0000000000000000 # SYSENTER_EIP, r/w
+#0x00000179 0x0000000000000000 # Global Machine Check Capabilities, r/o
+#0x0000017A 0x0000000000000000 # Global Machine Check Status, r/w, volatile
+#0x0000017B 0x0000000000000000 # Global Machine Check Exception Reporting Control, r/w
+#0x000001D9 0x0000000000000000 # Debug Control, r/w
+#0x000001DB 0x0000000000000000 # Last Branch From IP, r/o, volatile
+#0x000001DC 0x0000000000000000 # Last Branch To IP, r/o, volatile
+#0x000001DD 0x0000000000000000 # Last Exception From IP, r/o, volatile
+#0x000001DE 0x0000000000000000 # Last Exception To IP, r/o, volatile
+#0x00000200 0x0000000000000000 # Variable-Size MTRRs Base, r/w
+#0x00000201 0x0000000000000000 # "
+#0x00000202 0x0000000000000000 # "
+#0x00000203 0x0000000000000000 # "
+#0x00000204 0x0000000000000000 # "
+#0x00000205 0x0000000000000000 # "
+#0x00000206 0x0000000000000000 # "
+#0x00000207 0x0000000000000000 # "
+#0x00000208 0x0000000000000000 # "
+#0x00000009 0x0000000000000000 # "
+#0x0000020A 0x0000000000000000 # "
+#0x0000020B 0x0000000000000000 # "
+#0x0000020C 0x0000000000000000 # "
+#0x0000020D 0x0000000000000000 # "
+#0x0000020E 0x0000000000000000 # "
+#0x0000020F 0x0000000000000000 # Variable-Size MTRRs Mask, r/w
+#0x00000210 0x0000000000000000 #  NOTE:  The documuentation states this MSR range is from
+#0x00000211 0x0000000000000000 #         "0000_020[1...F]".  I am interpreting that as
+#0x00000212 0x0000000000000000 #         "0000_02[10...1F]".  This may not be correct.
+#0x00000213 0x0000000000000000 #
+#0x00000214 0x0000000000000000 # "
+#0x00000215 0x0000000000000000 # "
+#0x00000216 0x0000000000000000 # "
+#0x00000217 0x0000000000000000 # "
+#0x00000218 0x0000000000000000 # "
+#0x00000219 0x0000000000000000 # "
+#0x0000021A 0x0000000000000000 # "
+#0x0000021B 0x0000000000000000 # "
+#0x0000021C 0x0000000000000000 # "
+#0x0000021D 0x0000000000000000 # "
+#0x0000021E 0x0000000000000000 # "
+#0x0000021F 0x0000000000000000 # "
+#0x00000250 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x00000258 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x00000259 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x00000268 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x00000269 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x0000026A 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x0000026B 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x0000026C 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x0000026D 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x0000026E 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x0000026F 0x0000000000000000 # Fixed-Size MTRRs, r/o
+#0x00000277 0x0000000000000000 # Page Attribute Table, r/w
+#0x000002FF 0x0000000000000000 # MTRR Default Memory Type, r/w
+#0x000006A0 0x0000000000000000 # User CET, r/w
+#0x000006A2 0x0000000000000000 # Supervisor CET, r/w
+#0x000006A4 0x0000000000000000 # PL0 Shadow Stack Pointer, r/w
+#0x000006A5 0x0000000000000000 # PL1 Shadow Stack Pointer, r/w
+#0x000006A6 0x0000000000000000 # PL2 Shadow Stack Pointer, r/w
+#0x000006A7 0x0000000000000000 # PL3 Shadow Stack Pointer, r/w
+#0x000006A8 0x0000000000000000 # Interrupt SSP Table Address, r/w
+#0x00000802 0x0000000000000000 # APIC ID
+#0x00000803 0x0000000000000000 # APIC Version
+#0x00000808 0x0000000000000000 # Task Priority, r/w, volatile
+#0x00000809 0x0000000000000000 # Arbitration Priority, r/o
+#0x0000080A 0x0000000000000000 # Processor Priority, r/o
+#0x0000080B 0x0000000000000000 # End Of Interrupt, write-1-only
+#0x0000080D 0x0000000000000000 # Logical Destination Register, r/o
+#0x0000080F 0x0000000000000000 # Spurrious Interrupt Vector, r/w
+#0x00000810 0x0000000000000000 # In Service Register, r/o
+#0x00000811 0x0000000000000000 # "
+#0x00000812 0x0000000000000000 # "
+#0x00000813 0x0000000000000000 # "
+#0x00000814 0x0000000000000000 # "
+#0x00000815 0x0000000000000000 # "
+#0x00000816 0x0000000000000000 # "
+#0x00000817 0x0000000000000000 # "
+#0x00000818 0x0000000000000000 # Trigger Mode Register, r/o
+#0x00000819 0x0000000000000000 # "
+#0x0000081A 0x0000000000000000 # "
+#0x0000081B 0x0000000000000000 # "
+#0x0000081C 0x0000000000000000 # "
+#0x0000081D 0x0000000000000000 # "
+#0x0000081E 0x0000000000000000 # "
+#0x0000081F 0x0000000000000000 # "
+#0x00000820 0x0000000000000000 # Interrupt Request Register, r/o
+#0x00000821 0x0000000000000000 # "
+#0x00000822 0x0000000000000000 # "
+#0x00000823 0x0000000000000000 # "
+#0x00000824 0x0000000000000000 # "
+#0x00000825 0x0000000000000000 # "
+#0x00000826 0x0000000000000000 # "
+#0x00000827 0x0000000000000000 # "
+#0x00000828 0x0000000000000000 # Error Status Register, r/write-0-only
+#0x00000830 0x0000000000000000 # Interrupt Command, r/w
+#0x00000832 0x0000000000000000 # LVT Timer, r/w
+#0x00000833 0x0000000000000000 # LVT Thermal Sensor, r/w
+#0x00000834 0x0000000000000000 # LVT Performance Monitor, r/w
+#0x00000835 0x0000000000000000 # LVT LINT1 (?), r/w
+#0x00000836 0x0000000000000000 # LVT LINT0 (?), r/w
+#0x00000837 0x0000000000000000 # LVT Error, r/w
+#0x00000838 0x0000000000000000 # Timer Initial Count, r/w
+#0x00000839 0x0000000000000000 # Timer Current Count, r/o
+#0x0000083E 0x0000000000000000 # Timer Divide Configuration, r/w
+#0x0000083F 0x0000000000000000 # Self IPI, w/o
+#0x00000840 0x0000000000000000 # Extended APIC Feature, r/o
+#0x00000841 0x0000000000000000 # Extended APIC Control, r/w
+#0x00000842 0x0000000000000000 # Specific End Of Interrupt, r/w
+#0x00000848 0x0000000000000000 # Interrupt Enable 0, r/w
+#0x00000849 0x0000000000000000 # Interrupt Enable 1, r/w
+#0x0000084A 0x0000000000000000 # Interrupt Enable 2, r/w
+#0x0000084B 0x0000000000000000 # Interrupt Enable 3, r/w
+#0x0000084C 0x0000000000000000 # Interrupt Enable 4, r/w
+#0x0000084D 0x0000000000000000 # Interrupt Enable 5, r/w
+#0x0000084E 0x0000000000000000 # Interrupt Enable 6, r/w
+#0x0000084F 0x0000000000000000 # Interrupt Enable 7, r/w
+#0x00000850 0x0000000000000000 # Extended Interrupt Local Vector Table, r/w
+#0x00000851 0x0000000000000000 # "
+#0x00000852 0x0000000000000000 # "
+#0x00000853 0x0000000000000000 # "
+#0x00000C81 0x0000000000000000 # L3 QoS Configuration, r/w
+#0x00000C8D 0x0000000000000000 # Monitoring Event Select, r/w
+#0x00000C8E 0x0000000000000000 # QOS L3 Counter, r/o
+#0x00000C8F 0x0000000000000000 # Resource Association, r/w
+#0x00000C90 0x0000000000000000 # L3 QOS Allocation Mask, r/w
+#0x00000C91 0x0000000000000000 # "
+#0x00000C92 0x0000000000000000 # "
+#0x00000C93 0x0000000000000000 # "
+#0x00000C94 0x0000000000000000 # "
+#0x00000C95 0x0000000000000000 # "
+#0x00000C96 0x0000000000000000 # "
+#0x00000C97 0x0000000000000000 # "
+#0x00000C98 0x0000000000000000 # "
+#0x00000C99 0x0000000000000000 # "
+#0x00000C9A 0x0000000000000000 # "
+#0x00000C9B 0x0000000000000000 # "
+#0x00000C9C 0x0000000000000000 # "
+#0x00000C9D 0x0000000000000000 # "
+#0x00000C9E 0x0000000000000000 # "
+#0x00000C9F 0x0000000000000000 # "
+#0x00000DA0 0x0000000000000000 # Extended Supervisor State, r/w
+#0xC0000080 0x0000000000000000 # Extended Feature Enable, r/w
+#0xC0000081 0x0000000000000000 # SYSCALL Target Address, r/w
+#0xC0000082 0x0000000000000000 # Long Mode SYSCALL Target Address, r/w
+#0xC0000083 0x0000000000000000 # Compatibility Mode SYSCALL Target Address, r/w
+#0xC0000084 0x0000000000000000 # SYSCALL Flag Mask, r/w
+#0xC00000E7 0x0000000000000000 # Read-Only Max Performance Frequency Clock Count, r/o, volatile
+#0xC00000E8 0x0000000000000000 # Read-Only Actual Performance Frequency Clock Count, r/o, volatile
+#0xC00000E9 0x0000000000000000 # Instructions Retired Performance Count, r/o, volatile
+#0xC0000100 0x0000000000000000 # FS Base, r/w
+#0xC0000101 0x0000000000000000 # GS Base, r/w
+#0xC0000102 0x0000000000000000 # Kernel GS Base, r/w
+#0xC0000103 0x0000000000000000 # Auxiliary Time Stamp Counter, r/w, volatile
+#0xC0000104 0x0000000000000000 # Time Stamp Counter Ratio, r/w
+#0xC0000200 0x0000000000000000 # L3 QOS Bandwidth Control, r/w
+#0xC0000201 0x0000000000000000 # "
+#0xC0000202 0x0000000000000000 # "
+#0xC0000203 0x0000000000000000 # "
+#0xC0000204 0x0000000000000000 # "
+#0xC0000205 0x0000000000000000 # "
+#0xC0000206 0x0000000000000000 # "
+#0xC0000207 0x0000000000000000 # "
+#0xC0000208 0x0000000000000000 # "
+#0xC0000209 0x0000000000000000 # "
+#0xC000020A 0x0000000000000000 # "
+#0xC000020B 0x0000000000000000 # "
+#0xC000020C 0x0000000000000000 # "
+#0xC000020D 0x0000000000000000 # "
+#0xC000020E 0x0000000000000000 # "
+#0xC000020F 0x0000000000000000 # "
+#0xC0000410 0x0000000000000000 # MCA Interrupt Configuration, r/w
+#0xC0010000 0x0000000000000000 # Performance Event Select 0, r/w
+#0xC0010001 0x0000000000000000 # Performance Event Select 1, r/w
+#0xC0010002 0x0000000000000000 # Performance Event Select 2, r/w
+#0xC0010003 0x0000000000000000 # Performance Event Select 3, r/w
+#0xC0010004 0x0000000000000000 # Performance Event Counter 0, r/w, volatile
+#0xC0010005 0x0000000000000000 # Performance Event Counter 1, r/w, volatile
+#0xC0010006 0x0000000000000000 # Performance Event Counter 2, r/w, volatile
+#0xC0010007 0x0000000000000000 # Performance Event Counter 3, r/w, volatile
+#0xC0010010 0x0000000000000000 # System Configuration, r/w
+#0xC0010015 0x0000000000000000 # Hardware Configuration, r/w
+##Note:  IO Range Base addresses given as MSRC001_001[6..8] (p 161)
+##       IO Range Mask addresses given as MSRC001_001[7..9] (p 162)
+##       Intrepreting as MSRC001_001[6,8] and MSRC001_001[7,9].
+##       See https://community.amd.com/t5/newcomers-start-here/ppr-documentation-errata/m-p/561391#M2275
+#0xC0010016 0x0000000000000000 # IO Range Base 0, r/w
+#0xC0010017 0x0000000000000000 # IO Range Mask 0, r/w
+#0xC0010018 0x0000000000000000 # IO Range Base 1, r/w
+#0xC0010019 0x0000000000000000 # IO Range Mask 1, r/w
+#0xC001001A 0x0000000000000000 # Top Of Memory, r/w
+#0xC001001D 0x0000000000000000 # Top Of Memory 2
+#0xC0010022 0x0000000000000000 # Machine Check Exception Redirection, r/w
+#0xC0010030 0x0000000000000000 # Processor Name String
+#0xC0010031 0x0000000000000000 # "
+#0xC0010032 0x0000000000000000 # "
+#0xC0010033 0x0000000000000000 # "
+#0xC0010034 0x0000000000000000 # "
+#0xC0010035 0x0000000000000000 # "
+#0xC0010050 0x0000000000000000 # IO Trap, r/w
+#0xC0010051 0x0000000000000000 # "
+#0xC0010052 0x0000000000000000 # "
+#0xC0010053 0x0000000000000000 # "
+#0xC0010054 0x0000000000000000 # IO Trap Control, r/w
+#0xC0010055 0x0000000000000000 # [Reserved]
+#0xC0010056 0x0000000000000000 # SMI Trigger IO Cycle, r/w
+#0xC0010058 0x0000000000000000 # MMIO Configuration Base Address
+0xC0010061 0x0000000000000000 # P-state Current Limit, r/o, volatile
+0xC0010062 0x0000000000000000 # P-state Control, r/w
+0xC0010063 0x0000000000000000 # P-state Status, r/o, volatile
+0xC0010064 0x0000000000000000 # P-state 7 (or is it 0?), r/w
+0xC0010065 0x0000000000000000 # P-state 6, r/w
+0xC0010066 0x0000000000000000 # P-state 5, r/w
+0xC0010067 0x0000000000000000 # P-state 4, r/w
+0xC0010068 0x0000000000000000 # P-state 3, r/w
+0xC0010069 0x0000000000000000 # P-state 2, r/w
+0xC001006A 0x0000000000000000 # P-state 1, r/w
+0xC001006B 0x0000000000000000 # P-state 0, r/w
+#0xC0010073 0x0000000000000000 # C-state Base Address, r/w
+#0xC0010074 0x0000000000000000 # CPU Watchdog Timer, r/w
+#0xC0010111 0x0000000000000000 # SMM Base Address, r/o
+#0xC0010112 0x0000000000000000 # SMM TSeg Base Address, r/w
+#0xC0010113 0x0000000000000000 # SMMTSeg Mask, r/w
+#0xC0010114 0x0000000000000000 # Virtual Machine Control, r/w
+#0xC0010115 0x0000000000000000 # IGNNE, r/w
+#0xC0010116 0x0000000000000000 # SMM Control, w/o
+#0xC0010117 0x0000000000000000 # Virtual Machine Host Save Physical Address, r/w
+#0xC0010118 0x0000000000000000 # SVM Lock Key, r/w
+#0xC001011A 0x0000000000000000 # Local SMI Status, r/w
+#0xC001011B 0x0000000000000000 # AVIC Doorbell, w/o
+#0xC001011E 0x0000000000000000 # VM Page Flush, w/o
+#0xC0010130 0x0000000000000000 # Guest Host Communication Block, r/w
+#0xC0010131 0x0000000000000000 # SEV Status, r/o
+#0xC0010140 0x0000000000000000 # OS Visible Work-around Length, r/w
+#0xC0010141 0x0000000000000000 # OS Visible Work-around Status, r/w
+0xC0010200 0x0000030FFFD7FFFF # Performance Event Select  0, r/w
+0xC0010201 0x0000FFFFFFFFFFFF # Performance Event Counter 0, r/w, volatile
+0xC0010202 0x0000030FFFD7FFFF # Performance Event Select  1, r/w
+0xC0010203 0x0000FFFFFFFFFFFF # Performance Event Counter 1, r/w, volatile
+0xC0010204 0x0000030FFFD7FFFF # Performance Event Select  2, r/w
+0xC0010205 0x0000FFFFFFFFFFFF # Performance Event Counter 2, r/w, volatile
+0xC0010206 0x0000030FFFD7FFFF # Performance Event Select  3, r/w
+0xC0010207 0x0000FFFFFFFFFFFF # Performance Event Counter 3, r/w, volatile
+0xC0010208 0x0000030FFFD7FFFF # Performance Event Select  4, r/w
+0xC0010209 0x0000FFFFFFFFFFFF # Performance Event Counter 4, r/w, volatile
+0xC001020A 0x0000030FFFD7FFFF # Performance Event Select  5, r/w
+0xC001020B 0x0000FFFFFFFFFFFF # Performance Event Counter 5, r/w, volatile
+0xC0010230 0x0F07DC000040FFFF # L3 Performance Event Select, r/w
+0xC0010231 0x0001FFFFFFFFFFFF # Performance Event Counter, r/w, volatile
+0xC0010232 0x0F07DC000040FFFF # L3 Performance Event Select, r/w
+0xC0010233 0x0001FFFFFFFFFFFF # Performance Event Counter, r/w, volatile
+0xC0010234 0x0F07DC000040FFFF # L3 Performance Event Select, r/w
+0xC0010235 0x0001FFFFFFFFFFFF # Performance Event Counter, r/w, volatile
+0xC0010236 0x0F07DC000040FFFF # L3 Performance Event Select, r/w
+0xC0010237 0x0001FFFFFFFFFFFF # Performance Event Counter, r/w, volatile
+0xC0010238 0x0F07DC000040FFFF # L3 Performance Event Select, r/w
+0xC0010239 0x0001FFFFFFFFFFFF # Performance Event Counter, r/w, volatile
+0xC001023A 0x0F07DC000040FFFF # L3 Performance Event Select, r/w
+0xC001023B 0x0001FFFFFFFFFFFF # Performance Event Counter, r/w, volatile
+0xC0010240 0x1800000F0040FFFF # Data Fabric Performance Event Select, r/w
+0xC0010241 0x0000FFFFFFFFFFFF # Data Fabric Performance Event Counter, r/w, volatile
+0xC0010242 0x1800000F0040FFFF # Data Fabric Performance Event Select, r/w
+0xC0010243 0x0000FFFFFFFFFFFF # Data Fabric Performance Event Counter, r/w, volatile
+0xC0010244 0x1800000F0040FFFF # Data Fabric Performance Event Select, r/w
+0xC0010245 0x0000FFFFFFFFFFFF # Data Fabric Performance Event Counter, r/w, volatile
+0xC0010246 0x1800000F0040FFFF # Data Fabric Performance Event Select, r/w
+0xC0010247 0x0000FFFFFFFFFFFF # Data Fabric Performance Event Counter, r/w, volatile
+0xC0010299 0x0000000000000000 # RAPL Power Unit, r/o, volatile
+0xC001029A 0x0000000000000000 # Core Energy Status, r/o, volatile
+0xC001029B 0x0000000000000000 # Package Energy Status, r/o, volatile
+0xC00102F0 0x0000000000000000 # Protected Processor Inventory Number Control, r/o
+0xC00102F1 0x0000000000000000 # Protected Processor Inventory Number, r/o
+#0xC0011002 0x0000000000000000 # CPUID Features for CPUID Fn00000007_E[A,B]X, r/w
+#0xC0011003 0x0000000000000000 # Thermal and Power Management CPUID Features, r/w
+#0xC0011004 0x0000000000000000 # CPUID Features for CPUID Fn00000001_E[C,D]X, r/w
+#0xC0011005 0x0000000000000000 # CPUID Features for CPUID Fn80000001_E[C,D]X, r/w
+#0xC0011019 0x0000000000000000 # Address Mask for DR1 Breakpoint, r/w
+#0xC001101A 0x0000000000000000 # Address Mask for DR2 Breakpoint, r/w
+#0xC001101B 0x0000000000000000 # Address Mask for DR3 Breakpoint, r/w
+#0xC001101C 0x0000000000000000 # Address Mask for DR0 Breakpoints, r/w
+#0xC0011030 0x0000000000000000 # IBS Fetch Control, r/w, volatile
+#0xC0011031 0x0000000000000000 # IBS Fetch Linear Address, r/w, volatile
+#0xC0011032 0x0000000000000000 # IBS Fetch Physical Address, r/w, volatile
+#0xC0011033 0x0000000000000000 # IBS Execution Control, r/w, volatile
+#0xC0011034 0x0000000000000000 # IBS Op RIP, r/w, volatile
+#0xC0011035 0x0000000000000000 # IBS Op Data, r/w, volatile
+#0xC0011036 0x0000000000000000 # IBS Op Data 2, r/w, volatile
+#0xC0011037 0x0000000000000000 # IBS Op Data 3, r/w, volatile
+#0xC0011038 0x0000000000000000 # IBS DC Linear Address, r/w, volatile
+#0xC0011039 0x0000000000000000 # IBS DC Physical Address, r/w, volatile
+#0xC001103A 0x0000000000000000 # IBS Control, r/o
+#0xC001103B 0x0000000000000000 # IBS Branch Target Address, r/w, volatile
+#0xC001103C 0x0000000000000000 # IBS Fetch Control Extended, r/o, volatile