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Source code of the STM32 MCU which acts like a USB-SPI bridge on a sx1302/sx1303 USB Corecell gateway.

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Lora-net/sx1302_spi_usb_bridge

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Corecell USB STM

Corecell USB STM is a project that manages communication between a host, generally a linux host, and the radio front end (SX1302/SX1303 & SX1261). The µC is mainly a SPI-USB bridge. The communication is achieved through a USB VCP (Virtual Com Port)

Compiler & IDE

This project has been developed with STM32CubeIDE (Version: 1.2.0)

This IDE includes everything that is required to compile & debug the project on the µC.

Project configuration

The project configuration (clock, gpio, spi, usb, ...) has been done with STM32CubeMX.

If you re-generate the project with STM32CubeMX, some files and the project defines will be overwritten. These files have been lightly modified and these modifications need to be re-applied. Git discard is a good tool to find them and cancel the modifications.

Search for the the tag @CUSTOM_SEMTECH and re-apply them

The project define #DEBUG will be added in the release. Please remove it.

Boot mode

This project can force the µC in boot mode (USB DFU boot mode). If modifications to the source code are made, then it is critical to check that the new firmware still allows the use of the boot command.

Licenses

This project uses several components under different licensing

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Source code of the STM32 MCU which acts like a USB-SPI bridge on a sx1302/sx1303 USB Corecell gateway.

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