Better usage of load/store multiple #4
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milica-lazarevic
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cme
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May 31, 2023
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@milica-lazarevic what is the status of this? Can we port it to LLVM 16? |
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This PR has been ported to LLVM 16. |
djtodoro
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LoadStoreMultiple optimization has been moved to the standalone pass so it can be expanded. Potentially, its position in a pipeline could be changed.
Additional support is added to recognize more sequences. Before, a sequence like this wasn't accepted: lw a1, 4(a0) lw a3, 12(a0) lw a2, 8(a0) Now, when we're sorting instructions by the reg:offset pair internally, the above is accepted.
Beside regular instruction sequence, we're also looking for an instruction sequence that's "missing" one(or more) instruction to be complete and interchangeable with lwm/swm instruction. The sequence is optimizable if the Rt register in missing instruction is available.
We're handling the situation where the instruction sequence is regular, except for one instruction having a "wrong" Rt register number. A sequence like that is optimizable if the register with the expected register number is available. In that case, we're emitting one additional move instruction after lwm/swm.
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Since we have confirmed a |
This reverts commit 5ea10a5.
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Last commit ("NanoMIPS: NMLoadStoreMultiple add reg gap support") has been temporarily reverted due to a bug. |
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LoadStoreMultiple optimization has been moved to the standalone pass. Compared to the previous implementation, we regocnize sequences not sorted by the reg:offset pairs as optimizable. Please take a look into the example below:
Now, a sequence like the following is optimizable:
lw a0, 8(a4)lw a2, 16(a4)=>lwm a0, 8(a4), 3lw a1, 12(a4)Also, there is support for optimizing the following sequences:
lw a0, 8(a4)lw a1, 12(a4)=>lwm a0, 8(a4), 4lw a3, 20(a4)lw a0, 8(a4)lw a1, 12(a4)=>lwm a0, 8(a4), 3move a3, a2lw a3, 16(a4)